LTC4352 Low Voltage Ideal Diode Controller with Monitoring FeaTures DescripTion n Low Loss Replacement for Power Diode The LTC®4352 creates a near-ideal diode using an external n Controls N-Channel MOSFET N-channel MOSFET. It replaces a high power Schottky diode n 0V to 18V Supply ORing or Holdup and the associated heat sink, saving power and board area. n 0.5μs Turn-On and Turn-Off Time The ideal diode function permits low loss power ORing n Undervoltage and Overvoltage Protection and supply holdup applications. n Open MOSFET Detect The LTC4352 regulates the forward voltage drop across n Status and Fault Outputs the MOSFET to ensure smooth current transfer in diode- n Hot Swappable OR applications. A fast turn-on reduces the load voltage n Reverse Current Enable Input droop during supply switch-over. If the input supply fails n 12-Pin MSOP and DFN (3mm × 3mm) Packages or is shorted, a fast turn-off minimizes reverse currents. The controller operates with supplies from 2.9V to 18V. applicaTions For lower voltages, an external supply is needed at the V pin. Power passage is disabled during undervoltage n Redundant Power Supplies CC or overvoltage conditions. The controller also features an n Supply Holdup open MOSFET detect circuit that flags excessive voltage n Telecom Infrastructure drop across the pass transistor in the on state. A REV pin n Computer Systems and Servers enables reverse current, overriding the diode behavior when desired. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT and PowerPath are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical applicaTion 2.9V to 18V Ideal Diode Power Dissipation vs Load Current 4.0 Si7336ADP 3.5 2.9V TO 18V TO LOAD 0.1µF* W) 3.0 N ( DIODE (SBG1025L) O 2.5 TI VCCCPO SOURCE VIN GATE STOAUTUTS MSTOASTFUEST ON DISSIPA 2.0 POWER 0.1µF UV LTC4352 ER 1.5 SAVED W OV FAULT FAULT PO 1.0 REV GND 0.5 4352 TA01 MOSFET (Si7336ADP) *OPTIONAL 0 0 2 4 6 8 10 LOAD CURRENT (A) 4352 TA01b 4352fa 1

LTC4352 absoluTe MaxiMuM raTings (Notes 1, 2) FAULT, STATUS Currents ..........................................5mA V , SOURCE Voltages ...................................–2V to 24V IN Operating Ambient Temperature Range V Voltage ..................................................–0.3V to 7V CC LTC4352C ................................................0°C to 70°C OUT Voltage ...................................................–2V to 24V LTC4352I .............................................–40°C to 85°C CPO, GATE Voltages (Note 3) .....................–0.3V to 30V LTC4352H ..........................................–40°C to 150°C CPO D.C. Current ...................................................10mA Storage Temperature Range ..................–65°C to 150°C UV, OV, REV Voltages ................................–0.3V to 24V Lead Temperature (Soldering, 10 sec) FAULT, STATUS Voltages ............................–0.3V to 24V MS Package ......................................................300°C pin conFiguraTion TOP VIEW TOP VIEW VIN 1 12 SOURCE VCC 2 11 GATE VVCINC 12 1121 SGOATUERCE UV 3 13 10 CPO UV 3 10 CPO OV 4 9 GND OV 4 9 GND STATUS 5 8 OUT STATUS 5 8 OUT FAULT 6 7 REV FAULT 6 7 REV DD PACKAGE MS PACKAGE 12-PIN (3mm × 3mm) PLASTIC DFN 12-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 43°C/W TJMAX = 150°C, θJA = 164°C/W EXPOSED PAD (PIN 13) PCB GND CONNECTION OPTIONAL orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4352CDD#PBF LTC4352CDD#TRPBF LDPJ 12-Pin (3mm × 3mm) Plastic DFN 0°C to 70°C LTC4352IDD#PBF LTC4352IDD#TRPBF LDPJ 12-Pin (3mm × 3mm) Plastic DFN –40°C to 85°C LTC4352HDD#PBF LTC4352HDD#TRPBF LDPJ 12-Pin (3mm × 3mm) Plastic DFN –40°C to 150°C LTC4352CMS#PBF LTC4352CMS#TRPBF 4352 12-Lead Plastic MSOP 0°C to 70°C LTC4352IMS#PBF LTC4352IMS#TRPBF 4352 12-Lead Plastic MSOP –40°C to 85°C LTC4352HMS#PBF LTC4352HMS#TRPBF 4352 12-Lead Plastic MSOP –40°C to 150°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4352fa 2

LTC4352 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 12V, V = V , V = V , V Open, unless otherwise noted. A IN SOURCE IN OUT IN CC SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supplies V Input Operating Range l 2.9 18 V IN With External 2.9V to 4.7V V Supply l 0 V V CC CC With External 4.7V to 6V V Supply l 0 18 V CC V V External Supply Range l 2.9 6 V CC(EXT) CC V V Internal Regulator Voltage l 3.5 4.1 4.7 V CC(INT) CC I V Supply Current l 1.4 3 mA IN IN V = 0V, V = 5V, V = 18V l –10 –13 µA IN CC OUT V = 0V, V = 5V, V = 18V (LTC4352H) l –10 –25 µA IN CC OUT I External V Supply Current V = 5V, V = 0V l 1.25 2.5 mA CC CC CC IN V V Undervoltage Lockout Threshold V Rising l 2.45 2.57 2.7 V CC(UVLO) CC CC ΔV V Undervoltage Lockout Hysteresis l 50 70 90 mV CC(HYST) CC Ideal Diode Control V Forward Regulation Voltage (V − V ) l 10 25 40 mV FWD(REG) IN OUT ΔV MOSFET Gate Drive (V – V ) V = 0.1V, I = 0 and –1μA l 5 6.1 7.5 V GATE GATE SOURCE FWD t GATE Turn-On Delay C = 10nF, V = 0.2V l 0.25 0.5 µs ON(GATE) GATE FWD t GATE Turn-Off Delay C = 10nF, V = −0.2V l 0.2 0.5 µs OFF(GATE) GATE FWD Input/Output Pins V UV, OV Threshold Voltage V Falling, V Rising l 490 500 510 mV UV,OV(TH) UV OV ΔV UV, OV Threshold Hysteresis l 2.5 5 8.5 mV UV,OV(HYST) V REV Threshold Voltage l 0.8 1.0 1.2 V REV(TH) (LTC4352H) l 0.8 1.0 1.25 V I UV, OV Current V = 0.5V l 0 ±1 µA UV,OV I REV Current V = 1V l 7 10 13 µA REV REV I OUT Current V = 0V, 12V l –13 200 µA OUT OUT I SOURCE Current V = 0V l –85 –130 µA SOURCE SOURCE I CPO Pull-Up Current V = V = 2.9V l –60 –90 –115 µA CPO(UP) CPO IN V = V = 18V l –50 –75 –100 µA CPO IN I GATE Fast Pull-Up Current V = 0.2V, ΔV = 0V, V = 17V –1.5 A GATE FWD GATE CPO GATE Fast Pull-Down Current V = –0.2V, ΔV = 5V 1.5 A FWD GATE GATE Off Pull-Down Current V = 0V, ΔV = 2.5V l 60 100 145 µA UV GATE I STATUS, FAULT Leakage Current V = 18V l 0 ±1 µA FLT,STAT(IN) I STATUS, FAULT Pull-Up Current V = 0V l –8 –10 –12 µA FLT,STAT(UP) V STATUS, FAULT Output Low Voltage I = 1.25mA l 0.2 0.4 V OL V STATUS, FAULT Output High Voltage I = –1μA l V – 1 V – 0.5 V OH CC CC ΔV MOSFET On Detect Threshold STATUS Pulls Low, V = 50mV l 0.3 0.7 1.1 V GATE(ST) FWD STATUS Pulls Low, V = 50mV (LTC4352H) l 0.28 0.7 1.1 V FWD V Open MOSFET Threshold (V – V ) FAULT Pulls Low l 200 250 300 mV FWD(FLT) IN OUT Note 1: Stresses beyond those listed under Absolute Maximum Ratings pins are negative. All voltages are referenced to GND unless otherwise may cause permanent damage to the device. Exposure to any Absolute specified. Maximum Rating for extended periods may affect device reliability and Note 3: Internal clamps limit the GATE and CPO pins to a minimum of 5V lifetime. above, and a diode below SOURCE. Driving these pins to voltages beyond Note 2: All currents into device pins are positive; all currents out of device the clamp may damage the device. 4352fa 3

LTC4352 Typical perForMance characTerisTics T = 25°C, V = 12V, V = V , V = V , A IN SOURCE IN OUT IN V Open, unless otherwise noted. CC V Current vs Voltage with IN V Current vs Voltage External V V Current vs Voltage IN CC CC 1.6 300 1.50 VCC = 5V VIN = 0V 250 1.25 1.2 200 1.00 A) A)150 A) I (mIN 0.8 I (µIN100 I (mCC0.75 0.50 50 0.4 0 0.25 0 –50 0 0 3 6 9 12 15 18 0 1 2 3 4 5 0 1 2 3 4 5 6 VIN (V) 4352 G01 VIN (V) 4352 G02 VCC (V) 4352 G03 OUT Current vs Voltage CPO Voltage vs Current GATE Voltage vs Current 300 7 7 VOUT = VIN – 0.1V 250 6 VIN = 18V 6 VIN = 18V 5 5 200 V) V) µA) 150 (URCE 4 VIN = 2.9V (URCE 4 VIN = 2.9V (UT VSO 3 VSO 3 O100 – – I 50 V CPO 2 V GATE 2 1 1 0 0 0 –50 –1 –1 0 3 6 9 12 15 18 0 –20 –40 –60 –80 –100 –120 0 –20 –40 –60 –80 –100 –120 VOUT (V) 4352 G04 ICPO (µA) 4352 G05 IGATE (µA) 4352 G06 STATUS, FAULT Output Low STATUS, FAULT Output High Voltage vs Current Voltage vs Current 1 4.0 3.5 0.8 3.0 2.5 0.6 V) V) (OL (OH 2.0 V V 0.4 1.5 1.0 0.2 0.5 0 0 0 1 2 3 4 5 0 –2 –4 –6 –8 –10 –12 CURRENT (mA) CURRENT (µA) 4352 G07 4352 G08 4352fa 4

LTC4352 pin FuncTions V (Pin 1): Voltage Sense and Supply Input. Connect this pulls this pin up to a diode below V . It may be pulled IN CC pin to the power input side of the MOSFET. The low voltage above V using an external pull-up. Tie to GND or leave CC supply V is generated from V . The voltage sensed at open if unused. CC IN this pin is used to control the MOSFET gate. REV (Pin 7): Reverse Current Enable Input. Connect this V (Pin 2): Low Voltage Supply. Connect a 0.1μF capacitor pin to GND for normal diode operation that blocks reverse CC from this pin to ground. When V ≥ 2.9V, this pin provides current. Driving this pin above 1V fully turns on the MOSFET IN decoupling for an internal regulator that generates a 4.1V gate to allow reverse current. An internal 10µA current supply. For applications where V < 2.9V, connect an source pulls this pin to GND. IN external supply voltage in the range 2.9V to 6V to this pin. OUT (Pin 8): Output Voltage Sense Input. Connect this UV (Pin 3): Undervoltage Comparator Input. Connect this pin to the output side of the MOSFET. The voltage sensed pin to an external resistive divider from V . If the volt- at this pin is used to control the MOSFET gate. IN age at this pin falls below 0.5V, an undervoltage fault is GND (Pin 9): Device Ground. detected and the MOSFET is turned off. The comparator has a built-in hysteresis of 5mV. Tie to V if unused. CPO (Pin 10): Charge Pump Output. Connect a capacitor CC from this pin to the SOURCE pin. The value of this capaci- OV (Pin 4): Overvoltage Comparator Input. Connect this tor is approximately 10x the gate capacitance (C ) of the ISS pin to an external resistive divider from V . If the volt- IN MOSFET switch. The charge stored on this capacitor is age at this pin rises above 0.5V, an overvoltage fault is used to pull-up the gate during a fast turn-on. Leave this detected and the MOSFET is turned off. The comparator pin open if fast turn-on is not needed. has a built-in hysteresis of 5mV. Tie to GND if unused. GATE (Pin 11): MOSFET Gate Drive Output. Connect this STATUS (Pin 5): MOSFET Status Output. This pin is pulled pin to the gate of the external N-channel MOSFET switch. low by an open-drain output when the external MOSFET An internal clamp limits the gate voltage to 6.1V above, is on. An internal 10µA current source pulls this pin up and a diode below SOURCE. During fast turn-on a 1.5A to a diode below V . It may be pulled above V using CC CC pull-up charges GATE to CPO. During fast turn-off a 1.5A an external pull-up. Tie to GND or leave open if unused. pull-down discharges GATE to SOURCE. FAULT (Pin 6): Fault Output. This pin is pulled low by an SOURCE (Pin 12): MOSFET Gate Drive Return. Connect open-drain output when a fault occurs. This fault could this pin to the source of the external N-channel MOSFET either be an undervoltage fault, an overvoltage fault, or switch. an open MOSFET fault. The external MOSFET is turned off for undervoltage and overvoltage faults, while it is left on EXPOSED PAD (Pin 13, DD Package Only): Exposed pad for open MOSFET fault. An internal 10µA current source may be left open or connected to device ground. 4352fa 5

LTC4352 FuncTional DiagraM VCC VIN CPO 2 1 10 CHARGE VCC PUMP f = 3MHz 100µA + 4.1V LDO + – GATE OFF AMP 11 GATE – ENABLE + REVERSE 25mV +– 12 SOURCE CURRENT CP4 8 OUT DISABLE VIN – LDO + 7 REV – VCC LOW – 1V VCC 10µA CP5 2.57V + CP3 10µA 0.7V CP6 GATE +– + 5 STATUS UV 3 – M1 UV FAULT SOURCE – + CP2 VCC 0.5V OPEN 10µA MOSFET DETECT – 6 FAULT OV FAULT M2 OV 4 + CP1 Z 9 13 *DD PACKAGE ONLY 4352 FD GND EXPOSED PAD* 4352fa 6

LTC4352 operaTion The LTC4352 controls either single or back-to-back limit the GATE to SOURCE voltage to 6.1V, and the CPO to N-channel MOSFETs in order to emulate an ideal diode. SOURCE voltage to 6.7V. The same clamps also limit the CPO Dual MOSFETs eliminate current flow from the input to the and GATE pins to a diode voltage below the SOURCE pin. output in an input undervoltage or overvoltage condition. OV, UV, and V comparators, CP1 to CP3, control power CC When enabled, an amplifier (AMP) monitors the voltage passage. The MOSFET is held off whenever the OV pin between the V and OUT pins, and drives the GATE pin. is above 0.5V, the UV pin is below 0.5V, or the V pin is IN CC The amplifier controls the gate of the external MOSFET below 2.57V. There is a 40µs delay from all three condi- to servo its forward voltage drop (V – OUT) to 25mV. tions becoming good to GATE being allowed to turn on. IN The gate voltage rises to enhance the MOSFET if the load Overvoltage causes a fast turn-off, while undervoltage current causes more than 25mV of drop. For large output activates a 100μA pull-down on GATE after a 7μs delay. currents the MOSFET gate is driven fully on and the voltage Open-drain pull-down, M1, pulls the STATUS pin low when drop is equal to I • R . LOAD DS(ON) the GATE to SOURCE voltage exceeds 0.7V, to indicate that In the case of an input supply short-circuit, when the power is passing through the MOSFET. The FAULT output, MOSFET is conducting, a large reverse current starts M2, pulls low during an undervoltage or overvoltage fault flowing from the load towards the input. The AMP detects condition. It also pulls low when GATE is fully on and this failure condition as soon as it appears, and turns off the forward voltage drop exceeds 250mV, indicating the the MOSFET by pulling down the GATE pin. The REV pin MOSFET has too much current or has failed open circuit. can be used to allow reverse current, overriding the diode Note that this open MOSFET fault does not turn off the behavior. MOSFET unlike the undervoltage and overvoltage faults. The AMP quickly pulls-up the GATE pin whenever it senses LDO is a low dropout regulator that generates a 4.1V a large forward voltage drop. An external capacitor between supply at the V pin from the V input. When a supply CC IN the CPO and SOURCE pins is needed for fast gate pull-up. below 2.9V is being ORed, an external supply in the 2.9V This capacitor is charged up, at device power-up, by the to 6V range is required at the V pin. Comparator CP4 CC internal charge-pump. This stored charge is used for the will disable LDO when V is below V . IN CC fast gate pull-up. The GATE pin sources current from the CPO pin, and sinks current to the SOURCE and GND pins. Internal clamps 4352fa 7

LTC4352 applicaTions inForMaTion High availability systems often employ parallel-connected common supply voltage it turns off the MOSFET, thereby power supplies or battery feeds to achieve redundancy matching the function and performance of an ideal diode. and enhance system reliability. ORing diodes have been a popular means of connecting these supplies at the Power Supply Configuration point of load. Diodes with storage capacitors also hold The LTC4352 can operate with supplies down to 0V. This up supply voltages when an input voltage sags or has a requires powering the V pin with an always present CC brownout. The disadvantage of these approaches is the external supply in the 2.9V to 6V range. If not always diode’s significant forward voltage drop and the resulting present, a series 470Ω resistor or Schottky diode limits power loss. Additionally, diodes provide no information device power dissipation and backfeeding of low V CC concerning the status of the sourcing supply. Separate supply when V is high. For a 2.9V to 4.7V V supply, IN CC control must therefore be added to ensure that a supply V should be lower than V . A 0.1µF bypass capacitor IN CC that is out of range is not allowed to affect the load. should also be connected between the V and GND pins, CC The LTC4352 solves these problems by using an external close to the device. Figure 2 illustrates this. N-channel MOSFET as the pass element (see Figure 1). If V operates above 2.9V then the external supply at IN The MOSFET is turned on when power is being passed, V is not needed. The 0.1µF capacitor is still required CC allowing for a low voltage drop from the supply to the load. for bypassing. When the input source voltage drops below the output Q1 Si7336ADP 12V TO LOAD C2 R4 R5 2.7k 2.7k 0.1µF CPO SOURCE VIN GATE OUT D1 C1 VCC STATUS MONOSFET 0.1µF UV LTC4352 D2 OV FAULT FAULT REV GND DD12:: GRREDEE LNE DLE LDN L1N26113C5A1CL 4352 F01 Figure 1. 12V Ideal Diode with Status and Fault Indicators 2.9V TO 18V TO LOAD 0V TO VCC TO LOAD 0V TO 18V TO LOAD 2.9V TO 4.7V 4.7V TO 6V VIN GATE OUT VIN GATE OUT VIN GATE OUT VCC VCC VCC LTC4352 LTC4352 LTC4352 0.1µF 0.1µF 0.1µF GND GND GND 4352 F02 Figure 2. Power Supply Configurations 4352fa 8

LTC4352 applicaTions inForMaTion CPO and GATE Start-Up N-channel MOSFETs. The maximum allowable drain-source voltage, BV , must be higher than the supply voltages In single MOSFET applications, CPO is initially pulled up DSS as the full supply voltage can appear across the MOSFET to a diode below the SOURCE pin (Figure 3). In back-to- when the input falls to 0V. back MOSFET applications, CPO starts off at 0V, since SOURCE is near ground (Figure 4). CPO starts ramping The FAULT pin pulls low to signal an open MOSFET fault up 10µs after V clears its undervoltage lockout level. whenever the forward voltage drop across the enhanced CC Another 40µs later, GATE will also start ramping up with MOSFET exceeds 250mV. The R should be small DS(ON) CPO if UV, OV and V – OUT conditions allow it to. The enough to conduct the maximum load current while not IN ramp rate is decided by the CPO pull-up current into the triggering such a fault (when using FAULT), and to stay combined CPO and GATE pin capacitances. An internal within the MOSFET’s power rating at the maximum load clamp limits the CPO voltage to 6.7V above SOURCE, current. while the final GATE voltage is determined by the forward drop servo amplifier. CPO Capacitor Selection The recommended value of the capacitor between the MOSFET Selection CPO and SOURCE pins is approximately 10x the input The LTC4352 drives N-channel MOSFETs to conduct the capacitance, C , of the MOSFET. A larger capacitor takes ISS load current. The important features of the MOSFET are a correspondingly longer time to charge up by the internal its threshold voltage, the maximum drain-source voltage charge pump. A smaller capacitor suffers more voltage BV , and the on-resistance R . drop during a fast gate turn-on event as it shares charge DSS DS(ON) with the MOSFET gate capacitance. The gate drive for the MOSFET is guaranteed to be between 5V and 7.5V. This allows the use of logic level threshold VIN = 5V CPO VIN = 5V CPO C2 = 0.1µF C2 = 0.1µF GATE GATE OUT VOLTAGE OUT VOLTAGE (5V/DIV) (5V/DIV) VIN, SOURCE VIN VCC VCC TIME (2.5ms/DIV) 4352 FO3 TIME (2.5ms/DIV) 4352 FO4 Figure 3. Start-up Waveform for Single MOSFET Application Figure 4. Start-up Waveform for Back-to-Back MOSFET Application 4352fa 9

LTC4352 applicaTions inForMaTion Undervoltage and Overvoltage Protection Inrush Control Unlike a regular diode, the LTC4352 can prevent out of The LTC4352 can be used for inrush control in applications range input voltages from affecting the load voltage. This where the input supply is hot-plugged. See Figure 6. The requires back-to-back MOSFETs, and resistive dividers CPO capacitor is omitted, since fast turn-on with stored from the input to the UV and OV pins. For an example, charge is not desired here. Undervoltage holds the gate see Figure 5. off till the short pin makes contact. 40µs after the UV level is satisfied, the MOSFET gate ramps up due to the CPO MOSFET Q2 is required to block conduction through the pull-up current. A RC network on the gate further slows body diode of Q1 when its gate is held off. The resistive down the output dV/dt, while allowing fast turn-off during dividers set up the input voltage range where the ideal reverse current or overvoltage conditions. Resistor R diode control is allowed to operate. Outside this range, G prevents high frequency oscillations in Q2. A dedicated the gate is held off and the FAULT pin pulls low. hot swap controller may be needed if overcurrent protec- When using a CPO capacitor in circuit with back-to-back tion is also desired. MOSFETs, there will be a large inrush current to the load capacitance due to the fast gate turn-on after UV, OV levels are met. Without the capacitor, the inrush will depend on the CPO pull-up current charging up the gate capacitance. Q2 Q1 Si7336ADP Si7336ADP 12V TO LOAD Q2 Q1 Z1 Si7336ADP Si7336ADP R6 1R0GΩ 5V TO LOAD 10k CG 0.1µF 0.15µF 105k R3 VIN SOURCE GATEOUT C2 UV 311.6%k R3 VIN CPO SOURCE GATE OUT 5.11k R2 LTC4352 CPO NC UV FAULT OV 1k R2 STATUS GND 1% OV LTC4352 VCC C1 GND Z1: DIOD4E35S2 F 0I6NC. SMAJ12A 3.019%k R1 0.1µF GND REV BACKPLANE CONNECTORS PLUG-IN CARD 4352 F05 Figure 5. 5V Ideal Diode with UV and OV Protection Figure 6. Inrush and Ideal Diode Control on a Hot Swap Card 4352fa 10

LTC4352 applicaTions inForMaTion External CPO Supply Design Example The internal charge pump takes milliseconds to charge The following design example demonstrates the calcula- up the CPO pin capacitor especially during device power tions involved for selecting components in a 12V system up. This time can be shortened by connecting an external with 10A maximum load current (see Figure 1). supply to the CPO pin. A series resistor is needed to limit First, calculate the R of the MOSFET to achieve the DS(ON) the current into the internal clamp between the CPO and desired forward drop at full load. Assuming a V of FWD SOURCE pins. The CPO supply should also be higher than 50mV (which is comfortably below the 200mV minimum the main input supply to meet the gate drive requirements open MOSFET fault threshold): of the MOSFET. Figure 7 shows such a 5V ideal diode ap- plication, where a 12V supply is connected to the CPO pin V 50mV R ≤ FWD = =5mΩ through a 1k resistor. The 1k limits the current into the DS(ON) I 10A LOAD CPO pin to 5.3mA, when the SOURCE pin is grounded. The Si7336ADP offers a good solution, in a SO-8 sized Input Transient Protection package, with a maximum R of 4mΩ and BV of DS(ON) DSS 30V. The maximum power dissipation in the MOSFET is: When the capacitances at the input and output are very small, rapid changes in current can cause transients that P = I2 • R = (10A)2 • 4mΩ = 0.4W LOAD DS(ON) exceed the 24V Absolute Maximum Rating of the V and IN With a maximum steady-state thermal resistance, θ , OUT pins. In ORing applications using a single MOSFET, one JA of 65°C/W, 0.4W causes a modest 26°C rise in junction surge suppressor connected from OUT to ground clamps temperature of the Si7336ADP above the ambient. all the inputs. In the absence of a surge suppressor, an output capacitance of 10μF is sufficient in most applications The input capacitance, C , of the Si7336ADP is about ISS to prevent the transient from exceeding 24V. Back-to-back 6500pF. Slightly exceeding the 10x recommendation, a MOSFET applications, depending on voltage levels, may 0.1µF capacitor is selected for C2. require a surge suppressor on each supply input. Q1 Si7336ADP 5V TO LOAD VIN GATE OUT 12V SOURCE R7 C2 LTC4352 1k 0.1µF CPO GND 4352 F07 Figure 7. 5V Ideal Diode with External 12V Powering CPO for Faster Start-up and Refresh 4352fa 11

LTC4352 applicaTions inForMaTion LEDs, D1 and D2, require around 3mA for good luminous associated with the power path through the MOSFET should intensity. Accounting for a 2V diode drop and 0.5V V , have low resistance. See Figure 8. OL R1 and R2 are set to 2.7k. It is also important to put C1, the bypass capacitor for the V pin, as close as possible between V and GND. Also PCB Layout Considerations CC CC place C2 near the CPO and SOURCE pins. Surge suppres- Connect the VIN and OUT pin traces as close as possible sors, when used, should be mounted close to the LTC4352 to the MOSFET’s terminals. Keep the traces to the MOSFET using short lead lengths. wide and short to minimize resistive losses. The PCB traces CURRENT FLOW Q1 CURRENT FLOW SO-8 S D FROM INPUT S D TO LOAD SUPPLY W W S D G D TRACK WIDTH W: VIA TO GROUND PLANE 0.03˝ PER AMPERE ON 1OZ CU FOIL 12 11 10 9 8 7 E C R E D T SOU GAT GN OU LTC4352 MSOP-12 C C N V VI 1 2 3 4 5 6 C1 VIA TO GROUND PLANE 4352 F08 DRAWING IS NOT TO SCALE! Figure 8. Recommended PCB Layout for Power MOSFET 4352fa 12

LTC4352 Typical applicaTions Plug-in Card Supply Holdup Using Ideal Diode at Input Q1 Si7336ADP HOT SWAP 12V TO LOAD CONTROLLER SOURCE VIN GATE OUT + CHOLDUP LTC4352 GND GND GND 4352 TA02 BACKPLANE CONNECTORS PLUG-IN CARD Ideal Diode with Reverse Input Protection Q1 Si4438DY 3.5V TO 9V 10A LOAD 0.1µF D3 CPO SOURCE VIN GATE OUT 1N4148 D5 OR VCC STATUS SMAJ17A BAT85 UV LTC4352 C1 OV FAULT 0.1µF REV GND D4 4352 TA04 BAT85 4352fa 13

LTC4352 package DescripTion DD Package 12-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1725 Rev A) R = 0.115 0.40 ± 0.10 TYP 7 12 0.70 ±0.05 3.50 ±0.05 2.38 ±0.05 3.00 ±0.10 2.38 ±0.10 2.10 ±0.05 1.65 ±0.05 (4 SIDES) 1.65 ± 0.10 PIN 1 PIN 1 NOTCH PACKAGE TOP MARK R = 0.20 OR OUTLINE (SEE NOTE 6) 0.25 × 45° CHAMFER 6 1 0.25 ± 0.05 0.200 REF 0.75 ±0.05 0.23 ± 0.05 0.45 BSC 0.45 BSC 2.25 REF 2.25 REF (DD12) DFN 0106 REV A 0.00 – 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW—EXPOSED PAD APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE MS Package 12-Lead Plastic MSOP (Reference LTC DWG # 05-08-1668 Rev Ø) 4.039 ± 0.102 (.159 ± .004) 0.889 ± 0.127 (NOTE 3) 0.406 ± 0.076 (.035 ± .005) 121110 9 87 (.016 ± .003) REF 5.23 DETAIL “A” 3.00 ± 0.102 3.20 – 3.45 0.254 4.90 ± 0.152 (.206) (.118 ± .004) MIN (.126 – .136) (.010) 0° – 6° TYP (.193 ± .006) (NOTE 4) GAUGE PLANE 0.53 ± 0.152 1 2 3 4 5 6 0.42 ± 0.038 0.65 (.021 ± .006) 1.10 0.86 (.0165 ± .0015) (.0256) (.043) (.034) TYP BSC DETAIL “A” MAX REF RECOMMENDED SOLDER PAD LAYOUT 0.18 SEATING (.007) PLANE 0.22 – 0.38 0.1016 ± 0.0508 (.009 – .015) (.004 ± .002) TYP 0.650 NOTE: (.0256) MSOP (MS12) 1107 REV Ø 1. DIMENSIONS IN MILLIMETER/(INCH) BSC 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 4352fa 14

LTC4352 revision hisTory REV DATE DESCRIPTION PAGE NUMBER A 12/10 Added H-grade information 2,3 Revised FAULT pin description in Pin Functions 5 Revised Functional Diagram 6 Added text to Operation section 7 Revised Figures 2, 5, 6 in Applications Information 8, 10 Added new Typical Application 13 Revised Typical Application and Related Parts list 16 4352fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 15 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC4352 Typical applicaTion 0V to 18V Ideal Diode-OR Si7336ADP VIN1 TO LOAD 0V TO 18V 0.1µF 5V CPO SOURCE VIN GATE OUT VCC STATUS 0.1µF UV LTC4352 OV FAULT REV GND Si7336ADP VIN2 0V TO 18V 0.1µF 5V CPO SOURCE VIN GATE OUT VCC STATUS 0.1µF UV LTC4352 OV FAULT REV GND 4352 TA03 relaTeD parTs PART NUMBER DESCRIPTION COMMENTS LTC1473/LTC1473L Dual PowerPath™ Switch Driver N-Channel, 4.75V to 30V/3.3V to 10V, SSOP-16 LTC1479 PowerPath Controller for Dual Battery Systems Three N-Channel Drivers, 6V to 28V, SSOP-36 LTC4350 Hot Swappable Load Share Controller N-Channel, 1.5V to 12V, Share Bus, SSOP-16 LTC4354 Negative Voltage Diode-OR Controller and Monitor Dual N-Channel, –4.5V to –80V, SO-8, DFN-8 LTC4355 Positive High Voltage Ideal Diode-OR and Monitor Dual N-Channel, 9V to 80V, SO-16, DFN-14 LTC4357 Positive High Voltage Ideal Diode Controller N-Channel, 9V to 80V, MSOP-8, DFN-6 LTC4358 5A Ideal Diode Internal N-Channel, 9V to 26.5V, TSSOP-16, DFN-14 LTC4411 2.6A Low Loss Ideal Diode in ThinSOT™ Internal P-Channel, 2.6V to 5.5V, 40μA I , SOT-23 Q LTC4412/LTC4412HV Low Loss PowerPath Controller in ThinSOT P-Channel, 2.5V to 28V/36V, 11μA I , TSOT-23 Q LTC4413/LTC4413-1 Dual 2.6A, 2.5V to 5.5V, Ideal Diodes in DFN-10 Dual Internal P-Channel, 2.5V to 5.5V, DFN-10 LTC4414 36V Low Loss PowerPath Controller for Large PFETs P-Channel, 3V to 36V, 30μA I , MSOP-8 Q LTC4416/LTC4416-1 36V Low Loss Dual PowerPath Controller for Large PFETs Dual P-Channel, 3.6V to 36V, 70μA I , MSOP-10 Q 4352fa 16 Linear Technology Corporation LT 1210 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2008