LTC4315 2-Wire Bus Buffer with High Noise Margin FEATURES DESCRIPTION n Bidirectional Buffer Increases Fanout The LTC4315 is a hot-swappable 2-wire bus buffer n High Noise Margin with VIL = 0.3 • VCC that provides bidirectional buffering, while maintain- n Compatible with Non-Compliant I2C Devices That ing a low offset voltage and high noise margin up to Drive a High VOL 0.3 • VCC. The high noise margin allows the LTC4315 to be n Selectable Rise Time Accelerator Current interoperable with devices that drive a high V (>0.4V) OL n Level Shift 1.5V, 1.8V, 2.5V, 3.3V and 5V Busses and allows multiple LTC4315s to be cascaded. The LTC4315 n Prevents SDA and SCL Corruption During Live Board supports level translation between 1.5V, 1.8V, 2.5V, 3.3V Insertion and Removal from Backplane and 5V busses. n Stuck Bus Disconnect and Recovery During insertion, the SDA and SCL lines are precharged to n Compatible with I2C, I2C Fast Mode and SMBus 1V to minimize bus disturbances. Connection is established n ±4kV Human Body Model ESD Ruggedness between the input and output after ENABLE is asserted n High Impedance SDA, SCL pins When Unpowered high and a stop bit or bus idle condition has been detected n 12-Lead (4mm × 3mm) DFN and 12-Lead MSOP on the SDA and SCL pins. Packages If both data and clock are not simultaneously high at least once in 45ms and DISCEN is high, a FAULT signal APPLICATIONS is generated indicating a stuck bus low condition and the n Capacitance Buffers/Bus Extender input is disconnected from the output. Up to 16 clock n Live Board Insertion pulses are subsequently generated to free the stuck bus. n Telecommunications Systems Including ATCA A three state ACC pin enables input and output side rise n Level Translation time accelerators of various strengths. n PMBus L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their n Servers respective owners. Protected by U.S. patents, including 6356140, 6650174, 7032051, 7478286. TYPICAL APPLICATION 400kHz Operation 3.3V 5V RBUS_IN = 2.7kΩ, CBUS_IN = 50pF RBUS_OUT = 1.3kΩ, CBUS_OUT = 400pF, ACC = 0V 0.01μF 2.7k 2.7k VCC VCC2 10k 1.3k 1.3k 10k SCLOUT DISCEN DIV ENABLE 1V/ SCLIN LTC4315 READY READY SCL1 SCLIN SCLOUT SCL2 SDA1 SDAIN SDAOUT SDA2 500ns/DIV 4315 TA01b ACC FAULT FAULT GND 4315 TA01a 4315f 1

LTC4315 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltages V , V ...........................–0.3V to 6V Operating Ambient Temperature Range CC CC2 Input Voltages ACC, DISCEN, ENABLE .........–0.3V to 6V LTC4315C ................................................0°C to 70°C Input/Output Voltages SDAIN, SCLIN, SCLOUT, LTC4315I..............................................–40°C to 85°C SDAOUT .......................................................–0.3V to 6V Storage Temperature Range ..................–65°C to 150°C Output Voltages FAULT, READY ...................–0.3V to 6V Lead Temperature (Soldering, 10 sec) Output Sink Currents MSOP ...............................................................300°C FAULT, READY ...................................................50mA PIN CONFIGURATION TOP VIEW TOP VIEW ENABLE 1 12 VCC ENABLE 1 12 VCC DISCEN 2 11 VCC2 DISCEN 2 11 VCC2 SCLOUT 3 10 SDAOUT SCLOUT 3 10 SDAOUT 13 SCLIN 4 9 SDAIN SCLIN 4 9 SDAIN ACC 5 8 FAULT ACC 5 8 FAULT GND 6 7 READY GND 6 7 READY MS PACKAGE 12-LEAD PLASTIC MSOP DE PACKAGE TJMAX = 150°C, θJA = 135°C/W 12-LEAD (4mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 43°C/W EXPOSED PAD (PIN 13) PCB CONNECTION TO GND IS OPTIONAL ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4315CDE#PBF LTC4315CDE#TRPBF 4315 12-Lead (4mm × 3mm) DFN 0°C to 70°C LTC4315IDE#PBF LTC4315IDE#TRPBF 4315 12-Lead (4mm × 3mm) DFN –40°C to 85°C LTC4315CMS#PBF LTC4315CMS#TRPBF 4315 12-Lead Plastic MSOP 0°C to 70°C LTC4315IMS#PBF LTC4315IMS#TRPBF 4315 12-Lead Plastic MSOP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4315f 2

LTC4315 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = V = 3.3V unless otherwise noted. A CC CC2 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply/Start-Up V Input Supply Voltage l 2.9 5.5 V CC V 2-Wire Bus Supply Voltage (Note 3) l 1.4 5.5 V DD,BUS V Output Side Accelerator l 2.25 5.5 V CC2 Supply Voltage I Input Supply Current V = V = V = 5.5V, V = 0V (Note 4) l 6 8.1 10 mA CC ENABLE CC CC2 SDAIN,SCLIN I Input Supply Current V = 0V, V = V = 5.5V, V = 0V l 2.3 3.3 4.3 mA CC(DISABLED) ENABLE CC CC2 SDAIN,SCLIN I V Supply Current V = V = V = 5.5V, V = 0V (Note 4) l 0.2 0.31 0.4 mA CC2 CC2 ENABLE CC CC2 SDAIN,SCLIN I V Supply Current V = 0V, V = V = 5.5V, V = 0V l 0.15 0.25 0.35 mA CC2(DISABLED) CC2 ENABLE CC CC2 SDAIN,SCLIN V V UVLO Threshold V Rising l 2.55 2.7 2.85 V TH_UVLO CC CC V UVLO Threshold Hysteresis 200 mV CC_UVLO(HYST) Voltage V Precharge Voltage SDA, SCL Pins Open l 0.8 1 1.2 V PRE Buffers V Buffer Offset Voltage I = 4mA, Driven V = 50mV l 100 190 280 mV OS(SAT) OL SDA,SCL I = 500μA, Driven V = 50mV l 15 60 120 mV OL SDA,SCL V Buffer Offset Voltage I = 4mA, Driven V = 200mV l 50 120 180 mV OS OL SDA,SCL I = 500μA, Driven V = 200mV l 15 60 115 mV OL SDA,SCL V Buffer Input Logic Low (Notes 5 and 6) l 0.3 • V 0.33 • V 0.36 • V V IL(FALLING) MIN MIN MIN Voltage V V Hysteresis Voltage 50 mV IL(HYST) IL I Input Leakage Current SDA, SCL Pins = 5.5V, V = 5.5V, 0V l ±10 μA LEAK CC C Input Capacitance SDA, SCL Pins (Note 7) l 10 pF IN Rise Time Accelerators dV Minimum Slew Rate SDA, SCL Pins, V = V = 5V l 0.1 0.2 0.4 V/μs CC CC2 dt (RTA) Requirement V Rise Time Accelerator DC V = V = 5V (Note 5) l 0.38 • V 0.41 • V 0.44 • V V RTA(TH) CC CC2 MIN MIN MIN Threshold Voltage ΔV Buffers Off to Accelerator On SDA, SCL Pins, V = V = 5V (Note 5) l 0.05 • V 0.07 • V V ACC CC CC2 MIN MIN Voltage I Rise Time Accelerator Pull-Up SDA, SCL Pins RTA Current ACC Grounded, V = V = 5V (Note 8) l 15 25 40 mA CC CC2 ACC Open, V = V = 5V (Note 8) l 1.5 2.5 3.5 mA CC CC2 Enable/Control V ENABLE Threshold Voltage l 1 1.4 1.8 V EN(TH) V DISCEN Threshold Voltage l 1 1.4 1.8 V DISCEN(TH) I Input Leakage Current DISCEN, ENABLE Pins, V = 5.5V l 0.1 ±1 μA LEAK CC V ACC Input Low Threshold V = 5V l 0.2 • V 0.3 • V 0.4 • V V ACC(L,TH) CC CC CC CC Voltage V ACC Input High Threshold V = 5V l 0.7 • V 0.8 • V 0.9 • V V ACC(H,TH) CC CC CC CC Voltage I ACC High, Low Input Current V = V = 5V, V = 5V, 0V l ±23 ±40 μA ACC(IN,HL) CC CC2 ACC 4315f 3

LTC4315 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = V = 3.3V unless otherwise noted. A CC CC2 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I Allowable Leakage Current in V = V = 5V l ±5 μA ACC(IN, Z) CC CC2 the Open State V READY Output Low Voltage I = 3mA, V = 5V l 0.4 V READY(OL) READY CC I READY Off Leakage Current V = V = 5V l 0.1 ±5 μA READY(OH) CC READY Stuck Low Timeout Circuitry t Bus Stuck Low Timer SDAOUT or SCLOUT < 0.3 • V (Note 5) l 35 45 55 ms TIMEOUT MIN V FAULT Output Low voltage I = 3mA l 0.4 V FAULT(OL) FAULT I FAULT Off Leakage Current V = V = 5V l 0.1 ±5 μA FAULT(OH) CC FAULT I2C Interface Timing f I2C Frequency Max l 400 kHz SCL(MAX) t SCL, SDA Fall Delay V = V = V = 5V, C = 100pF, 130 250 ns PDHL CC CC2 DD(BUS) BUS R = 10kΩ (Note 7) BUS t SCL, SDA Fall Times V = V = V = 5V, C = 100pF, 20 300 ns f CC CC2 DD(BUS) BUS R = 10kΩ (Note 7) BUS t Bus Idle Time l 55 95 175 μs IDLE Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: V = minimum of V and V if V > 2.25V, otherwise MIN CC CC2 CC2 may cause permanent damage to the device. Exposure to any Absolute V = V . MIN CC Maximum Rating condition for extended periods may affect device Note 6: V is tested for the following (V , V ) combinations; IL CC CC2 reliability and lifetime. (2.9V, 5.5V), (5.5V, 2.25V), (3.3V, 3.3V) and (5V, 0V). Note 2: All currents into pins are positive and all voltages are referenced Note 7: Guaranteed by design and not tested. to GND unless otherwise indicated. Note 8: Measured in a special DC mode with V = V + 1V. SDA,SCL RTA(TH) Note 3: The LTC4315 can level translate bus voltages ranging from The transient I during rising edges, when ACC is LOW, will depend on RTA 2.25V to 5.5V. In special cases, it can also level translate down to 1.4V. the bus loading condition and the slew rate of the bus. The LTC4315’s See the Applications Information section for more details. internal slew rate control circuitry limits the maximum bus rise rate to Note 4: Test performed with SDA, SCL buffers active. 75V/μs by controlling the transient I . RTA 4315f 4

LTC4315 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, V = V = 3.3V unless otherwise noted. A CC CC2 I Enabled Current vs Supply I Disabled Current vs Supply I Enabled Current vs Supply CC CC CC2 Voltage Voltage Voltage 9.0 4.0 0.4 VSDAIN,SCLIN = 0V VSDAIN,SCLIN = 0V VSDAIN,SCLIN = 0V VENABLE = 5.5V VENABLE = 0V VENABLE = 5.5V 8.5 3.5 8.0 0.3 mA) mA) mA) I (CC 7.5 I (CC 3.0 I (CC2 7.0 0.2 2.5 6.5 6.0 2.0 0.1 2 2.5 3 3.5 4 4.5 5 5.5 6 2 2.5 3 3.5 4 4.5 5 5.5 6 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC (V) VCC (V) VCC (V) 4315 G01 4315 G02 4315 G03 V vs I Different Driven OS BUS Buffer DC I vs Temperature Voltage Levels I vs Temperature OL RTA 12 250 16 VCC = VCC2 = VDD,BUS 11 VSDA,SCL(cid:1)(cid:30)(cid:1)(cid:17)(cid:15)(cid:23)(cid:1)(cid:116)(cid:1)(cid:55)DD,BUS 200 14 CBUS = 400pF, RBUS = 10kΩ 10 VSDA,SCL = 0.6V DRIVEN VSDA,SCL = 50mV ACC = 0V 100mV 9 mA) mV) 150 mA) 12 I (OL 87 VSDA,SCL = 0.4V V (OS 100 ≥200mV I (RTA 10 5V 6 3.3V 50 8 5 4 0 6 –50 –25 0 25 50 75 100 0 1 2 3 4 5 –50 –25 0 25 50 75 100 TEMPERATURE (°C) IBUS (mA) TEMPERATURE (°C) 4315 G04 4315 G05 4315 G06 t (70% to 30%) vs t (50% to 50%) vs F PDHL Bus Capacitance Bus Capacitance Bus Rise Time (40% to 70%) vs C BUS 100 200 100 VCC = VCC2 = VDD,BUS VCC = VCC2 = VDD,BUS VCC = VCC2 = VDD,BUS RBUS = 10kΩ RBUS = 10kΩ ACC = 0V 5V 75 175 5V 5V 75 t (ns)F 50 3.3V t (ns)PDHL 150 3.3V t (ns)RISE 3.3V 50 25 125 0 100 25 0 200 400 600 800 1000 0 200 400 600 800 1000 0 200 400 600 800 CBUS (pF) CBUS (pF) CBUS (pF) 4315 G07 4315 G08 4315 G09 4315f 5

LTC4315 PIN FUNCTIONS ACC (Pin 5): Three-State Acceleration Strength Selector. READY (Pin 7): Connection Ready Status Output. This This pin controls the current strength of the rise time open drain N-channel MOSFET output pulls low when accelerators on both the input and output sides. Rise the input and output sides are disconnected. READY is time accelerators (RTAs) are disabled if ACC is high, pulled high when ENABLE is high and a connection has in current source mode if ACC is open and in the slew been established between the input and output. Connect limited switch mode if ACC is low. See Table 1 in the a pull-up resistor, typically 10k, from this pin to the bus Applications Information section. Grounding V selec- pull-up supply. Leave open or tie to GND if unused. CC2 tively disables the output side RTAs independent of the SCLIN (Pin 4): Serial Bus 1 Clock Input/Output. Connect ACC setting. this pin to the SCL line on the upstream bus. Connect an DISCEN (Pin 2): Enable Input to Disconnect Stuck Bus. external pull-up resistor or current source between this When this pin is high, stuck busses are automatically pin and the bus supply. The bus supply must be ≥ V CC disconnected after a timeout period of 45ms and FAULT if rise time accelerators are enabled. Do not leave open. is pulled low. Up to sixteen clock pulses are subsequently SCLOUT (Pin 3): Serial Bus 2 Clock Input/Output. Con- applied to SCLOUT. When DISCEN is low, stuck busses nect this pin to the SCL bus segment where stuck low are neither disconnected nor clocked but FAULT is pulled recovery is desired. Connect an external pull-up resistor low. Connect to GND if unused. or current source between this pin and the bus supply. ENABLE (Pin 1): Connection Enable Input. When driven The bus supply must be ≥ V if rise time accelerators CC2 low, the ENABLE pin isolates SDAIN and SCLIN from are enabled. Do not leave open. SDAOUT and SCLOUT, asserts READY low, disables rise SDAIN (Pin 9): Serial Bus 1 Data Input/Output. Connect time accelerators and inhibits automatic clock and stop bit this pin to the SDA line on the upstream bus. Connect an generation during a bus stuck low fault condition. When external pull-up resistor or current source between this pin driven high, the ENABLE pin connects SDAIN and SCLIN and the bus supply. The bus supply must be ≥ V if rise time CC to SDAOUT and SCLOUT after a stop bit or bus idle has accelerators are enabled. Do not leave open. been detected on both busses. Driving ENABLE high also enables automatic clock generation during a fault condition, SDAOUT (Pin 10): Serial Bus 2 Data Input/Output. Con- if DISCEN is tied high. During a fault condition, a rising nect this pin to the SDA bus segment where stuck low edge on the ENABLE pin forces a connection between recovery is desired. Connect an external pull-up resistor SDAIN and SDAOUT and SCLIN and SCLOUT. When using or current source between this pin and the bus supply. the LTC4315 in a Hot Swap™ application with staggered The bus supply must be ≥ VCC2 if rise time accelerators pins, connect a 10k resistor between ENABLE and GND are enabled. Do not leave open. to ensure correct functionality. Connect to V if unused. CC V (Pin 12): Power Supply Voltage. Power this pin from CC Exposed Pad (DE12 Package Only): Exposed pad may a supply between 2.9V and 5.5V. Bypass with at least be left open or connected to device GND. 0.01μF to GND. FAULT (Pin 8): Stuck Bus Fault Output. This open drain VCC2 (Pin 11): SDAOUT, SCLOUT Rise Time Accelerator N-channel MOSFET output pulls low if a simultaneous Power Supply Voltage. When powering VCC2, use a supply high on SCLOUT and SDAOUT does not occur in 45ms. In voltage ranging from 2.25V to 5.5V and bypass with at normal operation FAULT is high. Connect a pull-up resis- least 0.01μF to GND. Output side rise time accelerators are tor, typically 10k, from this pin to the bus pull-up supply. active if VCC2 ≥ 2.25V and ACC is low or open. Grounding Leave open or tie to GND if unused. VCC2 disables output side rise time accelerators indepen- dent of the state of ACC. GND (Pin 6): Device Ground. 4315f 6

LTC4315 BLOCK DIAGRAM VCC 200k 200k VCC2 PRECHARGE 200k 200k IRTA IRTA PRECHARGE PRECHARGE CONNECT CONNECT SCLIN SCLOUT VCC VCC2 SLEW RATE SLEW RATE DETECTOR DETECTOR IRTA 0.2V/μs 0.2V/μs IRTA CONNECT SDAIN SDAOUT SLEW RATE SLEW RATE DETECTOR DETECTOR 0.2V/μs 0.2V/μs RTA_SCLOUT_EN RTA_SCLIN_EN RTA_SDAIN_EN I2C Hot SwapTM I2C Hot Swap LOGIC LOGIC LOGIC + + VIL(cid:1)(cid:30)(cid:1)(cid:17)(cid:15)(cid:20)(cid:20)(cid:1)(cid:116)(cid:1)(cid:55)MIN – – VIL(cid:1)(cid:30)(cid:1)(cid:17)(cid:15)(cid:20)(cid:20)(cid:1)(cid:116)(cid:1)(cid:55)MIN 45ms TIMER + + VIL(cid:1)(cid:30)(cid:1)(cid:17)(cid:15)(cid:20)(cid:20)(cid:1)(cid:116)(cid:1)(cid:55)MIN – – VIL(cid:1)(cid:30)(cid:1)(cid:17)(cid:15)(cid:20)(cid:20)(cid:1)(cid:116)(cid:1)(cid:55)MIN DISCEN RTA_SDAOUT_EN ACC READY VCC2 UVLO 95μs CONNECT TIMER VCC + PRECHARGE 2.7V/2.5V – CONNECT FAULT ENABLE + 1.4V/1.3V – GND 4315 BD 4315f 7

LTC4315 OPERATION The Block Diagram shows the major functional blocks and data pins for 95μs after that transition. A stop bit or of the LTC4315. The LTC4315 is a high noise margin bus bus idle is required on both sides to reactivate the buffers buffer which provides capacitance buffering for I2C signals. and RTAs. The precharge circuit is not affected by V . CC2 Capacitance buffering is achieved by using back to back When a SDA/SCL pin is driven below the V level, the IL buffers on the clock and data channels, which isolate buffers are turned on and the logic low level is propagated the SDAIN and SCLIN capacitances from the SDAOUT though the LTC4315 to the other side. A high occurs when and SCLOUT capacitances respectively. All SDA and SCL all devices on the input and output sides release high. pins are fully bidirectional. The high noise margin allows Once the bus voltages rise above the V level, the buffers the LTC4315 to operate with non-compliant I2C devices IL are turned off. The RTAs are turned on at a slightly higher that drive a high V , permits a number of LTC4315s to OL voltage. The RTAs accelerate the rising edges of the SDA/ be connected in series and improves the reliability of I2C SCL inputs and outputs up to voltages of 0.9 • V and CC communications in large noisy systems. When enabled, 0.9 • V respectively, provided that the busses on their CC2 rise time accelerator (RTA) pull-up currents (I ) turn on RTA own are rising at a minimum rate of 0.4V/μs as determined during rising edges to reduce bus rise time. In a typical by internal slew rate detectors. ACC is a three-state input application, the input bus is pulled up to V and the CC that controls the RTA pull-up current strength I . RTA output bus is pulled up to V , although these are not CC2 requirements. V is the primary power supply to the The LTC4315 detects a bus stuck low (fault) condition CC LTC4315. V and V serve as the input and output side when both clock and data busses are not simultaneously CC CC2 rise time accelerator supplies respectively. Grounding V high at least once in 45ms. When a stuck bus occurs, the CC2 selectively disables the output side RTAs. LTC4315 asserts the FAULT flag. If DISCEN is tied high, the LTC4315 also disconnects the input and output sides and When the LTC4315 first receives power on its V pin, it CC after waiting at least 40μs, generates up to sixteen 5.5kHz starts out in an under voltage lockout mode (UVLO) until clock pulses on the SCLOUT pin and a stop bit to attempt its V exceeds 2.7V. The buffers and RTAs are disabled CC to free the stuck bus. Should the stuck bus release high and the LTC4315 ignores the logic state of its clock and during this period, clock generation is terminated and the data pins. During this time the precharge circuit forces a FAULT flag is cleared. nominal voltage of 1V on the SDA and SCL pins through 200k resistors. If DISCEN is tied low, a stuck bus event only causes FAULT flag assertion. Disconnection of the input and output sides Once the LTC4315 exits UVLO and its ENABLE pin has and clock generation are not done. Once the stuck bus been asserted high, it monitors the clock and data pins recovers and FAULT flag has been cleared, connection is for a stop bit or a bus idle condition. When a combination re-established between the input and output after a stop of either condition is detected simultaneously on the input bit or bus idle condition is detected. Toggling the ENABLE and output sides, the LTC4315 activates the connections pin after a fault condition has occurred forces a connec- between SDAIN and SDAOUT, and SCLIN and SCLOUT tion between the input and output. When powering into respectively, asserts READY high and deactivates the a stuck low condition, the input and output sides remain precharge circuit. If ACC is low or open, RTAs are also disconnected. After the timeout period, a stuck low fault enabled at this time. V transitions from a high to a low CC2 condition is detected and the behavior is as described or vice versa across a 1.8V threshold cause the LTC4315 previously. to disable the buffers and RTAs and to ignore the clock 4315f 8

LTC4315 APPLICATIONS INFORMATION The LTC4315 provides capacitance buffering, data and Figures 1 and 2 show the rising waveforms of heavily clock Hot Swap capability and level translation of I2C signals loaded SDAIN and SDAOUT busses with the ACC pin set for on its clock and data pins. The high noise margin of the strong mode and 2.5mA current source mode respectively. LTC4315 permits interoperability with I2C devices that drive In both figures, during a rising edge, the buffers are active a high V , permits series connection of multiple LTC4315s and the input and output sides connected, until the bus OL and provides improved I2C communication reliability. voltages on both the input and output sides are greater than The LTC4315 isolates backplane and card capacitances, 0.33 • V , where V is the lower of the V and V MIN MIN CC CC2 provides slew limited acceleration of rising edges and slew voltages. When each individual bus voltage rises above control of falling edges while level translating 1.5V, 1.8V, 0.41 • V , the RTA on that bus turns on. The effect of the MIN 2.5V, 3.3V and 5V busses. These features are illustrated acceleration strength is shown in the SDA waveforms in in the following subsections. Figures 1 and 2 for identical bus loads. The RTAs supply 10mA and 2.5mA of pull-up current I in the strong and RTA RISE TIME ACCELERATOR (RTA) PULL-UP CURRENT current source modes respectively for the bus conditions STRENGTH shown in Figures 1 and 2. For identical bus loads, the bus rises faster in Figure 1 compared to Figure 2 because of After an input to output connection has been established the higher I . the RTAs on both the input and output sides of the SDA RTA and SCL busses are activated based on the state of the ACC pin and the V supply voltage. During positive bus CC2 transitions of at least 0.4V/μs, the RTAs provide pull-up currents to reduce rise time. Enabling the RTAs allows SDAOUT users to choose larger bus pull-up resistors to reduce power consumption and improve logic low noise margins, to design with bus capacitances outside of the I2C speci- 2V/DIV SDAIN VCC = VCC2 = 5V RBUS = 20k fication and to operate at a higher clock frequency. The CIN = COUT = 200pF ACC = 0V function of the ACC pin in setting I is summarized in RTA 1μs/DIV 4315 F01 Table 1. In the strong mode (ACC low) the acceleration is Figure 1. Bus Rising Edge for the Strong Acceleration Mode. slew limited to a maximum bus rise rate of 75V/μs. The V = V = 5V CC CC2 strong mode current is therefore directly proportional to the bus capacitance. The LTC4315 is capable of sourcing up to 40mA of current in the strong mode. If ACC is left open, rise time acceleration is provided by a 2.5mA pull up. SDAOUT TABLE 1: ACC Control of the RTA Current I RTA ACC I RTA Low Strong 2V/DIV SDAIN VCC = VCC2 = 5V RBUS = 20k Hi-Z 2.5mA CIN = COUT = 200pF ACC = OPEN High None 1μs/DIV 4315 F02 Figure 2. Bus Rising Edge for the Current Source The ACC pin has a resistive divider between V and ground CC Acceleration Mode. V = V = 5V CC CC2 to set its voltage to 0.5 • V if left open. CC 4315f 9

LTC4315 APPLICATIONS INFORMATION If V is tied low, output RTAs are disabled independent of CC2 3.3V 2.5V the state of the ACC pin. Using a combination of the ACC pin and the V voltage, the input and output side RTAs can C1 R1 R2 R3 R4 R5 R6 C2 CC2 0.01μF 10k 10k VCC VCC2 10k 10k 10k 10k 0.01μF be controlled independently. The RTAs are also internally DISCEN disabled during power up, V transitions described in CC2 ENABLE the Operation section and during a bus stuck low event. LTC4315 READY READY The RTAs when activated pull the bus up to SCL1 SCLIN SCLOUT SCL2 0.9 • V and 0.9 • V on the input and output sides of SDA1 SDAIN SDAOUT SDA2 CC CC2 the SDA and SCL pins. Independent supply voltages V ACC FAULT FAULT CC GND and VCC2 maximize acceleration range on both inputs and 4315 F04 outputs by allowing the RTA turn-off voltage to be set inde- pendently on the two sides. In order to prevent bus overdrive by the RTA, the bus supplies on the input and output sides Figure 4. Level Shift Application Where the LTC4315 VCC and V Pins are Connected to the Bus Pull-Up Supply Voltages of the LTC4315 must be greater than or equal to 0.9 • V CC2 CC and 0.9 • V respectively. An example is shown in Figure 3 CC2 where the input bus voltage is greater than V . During a CC PULL-UP RESISTOR VALUE SELECTION rising edge, the input bus rise rate will be accelerated by the RTA up to a voltage of 2.97V after which the bus rise To guarantee that the RTAs are activated during a rising rate will reduce to a value that is determined by the bus edge, the bus must rise on its own with a positive slew current and bus capacitance. The RTA turn-off voltage is rate of at least 0.4V/μs. To achieve this, choose a maximum less than the bus supply and the bus is not over driven. RBUS using the formula: ( ) This can also be accomplished by tying V to the input CC V –V DD,BUS(MIN) RTA(TH) bus supply and VCC2 to the output bus supply as shown RBUS≤ (1) in Figure 4. In this case the input and output busses are V 0.4 (cid:129)C BUS accelerated to 2.97V and 2.25V respectively µs R is the bus pull-up resistor, V is the 5V 3.3V BUS DD,BUS(MIN) minimum bus pull-up supply voltage, V is the RTA(TH) R101k R102k VCC VCC2 R103k R104k R105k R106k C0.101μF maximum voltage at which the RTA turns on and CBUS is DISCEN the equivalent bus capacitance. RBUS must also be large ENABLE enough to guarantee that: LTC4315 ( ) READY READY V –0.4V SCL1 SCLIN SCLOUT SCL2 R ≥ DD,BUS(MAX) (2) SDA1 SDAIN SDAOUT SDA2 BUS 4mA ACC FAULT FAULT GND This criterion ensures that the maximum bus current is 4315 F03 less than 4mA. Figure 3. Level Shift Application Where the SDAIN, SCLIN Bus Pull-Up Supply Voltages are Higher Than the Supply Voltages of the LTC4315 4315f 10

LTC4315 APPLICATIONS INFORMATION INPUT TO OUTPUT OFFSET VOLTAGE STUCK BUS DISCONNECT AND RECOVERY While propagating a logic low voltage on its SDA and SCL During an output bus stuck low condition (SCLOUT or pins, the LTC4315 introduces a positive offset voltage SDAOUT stuck low for at least 45ms) if DISCEN is tied between the input and output. When a logic low voltage high, the LTC4315 attempts to unstick the bus by first ≥200mV is driven on any of the LTC4315’s data or clock breaking the connection between the input and output. The pins, the LTC4315 regulates the voltage on the oppo- LTC4315 then asserts FAULT low and after 40μs, gener- site side to a slightly higher value. This is illustrated in ates up to sixteen 5.5KHz clock pulses on the SCLOUT Equation 3, which uses SDA as an example: pin. Should the stuck bus release high during this period, clock generation is stopped, a stop bit is generated and the V =V +50mV+15Ω(cid:129)VDD,BUS (3) FAULT flag is cleared. This process is shown in Figure 5 SDAOUT SDAIN R for the case where SDAOUT starts out stuck low and then BUS recovers. As seen from the figure, the LTC4315 pulls FAULT In Equation 3, V is the output bus supply voltage and READY low and breaks the connection between the DD,BUS and R is the SDAOUT bus pull-up resistance. input and output sides, when a stuck low condition on BUS SDA is detected. Clock pulses are then issued on SCLOUT For driven logic low voltages < 200mV Equation 3 does to attempt to unstick the SDAOUT bus. When SDAOUT not apply as the saturation voltage of the open collector recovers, clock pulsing is stopped, a stop bit is generated output transistor results in a higher offset. However, for on the output and FAULT and READY are released high. If any input logic low below 220mV, the output is guaranteed DISCEN is low and a stuck bus event occurs, the FAULT to be below a V of 400mV for bus pull-up currents up OL flag is driven low but the input and output sides stay con- to 4mA. See the Typical Performance section for offset nected and no clocking or stop bit generation occurs. When variation as a function of the driven logic low voltage and powering up into a stuck low condition, a connection is bus pull-up current. never made between the input and the output, as a stop bit or bus idle condition is never detected. After a timeout FALLING EDGE CHARACTERISTICS period of 45ms, the FAULT flag is asserted low and the The LTC4315 introduces a propagation delay on falling behavior is the same as described previously. edges due to the finite response time and finite current sink capability of its buffers. In addition the LTC4315 also READY slew limits the falling edge to an edge rate of 45V/μs. 5V/DIV The slew limited falling edge eliminates fast transitions FAULT 5V/DIV on the busses and minimizes transmission line effects AUTOMATIC CLOCKING in systems. Refer to the Typical Performance section for SCLOUT the propagation delay and fall times as a function of the 5V/DIV RECOVERS bus capacitance. DISCONNECT HIGH SDAIN AT TIMEOUT 5V/DIV SDAOUT STOP BIT DRIVEN 5V/DIV STUCK LOW > 45ms GENERATED LOW 1ms/DIV 4315 F05 Figure 5. Bus Waveforms During SDAOUT Stuck Low and Recovery Event 4315f 11

LTC4315 APPLICATIONS INFORMATION LIVE INSERTION, CAPACITANCE BUFFERING AND directly add together, making rise time requirements dif- LEVEL TRANSLATION APPLICATION ficult to meet. Placing an LTC4315 on the edge of each card isolates the card capacitance from the backplane. Figures 6 illustrates an application of the LTC4315 that For a given I/O card, the LTC4315 drives the capacitance takes advantage of the LTC4315’s Hot Swap, capacitance of everything on the card and devices on the backplane buffering and level translation features. If the I/O cards must drive only the small capacitance of the LTC4315 were plugged directly into the backplane without LTC4315 which is <10pF. buffers, all of the backplane and card capacitances would BACKPLANE CARD CONNECTOR CONNECTOR I/O PERIPHERAL CARD 1 5V C1 3.3V 0.01μF VCC VCC2 R5 R6 R1 R2 R3 R4 DISCEN 10k 10k 10k 10k 10k 10k C2 ACC 0.01μF LTC4315 READY READY FAULT FAULT SCLOUT CARD 1_SCL SCL SCLIN SDAOUT CARD 1_SDA SDA SDAIN ENABLE 1 ENABLE R7 GND 10k I/O PERIPHERAL CARD N (cid:115)(cid:0)(cid:0)(cid:0)(cid:115)(cid:0)(cid:0)(cid:0)(cid:115) C3 (cid:115)(cid:0)(cid:0)(cid:0)(cid:115)(cid:0)(cid:0)(cid:0)(cid:115) VCC VCC2 0.01μF R8 R9 DISCEN 10k 10k C4 ACC 0.01μF LTC4315 READY FAULT SCLOUT CARD N_SCL SCLIN SDAOUT CARD N_SDA SDAIN ENABLE N ENABLE R10 GND 10k 4315 F06 Figure 6. LTC4315 in an I2C Hot Swap Application with a Staggered Connector 4315f 12

LTC4315 APPLICATIONS INFORMATION In Figure 6, a staggered connector is used to connect the in order to meet the V = 0.7 • V requirement and IH DD,BUS LTC4315 to the backplane. V and GND are the longest not impact the logic high noise margin. Voltage level CC pins to ensure that the LTC4315 is powered and forcing translation down to 1.4V is allowed, but the logic high a 1V precharge voltage on the medium length SDA and noise margin will be lowered. An example of voltage level SCL pins before they contact the backplane. The 1V pre- translation from 3.3V to 1.8V is illustrated in Figure 7, charge voltage is applied to the SDA and SCL pins through where a 3.3V input voltage bus is translated to a 1.8V 200k resistors. Since cards are being plugged into a live output voltage bus. Tying V to 3.3V satisfies Equation 4. CC backplane whose SDA and SCL busses could be at any Grounding V disables the output RTAs. V defaults CC2 MIN voltage between 0 and V , precharging the LTC4315’s to V under these conditions, making the buffer turn-off CC CC SDA and SCL pins to 1V minimizes disturbances to the voltage 1.089V. A similar voltage translation can also be backplane bus when cards are being plugged in. The low performed going from a 3.3V bus supply on the output (<10pF) input capacitance of the LTC4315 also contributes side to a 1.8V bus supply on the input side if ACC is tied to minimizing bus disturbance as cards are being plugged high to disable the input RTAs and if V and V are CC CC2 in. With ENABLE being the shortest pin and also pulled to tied to the 3.3V bus supply. GND by a resistor, the staggered approach provides ad- ditional time for transients associated with live insertion to 3.3V 1.8V settle before the LTC4315 can be enabled. A 10k or lower pull-down resistor from ENABLE to GND is recommended. C1 R1 R2 R3 R4 R5 R6 0.01μF 10k 10k VCC VCC2 10k 10k 10k 10k If a connector is used where all pins are of equal length, DISCEN the benefit of the precharge circuit is lost. Also, the ENABLE ENABLE signal to the LTC4315 must be held low until all LTC4315 transients associated with the plugging in of a card into READY READY a live system die out. SCL1 SCLIN SCLOUT SCL2 SDA1 SDAIN SDAOUT SDA2 ACC FAULT FAULT LEVEL TRANSLATING TO VOLTAGES <2.25V GND 4315 F07 The LTC4315 can be used for level translation to bus volt- ages below 2.25V if certain conditions are met. In order to perform this level translation, RTAs on the low voltage Figure 7. Voltage Level Translation from 3.3V to 1.8V Using side need to be disabled in order to prevent an overdrive the LTC4315 of the low voltage bus. Since the maximum buffer turn-on and turn-off voltages are 0.36 • V , the minimum bus MIN supply voltage is determined by the following equation, 0.36(cid:129)V V ≥ MIN (4) DD,BUS(MIN) 0.7 4315f 13

LTC4315 APPLICATIONS INFORMATION TELECOMMUNICATIONS SYSTEMS being hot swapped. In Figure 8, the RTA of the LTC4315 on the shelf manager supplies 2.5mA of pull-up current, The LTC4315 has several features that make it an excel- allowing the 1μs rise time requirement to be met on the lent choice for use in telecommunications systems such heavily loaded backplane for loads well beyond the 690pF as ATCA. Referring to Figures 8 and 9, buffers are used maximum specification. The 0.33 • V turn-off voltage on the edges of the field replaceable units (FRUs) and MIN of the LTC4315’s buffers provides a large logic low noise shelf managers to shield devices on these cards from the margin in these systems. large backplane capacitance. The input capacitance of the LTC4315 is less than the 10pF maximum specification for In the bused ATCA application shown in Figure 8, the buffers used in bussed ATCA applications. The LTC4315 LTC4315s located on the shelf managers #1 and #2 and on buffers can drive capacitances >1nF, which is greater than the FRUs, drive the large backplane capacitance while the the maximum backplane capacitance of 690pF in bused microcontrollers on the shelf managers and the I2C slave ATCA systems. The precharge feature, the low input devices on the FRUs drive the small input capacitance of the capacitance of the LTC4315 and the high impedance of LTC4315. The LTC4315 on only one of the shelf managers the SDA and SCL pins of the LTC4315 when it is unpow- is enabled at any given time. The hot insertion logic on ered, minimize disturbances to the bus when cards are the LTC4315 allows the FRUs to be plugged or unplugged FRU #1 SHELF MANAGER #1 BACKPLANE 3.3V 3.3V R101k VCC VCC2 R2.27k IPSMCBL-A VCCLTC431V5CC2 R103k R104k SCLIN SCLOUT SCLIN SCLOUT μP LTC4315 3.3V ACC ENABLE 3.3V I2C ACC IPMB-B DEVICE IPMB-B DETAILS (NOT SHOWN) ARE IDENTICAL TO IPMB-A VCC VCC2 LTC4315 SCLIN SCLOUT 3.3V ACC FRU #N (cid:115)(cid:0)(cid:0)(cid:0)(cid:115)(cid:0)(cid:0)(cid:0)(cid:115) 3.3V VCC VCC2 R5 R6 LTC4315 10k 10k IPMB-A SCLIN SCLOUT 3.3V ACC 3.3V I2C SHELF MANAGER #2 DEVICE IDENTICAL TO SHELF MANAGER #1 VCC VCC2 IPMB-B LTC4315 SCL IPMB-B SCLIN SCLOUT 3.3V ACC 4315 F08 Figure 8. LTC4315s Used in a Bused ATCA Application. Only the Clock Path Is Shown for Simplicity. 4315f 14

LTC4315 APPLICATIONS INFORMATION from a live backplane. The features mentioned previously Cascading and Interoperability with Other LTC Buffers provide noise immunity and allow timing specifications to and Non-Compliant I2C Devices be met for a wide range of backplane loading conditions. Multiple LTC4315s can be cascaded or the LTC4315 can be In the 6 × 4 radial configuration shown in Figure 9, the cascaded with other LTC bus buffers. Cascades often exist LTC4314s on the shelf managers and the LTC4315s on in large I2C systems, where multiple I/O cards having bus the FRUs drive the large backplane capacitance while the buffers connect to a common backplane bus. Two issues I2C slave devices on the FRUs only drive the small input need to be considered when using such cascades—the capacitance of the LTC4315. The LTC4314s on only one additive nature of the buffer logic low offset voltages and the of the shelf managers are enabled at a given time. All the impact of the RTA-buffer interaction on the noise margin. benefits provided by the LTC4315 in Figure 8 apply to Figure 9 as well. FRU #1 3.3V SHELF MANAGER #1 BACKPLANE 3.3V R1 10k VCC VCC2 R2 VCC VCC2 R3 R4 LTC4314#1 10k IPMB-A LTC4315 10k 10k SCL1 SCLIN SCLOUT1 SCLIN SCLOUT ENABLE1A ENABLE1 SCLOUT2 3.3V ACC μP ENABLE2A ENABLE2 SCLOUT3 3.3V I2C ENABLE3A ENABLE3 SCLOUT4 DEVICE ENABLE4A ENABLE4 3.3V ACC VCC VCC2 IPMB-B LTC4315 3.3V (cid:115)(cid:0)(cid:0)(cid:0)(cid:115)(cid:0)(cid:0)(cid:0)(cid:115) SCL1 3.3V SACCLCIN SCLOUT VCC VCC2 R5 (cid:115)(cid:0)(cid:0)(cid:0)(cid:115)(cid:0)(cid:0)(cid:0)(cid:115) FRU #24 (cid:115)(cid:0)(cid:0)(cid:0)(cid:115)(cid:0)(cid:0)(cid:0)(cid:115) LTC4314#6 10k SCLIN 3.3V ENABLE21A ENABLE1 SCLOUT1 ENABLE22A ENABLE2 SCLOUT2 VCC VCC2 R6 R7 IPMB-A ENABLE23A ENABLE3 SCLOUT3 SCL24 LTC4315 10k 10k ENABLE24A ENABLE4 SCLOUT4 SCLIN SCLOUT 3.3V ACC SCL1 3.3V ACC IPMB-B DETAILS (NOT SHOWN) ARE IDENTICAL TO IPMB-A IPMB-B (cid:115)(cid:0)(cid:0)(cid:0)(cid:115)(cid:0)(cid:0)(cid:0)(cid:115) 3.3V DEIV2CICE SCL24 VCC VCC2 IPMB-B LTC4315 IPMB-A(X24) SCL24 SCLIN SCLOUT SHELF MANAGER #2 SCL1 3.3V ACC IDENTICAL TO SHELF MANAGER #1 IPMB-B(X24) (cid:115)(cid:0)(cid:0)(cid:0)(cid:115)(cid:0)(cid:0)(cid:0)(cid:115) 4315 F09 SCL24 Figure 9. LTC4315s Used in a Radially Connected Telecommunications System in a 6 × 4 Arrangement. Only the Clock Path Is Shown for Simplicity. The Data Pathway Is Identical. 4315f 15

LTC4315 APPLICATIONS INFORMATION First, when two or more buffers are connected in a cas- Figure 10 shows the LTC4315 operating on a bus shared cade configuration, if the sum of the offsets across the with LTC4300A and LTC4307 buffers. The correspond- cascade (refer to Equation 3 and the data sheets of the ing SCL waveforms are shown in Figure 11. The RTAs corresponding buffers) plus the worst-case driven logic on the LTC4300A and the LTC4307 cannot be disabled. low voltage exceeds the minimum buffer turn-off voltage, The backplane in Figure 11 has five I/O cards connected signals will not be propagated across the cascade. The to it. Each I/O card has a LTC bus buffer on its outside maximum driven logic low voltage must be set accord- edge for SDA/SCL hot swap onto the backplane. In this ingly, for correct operation in such cascades. Second, noise margin is affected by cascading the LTC4315 LTC4300A/ with buffers whose RTA turn-on voltage is lower than the LTC4307 SCL3 RTAs LTC4315 buffer turn-off voltage. The VIL for the LTC4315 2V/DIV TURN ON is set to 0.3 • V to achieve high noise margin provided MIN that the LTC4315 buffers do not contend with RTAs of LTC4315 other products. To maximize logic low noise margin, SCL2 BUFFERS 2V/DIV TURN OFF disable the RTAs of the other LTC buffers if possible and use the RTAs of the LTC4315 in cascading applications. LTC4315 To permit interoperability with other LTC buffers whose SCL1 RTA 2V/DIV TURNS ON RTAs cannot be disabled, the LTC4315 senses the RTA 1μs/DIV 4315 F11 current and turns off its buffers below 0.3 • V . This MIN eliminates contention between the LTC4315 buffers and Figure 11. Corresponding SCL Switching Waveforms. No Glitches other RTAs, making the SDA/SCL waveforms monotonic. Are Seen. I/O CARD #1 I/O CARD #2 TO #4 5V 3.3V C1 0.01μF R5k1 VCC VCC2 R2.27k VCC R2.37k LTC4315 LTC4300A SCL2 SCL1 SCLIN SCLOUT SCLIN SCLOUT SCL3 GND ACC *CB2 GND 690pF CB1 100pF I/O CARD #5 *PARASITIC BACKPLANE CAPACITANCE VCC R4 5k LTC4307 SCLIN SCLOUT SCL4 GND BACKPLANE 4315 F10 Figure 10. The LTC4315 Operating in a Cascade with Other LTC Buffers with Active RTAs. Only the Clock Pathway Is Shown for Simplicity 4315f 16

LTC4315 APPLICATIONS INFORMATION example, there are three LTC4300As, one LTC4307 and 1000 one LTC4315. The SCL1 bus is driven by an I2C master (master not shown). When the SCL2 voltage crosses 0.6V and 0.8V, the RTAs on the LTC4300A and LTC4307 turn on respectively and source current into SCL2. The F) p LTC4315 detects this and turns off its buffers, releasing (US 100 M = 1 B SCL1 and SCL2 high. Contention between the LTC4315 C buffers and the LTC4300A and LTC4307 RTAs is prevented M = 2 and the SCL1, SCL2 and SCL3 waveforms in Figure 11 are M = 3 monotonic. The logic low noise margin is reduced because 10 the LTC4315 buffers turn off when the SCL1 voltage is 0 2 4 6 8 10 approximately 0.6V. RBUS (kΩ) 4315 F12 Generally, noise margin will be reduced if other RTAs Figure 12. Recommended Maximum R1 and CB1 Values for the turn on at a voltage less than 0.3 • V . The reduction MIN LTC4315 Operating with Multiple LTC4300As in a 3.3V System. in noise margin is a function of the number of LTC4315s and the number and turn-on voltage of other RTAs, whose current must be sunk by the LTC4315 buffers. The same 10000 arguments apply for non-LTC buffer products whose RTA turn-on voltage is less than 0.3 • V . MIN Interoperability is improved by reducing the interaction time between the LTC4315 buffers and other RTAs by reducing F) p R1 and CB1. The following guidelines are recommended (US1000 B C for single supply systems, M = 1 a. For 5V systems choose R1 < 20k and CB1 < 1nF. There are no other constraints. 100 b. For 3.3V systems, refer to Figures 12 and 13 for opera- 0 2 4 6 8 10 tion with LTC4300As and LTC4307s. In the figures: RBUS (kΩ) 4315 F13 Number of LTC4300As or LTC4307s M= Figure 13. Recommended Maximum R1 and CB1 Values for the Number of LTC4315s LTC4315 Operating with Multiple LTC4307s in a 3.3V System. R1 and CB1 must be chosen to be below the curves for a specific value of M. For M greater than the values shown in the figures, non-idealities do not result. R1 < 20k and CB1 <1nF are still recommended. 4315f 17

LTC4315 APPLICATIONS INFORMATION The LTC4315 is interoperable with non-compliant I2C Repeater Application devices that drive a high V > 0.4V. Figure 14 shows the OL Multiple LTC4315s can be cascaded in a repeater applica- LTC4315 in an application where a microcontroller com- tion where a large 2-wire system is broken into smaller municates through the LTC4315 with a non-compliant I2C sections as shown in Figure 15. The high noise margin device that drives a V of 0.6V. The LTC4313 buffers are OL and low offset of the LTC4315 allows multiple devices active up to a bus voltage of 0.3 • V which is 1.089V in MIN to be cascaded while still providing good system level this case, yielding a noise margin of 0.489V. noise margin. In the repeater circuit shown in Figure 15, if SCL1/SDA1 is driven externally to 200mV, SCL2/SDA2 3.3V 5V is regulated to ~440mV worst-case by the cascade of C1 0.01μF R101k R102k R103k R104k VCC VCC2 R105k R106k LTC4315s. The buffer turn-off voltage is 1.089V yielding LTC4315 a minimum logic low noise margin of ~650mV. In Figure DISCEN 15, use of RTAs combined with an increased level of ENABLE FAULT buffering reduces transition times and permits operation μP READY at a higher frequency. SCLIN SCLOUT SDAIN SDAOUT ACC NON-COMPLIANT GND I2C DEVICE 4315 F14 VOL = 0.6V Figure 14. Communication with a Non-Compliant I2C Device Using the LTC4315. 3.3V C1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 0.01μF 10k 10k VCC VCC2 10k 10k VCC VCC2 10k 10k VCC VCC2 10k 10k 10k 10k DISCEN DISCEN DISCEN ENABLE READY ENABLE READY ENABLE READY READY LTC4315 LTC4315 LTC4315 SCL1 SCLIN SCLOUT SCLIN SCLOUT SCLIN SCLOUT SCL2 SDA1 SDAIN SDAOUT SDAIN SDAOUT SDAIN SDAOUT SDA2 ACC FAULT ACC FAULT ACC FAULT FAULT GND GND GND 4315 F15 Figure 15. LTC4315s in a Repeater Application 4315f 18

LTC4315 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 12-Lead Plastic MSOP (Reference LTC DWG # 05-08-1668 Rev Ø) 4.039 ± 0.102 (.159 ± .004) 0(..808395 ±± 0.0.10257) (NOTE 3) 0.406 ± 0.076 1211109 87 (.016 ± .003) REF (5.M2.20IN36) (3.1.2206 –– 3.1.4356) (0.0.21504) DETAIL “A0”° – 6° TYP (4.1.9903 ± ± 0.0.10562) (3.1.(01N08O ± ±T E0 . .0410)042) GAUGE PLANE 0.53 ± 0.152 0.42 ± 0.038 0.65 (.021 ± .006) 1.10 1 2 3 4 5 6 0.86 (.0165 ± .0015) (.0256) (.043) (.034) TYP BSC DETAIL “A” MAX REF RECOMMENDED SOLDER PAD LAYOUT 0.18 SEATING (.007) PLANE 0.22 – 0.38 0.1016 ± 0.0508 NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) (.009T Y– P.015) 0.650 (.004 ± .002) 2. DRAWING NOT TO SCALE (.0256) MSOP (MS12) 1107 REV Ø 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. BSC MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX DE/UE Package 12-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1695 Rev D) 4.00 ±0.10 R = 0.115 0.40 ± 0.10 (2 SIDES) TYP 7 12 0.70 ±0.05 R = 0.05 TYP 3.30 ±0.05 3.30 ±0.10 3.60 ±0.05 3.00 ±0.10 2.20 ±0.05 1.70 ± 0.05 (2 SIDES) 1.70 ± 0.10 PIN 1 PIN 1 NOTCH TOP MARK R = 0.20 OR PACKAGE (NOTE 6) 0.35 × 45° OUTLINE CHAMFER 6 1 (UE12/DE12) DFN 0806 REV D 0.25 ± 0.05 0.200 REF 0.75 ±0.05 0.25 ± 0.05 0.50 BSC 0.50 BSC 2.50 REF 2.50 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED NOTE: 1. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4315f 19 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC4315 TYPICAL APPLICATION Cascaded Application with Level Shifting and Operation with a Non-Compliant I2C Device. 2.5V 3.3V 5V R1 R2 R3 R4 C1 R5 R6 10k 10k VCC VCC2 10k 10k 0.01μF VCC VCC2 10k 10k DISCEN DISCEN ENABLE READY ENABLE READY LTC4315 LTC4315 SCL1 SCLIN SCLOUT SCLIN SCLOUT SCL2 SDA1 SDAIN SDAOUT SDAIN SDAOUT SDA2 ACC FAULT BACKPLANE OR ACC FAULT GND LONG CABLE RUN GND NON-COMPLIANT I2C DEVICE VOL = 0.6V 4315 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC4300A-1/ Hot-Swappable 2-Wire Bus Buffers -1: Bus Buffer with READY and ENABLE LTC4300A-2/ -2: Dual Supply Buffer with ACC LTC4300A-3 -3: Dual Supply Buffer and ENABLE LTC4302-1/ Addressable 2-Wire Bus Buffer Address Expansion, GPIO, Software Controlled LTC4302-2 LTC4303/ Hot-Swappable 2-Wire Bus Buffer with Provides Automatic Clocking to Free Stuck I2C Busses LTC4304 Stuck Bus Recovery LTC4305/ 2- or 4-Channel, 2 Wire Bus Two or Four Software Selectable Downstream Busses, Stuck Bus Disconnect, Rise Time LTC4306 Multiplexers with Capacitance Buffering Accelerators, Fault Reporting, ±10kV HBM ESD LTC4307 Low Offset Hot-Swappable 2-Wire Bus 60mV Bus Offset, 30ms Stuck Bus Disconnect and Recovery, Rise Time Accelerators, ±5kV Buffer with Stuck Bus Recovery HBM ESD LTC4307-1 High Definition Multimedia Interface 60mV Buffer Offset, 3.3V to 5V Level Shifting, ±5kV HBM ESD (HDMI) Level Shifting 2-Wire Bus Buffer LTC4308 Low Voltage, Level Shifting Bus Buffer with 1V Precharge, ENABLE and READY, 0.9V to 5.5V Level Translation, 30ms Hot-Swappable 2-Wire Bus Buffer with Stuck Bus Disconnect and Recovery, Output Side Rise Time Accelerators, ±6kV HBM ESD Stuck Bus Recovery LTC4309 Low Offset Hot-Swappable 2-Wire Bus 60mV Buffer Offset, 30ms Stuck Bus Disconnect and Recovery, Rise Time Accelerators, ±5kV Buffer with Stuck Bus Recovery HBM ESD, 1.8V to 5.5V Level Translation LTC4310-1/ Hot-Swappable I2C Isolators Bidirectional I2C Communication Between Two Isolated Busses, LTC4310-1: 100kHz Bus, LTC4310-2 LTC4310-2: 400kHz Bus LTC4311 Low Voltage I2C/SMBus Accelerator Rise Time Acceleration with ENABLE, ±8kV HBM ESD LTC4312/ 2- or 4-Channel, Hardware Selectable 2 Two or Four Pin Selectable Downstream Busses, V Up to 0.3 • V , Stuck Bus Disconnect, IL CC LTC4314 Wire Bus Multiplexers with Capacitance Rise Time Accelerators, 45ms Stuck Bus Disconnect and Recovery, ±4kV HBM ESD Buffering LTC4313-1/ High Noise Margin 2-Wire Bus Buffers V = 0.3 • V , Rise Time Accelerators, Stuck Bus Disconnect, 1V Precharge, ±4kV HBM ESD IL CC LTC4313-2/ LTC4313-3 4315f 20 Linear Technology Corporation LT 1011 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2011