LTC4290/LTC4271 8-Port PoE/PoE+/LTPoE++ PSE Controller FEATURES DESCRIPTION n Eight Independent PSE Channels The LTC®4290/LTC4271 chipset is an 8-port power sourc- n Compliant with IEEE 802.3at Type 1 and 2 ing equipment (PSE) controller designed for use in IEEE n Chipset Provides Electrical Isolation 802.3at Type 1 and Type 2 (high power) compliant Power n Reduced BOM Cost over Ethernet (PoE) systems. Transformer-isolated com- n Eliminates up to 6 High Speed Opto-Couplers munication protocol replaces expensive opto-couplers n Eliminates Isolated 3.3V Power Supply and complex isolated 3.3V supply resulting in significant n Low Power Dissipation BOM cost savings. The LTC4290/LTC4271 chipset delivers n 0.25Ω Sense Resistance Per Channel lowest-in-industry heat dissipation by utilizing low-R DS(ON) n Very High Reliability 4-Point PD Detection external MOSFETs and 0.25Ω sense resistors. n 2-Point Forced Voltage Advanced power management features include per-port n 2-Point Forced Current 12-bit current monitoring ADCs, DAC-programmable cur- n V and V Monitoring EE PORT rent limit, and versatile fast shut-down of preselected ports. n 1 Second Rolling I Averaging PORT Advanced power management host software is available n Supports 2-Pair and 4-Pair Output Power under a no-cost license. PD discovery uses a proprietary n 1MHz I2C Compatible Serial Control Interface dual-mode 4-point detection mechanism ensuring excel- n Available In Three Power Grades lent immunity from false PD detection. Midspan PSEs n A-Grade – LTPoE++™ 38.7W to 90W are supported with 2-event classification and a 2 second n B-Grade – PoE+ 25.5W backoff timer. The LTC4290/LTC4271 includes an I2C n C-Grade – PoE 13W serial interface operable up to 1MHz. n Available In a 40-Lead 6mm × 6mm (LTC4290) and 24-Lead 4mm × 4mm (LTC4271) QFN Package The LTC4290/LTC4271 is available in multiple power grades allowing delivered PD power up to 90W. APPLICATIONS L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks n PoE PSE Switches/Routers and LTPoE++ is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. n PoE PSE Midspans TYPICAL APPLICATION 3.3V 0.1µF GP0 VDD33 XIO0 XIO1 0.22µF LTC4290/LTC4271 FAMILY GP1 100V S1B NROEQ IUSOIRLEADT IOONN MID CPD CPA OUTn PORTn MAX I2C INTERFACE RESET 100Ω(cid:127) (cid:127) 100Ω LTC4290 DELIVERED MAUSTDO 3.3V –54V GATEn S1B GRADE ISOLATION LTPoE++ PoE+ PoE POWER INT CND 100Ω 100Ω CNA SENSEn 0.25Ω –54V A Transformer l l l 90W SSCDLAIN LTC4271 DPD DPA LTC4290 01.0202VµF S1B B Transformer l l 25.5W SDAOUT 100Ω(cid:127) (cid:127) 100Ω OUT1 PORT1 C Transformer l 13W 3.3V –54V AD0 AAADDD123 DND 100Ω 10Ω 100Ω DNA SEGNASTEE11 0.25Ω S1–B54V AD6 DGND CAP1 AGND CAP2 VEE VSSK 1µF 0.1µF + 2nF 2kV 1µF >47µF SYSTEM BULK CAP –54V –54V 429071 TA01a 429071fb 1 For more information www.linear.com/LTC4290

LTC4290/LTC4271 ABSOLUTE MAXIMUM RATINGS (Notes 1, 4) (Note 1) LTC4290 LTC4271 Supply Voltages Supply Voltages AGND – V ...........................................–0.3V to 80V V – DGND .........................................–0.3V to 3.6V EE DD VSSK (Note 7) .....................V – 0.3V to V + 0.3V Digital Pins EE EE Digital Pins SCL, SDAIN, SDAOUT, INT, RESET, MSD, ADn, AUTO, XIOn .................................V – 0.3V to CAP2 + 0.3V MID, GPn ........................DGND – 0.3V to V + 0.3V EE DD Analog Pins Analog Pins SENSEn, GATEn, OUTn ........V – 0.3V to V + 80V CAP1 (Note 13) ...........................–0.3V to DGND + 2V EE EE CAP2 (Note 13) .......................V –0.3V to V + 5V CPD, CND, DPD, DND ......DGND – 0.3V to V + 0.3V EE EE DD CPA, CNA, DPA, DNA ..............V – 0.3V to V + 0.3 Operating Ambient Temperature Range EE EE Operating Ambient Temperature Range LTC4271I..............................................–40°C to 85°C LTC4290I .............................................–40°C to 85°C Junction Temperature (Note 2) ............................ 125°C Junction Temperature (Note 2) ............................ 125°C Storage Temperature Range ..................–65°C to 150°C Storage Temperature Range ..................–65°C to 150°C 429071fb 2 For more information www.linear.com/LTC4290

LTC4290/LTC4271 PIN CONFIGURATION LTC4290 LTC4271 TOP VIEW TOP VIEW VEE CPA CNA DPA DNA NC NC VEE NC NC VEE 1 40 39 38 37 36 35 34 33 32 31 30 VEE MSD GP0 GP1 AUTO VDD33 CAP1 24 23 22 21 20 19 GATE1 2 29 GATE8 AD0 1 18 SCL OUT1 3 28 OUT8 AD1 2 17 SDAIN GATE2 4 27 GATE7 OUT2 5 41 26 OUT7 AD2 3 25 16 SDAOUT CAP2 6 VSSK 25 AGND AD3 4 DGND 15 INT AD6 5 14 RESET GATE3 7 24 GATE6 MID 6 13 DNC OUT3 8 23 OUT6 GATE4 9 22 GATE5 7 8 9 10 11 12 OUT4 10 11 12 13 14 15 16 17 18 19 20 21 OUT5 NC CPD CND DPD DND VDD33 0 1 2 3 4 5 6 7 8 1 O E E E E E E E E O XI NS NS NS NS NS NS NS NS XI UF PACKAGE E E E E E E E E S S S S S S S S 24-LEAD (4mm × 4mm) PLASTIC QFN UJ PACKAGE TJMAX = 125°C, θJC = 4°C/W 40-LEAD (6mm × 6mm) PLASTIC QFN EXPOSED PAD (PIN 25) IS DGND, MUST BE SOLDERED TO PCB TJMAX = 125°C, θJC = 2°C/W EXPOSED PAD (PIN 41) IS VSSK, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION MAX PWR TEMPERATURE RANGE LTC4271IUF#PBF LTC4271IUF#TRPBF 4271 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C LTC4290AIUJ#PBF LTC4290AIUJ#TRPBF LTC4290AUJ 40-Lead (6mm × 6mm) Plastic QFN 90W –40°C to 85°C LTC4290BIUJ#PBF LTC4290BIUJ#TRPBF LTC4290BUJ 40-Lead (6mm × 6mm) Plastic QFN 25.5W –40°C to 85°C LTC4290CIUJ#PBF LTC4290CIUJ#TRPBF LTC4290CUJ 40-Lead (6mm × 6mm) Plastic QFN 13W –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 429071fb 3 For more information www.linear.com/LTC4290

LTC4290/LTC4271 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. AGND – V = 54V and V – DGND = 3.3V unless otherwise noted. A EE DD (Notes 3 & 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Main PoE Supply Voltage AGND – V EE EE For IEEE Type 1 Compliant Output l 45 57 V l For IEEE Type 2 Compliant Output 51 57 V l For LTPoE++ Compliant Output 54.75 57 V Undervoltage Lock-Out AGND – V l 20 25 30 V EE V V Supply Voltage V – DGND l 3.0 3.3 3.6 V DD DD DD Undervoltage Lock-Out V – DGND 2.7 V DD V Internal Regulator Supply Voltage V – DGND 1.84 V CAP1 CAP1 V Internal Regulator Supply Voltage V – V 4.3 V CAP2 CAP2 EE I V Supply Current (AGND – V ) = 55V l 9 15 mA EE EE EE R V Supply Resistance V < 15V l 12 kΩ EE EE EE I V Supply Current (V – DGND) = 3.3V l 10 15 mA DD DD DD Detection Detection Current – Forced Current First Point, AGND – V = 9V l 220 240 260 µA OUTn Second Point, AGND – V = 3.5V l 143 160 180 µA OUTn Detection Voltage – Forced Voltage AGND – V , 5µA ≤ I ≤ 500µA OUTn OUTn First Point l 7 8 9 V Second Point l 3 4 5 V Detection Current Compliance AGND – V = 0V l 0.8 0.9 mA OUTn V Detection Voltage Compliance AGND – V , Open Port l 10.4 12 V OC OUTn Detection Voltage Slew Rate AGND – V , C = 0.15µF l 0.01 V/µs OUTn PORT Min. Valid Signature Resistance l 15.5 17 18.5 kΩ Max. Valid Signature Resistance l 27.5 29.7 32 kΩ Classification V Classification Voltage AGND – V , 0mA ≤ I ≤ 50mA l 16.0 20.5 V CLASS OUTn OUTn Classification Current Compliance V = AGND l 53 61 67 mA OUTn Classification Threshold Current Class 0-1 l 5.5 6.5 7.5 mA Class 1-2 l 13.5 14.5 15.5 mA l Class 2-3 21.5 23 24.5 mA l Class 3-4 31.5 33 34.9 mA l Class 4-Overcurrent 45.2 48 50.8 mA V Classification Mark State Voltage AGND – V , 0.1mA ≤ I ≤ 5mA l 7.5 9 10 V MARK OUTn CLASS Mark State Current Compliance V = AGND l 53 61 67 mA OUTn Gate Driver GATE Pin Pull-Down Current Port Off, V = V + 5V l 0.4 mA GATEn EE Port Off, V = V + 1V l 0.08 0.12 mA GATEn EE GATE Pin Fast Pull-Down Current V = V + 5V 30 mA GATEn EE GATE Pin On Voltage V – V , I = 1µA l 8 12 14 V GATEn EE GATEn Output Voltage Sense V Power Good Threshold Voltage V – V l 2 2.4 2.8 V PG OUTn EE OUT Pin Pull-Up Resistance to AGND 0V ≤ (AGND – V ) ≤ 5V l 300 500 700 kΩ OUT 429071fb 4 For more information www.linear.com/LTC4290

LTC4290/LTC4271 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. AGND – V = 54V and V – DGND = 3.3V unless otherwise noted. A EE DD (Notes 3 & 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Overcurrent Sense Voltage V – V , CUT SENSEn EE hpen = 0Fh, cutn = D4h l 89 94 99 mV l hpen = 0Fh, cutn = E2h (Note 12) 152 159 168 mV Overcurrent Sense in AUTO Pin Mode Class 0, Class 3 l 89 94 99 mV Class 1 l 26 28 30 mV l Class 2 49 52 55 mV l Class 4 152 159 168 mV V Active Current Limit in 802.3af Compliant Mode V – V , hpen = 0Fh, limn = 80h, LIM SENSEn EE (AGND – V ) = 55V EE V < V < AGND – 29V l 102 106 112 mV EE OUT l AGND – V = 0V (Note 12) 25 50 mV OUT Active Current Limit in High Power Mode hpen = 0Fh, limn = C0h, (AGND – V ) = 55V EE V – V = 0 – 10V l 204 212 225 mV OUT EE l V + 23V < V < AGND – 29V 102 106 115 mV EE OUT l AGND – V = 0V (Note 12) 25 50 mV OUT Active Current Limit in AUTO Pin Mode V < V < AGND – 10V, EE OUT (AGND – V ) = 55V EE Class 0 to Class 3 l 102 106 112 mV l Class 4 204 212 225 mV V DC Disconnect Sense Voltage V – V , rdis Bit = 0 l 2.6 3.8 4.9 mV MIN SENSE EE V – V , rdis Bit = 1 (Note 12) l 1.3 1.9 2.45 mV SENSE EE V Short-Circuit Sense V – V – V (Note 12) SC SENSEn EE LIM rdis Bit = 0 l 125 200 255 mV l rdis Bit = 1 70 100 125 mV Port Current Readback Resolution No Missing Codes, Reported as 14 Bits 12 Bits LSB Weight V – V 30.518 µV/LSB SENSEn EE Conversion Period 25.1 ms/ Convert Port Voltage Readback Resolution No Missing Codes, Reported as 14 Bits 12 Bits LSB Weight AGND – V 5.8350 mV/LSB OUTn Digital Interface V Digital Input Low Voltage ADn, RESET, MSD, GPn, AUTO, MID l 0.8 V ILD (Note 6) I2C Input Low Voltage SCL, SDAIN (Note 6) l 1.0 V V Digital Input High Voltage (Note 6) l 2.2 V IHD Digital Output Voltage Low I = 3mA, I = 3mA l 0.4 V SDAOUT INT I = 5mA, I = 5mA l 0.7 V SDAOUT INT Internal Pull Up to V ADn, RESET, MSD, GPn 50 kΩ DD Internal Pull Down To DGND AUTO, MID 50 kΩ 429071fb 5 For more information www.linear.com/LTC4290

LTC4290/LTC4271 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. AGND – V = 54V and V – DGND = 3.3V unless otherwise noted. A EE DD (Notes 3 & 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS XIO V XIO Digital Output Low V – V , I = 5mA l 0.7 V OLX XIOn EE XIOn V XIO Digital Output High V – V , I = 100µA l 3.5 V OHX XIOn EE XIOn XIO Digital Input Low Voltage V – V l 0.8 V XIOn EE XIO Digital Input High Voltage V – V l 3.4 V XIOn EE Internal Pull Up to CAP2 XIO0, XIO1 50 kΩ PSE Timing Characteristics t Detection Time Beginning To End of Detection (Note 7) 220 ms DET t Class Event Duration (Note 7) 12 ms CLE t Class Event Turn On Duration C = 0.6µF (Note 7) l 0.1 ms CLEON PORT t Mark Event Duration (Note 7, Note 11) 8.6 ms ME t Last Mark Event Duration (Note 7, Note 11) l 16 22 ms MEL t Power On Delay in AUTO Pin Mode From End of Valid Detect to Application of l 60 ms PON Power to Port (Note 7) Turn-On Rise Time (AGND – V ): 10% to 90% of (AGND - l 15 24 µs OUT V ) C = 0.15µF (Note 7) EE PORT Turn-On Ramp Rate C = 0.15µF (Note 7) l 10 V/µs PORT t Turn-On Class Transition C = 0.15µF (Note 7) l 0.1 ms TOCL PORT t Fault Delay From I or I Fault to Next Detect l 1.0 1.1 s ED CUT LIM (Note 7) Midspan Mode Detection Backoff R = 15.5kΩ (Note 7) l 2.3 2.5 2.7 s PORT Power Removal Detection Delay From Power Removal After t to Next l 1.0 1.3 2.5 s DIS Detect (Note 7) t Maximum Current Limit Duration During Port (Note 7) l 52 59 66 ms START Start-Up t Maximum Overcurrent Duration After Port Start- (Note 7) l 52 59 66 ms CUT Up Maximum Overcurrent Duty Cycle (Note 7) l 5.8 6.3 6.7 % t Maximum Current Limit Duration After Port Start- t = 1 (Note 7, Note 12) l 10 12 14 ms LIM LIM Up – t Enabled LIM Maximum Current Limit Duration After Port Start- t = 0 (Note 7, Note 12) l 52 59 66 ms LIM Up – t as t LIM CUT t Maintain Power Signature (MPS) Pulse Width Current Pulse Width to Reset Disconnect l 1.6 3.6 ms MPS Sensitivity Timer (Note 7, Note 8) t Maintain Power Signature (MPS) Dropout Time (Note 7, Note 5) l 320 350 380 ms DIS t Masked Shut Down Delay (Note 7) 6.5 µs MSD I2C Watchdog Timer Duration (Note 7) l 1.5 2 3 s Minimum Pulse Width for Masked Shut Down (Note 7) l 3 µs Minimum Pulse Width for RESET (Note 7) l 4.5 µs 429071fb 6 For more information www.linear.com/LTC4290

LTC4290/LTC4271 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. AGND – V = 54V and V – DGND = 3.3V unless otherwise noted. A EE DD (Notes 3 & 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I2C Timing f Clock Frequency (Note 7) l 1 MHz SCLK t Bus Free Time Figure 5 (Notes 7, 9) l 480 ns 1 t Start Hold Time Figure 5 (Notes 7, 9) l 240 ns 2 t SCL Low Time Figure 5 (Notes 7, 9) l 480 ns 3 t SCL High Time Figure 5 (Notes 7, 9) l 240 ns 4 t SDAIN Data Hold Time Figure 5 (Notes 7, 9) l 60 ns 5 t Data Clock to SDAOUT Valid Figure 5 (Notes 7, 9) l 130 ns 5 t Data Set-Up Time Figure 5 (Notes 7, 9) l 80 ns 6 t Start Set-Up Time Figure 5 (Notes 7, 9) l 240 ns 7 t Stop Set-Up Time Figure 5 (Notes 7, 9) l 240 ns 8 t SCL, SDAIN Rise Time Figure 5 (Notes 7, 9) l 120 ns r t SCL, SDAIN Fall Time Figure 5 (Notes 7, 9) l 60 ns f Fault Present to INT Pin Low (Notes 7, 9, 10) l 150 ns Stop Condition to INT Pin Low (Notes 7, 9, 10) l 1.5 µs ARA to INT Pin High Time (Notes 7, 9) l 1.5 µs SCL Fall to ACK Low (Notes 7, 9) l 130 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 7: Guaranteed by design, not subject to test. may cause permanent damage to the device. With the exception of (VDD – Note 8: The IEEE 802.3 specification allows a PD to present its DGND), exposure to any Absolute Maximum Rating condition for extended Maintain Power Signature (MPS) on an intermittent basis without being periods may affect device reliability and lifetime. disconnected. In order to stay powered, the PD must present the MPS for Note 2: This IC includes overtemperature protection that is intended t within any t time window. MPS MPDO to protect the device during momentary overload conditions. Junction Note 9: Values Measured at V and V ILD IHD temperature will exceed 140ºC when overtemperature protection is active. Note 10: If a fault condition occurs during an I2C transaction, the INT pin Continuous operation above the specified maximum operating junction will not be pulled down until a stop condition is present on the I2C bus. temperature may impair device reliability. Note 11: Load characteristics of the LTC4290 during Mark: 7V < (AGND – Note 3: All currents into device pins are positive; all currents out of device V ) < 10V or I < 50µA. OUTn OUT pins are negative. Note 12: See the LTC4271 Software Programming documentation for Note 4: The LTC4290 operates with a negative supply voltage (with information on serial bus usage and device configuration and status respect to AGND). To avoid confusion, voltages in this data sheet are registers. referred to in terms of absolute magnitude. Note 13: Do not source or sink current from CAP1 and CAP2. Note 5: t is the same as t defined by IEEE 802.3 DIS MPDO Note 6: The LTC4271 digital interface operates with respect to DGND. All logic levels are measured with respect to DGND. 429071fb 7 For more information www.linear.com/LTC4290

LTC4290/LTC4271 TYPICAL PERFORMANCE CHARACTERISTICS 802.3af Power On Sequence in 802.3at Power On Sequence in Power On Sequence with 10V PP AUTO Pin Mode AUTO Pin Mode 60Hz Noise 0 0 5 AGND AGND PORT OFF FORCED VOLTAGE DETECTION –10 –10 0 AGND GE (V) –20 FORCEDD ECTUERCRTEIONNT GE (V) –20 FORCEDD ECTUERCRTEIONNT GE (V) –5 OLTA –30 FORCEDDE VTOECLTTAIOGNE OLTA –30 FORCEDDE VTOECLTTAIOGNE OLTA –10 PORT V –40 CVLEAES =S – 35 5PVD CLASSIFIC8A0T2I.3OaNf PORT V –40 CVLEAES =S – 45 5PVD CLASSIFIC8A0T2I.3OaNt PORT V –15 FORCEDD ECTUERCRTEIONNT 802.3af CLASSIFICATION –50 POWER ON –50 POWER ON –20 VEE VEE DETECT WITH 60Hz NOISE NORMAL DETECT POWER ON –60 –60 –25 50ms/DIV 50ms/DIV 50ms/DIV 429071 G01 429071 G02 429071 G03 Classification Transient Response Powering Up into a 180µF Load to 40mA Load Step Classification Current Compliance 0 PORT V2O0LAVTG/ADNGIDVE VEE = –54V CURPRO4E0NRmTTA VVDEED == –35.34VV E (V) ––24 20mA/DIV G –6 A VEE 0mA OLT –8 LOAD FULLY CHARGED V ON –10 PORT2 0C0UmRAR/EDNIVT FOLDBACK CURRENT4 2L5IMmIAT PORT SIFICATI––1124 0mA VOLTAGE AS GATE VOLTAGE FET ON 1V/DIV CL–16 10V/DIV –20V –18 VEE –20 429071 G05 0 10 20 30 40 50 60 70 50µs/DIV 5ms/DIV CLASSIFICATION CURRENT (mA) 429071 G04 429071 G06 V Supply Current vs Voltage V Supply Current vs Voltage DD EE 15.0 9.0 8.5 A)12.0 A) m m NT ( NT ( 8.0 RE 9.0 RE R R U U 7.5 C C PLY 6.0 PLY UP UP 7.0 S S I DD 3.0 85°C I EE 6.5 85°C 25°C 25°C –40 –40 0.0 6.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 –60 –50 –40 –30 –20 VDD SUPPLY VOLTAGE (V) VEE SUPPLY VOLTAGE (V) 429071 G07 429071 G08 429071fb 8 For more information www.linear.com/LTC4290

LTC4290/LTC4271 TYPICAL PERFORMANCE CHARACTERISTICS 802.3at I Threshold 802.3at I Threshold LIM CUT vs Temperature vs Temperature 220 880 166 664 PORT 1 PORT 1 REG 48h = C0h REG 47h = E2h 164 656 RSENSE = 0.25Ω RSENSE = 0.25Ω 864 216 162 648 V (mV)LIM 212 848 LIMI (mA) V (mV)CUT 116508 664302 CUTI (mA) 208 156 624 832 154 616 204 816 152 608 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) 429071 G09 429071 G10 DC Disconnect Threshold vs Temperature 802.3at Current Limit Foldback 2.50 10 900 225 PORT 1 PORT 1 REG 47h = E2h 800 REG 48h = C0h 200 2.25 RSENSE = 0.25Ω 9 700 RSENSE = 0.25Ω 175 600 150 V (mV)MIN21..0705 87 MINI (mA) I (mA)LIM 540000 112050 LIMV (mV) 300 75 200 50 1.50 6 100 25 1.25 5 0 0 –40 –20 0 20 40 60 80 100 120 –54 –45 –36 –27 –18 –9 0 TEMPERATURE (°C) VOUTn (V) 429071 G11 429071 G12 INT and SDAOUT Pull Down MOSFET Gate Drive With Fast Voltage vs Load Current Pull Down 3.0 GND VDD = 3.3V PORT VEE = –54V 2.5 VOLTAGE V) 20V/DIV E ( 2.0 AG VEE LT O FAST PULL DOWN V 1.5 GATE WN VOLTAGE LDO 1.0 10V/DIV VEE CURRENT LIMIT L 50Ω U P FAULT 0.5 PORT APPLIED 50Ω FAULT REMOVED CURRENT 500mA/DIV 0mA 0.0 0 10 20 30 40 50 60 429071 G14 100µs/DIV LOAD CURRENT (mA) 429071 G13 429071fb 9 For more information www.linear.com/LTC4290

LTC4290/LTC4271 TEST TIMING DIAGRAMS tDET CLASSIFICATION FORCED- FORCED-CURRENT VOLTAGE tME 0V VPORTn tMEL VOC VMARK 15.5V VCLASS 20.5V tCLE tCLE PD CONNECTED tCLEON tPON VEE INT 429071 F01 Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-auto Modes VLIM VCUT VSENSEn TO VEE 0V tSTART, tCUT INT 429071 F02 Figure 2. Current Limit Timing VTSOE NVSEEEn VMIN INT tMPS tDIS 429071 F03 Figure 3. DC Disconnect Timing 429071fb 10 For more information www.linear.com/LTC4290

LTC4290/LTC4271 TEST TIMING DIAGRAMS VGATEn tMSD VEE MSD 429071 F04 Figure 4. Shut Down Delay Timing t3 tr t4 tf SCL t2 t5 t6 t7 t8 SDA t1 429071 F05 Figure 5. I2C Interface Timing 429071fb 11 For more information www.linear.com/LTC4290

LTC4290/LTC4271 2 I C TIMING DIAGRAMS SCL SDA AD6 1 0 AD3 AD2 AD1 AD0 R/WACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK START BY ACK BY ACK BY ACK BY STOP BY MASTER SLAVE SLAVE SLAVE MASTER FRAME 1 FRAME 2 FRAME 3 SERIAL BUS ADDRESS BYTE REGISTER ADDRESS BYTE DATA BYTE 429071 F06 Figure 6. Writing to a Register SCL SDA AD6 1 0 AD3 AD2 AD1 AD0R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK AD6 1 0 AD3 AD2 AD1 AD0R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK START BY ACK BY ACK BY REPEATED ACK BY NO ACK BY STOP BY MASTER SLAVE SLAVE START BY SLAVE MASTER MASTER MASTER FRAME 1 FRAME 2 FRAME 1 FRAME 2 SERIAL BUS ADDRESS BYTE REGISTER ADDRESS BYTE SERIAL BUS ADDRESS BYTE DATA BYTE 429071 F07 Figure 7. Reading from a Register SCL SDA AD6 1 0 AD3 AD2 AD1 AD0R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK START BY ACK BY NO ACK BY STOP BY MASTER SLAVE MASTER MASTER FRAME 1 FRAME 2 SERIAL BUS ADDRESS BYTE DATA BYTE 429071 F08 Figure 8. Reading the Interrupt Register (Short Form) SCL SDA 0 0 0 1 1 0 0 R/W ACKAD6 1 0 AD3 AD2 AD1AD0 1 ACK START BY ACK BY NO ACK BY STOP BY MASTER SLAVE MASTER MASTER FRAME 1 FRAME 2 ALERT RESPONSE ADDRESS BYTE SERIAL BUS ADDRESS BYTE 429071 F09 Figure 9. Reading from Alert Response Address 429071fb 12 For more information www.linear.com/LTC4290

LTC4290/LTC4271 PIN FUNCTIONS LTC4290 AGND (Pin 25): Analog Ground. Connect AGND to the return for the V supply. V (Pins 1, 30, 33, 40): Main PoE Supply Input. Con- EE EE nect to a –45V to –57V supply, relative to AGND. Voltage DNA (Pin 36): Data Transceiver Negative Input Output depends on PSE type (Type 1, Type 2 or LTPoE++). (Analog). Connect to DND through a data transformer. GATEn (Pins 2, 4, 7, 9, 22, 24, 27, 29): Port n Gate Drive. DPA (Pin 37): Data Transceiver Positive Input Output GATEn should be connected to the gate of the external (Analog). Connect to DPD through a data transformer. MOSFET for port n. When the MOSFET is turned on, the CNA (Pin 38): Clock Transceiver Negative Input Output gate voltage is driven to 12V (typ) above V . During a EE (Analog). Connect to CND through a data transformer. current limit condition, the voltage at GATEn will be re- duced to maintain constant current through the external CPA (Pin 39): Clock Transceiver Positive Input Output MOSFET. If the fault timer expires, GATEn is pulled down, (Analog). Connect to CPD through a data transformer. turning the MOSFET off and recording a port fault event. VSSK (Exposed Pad Pin 41): Kelvin Sense to V . Connect EE If the port is unused, float the GATEn pin. to sense resistor common node. Do not connect directly OUTn (Pins 3, 5, 8, 10, 21, 23, 26, 28): Port n Output to VEE plane. See Layout Guide. Voltage Monitor. OUTn should be connected to the output Common Pins port. A current limit foldback circuit limits the power dis- NC, DNC (LTC4271 Pins 7,13; LTC4290 Pins 31, 32, 34, sipation in the external MOSFET by reducing the current 35): All pins identified with “NC” or “DNC” must be left limit threshold when the drain-to-source voltage exceeds unconnected. 10V. The port n Power Good bit is set when the voltage from OUTn to VEE drops below 2.4V (typ). A 500k resistor LTC4271 is connected internally from OUTn to AGND when the port AD0 (Pin 1): Address Bit 0. Tie the address pins high or low is idle. If the port is unused, the OUTn pin must be floated. to set the starting I2C serial address to which the LTC4271 CAP2 (Pin 6): Analog Internal 4.3V Power Supply Bypass responds. The chip will respond to this address plus the Capacitor. Connect 0.1µF ceramic cap to VEE. next two incremental addresses. The base address of the first four ports will be (A 10A A A A )b. The second and XIO0 (Pin 11): General Purpose Digital Input Output. Logic 6 3 2 1 0 third groups of four ports will respond at the next two signal between V and V + 4.3V. Internal pull up. EE EE logical addresses. Internally pulled up to V . DD SENSEn (Pins 12, 13, 14, 15, 16, 17, 18, 19): Port AD1 (Pin 2): Address Bit 1. See AD0. n Current Sense Input. SENSEn monitors the external MOSFET current via a 0.5Ω or 0.25Ω sense resistor AD2 (Pin 3): Address Bit 2. See AD0. between SENSEn and V . Whenever the voltage across EE AD3 (Pin 4): Address Bit 3. See AD0. the sense resistor exceeds the overcurrent detection threshold V , the current limit fault timer counts up. If AD6 (Pin 5): Address Bit 6. See AD0. CUT the voltage across the sense resistor reaches the current MID (Pin 6): Midspan Mode Input. When high, the LTC4271 limit threshold V , the GATEn pin voltage is lowered to LIM acts as a midspan device. Internally pulled down to DGND. maintain constant current in the external MOSFET. See Applications Information for further details. If the port is CPD (Pin 8): Clock Transceiver Positive Input Output unused, the SENSEn pin must be tied to V . (Digital). Connect to CPA through a data transformer. EE XIO1 (Pin 20): General Purpose Digital Input Output. Logic signal between V and V + 4.3V. Internal pull up. EE EE 429071fb 13 For more information www.linear.com/LTC4290

LTC4290/LTC4271 PIN FUNCTIONS CND (Pin 9): Clock Transceiver Negative Input Output SDAIN (Pin 17): Serial Data Input. High impedance data (Digital). Connect to CNA through a data transformer. input for the I2C serial interface bus. The LTC4271 uses two pins to implement the bidirectional SDA function to simplify DPD (Pin 10): Data Transceiver Positive Input Output optoisolation of the I2C bus. To implement a standard (Digital). Connect to DPA through a data transformer. bidirectional SDA pin, tie SDAOUT and SDAIN together. DND (Pin 11): Data Transceiver Negative Input Output See Applications Information for more information. (Digital). Connect to DNA through a data transformer. SCL (Pin 18): Serial Clock Input. High impedance clock VDD33 (Pins 12, 20): VDD IO Power Supply. Connect to input for the I2C serial interface bus. The SCL pin should a 3.3V power supply relative to DGND. VDD33 must be be connected directly to the I2C SCL bus line. SCL must bypassed to DGND near the LTC4271 with at least a 0.1μF be tied high if the I2C serial interface bus is not used. capacitor. CAP1 (Pin 19): Core Power Supply Bypass Capacitor. Con- RESET (Pin 14): Reset Input, Active Low. When the RESET nect a 1µF Bypass capacitance to DGND for the internal pin is low, the LTC4290/LTC4271 is held inactive with all 1.8V regulator. Do not use other capacitor values. ports off and all internal registers reset to their power-up AUTO (Pin 21): AUTO Pin Mode Input. AUTO pin mode states. When RESET is pulled high, the LTC4271 begins allows the LTC4271 to detect and power up a PD even if normal operation. RESET can be connected to an external there is no host controller present on the I2C bus. The capacitor or RC network to provide a power turn-on delay. AUTO pin determines the state of the internal registers Internal filtering of the RESET pin prevents glitches less when the LTC4271 is reset or comes out of V UVLO than 1μs wide from resetting the LTC4290/LTC4271. DD (see LTC4271 Software Programming documentation). The Internally pulled up to V . DD states of these register bits can subsequently be changed INT (Pin 15): Interrupt Output, Open Drain. INT will pull via the I2C interface. Internally pulled down to DGND. Must low when any one of several events occur in the LTC4271. be tied locally to either V or DGND. DD It will return to a high impedance state when bits 6 or 7 GP1 (Pin 22): General Purpose Digital Input Output for are set in the Reset PB register (1Ah). The INT signal can customer applications. Referenced to DGND. be used to generate an interrupt to the host processor, eliminating the need for continuous software polling. In- GP0 (Pin 23): General Purpose Digital Input Output for dividual INT events can be disabled using the INT Mask customer applications. Referenced to DGND. register (01h). See LTC4271 Software Programming MSD (Pin 24): Maskable Shutdown Input. Active low. documentation for more information. The INT pin is only When pulled low, all ports that have their corresponding updated between I2C transactions. mask bit set in the mconfig register (17h) will be reset. SDAOUT (Pin 16): Serial Data Output, Open Drain Data Internal filtering of the MSD pin prevents glitches less Output for the I2C Serial Interface Bus. The LTC4271 uses than 1μs wide from resetting ports. The MSD Pin Mode two pins to implement the bidirectional SDA function to register can configure the MSD pin polarity. Internally simplify optoisolation of the I2C bus. To implement a stan- pulled up to V . DD dard bidirectional SDA pin, tie SDAOUT and SDAIN together. DGND (Exposed Pad Pin 25): Digital Ground. DGND should See Applications Information for more information. be connected to the return from the V supply. DD 429071fb 14 For more information www.linear.com/LTC4290

LTC4290/LTC4271 APPLICATIONS INFORMATION OVERVIEW LTC4290/LTC4271 Product Overview Power over Ethernet, or PoE, is a standard protocol for send- The LTC4290/LTC4271 is a fourth generation 8-port PSE ing DC power over copper Ethernet data wiring. The IEEE controller that implements eight PSE ports in either an group that administers the 802.3 Ethernet data standards endpoint or midspan design. Virtually all necessary circuitry added PoE powering capability in 2003. This original PoE is included to implement an IEEE 802.3at compliant PSE spec, known as 802.3af, allowed for 48V DC power at up design, requiring only an external power MOSFET and sense to 13W. This initial specification was widely popular, but resistor per channel; these minimize power loss compared 13W was not adequate for some requirements. In 2009, to alternative designs with onboard MOSFETs and increase the IEEE released a new standard, known as 802.3at or system reliability in the event a single channel fails. PoE+, increasing the voltage and current requirements to All grades of the LTC4290/LTC4271 offer advanced provide 25W of power. fourth generation PSE features, including per-port cur- The IEEE standard also defines PoE terminology. A device rent monitoring, V monitoring, port current policing, EE that provides power to the network is known as a PSE, or one second current averaging and four general purpose power sourcing equipment, while a device that draws power input/output pins. from the network is known as a PD, or powered device. The LTC4290/LTC4271 chipset implements a proprietary PSEs come in two types: Endpoints (typically network isolation scheme for inter-chip communication. This switches or routers), which provide data and power; and architecture dramatically reduces BOM cost by replacing Midspans, which provide power but pass through data. expensive opto-isolators and isolated power supplies with Midspans are typically used to add PoE capability to existing a single low-cost transformer. non-PoE networks. PDs are typically IP phones, wireless access points, security cameras, and similar devices. The LTC4290/LTC4271 comes in three grades which sup- port different PD power levels. PoE++ Evolution The A-grade LTC4290/LTC4271 chipset extends PoE Even during the process of creating the IEEE PoE+ 25.5W power delivery capabilities to LTPoE++ levels. LTPoE++ specification it became clear that there was a significant is a Linear Technology proprietary specification allowing and increasing need for more than 25.5W of delivered for the delivery of up to 90W to LTPoE++ compliant PDs. power. The A-grade LTC4290/LTC4271 chipset responds The LTPoE++ architecture extends the IEEE physical power to this market by allowing a reliable means of providing up negotiation to include 38.7W, 52.7W, 70W and 90W power to 90W of delivered power to a LTPoE++ PD. The LTPoE++ levels. The A-grade LTC4290/LTC4271 also incorporates specification provides reliable detection and classification all B- and C-grade features. extensions to the existing IEEE PoE protocols that are The B-grade LTC4290/LTC4271 is a fully IEEE-compliant backward compatible and interoperable with existing Type 1 Type 2 PSE supporting autonomous detection, classifica- and Type 2 PDs. Unlike other proprietary PoE++ solutions tion and powering of Type 1 and Type 2 PDs. The B-grade Linear’s LTPoE++ provides mutual identification between LTC4290/LTC4271 also incorporates all C-grade features. the PSE and PD. This ensures the LTPoE++ PD knows it may use the requested power at start-up because it has The C-grade LTC4290/LTC4271 is a fully autonomous detected a LTPoE++ PSE. LTPoE++ PSEs can differentiate 802.3af Type 1 PSE solution. Intended for use only with between a LTPoE++ PD and all other types of IEEE compli- the AUTO pin tied high, the C-grade chipset autonomously ant PDs allowing LTPoE++ PSEs to remain compliant and supports detection, classification and powering of Type 1 interoperable with existing equipment. PDs. As a Type 1 PSE, two event classification is prohibited and Class 4 PDs are automatically treated as Class 0 PDs. 429071fb 15 For more information www.linear.com/LTC4290

LTC4290/LTC4271 APPLICATIONS INFORMATION PoE BASICS draw more power than the PSE has available. The clas- sification step is optional; if a PSE chooses not to classify Common Ethernet data connections consist of two or four a PD, it must assume that the PD is a 13W (full 802.3af twisted pairs of copper wire (commonly known as CAT-5 power) device. cable), transformer-coupled at each end to avoid ground loops. PoE systems take advantage of this coupling ar- New in 802.3at rangement by applying voltage between the center-taps of the data transformers to transmit power from the PSE The newer 802.3at standard supersedes 802.3af and brings to the PD without affecting data transmission. Figure 10 several new features: shows a high level PoE system schematic. • A PD may draw as much as 25.5W. Such PDs (and the To avoid damaging legacy data equipment that does not PSEs that support them) are known as Type 2. Older expect to see DC voltage, the PoE spec defines a protocol 13W 802.3af equipment is classified as Type 1. Type 1 that determines when the PSE may apply and remove PDs will work with all PSEs; Type 2 PDs may require power. Valid PDs are required to have a specific 25k Type 2 PSEs to work properly. The LTC4290/LTC4271 common-mode resistance at their input. When such a PD is designed to work in both Type 1 and Type 2 PSE de- is connected to the cable, the PSE detects this signature signs, and also supports non-standard configurations resistance and turns on the power. When the PD is later at higher power levels. disconnected, the PSE senses the open circuit and turns • The Classification protocol is expanded to allow Type power off. The PSE also turns off power in the event of a 2 PSEs to detect Type 2 PDs, and to allow Type 2 PDs current fault or short circuit. to determine if they are connected to a Type 2 PSE. When a PD is detected, the PSE optionally looks for a Two versions of the new Classification protocol are classification signature that tells the PSE the maximum available: an expanded version of the 802.3af Class power the PD will draw. The PSE can use this informa- Pulse protocol, and an alternate method integrated tion to allocate power among several ports, to police the with the existing LLDP protocol (using the Ethernet current consumption of the PD, or to reject a PD that will CAT 5 20Ω MAX PSE RJ45 ROUNDTRIP RJ45 PD 0.05µF MAX 4 4 5 5 GND SPARE PAIR 1 1 AGND Tx Rx 2 DATA PAIR 2 1/8 I2C LTC4290/LTC4271 3 3 Rx Tx VEE GATE 6 DATA PAIR 6 GND PWRGD DC/DC + CONVERTER –54V LTC4265 VOUT 7 7 –54VIN –54VOUT – 8 8 SPARE PAIR 429071 F10 Figure 10. Power Over Ethernet System Diagram 429071fb 16 For more information www.linear.com/LTC4290

LTC4290/LTC4271 APPLICATIONS INFORMATION data path). The LTC4290/LTC4271 fully supports the Some LTC4266 registers have been obsoleted in the new Class Pulse protocol and is also compatible with LTC4290/LTC4271 chipset. The obsoleted registers are not the LLDP protocol (which is implemented in the data required for 802.3at compliant PSE operation. For more communications layer, not in the PoE circuitry). details about software differences between the LTC4266 and LTC4290/LTC4271, refer to the LTC4271 Software • Fault protection current levels and timing are adjusted Programming document. to reduce peak power in the MOSFET during a fault; this allows the new 25.5W power levels to be reached Operation with high power mode disabled is obsoleted in using the same MOSFETs as older 13W designs. the LTC4290/LTC4271 chipset. All operations previously available in low power mode are fully implemented as a Extended Power LTPoE++ subset of the high power mode capabilities. A-grade LTC4290/LTC4271 parts add the capability to autonomously deliver up to 90W of power to the PD. OPERATING MODES LTPoE++ PDs may forgoe 802.3 LLDP support and rely The LTC4290/LTC4271 includes eight independent ports, solely on the LTPoE++ Physical Classification to negotiate each of which can operate in one of four modes: manual, power with LTPoE++ PSEs; this greatly simplifies high- semi-auto, AUTO pin, or shutdown. power PDimplementations. Table 2. Operating Modes LTPoE++ may be optionally enabled for A-grade LTC4290/ AUTOMATIC LTC4271s by setting both the High Power Enable and AUTO DETECT/ I /I LTPoE++ Enable bits. CUT LIM MODE PIN OPMD CLASS POWER-UP ASSIGNMENT The higher levels of LTPoE++ delivery impose additional AUTO Pin 1 11b Enabled Automatically Yes at Reset layout and component selection constraints. LTC4290 pin Reserved 0 11b N/A N/A N/A selects allow the AUTO pin mode LTC4271 to autonomously Semi-auto 0 10b Host Upon No power up to supported power levels. If the AUTO pin is Enabled Request high, the XIO1 and XIO0 pins are sampled at reset to de- Manual 0 01b Once Upon No termine the maximum deliverable power. PDs requesting Upon Request more than the available power limits are not powered. Request Shutdown 0 00b Disabled Disabled No Table 1. LTPoE++ AUTO Pin Mode Maximum Delivered Power Capabilities In manual mode, the port waits for instructions from the POWER XIO1 XIO0 host system before taking any action. It runs a single 38.7W 0 0 detection or classification cycle when commanded to by 52.7W 0 1 the host, and reports the result in its Port Status register. 70W 1 0 The host system can command the port to turn on or off 90W 1 1 the power at any time. In semi-auto mode, the port repeatedly attempts to detect BACKWARD COMPATIBILITY and classify any PD attached to it. It reports the status of these attempts back to the host, and waits for a command The LTC4290/LTC4271 chipset is designed to be back- from the host before turning on power to the port. The ward compatible with the LTC4266, operating in Type host must enable detection (and optionally classification) 2 mode, without software changes; only minor layout for the port before detection will start. changes are required to implement a fully compliant IEEE 802.3at design. 429071fb 17 For more information www.linear.com/LTC4290

LTC4290/LTC4271 APPLICATIONS INFORMATION AUTO pin mode operates the same as semi-auto mode The automatic setting of I and I values only occurs CUT LIM except it will automatically turn on the power to the port if if the LTC4290/LTC4271 is reset with the AUTO pin high. detection is successful. AUTO pin mode will autonomously If the standalone application is a midspan, the MID pin must set the I and I values based on the class result. This CUT LIM be tied high to enable correct midspan detection timing. operational mode is only valid if the AUTO pin is high at reset or power-up and remains high during operation. DETECTION In shutdown mode, the port is disabled and will not detect or power a PD. Detection Overview Regardless of which mode it is in, the LTC4290/LTC4271 To avoid damaging network devices that were not designed will remove power automatically from any port that gener- to tolerate DC voltage, a PSE must determine whether the ates a current limit fault. It will also automatically remove connected device is a real PD before applying power. The power from any port that generates a disconnect event if IEEE specification requires that a valid PD have a common- disconnect detection is enabled. The host controller may mode resistance of 25k ±5% at any port voltage below also command the port to remove power at any time. 10V. The PSE must accept resistances that fall between 19k and 26.5k, and it must reject resistances above 33k Reset and the AUTO/MID Pins or below 15k (shaded regions in Figure 11). The PSE may The initial LTC4290/LTC4271 configuration depends on choose to accept or reject resistances in the undefined the state of the AUTO and MID pins during reset. Reset areas between the must-accept and must-reject ranges. In occurs at power-up, or whenever the RESET pin is pulled particular, the PSE must reject standard computer network low or the global Reset All bit is set. Changing the state of ports, many of which have 150Ω common-mode termina- AUTO or MID after power-up will not properly change the tion resistors that will be damaged if power is applied to port behavior of the LTC4290/LTC4271 until a reset occurs. them (the black region at the left of Figure 11). Although typically used with a host controller, the LTC4290/ RESISTANCE 0Ω 10k 20k 30k LTC4271 can also be used in a standalone mode with no connection to the serial interface. If there is no host pres- PD 150Ω (NIC) 23.75k 26.25k PSE 15k 19k 26.5k 33k ent, the AUTO pin must be tied high so that, at reset, all 429071 F11 ports will be configured to operate automatically. Each port Figure 11. IEEE 802.3af Signature Resistance Ranges will detect and classify repeatedly until a PD is discovered, set I and I according to the classification results, CUT LIM 4-Point Detection apply power to valid PDs, and remove power when a PD is disconnected. The LTC4290/LTC4271 uses a 4-point detection method to discover PDs. False-positive detections are minimized by Table 3 shows the I and I values that will be auto- CUT LIM checking for signature resistance with both forced-current matically set in standalone (AUTO pin) mode, based on and forced-voltage measurements. the discovered class. Initially, two test currents are forced onto the port (via the Table 3. I and I Values in Standalone Mode CUT LIM OUTn pin) and the resulting voltages are measured. The CLASS I I CUT LIM detection circuitry subtracts the two V-I points to determine Class 1 112mA 425mA the resistive slope while removing offset caused by series Class 2 206mA 425mA diodes or leakage at the port (see Figure 12). If the forced- Class 3 or 0 375mA 425mA current detection yields a valid signature resistance, two Class 4 638mA 850mA test voltages are then forced onto the port and the result- ing currents are measured and subtracted. Both methods 429071fb 18 For more information www.linear.com/LTC4290

LTC4290/LTC4271 APPLICATIONS INFORMATION If a valid signature resistance is detected and classification is enabled, the port will classify the PD and report that result as well. The port will then wait for at least 100ms (or 275 A) FIRST 2 seconds if midspan mode is enabled), and will repeat the NT (µ 25kΩ SLOPE DEPTEOCINTTION detection cycle to ensure that the data in the Port Status E R register is up-to-date. R 165 CU SECOND DETECTION If the port is in semi-auto mode and high power opera- VALID PD POINT tion is enabled, the port will not turn on in response to a power-on command unless the current detect result is 0V-2V VOLTAGE detect good. Any other detect result will generate a t OFFSET START 429071 F12 fault if a power-on command is received. In high power Figure 12. PD Detection mode the port must be placed in manual mode to force a must report valid resistances for the port to report a valid port on regardless of detect outcome. detection. PD signature resistances between 17k and 29k Behavior in AUTO pin mode is similar to semi-auto; how- (typically) are detected as valid and reported as Detect ever, after detect good is reported and the port is classified Good in the corresponding Port Status register. Values (if classification is enabled), it is automatically powered outside this range, including open and short circuits, are on without further intervention. In standalone (AUTO pin) also reported. If the port measures less than 1V at the mode, the I and I thresholds are automatically set; first forced-current test, the detection cycle will abort and CUT LIM see the Reset and the AUTO/MID Pins section for more Short Circuit will be reported. Table 4 shows the possible information. detection results. The signature detection circuitry is disabled when the Table 4. Detection Status port is initially powered up with the AUTO pin low, in MEASURED PD SIGNATURE DETECTION RESULT shutdown mode, or when the corresponding Detect En- Incomplete or Not Yet Tested Detect Status Unknown able bit is cleared. < 2.4k Short Circuit Detection of Legacy PDs Capacitance > 2.7µF C too High PD 2.4k < R < 17k R too Low Proprietary PDs that predate the original IEEE 802.3af stan- PD SIG 17k < R < 29k Detect Good dard are commonly referred to today as legacy devices. One PD > 29k R too High type of legacy PD uses a large common-mode capacitance SIG > 50k Open Circuit (>10μF) as the detection signature. Note that PDs in this Voltage > 10V Port Voltage Outside Detect Range range of capacitance are defined as invalid, so a PSE that detects legacy PDs is technically noncompliant with the More on Operating Modes IEEE spec. The LTC4290/LTC4271 can be configured to detect this type of legacy PD. Legacy detection is disabled The port’s operating mode determines when the LTC4290/ by default, but can be manually enabled on a per-port basis. LTC4271 runs a detection cycle. In manual mode, the port When enabled, the port will report Detect Good when it will idle until the host orders a detect cycle. It will then sees either a valid IEEE PD or a high-capacitance legacy run detection, report the results, and return to idle to wait PD. With legacy mode disabled, only valid IEEE PDs will for another command. be recognized. In semi-auto mode, the LTC4290/LTC4271 autonomously polls a port for PDs, but it will not apply power until com- manded to do so by the host. The Port Status register is updated at the end of each detection cycle. 429071fb 19 For more information www.linear.com/LTC4290

LTC4290/LTC4271 APPLICATIONS INFORMATION CLASSIFICATION If the LTC4290/LTC4271 is in AUTO pin mode, it will ad- ditionally use the classification result to set the I and CUT 802.3af Classification I thresholds. See the Reset and the AUTO/MID Pin LIM section for more information. A PD may optionally present a classification signature to the PSE to indicate the maximum power it will draw while The classification circuitry is disabled when the port is operating. The IEEE specification defines this signature as initially powered up with the AUTO pin low, in shutdown a constant current draw when the PSE port voltage is in the mode, or when the corresponding Class Enable bit is VCLASS range (between 15.5V and 20.5V), with the current cleared. level indicating one of 5 possible PD classes. Figure 13 shows a typical PD load line, starting with the slope of 802.3at 2-Event Classification the 25k signature resistor below 10V, then transitioning to The 802.3at specification defines two methods of classify- the classification signature current (in this case, Class 3) ing a Type 2 PD. A-grade and B-grade LTC4290/LTC4271 in the V range. Table 5 shows the possible clas- CLASS parts support 802.3at 2-event classification. sification values. One method adds extra fields to the Ethernet LLDP data Table 5. 802.3af and 802.3at Classification Values protocol; although the LTC4290/LTC4271 is compatible CLASS RESULT with this classification method, it cannot perform clas- Class 0 No Class Signature Present; Treat Like Class 3 sification directly since it doesn’t have access to the data Class 1 3W path. LLDP classification requires the PSE to power the Class 2 7W PD as a standard 802.3af (Type 1) device. It then waits for Class 3 13W the host to perform LLDP communication with the PD and Class 4 25.5W (Type 2) update the PSE port data. The LTC4290/LTC4271 supports changing the I and I levels on the fly, allowing the If classification is enabled, the port will classify the PD LIM CUT host to complete LLDP classification. immediately after a successful detection cycle in semi-auto or AUTO pin modes, or when commanded to in manual The second 802.3at classification method, known as mode. It measures the PD classification signature by ap- 2-event classification or ping-pong, is supported by plying 18V for 12ms (both values typical) to the port via the LTC4290/LTC4271. A Type 2 PD that is request- the OUTn pin and measuring the resulting current; it then ing more than 13W will indicate Class 4 during normal reports the discovered class in the Port Status register. 802.3af classification. If the LTC4290/LTC4271 sees Class 4, it forces the port to a specified lower voltage 60 (called the mark voltage, typically 9V), pauses briefly, and OVER PSE LOAD LINE then re-runs classification to verify the Class 4 reading 50 CURRENT 48mA (Figure 1). It also sets a bit in the High Power Status register A) 40 CLASS 4 to indicate that it ran the second classification cycle. The m NT ( 30 CLASS 3 33mA second cycle alerts the PD that it is connected to a Type RE 2 PSE which can supply Type 2 power levels. UR 23mA C 20 TYPICAL CLASS 2 2-event ping-pong classification is enabled by setting a bit CLASS 3 14.5mA in the port’s High Power Mode register. Note that a ping- 10 PD LOAD CLASS 1 LINE 6.5mA pong enabled port only runs the second classification cycle CLASS 0 0 when it detects a Class 4 device; if the first cycle returns 0 5 10 15 20 25 VOLTAGE (VCLASS) Class 0 to 3, the port determines it is connected to a Type 1 429071 F13 PD and does not run the second classification cycle. Figure 13. PD Classification 429071fb 20 For more information www.linear.com/LTC4290

LTC4290/LTC4271 APPLICATIONS INFORMATION Invalid Type 2 Class Combinations nominally 12V. The inrush period is maintained until the t timer expires. At this time if the inrush current limit The 802.3at specification defines a Type 2 PD class START level is still exceeded, the port will be turned back off and signature as two consecutive Class 4 results; a Class 4 a t fault reported. followed by a Class 0-3 is not a valid signature. In AUTO START pin mode, the LTC4290/LTC4271 will power a detected Current Limit PD regardless of the classification results, with one excep- tion: if the PDpresents an invalid Type 2 signature (Class Each LTC4290/LTC4271 port includes two current limit- 4 followed by Class 0 to 3), the LTC4290/LTC4271 will ing thresholds (ICUT and ILIM), each with a corresponding not provide power and will restart the detection process. timer (tCUT and tLIM). Setting the ICUT and ILIM thresholds To aid in diagnosis, the Port Status register will always depends on several factors: the class of the PD, the volt- report the results of the last class pulse, so an invalid age of the main supply (VEE), the type of PSE (Type 1 or Class 4–Class 2 combination would report a second class Type 2), the sense resistor (0.5Ω or 0.25Ω), the SOA of pulse was run in the High Power Status register (which the MOSFET, and whether or not the system is required implies that the first cycle found class 4), and Class 2 in to enforce class current levels. the Port Status register. Per the IEEE specification, the LTC4290/LTC4271 will al- low the port current to exceed I for a limited period of CUT POWER CONTROL time before removing power from the port, whereas it will actively control the MOSFET gate drive to keep the port The primary function of the LTC4290/LTC4271 is to current below I . The port does not take any action to control the delivery of power to the PSE port. It does this LIM limit the current when only the I threshold is exceeded, by controlling the gate drive voltage of an external power CUT but does start the t timer. If the current drops below MOSFET while monitoring the current via an external sense CUT the I current threshold before its timer expires, the resistor and the output voltage at the OUT pin. This circuitry CUT t timer counts back down, but at 1/16 the rate that it serves to couple the raw V input supply to the port in CUT EE counts up. If the t timer reaches 60ms (typical) the a controlled manner that satisfies the PDs power needs CUT port is turned off and the port t fault is set. This allows while minimizing both power dissipation in the MOSFET CUT the current limit circuitry to tolerate intermittent overload and disturbances on the V backplane. EE signals with duty cycles below about 6%; longer duty cycle overloads will turn the port off. Inrush Control The I current limiting circuit is always enabled and ac- Once the command has been given to turn on a port, the LIM tively limiting port current. The t timer is enabled only LTC4290/LTC4271 ramps up the GATE pin of that port’s LIM when the t Enable bit is set. This allows t to be set external MOSFET in a controlled manner. Under normal LIM LIM to a shorter value than t to provide more aggressive power-up circumstances, the MOSFET gate will rise until CUT MOSFET protection and turn off a port before MOSFET the port current reaches the inrush current limit level damage can occur. The t timer starts when the I (typically 425mA), at which point the GATE pin will be LIM LIM threshold is exceeded. When the t timer reaches 12ms servoed to maintain the specified I current. During LIM INRUSH (typical) the port is turned off and the port t fault is this inrush period, a timer (t ) runs. When output LIM START set. When the t Enable bit is disabled t behaviors charging is complete, the port current will fall and the GATE LIM LIM are tracked by the t timer, which counts up during both pin will be allowed to continue rising to fully enhance the CUT I and I events. MOSFET and minimize its on-resistance. The final V is LIM CUT GS 429071fb 21 For more information www.linear.com/LTC4290

LTC4290/LTC4271 APPLICATIONS INFORMATION I is typically set to a lower value than I to allow the I Foldback CUT LIM LIM port to tolerate minor faults without current limiting. The LTC4290/LTC4271 features a two-stage foldback circuit Per the IEEE specification, the LTC4290/LTC4271 will that reduces the port current if the port voltage falls below automatically set I to 425mA (shown in bold in Table 6) the normal operating voltage. This keeps MOSFET power LIM during inrush at port turn-on, and then switch to the dissipation at safe levels for typical 802.3af MOSFETs, programmed I setting once inrush has completed. To even at extended 802.3at power levels. Current limit and LIM maintain IEEE compliance, I should be kept at 425mA foldback behavior are programmable on a per-port basis. LIM for all Type 1 PDs, and 850mA if a Type 2 PD is detected. Table 6 gives examples of recommended I register LIM I is automatically reset to 425mA when a port turns off. LIM settings. Table 6. Example Current Limit Settings The LTC4290/LTC4271 will support current levels well INTERNAL REGISTER SETTING (hex) beyond the maximum values in the 802.3at specification. ILIM (mA) RSENSE = 0.5Ω RSENSE = 0.25Ω The shaded areas in Table 6 indicate settings that may 53 88 require a larger external MOSFET, additional heat sinking, 106 08 88 or setting t Enable. LIM 159 89 213 80 08 MOSFET Fault Detection 266 8A LTC4290/LTC4271 PSE ports are designed to tolerate 319 09 89 significant levels of abuse, but in extreme cases it is pos- 372 8B sible for the external MOSFET to be damaged. A failed 425 00 80 MOSFET may short source to drain, which will make the 478 8E port appear to be on when it should be off; this condition 531 92 8A may also cause the sense resistor to fuse open, turning 584 CB off the port but causing the LTC4290 SENSE pin to rise 638 10 90 to an abnormally high voltage. A failed MOSFET may also 744 D2 9A short from gate to drain, causing the LTC4290 GATE pin 850 40 C0 to rise to an abnormally high voltage. The LTC4290 OUT, SENSE and GATE pins are designed to tolerate up to 80V 956 4A CA faults without damage. 1063 50 D0 1169 5A DA If the LTC4290/LTC4271 sees any of these conditions for 1275 60 E0 more than 180μs, it disables all port functionality, reduces 1488 52 49 the gate drive pull-down current for the port and reports 1700 40 a FET Bad fault. This is typically a permanent fault, but 1913 4A the host can attempt to recover by resetting the port, or 2125 50 by resetting the entire chip if a port reset fails to clear the 2338 5A fault. If the MOSFET is in fact bad, the fault will quickly 2550 60 return, and the port will disable itself again. The remaining 2975 52 ports of the LTC4290/LTC4271 are unaffected. An open or missing MOSFET will not trigger a FET Bad fault, but will cause a t fault if the LTC4290/LTC4271 START attempts to turn on the port. 429071fb 22 For more information www.linear.com/LTC4290

LTC4290/LTC4271 APPLICATIONS INFORMATION Port Current Readback Although not recommended, the DC disconnect feature can be disabled by clearing the corresponding enable bits. The LTC4290/LTC4271 measures the current at each port Note that this defeats the protection mechanisms built with an internal A/D converter. Port data is only valid when into the IEEE specification, since a powered port will stay the port power is on and reads zero at all other times. The powered after the PD is removed. If the still-powered port converter has two modes: is subsequently connected to a non-PoE data device, the • 100ms mode: Samples are taken continuously and the device may be damaged. measured value is updated every 100ms The LTC4290/LTC4271 does not include AC disconnect • 1s mode: Samples are taken continuously; a moving circuitry, but includes AC Disconnect Enable bits to main- 1 second average is updated every 100ms tain compatibility with the LTC4259A. If the AC Disconnect Enable bits are set, DC disconnect will be used. Port Current Policing Masked Shutdown The LTC4290/LTC4271 can augment t current moni- CUT toring with a policing function to track the one second The LTC4290/LTC4271 provides a low latency port shed- current averages. A port violating the user-specified Port ding feature to quickly reduce the system load when Police Threshold will be shut off with both a tCUT and required. By allowing a pre-determined set of ports to Police event recorded. A port current Police event can be be turned off, the current on an overloaded main power differentiated from a port tCUT violation by reading both supply can be reduced rapidly while keeping high priority events bits; both bits are set for a Police violation while devices powered. Each port can be configured to high or only the tCUT bit is set for tCUT timer violations. low priority; all low-priority ports will shut down within 6.5μs after the MSD pin is pulled low, high priority ports Port Voltage Readback will remain powered. If a port is turned off via MSD, the The LTC4290/LTC4271 measures the output voltage at corresponding Detection and Classification Enable bits are each port with an internal A/D converter. Port data is cleared, so the port will remain off until the host explicitly only valid when the port power is on and reads zero at re-enables detection. all other times. In the LTC4290/LTC4271 chipset the active level of MSD is register configurable as active high or low. The default Disconnect is LTC4266-compatible active low behavior. The LTC4290/LTC4271 monitors powered ports to ensure the PD continues to draw the minimum specified current. A VEE Readback disconnect timer counts up whenever port current is below The LTC4290/LTC4271 measures the V voltage with an EE 7.5mA (typ), indicating that the PD has been disconnected. internal 12-bit A/D converter. If the t timer expires, the port will be turned off and the DIS disconnect bit in the fault event register will be set. If the General Purpose IO current returns before the t timer runs out, the timer DIS Two sets of general purpose IO pins are available in the resets. As long as the PD exceeds the minimum current LTC4290/LTC4271 chipset. The first set of general purpose level more often than t , it will remain powered. DIS IO are GP1 and GP0. These fully bidirectional IO are 3.3V CMOS IO on the LTC4271 chip. 429071fb 23 For more information www.linear.com/LTC4290

LTC4290/LTC4271 APPLICATIONS INFORMATION The second set of general purpose IO pins are XIO1 and I2C ADDRESS I2C ADDRESS XIO0. These fully bidirectional IO are 4.3V CMOS IO on LTC4271 LTC4271 the LTC4290 chip. 0 0 D D A 0100000 3.3V A 0100111 U U Code Download Q Q AD0 AD0 AD1 AD1 LTC4271 firmware is field-upgradable by downloading AD2 AD2 AD3 AD3 and executing RAM images. RAM images are volatile AD6 AD6 1 1 and must be re-downloaded after each V power cycle, AD 0100001 AD 0101000 DD U U Q Q but will remain valid during reset and V power events. EE Contact Linear Technology for code download procedures SCL SCL and RAM images. SDAIN SDAIN SDAOUT SDAOUT SCL 429071 F14 SERIAL DIGITAL INTERFACE SDA Overview Figure 14. Example I2C Bus Addressing The LTC4290/LTC4271 communicates with the host us- ing a standard SMBus/I2C 2-wire interface. The LTC4290/ is asserting the INT pin, it will also respond to the alert LTC4271 is a slave-only device, and communicates with response address (0001100b) per the SMBus specification. the host master using the standard SMBus protocols. Each LTC4290/LTC4271 is logically composed of two quads Interrupts are signaled to the host via the INT pin. The of four ports each. Each quad occupies separate, contigu- Timing Diagrams (Figures 5 through 9) show typical ous I2C addresses. The AD6, AD3-0 pins set the address communication waveforms and their timing relationships. of the base quad while the second quad is consecutively More information about the SMBus data protocols can be numbered. I2C addresses outside of the x10xxxxb range found at www.smbus.org. are considered illegal and will not respond. Each internal The LTC4290/LTC4271 requires both the VDD and VEE sup- quad is independent of the other quad, with the exception ply rails to be present for the serial interface to function. of writes to the Chip Reset, MSD Inversion and General Purpose Input Output registers. These registers are global Bus Addressing in nature and will affect all quads. The LTC4290/LTC4271’s primary 7-bit serial bus address Interrupts and SMBAlert is A 10A A A A b, with bit 6 controlled by AD6 and the 6 3 2 1 0 lower four bits set by the AD3-AD0 pins; this allows up to Most LTC4290/LTC4271 port events can be configured 16 LTC4290/LTC4271s, on a single bus. Sixteen LTC4290/ to trigger an interrupt, asserting the INT pin and alerting LTC4271 are equivalent to 32 quad PSEs or 128 ports. All the host to the event. This removes the need for the host LTC4290/LTC4271s also respond to the broadcast address to poll the LTC4290/LTC4271, minimizing serial bus traf- 0110000b, allowing the host to write the same command fic and conserving host CPU cycles. Multiple LTC4290/ (typically configuration commands) to multiple LTC4290/ LTC4271s can share a common INT line, with the host LTC4271s in a single transaction. If the LTC4290/LTC4271 using the SMBAlert protocol (ARA) to determine which LTC4290/LTC4271 caused an interrupt. 429071fb 24 For more information www.linear.com/LTC4290

LTC4290/LTC4271 APPLICATIONS INFORMATION Register Description EXTERNAL COMPONENT SELECTION For information on serial bus usage and device configura- Power Supplies and Bypassing tion and status, refer to the LTC4271 Software Program- ming documentation. The LTC4290/LTC4271 requires two supply voltages to operate. V requires 3.3V (nominally) relative to DGND. DD V requires a negative voltage of between –45V and ISOLATION REQUIREMENTS EE –57V for Type 1 PSEs, –51V to –57V for Type 2 PSEs, IEEE 802.3 Ethernet specifications require that network or –54.75V to –57V for LTPoE++ PSEs, relative to AGND. segments (including PoE circuitry) be electrically isolated from the chassis ground of each network interface de- Digital Power Supply vice. However, network segments are not required to be V provides digital power for the LTC4271 processor, DD isolated from each other, provided that the segments are and draws a maximum of 15mA. A ceramic decoupling connected to devices residing within a single building on cap of at least 0.1μF should be placed from V to DGND, DD a single power distribution system. as close as practical to each LTC4271 chip. A 1.8V core For simple devices such as small PoE switches, the isola- voltage supply is generated internally and requires a 1µF tion requirement can be met by using an isolated main ceramic decoupling cap between the CAP1 pin and DGND. power supply for the entire device. This strategy can be In the LTC4290/LTC4271, V should be delivered by the DD used if the device has no electrically conducting ports host controller’s non-isolated 3.3V supply. To maintain other than twisted-pair Ethernet. In this case, the SDAIN required isolation AGND and DGND must not be con- and SDAOUT pins can be tied together and will act as a nected in any way. standard I2C/SMBus SDA pin. If the device is part of a larger system, contains additional Main PoE Power Supply external non-Ethernet ports, or must be referenced to V is the main isolated PoE supply that provides power EE protective ground for some other reason, the Power over to the PDs. Because it supplies a relatively large amount Ethernet subsystem must be electrically isolated from the of power and is subject to significant current transients, rest of the system. it requires more design care than a simple logic supply. The LTC4290/LTC4271 chipset simplifies PSE isolation by For minimum IR loss and best system efficiency, set VEE allowing the LTC4271 chip to reside on the non-isolated near maximum amplitude (57V), leaving enough margin side. There it can receive power from the main logic sup- to account for transient over or undershoot, temperature ply and connect directly to the I2C/SMBus bus. Isolation drift, and the line regulation specifications of the particular between the LTC4271 and LTC4290 is implemented using power supply used. a proprietary transformer-based communication protocol. Bypass capacitance between AGND and V is very im- EE Additional details are provided in the Serial Bus Isolation portant for reliable operation. If a short circuit occurs at section of this data sheet. one of the output ports it can take as long as 1μs for the LTC4290 to begin regulating the current. During this time the current is limited only by the small impedances in the circuit and a high current spike typically occurs, causing a 429071fb 25 For more information www.linear.com/LTC4290

LTC4290/LTC4271 APPLICATIONS INFORMATION 3.3V 0.1µF GP0 VDD33 XIO0 XIO1 0.22µF 100V S1B GP1 NROEQ IUSOIRLEADT IOONN MID CPD CPA OUTn PORTn I2C INTERFACE RESET 100Ω(cid:127) (cid:127) 100Ω MSD 3.3V –54V GATEn S1B AUTO 0.25Ω INT 100Ω 100Ω SENSEn –54V CND CNA LTC4271 T1 LTC4290 SCL SDAIN DPD DPA 0.22µF 100V S1B SDAOUT 100Ω 100Ω (cid:127) (cid:127) OUT1 PORT1 3.3V –54V AD0 AD1 100Ω 100Ω GATE1 S1B AD2 DND DNA AD3 T2 0.25Ω AD6 DGND CAP1 10Ω AGND CAP2 VEE VSSK SENSE1 –54V 429071 F15 1µF 0.1µF + 2nF 2kV 1µF >47µF SYSTEM BULK CAP –54V –54V Figure 15. LTC4290/LTC4271 Proprietary Isolation voltage transient on the V supply and possibly causing External MOSFET EE the LTC4290/LTC4271 to reset due to a UVLO fault. A 1μF, Careful selection of the power MOSFET is critical to system 100V X7R capacitor placed near the V pin along with an EE reliability. LTC recommends either Fairchild IRFM120A, electrolytic bulk capacitor of at least 47µF is recommended FDT3612, FDMC3612 or Philips PHT6NQ10T for their to minimize spurious resets. proven reliability in Type 1 and Type 2 PSE applications. SOA curves are not a reliable specification for MOSFET Serial Bus Isolation selection. Contact LTC Applications before using a MOSFET The LTC4290/LTC4271 chipset uses transformers to other than one of these recommended parts. isolate the LTC4271 from the LTC4290. In this case, the SDAIN and SDAOUT pins can be shorted to each other Sense Resistor and tied directly to the I2C/SMBus bus. The transformers The LTC4290/LTC4271 is designed to use 0.25Ω current should be 10BASE-T or 10/100BASE-T with a 1:1 turns sense resistors to reduce power dissipation. Four com- ratio. It is important that the selected transformers do not monly available 1Ω resistors (sized according to power have common-mode chokes. These transformers typically dissipation) can be used in parallel in place of a single provide 1500V of isolation between the LTC4271 and the 0.25Ω resistor. In order to meet the I and I accuracy CUT LIM LTC4290. For proper operation strict layout guidelines required by the IEEE specification, the sense resistors must be met. should have ±1% tolerance or better, and no more than ±200ppm/°C temperature coefficient. In addition, the sense resistors must meet strict layout guidelines. 429071fb 26 For more information www.linear.com/LTC4290

LTC4290/LTC4271 APPLICATIONS INFORMATION Port Output Cap Each LTC4290 requires a 10Ω, 0805 resistor (R1) in series from supply AGND to the LTC4290 AGND pin. Across the Each port requires a 0.22μF cap across its outputs to keep LTC4290 AGND pin and V pin are an SMAJ58A, 58V the LTC4290 stable while in current limit during startup EE TVS (D1) and a 1µF, 100V bypass capacitor (C1). These or overload. Common ceramic capacitors often have sig- components must be placed close to the LTC4290 pins. nificant voltage coefficients; this means the capacitance is reduced as the applied voltage increases. To minimize this Finally, each port requires a pair of S1B clamp diodes: problem, X7R ceramic capacitors rated for at least 100V one from OUTn to supply AGND and one from OUTn to are recommended and must be located close to the PSE. supply V . The diodes at the ports steer harmful surges EE into the supply rails where they are absorbed by the surge Surge Protection suppressors and the V bypass capacitance. The layout EE of these paths must be low impedance. Ethernet ports can be subject to significant cable surge events. To keep PoE voltages below a safe level and protect the application against damage, protection components, LAYOUT GUIDELINES as shown in Figure 16, are required at the main supply, Strict adherence to board layout, parts placement and at the LTC4290 supply pins and at each port. routing guidelines is critical for optimal current reading Bulk transient voltage suppression (TVS ) and bulk accuracy, IEEE compliance, system robustness, and BULK capacitance (C ) are required across the main PoE thermal dissipation. Refer to the DC1842A Demo Board BULK supply and should be sized to accommodate system level as a layout reference. Contact LTC Applications to obtain surge requirements. a full set of layout guidelines, example layouts and BOMs. R1 10Ω AGND C1 1µF 100V D1 LTC4290 + SMAJ58A VEE CBULK VSSK SENSEn GATEn OUTn Cn TVSBULK 0.22µF X7R S1B 100V OUTn VEE TO RSENSEn Qn PORT S1B VEE 429071 F16 Figure 16. LTC4290 Surge Protection 429071fb 27 For more information www.linear.com/LTC4290

LTC4290/LTC4271 TYPICAL APPLICATION 8 7 5R RJ4CTO 1 2 3 4 5 6 7 8 2 NE 1 CON RJ450.01µFCONNECTOR200V1 2 3 4 5 60.01µF7200V8 429071 TA02 1µF0V 1µF0V 00 00 0.2Ω 0.2Ω 5 5 7 7 Ω Ω 1µF0V75 1µF0V75 00 00 0.2 0.2 F 0.22µ100VX7R C3612 (cid:127) (cid:127) (cid:127) (cid:127) M D B 1B %F S1 T1 (cid:127) (cid:127) (cid:127) (cid:127) S 1 RS Ω, 5 2 0. (cid:127) (cid:127) (cid:127) (cid:127) ort PSE PHY (NETWORK PHYSICAL LAYER CHIP) P - 8 Complete XIO0XIO1CPAOUT8GATE8SENSE8 LTC4290CNAOUT1DPAGATE1SENSE1 DNA AGNDVVSSKCAP2EE 1µF100V0.1µFX7R –54VISOLATED ISOLATEDGND +>47µFSYSTEMBULK CAP–54V –54V –54V 10Ω SMAJ-58A 1µF (cid:127)(cid:127) T2 (cid:127)(cid:127) T3 1µF MCJ58A F 2000V S 2n Ω Ω Ω Ω 100 3.3V 100 100 3.3V 100 1µF CPD CNDDPD DND µF 0. 1 1 1 P 3.3V VDD33 LTC427 T NDCA GP0GP1MIDRESETMSDAUTOINTSCLSDAINSDAOUAD0AD1AD2AD3AD6 DG 429071fb 28 For more information www.linear.com/LTC4290

LTC4290/LTC4271 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 0.70 0.05 4.50 0.05 2.45 0.05 3.10 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.20 TYP OR 4.00 0.10 0.75 0.05 R = 0.115 0.35 x 45º CHAMFER TYP (4 SIDES) 23 24 PIN 1 0.40 0.10 TOP MARK (NOTE 6) 1 2 2.45 0.10 (4-SIDES) (UF24) QFN 0105 0.200 REF 0.25 0.05 0.00 – 0.05 0.50 BSC NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION 5. EXPOSED PAD SHALL BE SOLDER PLATED (WGGD-X)—TO BE APPROVED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION 2. DRAWING NOT TO SCALE ON THE TOP AND BOTTOM OF PACKAGE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 429071fb 29 For more information www.linear.com/LTC4290

LTC4290/LTC4271 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UJ Package 40-Lead Plastic QFN (6mm × 6mm) (Reference LTC DWG # 05-08-1728 Rev Ø) 0.70 0.05 6.50 0.05 5.10 0.05 4.42 0.05 4.50 0.05 (4 SIDES) 4.42 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 6.00 0.10 0.75 0.05 R = 0.115 (4 SIDES) R = 0.10 TYP 39 40 TYP 0.40 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2 PIN 1 NOTCH R = 0.45 OR 0.35 x 45º CHAMFER 4.50 REF 4.42 0.10 (4-SIDES) 4.42 0.10 (UJ40) QFN REV Ø 0406 0.200 REF 0.25 0.05 0.00 – 0.05 0.50 BSC NOTE: BOTTOM VIEW—EXPOSED PAD 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 429071fb 30 For more information www.linear.com/LTC4290

LTC4290/LTC4271 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 4/13 Added A-grade and C-grade to entire data sheet 1 - 32 B 07/15 Updated surge protection recommendations 1, 26, 27, 28, 32 Simplified Power over Ethernet system diagram 16 429071fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 31 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconneFctoiorn m ofo irtse ciinrcfuoirtsm aast dioesnc rwibwedw h.leirneeina wr.cilol nmot/ LinTfrCin4g2e9 o0n existing patent rights.

LTC4290/LTC4271 TYPICAL APPLICATION Complete 8-Port PSE 3.3V 0.1µF 1µF 8 7 GP0 VDD33 XIO0 XIO1 GP1 CPD CPA 2 MID OUT8 1 RESET 100Ω (cid:127) (cid:127) GATE8 MAUSTDO 3.3V –54V SENSE8 0.22µF INT LTC4271 100Ω LTC4290 100V SSSCDDLAAIONUT DCNPDD T2 DCNPAA OUT1 S1B X7R GATE1 AAADDD012 31.030VΩ (cid:127) (cid:127) –54V SENSE1 RS RJ45 AD3 100Ω 0.25Ω, 1% FDMC3612 CONNECTOR AD6 DND T3 DNA 1 DGND CAP1 1µF 10Ω AGNDCAP2 VEEVSSK S1B CO02N.00N10EµVCFRTJO4R5 23 1µF SMCJ58A 11µ0F0V 0.1µF (cid:127) T1 (cid:127) 0.01µF 0.01µF 12 45 X7R 200V 200V 3 6 2nF 2000V SM58AAJ- ISO–L5A4TVED PHY (cid:127) (cid:127)(cid:127) (cid:127) 75Ω 75Ω 45 78 6 ISOLATED (NETWORK 02.0010µVF 7 GND PHYSICAL 8 >47µF+ LCAHYIEPR) (cid:127) (cid:127) 0.01µF 0.01µF SYSTEM 200V 200V BULK CAP (cid:127) 75Ω 75Ω –54V (cid:127) (cid:127) (cid:127) 429071 TA03 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC4257-1 IEEE 802.3af PD Interface Controller Internal 100V, 400mA Switch, Dual Current Limit, Programmable Class LTC4263 Single IEEE 802.3af PSE Controller Internal FET Switch LTC4265 IEEE 802.3at PD Interface Controller Internal 100V, 1A Switch, 2-Event Classification Recognition LTC4266 Quad IEEE 802.3at PoE PSE Controller With Programmable I /I , 2-Event Classification, and Port Current and Voltage Monitoring CUT LIM LTC4267 IEEE 802.3af PD Interface With Integrated Internal 100V, 400mA Switch, Dual Inrush Current, Programmable Class Switching Regulator LTC4267-1 IEEE 802.3af PD Interface With Integrated Internal 100V, 400mA Switch, Programmable Class, 200kHz Constant Frequency PWM Switching Regulator LTC4267-3 IEEE 802.3af PD Interface With Integrated Internal 100V, 400mA Switch, Programmable Class, 300kHz Constant Frequency PWM Switching Regulator LTC4269-1 IEEE 802.3af PD Interface With Integrated 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller, Flyback Switching Regulator 50kHz to 250kHz, Aux Support LTC4269-2 IEEE 802.3af PD Interface With Integrated 2-Event Classification, Programmable Class, Synchronous Forward Controller, 100kHz to Forward Switching Regulator 500kHz, Aux Support LTC4270/ 12-Port PoE/PoE+/LTPoE++™ PSE Transformer Isolation, Supports Type 1, Type 2 and LTPoE++ PDs LTC4271 Controller LTC4274 Single IEEE 802.3at PoE PSE Controller With Programmable I /I , 2-Event Classification, and Port Current and Voltage Monitoring CUT LIM LT4275 PoE/PoE+/LTPoE++ PD Controller External MOSFET, Programmable Class, –40°C to 125°C Operation LTC4278 IEEE 802.3af PD Interface With Integrated 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller, Flyback Switching Regulator 50kHz to 250kHz, 12V Aux Support LTC4311 SMBus/ I2C Accelerator Improved I2C Rise Time, Ensures Data Integrity 429071fb 32 Linear Technology Corporation LT 0715 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC4290 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC4290  LINEAR TECHNOLOGY CORPORATION 2012