LTC4257 IEEE 802.3af PD Power over Ethernet Interface Controller FEATURES DESCRIPTIOU ■ Complete Power Interface Port for IEEE 802.3af® The LTC®4257 provides complete signature and power Powered Devices (PDs) interface functions for a device operating in an IEEE ■ Onboard 100V, 400mA Power MOSFET 802.3af Power over Ethernet (PoE) system. The LTC4257 ■ Precision Input Current Limit simplifies Powered Device (PD) design by incorporating ■ Onboard 25k Signature Resistor the 25k signature resistor, the classification current source, ■ Programmable Classification Current (Class 0-4) input current limit with thermal foldback, undervoltage ■ Undervoltage Lockout lockout and power good signalling, all in a single 8-pin ■ Smart Thermal Protection package. By incorporating a high voltage power MOSFET ■ Power Good Signal onboard, the LTC4257 provides the system designer with ■ Available in 8-Pin SO and Low Profile (3mm × 3mm) reduced cost while also saving board space. DFN Packages The LTC4257 can interface directly with a variety of Linear Technology DC/DC converter products to provide a cost APPLICATIOU S effective power solution for IP phones, wireless access points and other PDs. Linear Technology also provides ■ IP Phone Power Management solutions for Power Sourcing Equipment (PSE) applica- ■ Wireless Access Points tions with quad network power controllers. ■ Telecom Power Control The LTC4257 is available in the 8-pin SO and low profile (3mm × 3mm) DFN packages. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATIOU LTC4257 Charging 300µF Load Capacitor Powered Device (PD) VIN 50V/DIV –48V FROM ~ + SMAJ58A LTC4257GND + VIN 20VV/ODUIVT POWEQERU ISPOMUERNCTING DF01SA 0.1µF RCLASS 100k M5µINF POSWWEIRTC SHUIPNPGLY + (PSE) ~ – RCLASS PWRGD SHDNRTN 3.3V 200mA/DIIIVN TO LOGIC VIN VOUT – 4257 TA01 PWRGD 50V/DIV 5ms/DIV 4225 TA02 4257fb 1

LTC4257 ABSOLUTE W AXIW UW RATIU GS (Notes 1, 2) Operating Ambient Temperature Range V Voltage ............................................. 0.3V to –100V IN V , PWRGD Voltage.............V + 100V to V – 0.3V LTC4257C ...............................................0°C to 70°C OUT IN IN R Voltage ............................V + 7V to V – 0.3V LTC4257I.............................................–40°C to 85°C CLASS IN IN Storage Temperature Range PWRGD Current .................................................. 10mA R Current .................................................. 100mA S8 Package....................................... –65°C to 150°C CLASS DD Package...................................... –65°C to 125°C Lead Temperature (Soldering, 10 sec)..................300°C PACKAGE/ORDER IU FORW ATIOU TOP VIEW TOP VIEW NC 1 8 GND NC 1 8 GND RCLASS 2 7 NC NC 3 6 PWRGD RCLASS 2 7 NC NC 3 6 PWRGD VIN 4 5 VOUT VIN 4 5 VOUT DD PACKAGE S8 PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN 8-LEAD PLASTIC SO TJMAX = 125°C, θJA = 43°C/W TJMAX = 150°C, θJA = 150°C/W EXPOSED PAD TO BE SOLDERED TO ELECTRICALLY ISOLATED PCB HEATSINK ORDER PART NUMBER S8 PART MARKING ORDER PART NUMBER DD PART MARKING* LTC4257CS8 4257 LTC4257CDD LACT LTC4257IS8 4257I LTC4257IDD Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grades are identified by a label on the shipping container. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Supply Voltage Voltage with Respect to GND Pin (Notes 4, 5, 6) IN Maximum Operating Voltage ● –57 V Signature Range ● –1.5 –9.5 V Classification Range ● –12.5 –21 V UVLO Turn-On Voltage ● –37.7 –39.2 –40.2 V UVLO Turn-Off Voltage ● –29.3 –30.5 –31.5 V I IC Supply Current when ON V = –48V, Pins 5, 6 Floating ● 3 mA IN_ON IN I IC Supply Current During Classification V = –17.5V, Pin 2 Floating, V Tied to GND ● 0.35 0.50 0.65 mA IN_CLASS IN OUT (Note 7) ∆ICLASS Current Accuracy During Classification 10mA < ICLASS < 40mA, –12.5V ≤ VIN ≤ –21V, ● ±3.5 % (Notes 8, 9) 4257fb 2

LTC4257 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS RSIGNATURE Signature Resistance –1.5V ≤ VIN ≤ –9.5V, VOUT Tied to GND, ● 23.25 26.00 kΩ IEEE 802.3af 2-Point Measurement (Notes 4, 5) V Power Good Output Low Voltage I = 1mA, V = –48V, PWRGD Referenced to V ● 0.5 V PG_OUT IN IN Power Good Trip Point V = –48V, Voltage Between V and V (Note 9) IN IN OUT V V Falling ● 1.3 1.5 1.7 V PG_THRES_FALL OUT V V Rising ● 2.7 3.0 3.3 V PG_THRES_RISE OUT IPG_LEAK Power Good Leakage VIN = 0V, PWRGD FET Off, VPWRGD = 57V ● 1 µA RON On-Resistance I = 300mA, VIN = –48V, Measured from VIN to VOUT 1.0 1.6 Ω (Note 9) ● 2.0 Ω IOUT_LEAK VOUT Leakage VIN = 0V, Power MOSFET Off, VOUT = 57V (Note 10) ● 150 µA I Input Current Limit V = –48V, V = –43V (Note 11) ● 300 350 400 mA LIMIT IN OUT I Overtemperature Input Current Limit (Note 11) 188 mA LIMIT_WARM TOVERTEMP Overtemperature Trip Temperature (Note 11) 120 °C TSHUTDOWN Thermal Shutdown Trip Temperature (Note 11) 140 °C Note 1: Stresses beyond those listed under Absolute Maximum Ratings power up from a voltage source with 20Ω series resistance on the first may cause permanent damage to the device. Exposure to any Absolute trial. Maximum Rating condition for extended periods may affect device Note 7: I does not include classification current programmed at IN_CLASS reliability and lifetime. Pin 2. Total supply current in classification mode will be I + I IN_CLASS CLASS Note 2: All voltages are with respect to GND pin. (see Note 8). Note 3: The LTC4257 operates with a negative supply voltage in the range Note 8: I is the measured current flowing through R . CLASS CLASS of –1.5V to –57V. To avoid confusion, voltages in this data sheet are ∆ICLASS accuracy is with respect to the ideal current defined as always referred to in terms of absolute magnitude. Terms such as I = 1.237/R . The current accuracy specification does not CLASS CLASS “maximum negative voltage” refer to the largest negative voltage and a include variations in R resistance. The total classification current for CLASS “rising negative voltage” refers to a voltage that is becoming more a PD also includes the IC quiescent current (I ). See Applications IN_CLASS negative. Information. Note 4: The LTC4257 is designed to work with two polarity protection Note 9: For the DD package, this parameter is assured by design and diodes between the PSE and PD. Parameter ranges specified in the wafer level testing. Electrical Characteristics are with respect to LTC4257 pins and are Note 10: I includes current drawn at the V pin by the power OUT_LEAK OUT designed to meet IEEE 802.3af specifications when these diode drops are good status circuit. This current is compensated for in the 25kΩ signature included. See Applications Information. resistance and does not affect PD operation. Note 5: Signature resistance is measured via the 2-point ∆V/∆I method as Note 11: The LTC4257 includes smart thermal protection. In the event of defined by IEEE 802.3af. The LTC4257 signature resistance is offset from an overtemperature condition, the LTC4257 will reduce the input current 25k to account for diode resistance. With two series diodes, the total PD limit by 50% to reduce the power dissipation in the package. If the part resistance will be between 23.75k and 26.25k and meet IEEE 802.3af continues heating and reaches the shutdown temperature, the current is specifications. The minimum probe voltages measured at the LTC4257 reduced to zero until the part cools below the overtemperature limit. The pins are –1.5V and –2.5V. The maximum probe voltages are –8.5V and LTC4257 is also protected against thermal damage from incorrect –9.5V. classification probing by the PSE. If the LTC4257 exceeds the Note 6: The LTC4257 includes hysteresis in the UVLO voltages to preclude overtemperature trip point, the classification load current is disabled. any start-up oscillation. Per IEEE 802.3af requirements, the LTC4257 will 4257fb 3

LTC4257 TYPICAL PERFORW AU CE CHARACTERISTICS Input Current vs Input Voltage 25k Detection Range Input Current vs Input Voltage Input Current vs Input Voltage 0.5 50 12.0 TA = 25°C TA = 25°C CLASS 1 OPERATION CLASS 4 11.5 0.4 40 A) A) A) m m m11.0 NT ( 0.3 NT ( 30 CLASS 3 NT ( E E E 85°C R R R10.5 R R R U U U T C 0.2 T C 20 CLASS 2 T C –40°C U U U10.0 P P P IN IN CLASS 1 IN 0.1 10 9.5 CLASS 0 0 0 9.0 0 –2 –4 –6 –8 –10 0 –10 –20 –30 –40 –50 –60 –12 –14 –16 –18 –20 –22 INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V) 4357 G02 4257 G01 4257 G03 Signature Resistance Normalized UVLO Threshold Input Current vs Input Voltage vs Input Voltage vs Temperature 3 28 2 EXCLUDES ANY LOAD CURRENT RESISTANCE = ∆V= V2 – V1 APPLICABLE TO TURN-ON mA) 2 TA = 25°C CE (k)Ω 2267 DTAIO =D 2E5S°:C S1B ∆I IIE2 E–E I 1UPPER LIMIT SHOLD (%) 1 AND TURN-0FF THRESHOLDS T ( AN RE N T H INPUT CURRE 1 SIGNATURE RESIS 222453 LTC4257 LOTNCL4Y257 +I E2E DE ILOODWESER LIMIT RMALIZED UVLO T –10 O N 0 22 –2 –40 –45 –50 –55 –60 V1: –1 –3 –5 –7 –9 –40 –20 0 20 40 60 80 INPUT VOLTAGE (V) V2: –2 –4 –6 –8 –10 TEMPERATURE (°C) INPUT VOLTAGE (V) 4257 G04 4257 G05 4257 G06 Power Good Output Low Voltage vs Current V Leakage Current Current Limit vs Input Voltage OUT 4 120 375 TA = 25°C VIN = 0V VOUT = VIN + 5V TA = 25°C 365 3 90 A)µ mA) 85°C V (V)PG_OUT 12 V CURRENT (OUT 3600 CURRENT LIMIT ( 334555 –2450°°CC 335 0 0 325 0 2 4 6 8 10 0 20 40 60 –40 –45 –50 –55 –60 CURRENT (mA) VOUT PIN VOLTAGE (V) INPUT VOLTAGE (V) 4257 G07 42571 G09 4257 G09 4257fb 4

LTC4257 PIU FUU CTIOU S NC (Pin 1): No Connect. PWRGD (Pin 6): Power Good Output, Open-Drain. Signals that the LTC4257 MOSFET is fully on. Low impedance R (Pin 2): External Class Select Input. Used to set the CLASS indicates power is good. PWRGD is high impedance current the LTC4257 maintains during classification. Con- during detection, classification and in the event of a nect a resistor between R and V (see Table 2). CLASS IN thermal overload. PWRGD is referenced to V . IN NC (Pin 3): No Connect. NC (Pin 7): No Connect V (Pin 4): Power Input. Tie to system –48V through the IN GND (Pin 8): Ground. Tie to system ground and to power input diode bridge. return through the input diode bridge. V (Pin 5): Power Output. Supplies –48V to the PD load OUT through an internal power MOSFET that limits input cur- rent. V is high impedance until the input voltage rises OUT above the turn-on UVLO threshold. Above the UVLO threshold the output is current limited to 350mA. BLOCK DIAGRAW CLASSIFICATION CURRENT SOURCE NC 1 1.237V + 8 GND – EN 25k SIGNATURE RESISTOR 7 NC RCLASS 2 6 PWRGD POWER GOOD CONTROL NC 3 CIRCUITS INPUT CURRENT EN 350mA + LIMIT – 0.3Ω VIN 4 5 VOUT BOLD LINE INDICATES HIGH CURRENT PATH 4257 BD 4257fb 5

LTC4257 APPLICATIOU S IU FORW ATIOU The LTC4257 is intended for use as the front end of a DETECTION V1 TIME Powered Device (PD) designed to IEEE 802.3af draft DETECTION V2 –10 CLASSIFICATION standard. The LTC4257 includes a trimmed 25k signature resistor, classification current source, and an inrush cur- V (V)IN––2300 UVLO UTUVRLON-OFF rent limit circuit. With these functions integrated into the TURN-ON –40 LTC4257, the signature and power interface for a PD that –50 meets all the requirements of IEEE 802.3af can be built with a minimum of external components. TIME –10 τ = RLOAD C1 Using an LTC4257 for the power and signature interface functions of a PD provides several advantages. The (V)UT–20 UOVFLFO UOVNLO UOVFLFO LTC4257 current limit circuit includes an onboard, 100V, VO–30 dV=ILIMIT dt C1 400mA power MOSFET with low leakage. This onboard –40 low leakage MOSFET avoids the possibility of corrupting –50 the 25k signature resistor while also saving board space TIME and cost. In addition, the IEEE 802.3af inrush current limit –10 requirement causes large transient power dissipation in V) POWER POWER POWER the PD; the LTC4257 manages this turn-on sequence GD ( –20 BAD GOOD BAD WR –30 through the use of smart thermal protection circuitry. The P –40 LTC4257 is designed to allow multiple turn-on sequences PWRGD TRACKS –50 VIN without overheating the miniature 8-lead package. In the event of excessive power cycling, the LTC4257 provides CURRENT thermally activated current-limit reduction to keep the ILIMIT LIMIT, ILIMIT onboard power MOSFET within its safe operating area. NT LOAD CURRENT, ILOAD E R Operation CUR ICLASS CLASSIFICATION PD ICLASS The LTC4257 has several modes of operation depending DETECTION I2 on the applied input voltage as shown in Figure 1 and DETECTION I1 summarized in Table 1. These various modes satisfy the V1 – 2 DIODE DROPS I1 = requirements defined in the IEEE 802.3af specification. 25kΩ V2 – 2 DIODE DROPS The input voltage is applied to the VIN pin and is with I2 = 25kΩ reference to the GND pin. This input voltage is always ICLASS DEPENDENT ON RCLASS SELECTION negative. To avoid confusion, voltages in this data sheet ILIMIT = 350mA (NOMINAL) are always referred to in terms of absolute magnitude. ILOAD = RLVOINAD Terms such as maximum negative voltage refer to the GND largest negative voltage and a rising negative voltage LTC4257 refers to a voltage that is becoming more negative. Refer- IIN 2 RCLASSGND 8 R9 RLOAD ences to electrical parameters in this applications section PSE VIN RCLASS PWRGD 6 C1 VOUT use the nominal value. Refer to the Electrical Characteris- 4 5 tics section for the range of values a particular parameter VIN VOUT 4257 F01 will have. Figure 1. Output Voltage, PWRGD and PD Current as a Function of Input Voltage 4257fb 6

LTC4257 APPLICATIOU S IU FORW ATIOU Table 1. LTC4257 Operational Mode Detection as a Function of Input Voltage During detection, the PSE will apply a voltage in the range INPUT VOLTAGE of –2.8V to –10V on the cable and look for a 25k signature (V with RESPECT to GND) LTC4257 MODE OF OPERATION IN resistor. This identifies the device at the end of the cable 0V to –1.4V Inactive as a PD. With the terminal voltage in this range, the LTC4257 –1.5V to –10V 25k Signature Resistor Detection connects an internal 25k resistor between GND and the V –11V to –12.4V Classification Load Current Ramps up from IN 0% to 100% pins. This precision, temperature compensated resistor presents the proper characteristics to alert the Power –12.5V to UVLO* Classification Load Current Active Sourcing Equipment (PSE) at the other end of the cable that UVLO* to –57V Power Applied to PD Load a PD is present and desires power to be applied. *UVLO includes hysteresis. Rising input threshold ≅ –39.2V The power applied to a PD is allowed to use either of two Falling input threshold ≅ –30.5V polarities and the PD must be able to accept this power so it is common to install a diode bridge on the input. The Series Diodes LTC4257 is designed to compensate for the voltage and The IEEE 802.3af defined operating modes for a PD resistance effects of these two series diodes. The signa- reference the input voltage at the RJ45 connector on the ture range extends below the IEEE range to accommodate PD. However, PD circuitry must include diode bridges the voltage drop of the diodes. The IEEE specification between the RJ45 connector and the LTC4257 (Figure 2). requires the PSE to use a ∆V/∆I measurement technique The LTC4257 takes this into account by compensating for to keep the DC offset of these diodes from affecting the these diode drops in the threshold points for each range of signature resistance measurement. However, the diode operation. Since the voltage ranges specified in the LTC4257 resistance appears in series with the signature resistor electrical specifications are with respect to the IC pins for and must be included in the overall signature resistance both the signature and classification ranges, the LTC4257 of the PD. The LTC4257 compensates for the two series lower end extends two diode drops below the IEEE 802.3af diodes in the signature path by offsetting the resistance specification. A similar adjustment is made for the UVLO so that a PD built using the LTC4257 will meet the IEEE voltages. requirements. RJ45 TX+ T1 1 TX– BR1 2 RX+ TO PHY 3 RX– POWERED DEVICE (PD) 6 8 INTERFACE GND AS DEFINED SPARE+ BY IEEE 802.3af 4 BR2 LTC4257 5 D3 4 VIN 7 SPARE– 4257 F02 8 Figure 2. PD Front End Using Diode Bridges on Main and Spare Inputs 4257fb 7

LTC4257 APPLICATIOU S IU FORW ATIOU Classification Measured Current and Measured Voltage. The IEEE has since removed the Measured Voltage method from the Once the PSE has detected a PD, the PSE may optionally specification. The LTC4257 is compatible with the IEEE classify the PD. Classification provides a method for more 802.3af standard and also works with the obsolete Mea- efficient allocation of power by allowing the PSE to identify sured Voltage method. lower-power PDs and allocate less power for these de- vices. IEEE 802.3af defines five classes (Table 2) with In the Measured Current method (Figure 3), the PSE varying power levels. The designer selects the appropriate presents a fixed voltage between –15.5V and –20V to the classification based on the power consumption of the PD. PD. With the input voltage in this range, the LTC4257 For each class, there is an associated load current that the asserts a load current from the GND pin through the PD asserts onto the line during classification probing. The R resistor. The magnitude of the load current is set CLASS PSE measures the PD load current to determine the proper with the selection of the R resistor. The resistor value CLASS classification and PD power requirements. associated with each class is shown in Table 2. Table 2. Summary of IEEE 802.3af Power Classifications and In the Measured Voltage method (Figure 4), the PSE drives LTC4257 RCLASS Resistor Selection a current into the PD and monitors the voltage across the MAXIMUM NOMINAL LTC4257 PD terminals. The PSE current steps between classifica- POWER LEVELS CLASSIFICATION R CLASS tion load current values in order to classify the PD under AT INPUT OF PD LOAD CURRENT RESISTOR CLASS USAGE (W) (mA) (Ω, 1%) test. For PSE probe currents below the PD load current, the 0 Default 0.44 to 12.95 <5 Open LTC4257 will keep the PD terminal voltage below the 1 Optional 0.44 to 3.84 10.5 124 classification voltage range. For PSE probe currents above 2 Optional 3.84 to 6.49 18.5 68.1 the PD load current, the LTC4257 will force the PD terminal 3 Optional 6.49 to 12.95 28 45.3 voltage above the classification voltage range. 4 Reserved Reserved* 40 30.9 During classification, a moderate amount of power is *Class 4 is currently reserved and should not be used. dissipated in the LTC4257. IEEE 802.3af limits the classi- Early revisions of the IEEE 802.3af draft specification fication time to 75ms. The LTC4257 is designed to handle defined two methods that a PSE could use in order to the power dissipation for this time period. If the PSE perform PD classification. These methods are known as CURRENT PATH CURRENT PATH PSE PSE PROBING LTC4257 PROBING PSE LTC4257 V VOLTAGE VOLTAGE CURRENT SOURCE 2 RCLASS GND 8 SOURCE MONITOR 2 RCLASS GND 8 –15.5V TO –20.5V RCLASS CLOOANDSTANT RCLASS CLOOANDSTANT 4 VIN CURRENT 4 VIN CURRENT INTERNAL INTERNAL V 4257 F03 TO LTC4257 TO LTC4257 PSE PD PSE CURRENT MONITOR IF PSE PROBING CURRENT < LTC4257 LOAD CURRENT, PD TERMINAL VOLTAGE IS < 15V PSE PD IF PSE PROBING CURRENT > LTC4257 LOAD CURRENT, PD TERMINAL VOLTAGE IS > 20V 4257 F04 Figure 3. IEEE 802.3af Measured-Current Method Figure 4. IEEE 802.af Measured-Voltage Method of Classification Probing of Classification Probing 4257fb 8

LTC4257 APPLICATIOU S IU FORW ATIOU probing exceeds 75ms, the LTC4257 may overheat. In this from 0V to V . This sequence is shown in Figure 1. The IN situation, the thermal protection circuit will engage and LTC4257 includes a hysteretic UVLO circuit that keeps disable the classification current source in order to protect power applied to the load until the input voltage falls the part. The LTC4257 stays in classification mode until below the UVLO turn-off threshold. Once the input voltage the input voltage rises above the UVLO turn-on voltage. drops below –30V, the internal power MOSFET is turned off and the classification load current is re-enabled. Undervoltage Lockout C1 will discharge through the PD circuitry and the V OUT pin will go to a high impedance state. IEEE 802.3af dictates a maximum turn-on voltage of 42V and a minimum turn-off voltage of 30V for the PD. In Input Current Limit addition, the PD must maintain large on-off hysteresis to prevent resistive losses in the wiring between the PSE and IEEE 802.3af specifies a maximum inrush current and also the PD from causing start-up oscillation. The LTC4257 specifies a minimum load capacitor between the GND and incorporates an undervoltage lockout (UVLO) circuit that V pins. To control turn-on surge current in the system, OUT monitors line voltage to determine when to apply power the LTC4257 integrates a current limit circuit with the to the PD load (Figure 5). Before power is applied to the onboard power MOSFET and sense resistor to provide a load, the V pin is high impedance and at ground complete inrush control circuit without additional external OUT potential since there is no charge on capacitor C1. When components. The LTC4257 limits input current to less the input voltage rises above the UVLO turn-on threshold, than the 400mA maximum specified by 802.3af, allowing the LTC4257 removes the classification load current and the load capacitor to ramp up to the line voltage in a turns on the internal power MOSFET. C1 charges up under controlled manner. During this ramp up, a large amount of LTC4257 current limit control and the V pin transitions power is dissipated in the power MOSFET. The LTC4257 OUT LTC4257 GND 8 5Cµ1F+ LOPADD MIN TO PSE UNDERVOLTAGE LOCKOUT CIRCUIT 4 VIN VOUT 5 4257 F05 CURRENT-LIMITED TURN ON INPUT LTC4257 VOLTAGE POWER MOSFET 0V TO UVLO* OFF >UVLO* ON *UVLO INCLUDES HYSTERESIS RISING INPUT THRESHOLD ≅ –39.2V FALLING INPUT THRESHOLD ≅ –30.5V Figure 5. LTC4257 Undervoltage Lockout 4257fb 9

LTC4257 APPLICATIOU S IU FORW ATIOU is designed to accept this thermal load and is thermally design of a PD, it is necessary to determine if a step in the protected to avoid damage to the onboard power MOSFET. input voltage will cause the PWRGD signal to go inactive Note that the PD designer must ensure that the PD steady- and how to respond to this event. In some designs, the state power consumption falls within the limits shown in charge on C1 is sufficient to power the PD through this Table 2. event. In this case, it may be desirable to filter the PWRGD signal so that intermittent power bad conditions are Power Good ignored. Figure 10 demonstrates methods to insert a lowpass filter on the power good interface. The LTC4257 includes a power good circuit (Figure6) that is used to indicate to the PD circuitry that load capacitor C1 For PD designs that use a large load capacitor and also is fully charged and that the PD can start DC/DC converter consume a lot of power, it is important to delay activation operation. The power good circuit monitors the voltage of the PD circuitry with the PWRGD signal. If the PD cir- across the internal power MOSFET and PWRGD is as- cuitry is not disabled during the current-limited turn-on se- serted when the voltage drops below 1.5V. The power quence, the PD circuitry will rob current intended for charg- good circuit includes a large amount of hysteresis to allow ing up the load capacitor and create a slow rising input, the LTC4257 to operate near the current limit point without possibly causing the LTC4257 to go into thermal shutdown. inadvertently disabling PWRGD. The MOSFET voltage The PWRGD pin connects to an internal open-drain, 100V must increase to 3V before PWRGD is disabled. transistor capable of sinking 1mA. Low impedance indi- If a sudden increase in voltage appears on the input line, cates power is good. PWRGD is high impedance during this voltage step will be transferred through capacitor C1 signature and classification probing and in the event of a and appear across the power MOSFET. The response of thermal overload. the LTC4257 will depend on the magnitude of the voltage During turn-off, PWRGD is deactivated when the input step, the rise time of the step, the value of capacitor C1 and voltage drops below 30V. In addition, PWRGD may go the DC load. For fast rising inputs, the LTC4257 will active briefly at turn-on for fast rising input waveforms. attempt to quickly charge capacitor C1 using an internal PWRGD is referenced to the V pin and when active will secondary current limit circuit. In this scenario, the PSE IN be near the V potential. The PD DC/DC converter will current limit should provide the overall limit for the circuit. IN typically be referenced to V and care must be taken to For slower rising inputs, the 350mA current limit in the OUT ensure that the difference in potential of the PWRGD signal LTC4257 will set the charge rate of capacitor C1. In either does not cause any detrimental effects. Use of diode clamp case, the PWRGD signal may go inactive briefly while the D6, as shown in Figure 10, will alleviate any problems. capacitor is charged up to the new line voltage. In the R9 LTC4257 100k PWRGD 6 SHDN THERMAL SHUTDOWN PD UVLO LOAD – TO C1+ PSE 5µF MIN + + – 1.125V 300k 300k 4 VIN VOUT 5 4257 F06 Figure 6. LTC4257 Power Good 4257fb 10

LTC4257 APPLICATIOU S IU FORW ATIOU Thermal Protection part until it cools below the overtemperature set point. The LTC4257 current limit will continue switching between The LTC4257 includes smart thermal protection in order 0%, 50% and 100% current levels (Figure 7) until the load to provide full device functionality in a miniature package capacitor is fully charged. while maintaining safe operating temperatures. Several factors create the possibility for tremendous power If the PD is designed to operate at a high ambient tempera- dissipation within the LTC4257. IEEE 802.3af mandates ture and with the maximum allowable supply (57V), there that inrush current be limited to less than 400mA while will be a limit to the size load capacitor that can be charged standard telecom power can be as high as 57V. At turn on, up before the LTC4257 reaches the overtemperature trip before the load capacitor has charged up, the instanta- point. Hitting the overtemperature trip point intermittently neous power dissipated by the LTC4257 can be over 20W. does not harm the LTC4257, but it will delay completion of As the load capacitor charges up, the power dissipation in capacitor charging. Capacitors up to 200µF can be charged the LTC4257 will decrease until it reaches a steady-state without a problem. value dependent on the DC load current. The size of the During classification, excessive heating of the LTC4257 load capacitor determines how fast the power dissipation can occur if the PSE violates the 75ms probing time limit. in the LTC4257 subsides. At room temperature, the To protect the LTC4257, the thermal protection circuitry LTC4257 can handle load capacitors as large as 800µF will disable classification current if the die temperature without going into thermal shutdown. With a large load exceeds the overtemperature trip point. When the die capacitor like this, the LTC4257 die temperature will cools down below the trip point, classification current is increase by about 50°C during a single turn-on sequence. re-enabled. If for some reason power were removed from the part and then quickly reapplied so that the LTC4257 had to charge Once the LTC4257 has charged up to the load capacitor up the load capacitor again, the temperature rise would be and the PD is powered and running, there will be some excessive if safety precautions were not implemented. residual heating due to the DC load current of the PD flowing through the internal MOSFET. In some applica- The LTC4257 protects itself from thermal damage by tions, the LTC4257 power dissipation may be significant monitoring the die temperature. If the die temperature and if dissipated in the S8 package, excessive package exceeds the overtemperature trip point, the part switches heating could occur. This problem can be solved with the to a half-power mode where the current limit is set to 50% use of the DD package which has superior thermal perfor- of its normal level. This reduces power dissipation and mance. The DD package includes an exposed pad that helps prevent further heating. If the part continues to heat should be soldered to an isolated heatsink on the printed up and reaches the shutdown temperature, the current is circuit board. reduced to zero and very little power is dissipated in the T > 120°C UVLO TURN ON 100% 50% CURRENT CURRENT T < 120°C T < 120°C T > 140°C 0% CURRENT 4257 F07 Figure 7. Smart Thermal Protection State Diagram 4257fb 11

LTC4257 APPLICATIOU S IU FORW ATIOU EXTERNAL INTERFACE AND COMPONENT SELECTION Diode Bridges IEEE 802.3af allows power wiring in either of two configu- Transformer rations on the TX/RX wires, plus power can be applied to Nodes on an Ethernet network commonly interface to the the PD via the spare wire pair in the RJ45 connector. The outside world via an isolation transformer (Figure 8). For PD is required to accept power in either polarity on both powered devices, the isolation transformer must include the main and spare inputs, therefore it is common to install a center tap on the media (cable) side. Proper termination diode bridges on both inputs in order to accommodate the is required around the transformer to provide correct different wiring configurations. Figure 8 demonstrates an impedance matching and to avoid radiated and conducted implementation of these diode bridges. The specification emissions. Transformer vendors such as Pulse, Bel Fuse, also mandates that the leakage back through the unused Tyco and others (Table 3) can provide assistance with bridge be less than 28µA when the PD is powered with selection of an appropriate isolation transformer and 57V. proper termination methods. These vendors have trans- The IEEE standard includes an AC impedance requirement formers specifically designed for use in PD applications. in order to implement the AC disconnect function. Capaci- Table 3. Power over Ethernet Transformer Vendors tor C14 in Figure 8 is used to meet this AC impedance VENDOR CONTACT INFORMATION requirement. A 0.1µF capacitor is recommended for this Pulse Engineering 12220 World Trade Drive application. San Diego, CA 92128 Tel: 858-674-8100 The LTC4257 has several different modes of operation FAX: 858-674-8262 based on the voltage present between the V and GND IN http://www.pulseeng.com/ pins. The forward voltage drop of the input diodes in a PD Bel Fuse Inc. 206 Van Vorst Street design subtracts from the input voltage and will affect the Jersey City, NJ 07302 transition point between modes. When using the LTC4257, Tel: 201-432-0463 FAX: 201-432-9542 it is necessary to pay close attention to this forward http://www.belfuse.com/ voltage drop. Selection of oversized diodes will help keep Tyco Electronics 308 Constitution Drive the PD thresholds from exceeding IEEE specifications. Menlo Park, CA 94025-1164 Tel: 800-227-7040 The input diode bridge of a PD can consume 4% of the FAX: 650-361-2508 avialable power in some applications. It may be desirable http://www.circuitprotection.com/ to use Scottky diodes in order to reduce this power loss. RJ45 TX+ 16 T1 1 1 BR1 15 2 DF01SA TX– 14 3 2 RX+ 11 6 TO PHY 3 10 7 RX– 9 8 6 PULSE H2019 GND 8 SPARE+ 4 BR2 5 DF01SA C0.114µF D3 LTC4257 C1 7 100V SMAJ58A SPARE– TVS 4 5 8 VIN VOUT VOUT 4257 F08 Figure 8. PD Front End with Isolation Transformer, Diode Bridges and Capacitor 4257fb 12

LTC4257 APPLICATIOU S IU FORW ATIOU However, if the standard diode bridge is replaced with a drawn from the PSE. On the other hand, if the wall trans- Schottky bridge, the transition points between modes will former voltage is lower, the PSE will continue to supply be affected. The application circuit (Figure 11) shows a power to the PD and the wall transformer power will not be technique for using Schottky diodes while maintaining used. Proper operation should occur in either scenario. proper threshold points to meet IEEE 802.3af compliance. Auxiliary power can be applied after the LTC4257 as shown in option 2. In this configuration, the wall transformer does Auxiliary Power Source not need to exceed the LTC4257 turn-on UVLO requirement; In some applications, it may be desirable to power the PD however, it is necessary to include diode D9 to prevent the from an auxiliary power source such as a wall transformer. transformer from applying power to the LTC4257. The The auxiliary power can be injected into the PD at several transformer voltage requirements will be governed by the locations and various trade-offs exist. Power can be needs of the PD switcher and may exceed 57V. However, injected at the 3.3V or 5V output of the isolated power power priority issues require more intervention. If the wall supply with the use of a diode ORing circuit. This method transformer voltage is below the PSE voltage, then priority accesses the internal circuits of the PD after the isolation will be given to the PSE power. The PD will draw power from barrier and therefore meets the 802.3af isolation safety the PSE while the transformer will sit unused. This configu- requirements for the wall transformer jack on the PD. ration is not a problem in a PoE system. On the other hand, Power can also be injected into the PD interface portion of if the wall transformer voltage is higher than the PSE volt- the LT4257. In this case, it is necessary to ensure the user age, the PD will draw power from the transformer. In this cannot access the terminals of the wall transformer jack situation, it is necessary to address the issue of power on the PD since this would compromise the 802.3af cycling that may occur if a PSE is present. The PSE will detect isolation safety requirements. Figure 9 demonstrates three the PD and apply power. If the PD is being powered by the methods of diode ORing external power into a PD. Option wall transformer, then the PD will not meet the minimum 1 inserts power before the LTC4257 while options 2 and 3 load requirement and the PSE will subsequently remove insert power after the LTC4257. power. The PSE will again detect the PD and power cycling will start. With a transformer voltage above the PSE volt- If power is inserted before the LTC4257 (option 1), it is age, it is necessary to install a minimum load on the output necessary for the wall transformer to exceed the LTC4257 of the LTC4257 to prevent power cycling. Refer to the UVLO turn-on requirement and limit the maximum voltage LTC4257-1 data sheet for an alternative implementation of to 57V. This option provides input current limiting for the option 2 which uses the Signature Disable feature. transformer, provides valid power good signaling and sim- plifies power priority issues. As long as the wall transformer The third option also applies power after the LTC4257, while applies power to the PD before the PSE, it will take priority omitting diode D9. With the diode omitted, the transformer and the PSE will not power up the PD because the wall power voltage is applied to the LTC4257 in addition to the load. will corrupt the 25k signature. If the PSE is already pow- For this reason, it is necessary to ensure that the transformer ering the PD, the wall transformer power will be in parallel maintain the voltage between 44V and 57V to keep the with the PSE. In this case, priority will be given to the higher LTC4257 in its normal operating range. The third option has supply voltage. If the wall transformer voltage is higher, the the advantage of automatically disabling the 25k signature PSE should remove line voltage since no current will be when the external voltage exceeds the PSE voltage. 4257fb 13

LTC4257 APPLICATIOU S IU FORW ATIOU OPTION 1: AUXILIARY POWER INSERTED BEFORE LTC4257 RJ45 TX+ T1 1 D3 ~ + SMAJ58A TX– TVS C14 2 RX+ TO PHY BR1 0.1µF 3 DF01SA 100V ~ – 6 RX– 8 C1 LOPADD GND 4 SPARE+ ~ + LTC4257 5 BR2 7 DF01SA 8 SPARE– ~ – 4 VIN VOUT 5 + ISOLATED D8 WALL 44V TO 57V S1B TRANSFORMER – OPTION 2: AUXILIARY POWER INSERTED AFTER LTC4257 RJ45 TX+ T1 1 D3 SMAJ58A ~ + TX– TVS C14 MINIMUM 2 RX+ TO PHY BR1 0.1µF LOAD 3 DF01SA 100V 6 RX– ~ – 8 C1 LOPADD GND SPARE+ 4 ~ + LTC4257 5 BR2 D9 78 SPARE– ~DF01SA– 4 VIN VOUT 5 S1B + ISOLATED D10 WALL S1B TRANSFORMER – OPTION 3: AUXILIARY POWER APPLIED TO LTC4257 AND PD LOAD RJ45 TX+ T1 1 D3 SMAJ58A ~ + TX– TVS C14 2 RX+ TO PHY BR1 0.1µF 3 DF01SA 100V 6 RX– ~ – 8 C1 LOPADD GND SPARE+ 4 ~ + LTC4257 5 BR2 7 DF01SA 8 SPARE– ~ – 4 VIN VOUT 5 + ISOLATED D10 WALL 44V TO 57V S1B TRANSFORMER – 42571 F09 Figure 9. Auxiliary Power Source for PD 4257fb 14

LTC4257 APPLICATIOU S IU FORW ATIOU Classification Resistor Selection (R ) R pin should not be shorted to V as this would CLASS CLASS IN force the LTC4257 classification circuit to attempt to IEEE 802.3af allows classifying PDs into four distinct source very large currents. In this case, the LTC4257 will classes with class 4 being reserved for future use (Table2). quickly go into thermal shutdown. An external resistor connected from R to V (Fig- CLASS IN ure3) sets the value of the classification current. The Power Good Interface designer should determine which power category the PD falls into and then select the appropriate value of R The PWRGD signal is controlled by a high voltage, open- CLASS from Table 2. If a unique classification current is required, drain transistor. Examples of active-high and active-low the value of R can be calculated as: interface circuits for controlling the PD load are shown in CLASS Figure 10. R = 1.237V/(I – I ) CLASS DESIRED IN_CLASS In some applications it is desirable to ignore intermittent where I is the LTC4257 IC supply current during IN_CLASS power bad conditions. This can be accomplished by classification and is given in the electrical specifications. including capacitor C15 in Figure 10 to form a lowpass The R resistor must be 1% or better to avoid CLASS filter. With the components shown, power bad conditions degrading the overall accuracy of the classification cir- less than about 200µs will be ignored. Conversely, in other cuit. Resistor power dissipation will be 50mW maximum applications it may be desirable to delay assertion of and is transient so heating is typically not a concern. In PWRGD to the PD load. The PWRGD signal can be delayed order to maintain loop stability, the layout should with the addition of capacitor C17 in Figure 10. minimize capacitance at the R node. The classifica- CLASS tion circuit can be disabled by floating the R pin. The CLASS ACTIVE-LOW ENABLE, 5.1V SWING 8 R9 GND 100k PD LTC4257 R18 LOAD TO PSE 6 10k PWRGD SHDN + C1 D6 C15* 5µF 5.1V 0.047µF 4 VIN VOUT 5 100V MMBZ5231B 10V –48V *C15 OPTIONAL TO FILTER PWRGD. SEE APPLICATIONS INFORMATION ACTIVE-HIGH ENABLE FOR RUN PIN WITH INTERNAL PULLUP PD 8 R9 INTERNAL LOAD GND PULLUP 100k TO PSE LTC4257 R18 Q1 RUN 6 10k FMMT2222 PWRGD + C1 D6 C15* C17* 5µF MMBD4148 0.047µF 4 VIN VOUT 5 100V 10V –48V 4257 F10 *C15 AND C17 OPTIONAL TO FILTER PWRGD. SEE APPLICATIONS INFORMATION Figure 10. Power Good Interface Examples 4257fb 15

LTC4257 APPLICATIOU S IU FORW ATIOU Load Capacitor –57V (maximum allowed) and the PD has been detected and powered up, the load capacitor will be charged to IEEE 802.3af requires that the PD maintain a minimum nearly –57V. If for some reason the PSE voltage suddenly load capacitance of 5µF. It is permissible to have a much is reduced to –44V (minimum allowed), the input diodes larger load capacitor and the LTC4257 can charge very will reverse bias and PD power will be supplied solely by large load capacitors before thermal issues become a the load capacitor. Depending on the size of the load problem. However, the load capacitor must not be too capacitor and the DC load of the PD, the PD will not draw large or the PD design may violate two IEEE 802.3af any power from the PSE for a period of time. If this period requirements. The LTC4257 goes into current limit at of time exceeds the IEEE 802.3af 300ms disconnect turn-on and charges the load capacitor with between delay, the PSE may remove power from the PD. For this 300mA and 400mA. The IEEE specification allows this reason, it is necessary to evaluate the load capacitance level of inrush current for up to 50ms. Therefore, it is and load current to ensure that inadvertent shutdown necessary that the PD complete charging of the capacitor cannot occur. within the 50ms time limit. With a maximum input voltage of –57V, these conditions limit the size of the load Maintain Power Signature capacitor to 250µF. In an IEEE 802.3af system, the PSE uses the maintain Very small output capacitors (≤10µF) will charge very power signature (MPS) to determine if a PD continues to quickly in current limit. The rapidly changing voltage at require power. The MPS requires the PD to periodically the output may reduce the current limit temporarily, draw at least 10mA and also have an AC impedance less causing the capacitor to charge at a somewhat reduced than 26.25kΩ in parallel with 0.05µF. The PD application rate. Conversely, charging very large capacitors may circuits shown in this data sheet meet the requirements cause the current limit to increase slightly. In either case, necessary to maintain power. If either the DC current is once the output voltage reaches its final value, the input less than 10mA or the AC impedance is above 26.25kΩ, current limit will be restored to its nominal value. the PSE might disconnect power. The DC current must be If the load capacitor is too large there can be an additional less than 5mA and the AC impedance must be above 2MΩ problem with inadvertent power shutdown by the PSE. to guarantee power will be removed. Consider the following scenario. If the PSE is running at 4257fb 16

LTC4257 APPLICATIOU S IU FORW ATIOU Layout cable from causing damage. However, if the V pin is IN shorted to the GND pin inside the PD while the load The LTC4257 is relativity immune to layout problems. capacitor is charged, current will flow through the para- Excessive parasitic capacitance on the R pin should CLASS sitic body diode of the internal MOSFET and may cause be avoided. If using the DD package, include an electrically permanent damage to the LTC4257. isolated heat sink to which the exposed pad on the bottom of the package can be soldered. For optimal thermal Input Surge Suppression performance, make the heat sink as large as possible. Voltages in a PD can be as large as –57V, so high voltage The LTC4257 is specified to operate with an absolute layout techniques should be employed. maximum voltage of –100V and is designed to tolerate brief overvoltage events. However, the pins that interface The load capacitor connected between Pins 5 and 8 of the to the outside world (primarily V and GND) can routinely LTC4257 can store significant energy when fully charged. IN see peak voltages in excess of 10kV. To protect the The design of a PD must ensure that this energy is not LTC4257, it is highly recommended that a transient volt- inadvertently dissipated in the LTC4257. The polarity- age suppressor be installed between the bridge and the protection diode(s) prevent an accidental short on the LTC4257 (D3 in Figure 2). 4257fb 17

LTC4257 TYPICAL APPLICATIOU T2+VOUT8C4 TO C6100Fµ6.3V•113.3V @ 2.8A 9–VOUT •10 Q6Si7892DPD5B0540W R1247Ω Q7Q8FMMT718MMBT3904 C141FµR18C18100Ω1nF 5D8R4BAT5410k•4 4 4257 TA04C231000pF2kV •45 •1 3 SEPARATINGLINEFOR GROUNDPLANE R16330Ω C160.1Fµ50V R15•10.22Ω1/2WT31%8 Q3Si4490DY C173300pF R2810k Supply Q2MMBT3904 Q4MMBT2907ALT1 Q5MMBT3904 ISENSE VCRCMPC C22680pFC2106030.1Fµ h 3.3V, 2.8A High Efficiency Isolated Power L14.7Hµ C1BC1C0.82F0.82Fµµ100V100VR5D247KBAT54Q1MMBTA06 D1D412VD3AD3BBAS21LT1 R647ΩC10R74.7Fµ33Ω35VC91/4WR8R11R10100pF47Ω62k10k C12R9C130.1Fµ100Ω470pF50VR1330.1k1% VFBUVLOGATECC Q9LT1737CGN2N70023VOUTtEMINENABROSCAPNDLYSGNDPSFSTGNDONOCMPR233.65kR24R25R26R271%C19C20100k62k10k62k47pF0.47Fµ wit ace C1A10Fµ100V R14100k R1710k D712V rf + e nt Figure 11: PD Power I D11D9B1100B1100 D10D12B1100B1100C110.1FµD6100VSMAJ58A D13MMSD4148C24C250.010.01FFµµ200V200V R30R317575ΩΩNCGNDD14RNCB1100CLASS NPWCRGD D15VVINOUTB1100LTC4257CDD RCLASSD17D161%B1100B11003 NOTES: UNLESS OTHERWISE SPECIFIED1.ALL RESISTORS ARE 5%2.ALL CAPACITORS ARE 25V 3. FOR CLASS 1-SELECT R4 OPERATION. REFERCLASSTO DATA SHEET APPLICATIONS INFORMATION SECTION4.CONNECT TO CHASSIS GROUNDC4 TO C6: TDK C4532X5R0J107MC2, C23: AVX 1808GC102MATD1, D7: MM3Z12VT1D3: MMBD1505D9 TO D12, D14 TO D16: DIODES INC., B1100L1: COILCRAFT D01608C-472T1: PULSE H2019T2: PULSE PB2134T3: PULSE PA0184 R175ΩC70.01Fµ200V C21000pF2kV OUTTO PHY+TXOUT –TXOUT +RXOUT –RXOUT 1 2 3 6 7 8 R275ΩC30.01Fµ200V 4 T1+16TX 15–TX14 +RX11 10–9RX +SPARE –SPARE J2 1 2 3 6 4 5 7 8 RJ45 INFROMPSE 4257fb 18

LTC4257 PACKAGE DESCRIPTIOU S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .189 – .197 (4.801 – 5.004) .045 ±.005 NOTE 3 .050 BSC 8 7 6 5 .053 – .069 (1.346 – 1.752) .004 – .010 (0.101 – 0.254) .245 .150 – .157 MIN .160 ±.005 .228 – .244 (3.810 – 3.988) (5.791 – 6.197) NOTE 3 .014 – .019 .050 (0.355 – 0.483) (1.270) TYP BSC .030 ±.005 .010 – .020 × 45°(cid:31) TYP 1 2 3 4 (0.254 – 0.508) RECOMMENDED SOLDER PAD LAYOUT .008 – .010 (0.203 – 0.254) 0°– 8° TYP NOTE: INCHES 1. DIMENSIONS IN 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. (MILLIMETERS) MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) .016 – .050 2. DRAWING NOT TO SCALE (0.406 – 1.270) SO8 0303 DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) R = 0.115 0.38 ± 0.10 TYP 5 8 0.675 ±0.05 3.5 ±0.05 1.65 ±0.05 3.00 ±0.10 1.65 ± 0.10 2.15 ±0.05 (2 SIDES) (4 SIDES) (2 SIDES) PIN 1 PACKAGE TOP MARK OUTLINE (NOTE 6) (DD8) DFN 1203 4 1 0.25 ± 0.05 0.200 REF 0.75 ±0.05 0.25 ± 0.05 0.50 0.50 BSC BSC 2.38 ±0.10 2.38 ±0.05 0.00 – 0.05 (2 SIDES) (2 SIDES) BOTTOM VIEW—EXPOSED PAD RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2.DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6.SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 4257fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 19 However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC4257 TYPICAL APPLICATIOU PD Power Interface with 3.3V, 3A Nonisolated Power Supply L1 1µH J16321 RRTTXXXX–+–+ 11111645190XFTM1R132687 TTRRXXXXOOOOUUUUTTTT+–+– TPOHY R7R7551C02C021ΩΩ1.0.0234000011VVµµFF 3C02.k80V01µF ~~DFB0R11S+–A DTSVM301S.AC01J0µ15V4F8A NRNCCCLALSTSC42P5W7GRNGNDDC + C4121.0.1C7020Aµ10µVBVFF MMBZ5263.D58BV4 R10103k QFM2MT625 VIN VOUT 4 SPARE+ ~ + 75 75Ω02.0010µVF 75Ω02.0010µVF DFB0R12SA R1%CL2ASS UPDS5840 VOUT+ 8 SPARE– ~ – 2 9 10 + C9 + C12 3A.T3 V3A RJ45 CTX-02-152T422 • 1X050RµF 1X050RµF 6.3V 6.3V N1.O ATLELS :R UENSILSETSOSR O VTAHLEUREWSI SAER ES P5E%CIFIED R1090k 1R0100k LTC1871 • • 10XC05µ1R0F+ 10XC05µ1R3F+ 2 3 . . SRCEOELFNEENRCET CT ROT C TDLOAA STCSAH FASOSHRSE IECSTL GAASRPSOP UL1IN-C4DA OTPIOENRSA TINIOFNO.RMATION SECTION R101k8 Q2N17002 RITUHN SENVSINE 4 11 12 6.3V 6.3V CC11AB:: PTDAKN ACS5O7N50ICX 7ERC2EAV222A5AK4TR7P 1N41D468 FMMT22Q242 FB INTVCC Q3 C8: AVX 1808GC102MAT FREQ GATE FDC2512 CL19:, LCQ1L0B, C251128, TC11R3:O TMDK C4532X5ROJ107 80R.T6k MODE/SYNCGND T1: PULSE H2019 1% R15 R16 R17 RC 21k 1% 100Ω 750Ω C1nC1F12k R112%1.44k 46.7.C3µV5F R01.%51Ω VOUT– C6 4257 TA03 1µF 6.3V RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1737 High Power Isolated Flyback Controller Sense Output Voltage Directly from Primary-Side Winding LTC1871 Wide Input Range, No R ™ Current Mode Flyback, Adjustable Switching Frequency, Programmable Undervoltage SENSE Boost and SEPIC Controller Lockout, Optional Burst Mode® Operation at Light Load LTC3803 Current Mode Flyback DC/DC Controller in ThinSOT™ 200kHz Constant Frequency, Adjustable Slope Compensation, Optimized for High Input Voltage Applications LTC4257-1 IEEE 802.3af PD Interface Controller 100V, 400mA Internal Switch, Dual Current Limit LTC4258 Quad IEEE 802.3af Power over Ethernet Controller DC Disconnect Only, IEEE-Compliant PD Detection and Classification, Autonomous Operation or I2C™ Control LTC4259A-1 Quad IEEE 802.3af Power over Ethernet Controller AC or DC Disconnect, IEEE-Compliant PD Detection and Classification, Autonomous Operation or I2C Control LTC4267 IEEE 802.3af PD Interface Controller with 100V, 400mA Internal Switch, 16-Pin SSOP or 3mm × 5mm Integrated Switching Regulator DFN Packages Burst Mode is a registered trademark of Linear Technology Corporation. No RSENSE and ThinSOT are trademarks of Linear Technology Corporation. 4257fb 20 Linear Technology Corporation LT 1205 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2003

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: LTC4257IDD#TR LTC4257CS8 LTC4257CS8#TRPBF LTC4257CDD#TR LTC4257CS8#PBF LTC4257IS8#PBF LTC4257IS8#TR LTC4257CDD#TRPBF LTC4257IDD#TRPBF LTC4257IDD#PBF LTC4257CS8#TR LTC4257CDD LTC4257IS8 LTC4257IDD LTC4257IS8#TRPBF LTC4257CDD#PBF