LTC4226 Wide Operating Range Dual Hot Swap Controller FeaTures DescripTion n Allows Safe Board Insertion into Live Backplane The LTC®4226 dual Hot Swap™ controller allows two n Selectable Current Limit and Dual-Rate Timer power paths to be safely inserted and removed from a Accommodate Load Surges live backplane or powered connector. Using N-channel n Fast Response Limits Peak Fault Current pass transistors, supply voltages ranging from 4.5V to n Wide Operating Voltage Range: 4.5V to 44V 44V are ramped up at an adjustable rate. n Optional Auto-Retry or Latchoff after Three selectable ratios of current limit to circuit breaker Overcurrent Fault threshold accommodate noisy loads and momentary high n High Side Drive for External N-Channel MOSFET peak currents without interruption, while a dual-rate fault n Allows Parallel Power Paths for High Current timer protects the MOSFET from extended output over- Applications current events. FAULT outputs indicate the circuit breaker n Available in 16-Pin QFN (3mm × 3mm) and MSOP status. The LTC4226-1 remains off after a fault while the Packages LTC4226-2 automatically retries after a 0.5s delay. applicaTions The LTC4226 can also be configured as a bidirectional cur- rent limiter/circuit breaker. For high current applications, n Apple FireWire/IEEE 1394 two channels may be configured as parallel power paths. n Disk Drives L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot n Rugged 12V, 24V Applications Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Hot Board/Connector Insertion n Uni/Bidirectional Current Limiter/Circuit Breaker Typical applicaTion 2 Port FireWire Application PORT 1 1394 1394 SS3P5 30mΩ FDMS86500DC SOCKET PLUG Inrush after Load Connection 7V TO 33V VCC VCC1 SENSE1 GATE1 OUT1 10V/DIV ON1 FTMR1 CABLE INSERTION CURRENT FAULT1 220nF VOUT 10V/DIV LIMIT CLS LTC4226-2 GND SELECT FAULT2 220nF ON2 FTMR2 IOUT INRUSH VCC2 SENSE2 GATE2 OUT2 PORT 2 1A/DIV CURRENT 1394 1394 SOCKET PLUG 30mΩ FDMS86500DC 1ms/DIV 4226 TA01b SMCJ33A* VCC = 12V *36.7V TO 40.6V BV 4226 TA01a CLOAD = 1mF 4226f 1

LTC4226 absoluTe MaxiMuM raTings (Notes 1, 2) V ...........................................................–0.3V to 55V Operating Ambient Temperature Range CCn SENSEn, ONn, FAULTn, CLS .......................–0.3V to 55V LTC4226C ................................................0°C to 70°C GATEn (Note 3) ..........................................–0.3V to 68V LTC4226I .............................................–40°C to 85°C OUTn (Note 3) ............................................–0.3V to 55V Storage Temperature Range ..................–65°C to 150°C GATEn – OUTn (Note 3) .............................–0.3V to 18V MSOP Lead Temperature (Soldering, 10 sec) ........300°C FTMRn .........................................................–0.3V to 4V pin conFiguraTion TOP VIEW 1 2 T T ON1 FAUL FAUL ON2 TOP VIEW 16 15 14 13 FAULT1 1 16 FAULT2 VCC1 1 12 VCC2 ON1 2 15 ON2 SENSE1 2 11 SENSE2 VCC1 3 14 VCC2 17 SENSE1 4 13 SENSE2 GATE1 3 10 GATE2 GATE1 5 12 GATE2 OUT1 6 11 OUT2 OUT1 4 9 OUT2 FTMR1 7 10 FTMR2 5 6 7 8 GND 8 9 CLS R1 ND LS R2 MS PACKAGE TM G C TM 16-LEAD PLASTIC MSOP F F TJMAX = 125°C, θJA = 120°C/W UD PACKAGE 16-LEAD (3mm × 3mm) PLASTIC QFN TJMAX = 125°C, θJA = 68°C/W EXPOSED PAD (PIN 17), PCB GND CONNECTION OPTIONAL orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4226CUD-1#PBF LTC4226CUD-1#TRPBF LFRC 16-Lead (3mm × 3mm) Plastic QFN 0°C to 70°C LTC4226CUD-2#PBF LTC4226CUD-2#TRPBF LFRD 16-Lead (3mm × 3mm) Plastic QFN 0°C to 70°C LTC4226IUD-1#PBF LTC4226IUD-1#TRPBF LFRC 16-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C LTC4226IUD-2#PBF LTC4226IUD-2#TRPBF LFRD 16-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C LTC4226CMS-1#PBF LTC4226CMS-1#TRPBF 42261 16-Lead Plastic MSOP 0°C to 70°C LTC4226CMS-2#PBF LTC4226CMS-2#TRPBF 42262 16-Lead Plastic MSOP 0°C to 70°C LTC4226IMS-1#PBF LTC4226IMS-1#TRPBF 42261 16-Lead Plastic MSOP –40°C to 85°C LTC4226IMS-2#PBF LTC4226IMS-2#TRPBF 42262 16-Lead Plastic MSOP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4226f 2

LTC4226 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C, V = 12V. A CC SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supplies V Input Supply Range l 4.5 44 V CCn I Input Supply Current V = 12V l 0.7 2 mA CCn CC V Input Supply Undervoltage Lockout V Rising l 3 3.7 4.5 V CCn(UVL) CC ∆V Input Supply Undervoltage Lockout Hysteresis 200 mV CCn(HYST) Circuit Breaker and Current Limit V Circuit Breaker Threshold (V – SENSE) l 45 50 55 mV CB CC Channel-to-Channel V Mismatch l ±6 % CB V Current Limit Voltage (V – SENSE), CLS = 0V l 70 86 103 mV LIMIT CC (V – SENSE), CLS = Open l 93 115 136 mV CC (V – SENSE), CLS = 3V l 139 173 205 mV CC Channel-to-Channel V Mismatch l ±6 % LIMIT I Sense Pin Input Current (V – SENSE = 0V) l 40 200 µA SENSE CC Gate Drive ∆V External N-Channel Gate Drive (GATE – OUT) I = 0µA, –1µA; V > 6V l 10 12 16 V GATE GATE CC I = 0µA, –1µA; V < 6V l 8 12 16 V GATE CC I Gate Pull-Up Current GATE = OUT = 1V l –5 –9 –13 µA GATE(UP) I Gate Pull-Down Current GATE = 12V, OUT = 0V, ON = 0V l 1 3 5 mA GATE(DN) GATE = OUT = V = 12V, ON = 0V or FAULT = 0V l 50 150 300 µA CC GATE = 5V, OUT = 0V, ON = 3V, Severe Fault l 100 200 1000 mA Comparator Inputs V ON Pin Threshold Voltage V Rising l 1.17 1.24 1.3 V ON ON ∆V ON Pin Hysteresis Voltage 50 mV ON(HYST) I ON Pin Input Current V = 1.2V l 0 ±1 µA ON ON Fault Timer I FTMR Pin Pull-Up Current (Circuit Breaker) V = 0V, Circuit Breaker Fault l –1.4 –2 –2.6 µA FTMR(CB) FTMR I FTMR Pin Pull-Up Current (Current Limit) V = 0V, Current Limit Engaged, CLS = 0V l –14 –20 –26 µA FTMR(CL) FTMR V = 0V, Current Limit Engaged, CLS = Open l –25 –36 –46 µA FTMR V = 0V, Current Limit Engaged, CLS = 3V l –56 –80 –104 µA FTMR I FTMR Pin Pull-Down Current (Default) V = 1V, Default l 1.4 2 2.6 µA FTMR(DEF) FTMR I FTMR Pin Pull-Down Current (Reset) V = 1V, Reset l 70 100 130 µA FTMR(RST) FTMR V FTMR Pin Threshold Voltage (Trip) l 1.17 1.23 1.3 V FTMR(H) V FTMR Pin Threshold Voltage (Reset) l 0.1 0.2 V FTMR(L) Fault I/O V FAULT Pin Low Output Voltage Circuit Breaker Fault, I = 2mA l 0.2 0.4 V (OL) FAULT I FAULT Pin Low Output Pull-Down Current Circuit Breaker Fault, V = 5V, V = 12V l 2 5 10 mA (OL) FAULT CC V FAULT Pin Input Threshold Voltage No Internal Fault, External Input l 0.3 0.5 0.8 V FAULT I FAULT Pin Pull-Up Current No Internal Fault, V = 2V l –5 –10 –20 µA (OH) FAULT V FAULT Pin High Output Voltage No Internal Fault, I = 0µA, V = 12V l 2 3.8 5 V (OH) FAULT CC 4226f 3

LTC4226 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C, V = 12V. A CC SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Three-State Input V CLS Pin Low Threshold Voltage l 0.4 V CLS(L) V CLS Pin High Threshold Voltage l 2 V CLS(H) V CLS Pin Voltage in Open State 1.38 V CLS(Z) I Allowable CLS Pin Leakage in Open State l ±2 µA CLS(Z) I CLS Pin Low Input Current l –2 –4 –8 µA CLS(L) I CLS Pin High Input Current l 2 4 8 µA CLS(H) Timing Delay t Severe Overcurrent Fault to GATE Low C = 1nF, (V – SENSE = 4V) l 0.1 1 µs OFF(SENSE) GATE CC t FAULT Input Low to GATE Low C = 1nF l 3 6 30 µs OFF(FAULT) GATE t FTMR High to GATE Low C = 1nF l 3 7 30 µs OFF(FMTR) GATE t ON Low to GATE Low C = 1nF l 25 60 µs OFF(ON) GATE t V Enters Undervoltage to GATE Low C = 1nF l 25 60 µs OFF(UVLO) CC GATE t ON High to GATE High V Above Undervoltage l 5 10 20 ms ON(ON) CC Channel-to-Channel t Mismatch l ±10 % ON(ON) t V Exits Undervoltage to GATE High ON High l 25 50 100 ms ON(UVL) CC Channel-to-Channel t Mismatch l ±10 % ON(UVL) t Auto-Retry Delay LTC4226-2 Only l 0.25 0.5 1 s D(COOL) Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: Limits on maximum rating is defined as whichever limit occurs may cause permanent damage to the device. Exposure to any Absolute first. Internal clamps limit the GATE pin to a minimum of 12V above OUT, a Maximum Rating condition for extended periods may affect device diode voltage drop below OUT, or a diode voltage drop below GND. Driving reliability and lifetime. the GATE to OUT pin voltage beyond the clamp may damage the device. Note 2: All currents into pins are positive, all voltages are referenced to GND unless otherwise specified. 4226f 4

LTC4226 Typical perForMance characTerisTics T = 25°C, V = 12V, unless otherwise noted. A CC Circuit Breaker Voltage vs Circuit Breaker Voltage vs Supply Current vs Supply Voltage Supply Voltage Temperature 1000 60 55.0 800 55 52.5 (µA)C 600 (mV)B 50 (mV)B50.0 C C C I 400 V V 45 47.5 200 0 40 45.0 0 10 20 30 40 50 0 10 20 30 40 50 –50 –25 0 25 50 75 100 VCC (V) VCC (V) TEMPERATURE (°C) 4226 G01 4226 G02 4226 G03 Current Limit Voltage vs Current Limit Voltage vs Active Current Limit Delay vs Supply Voltage Temperature Sense Voltage 200 200 100 CGATE = 1nF CLS = 3V CLS = 3V s) AY (µ 10 CLS = 3V L 150 150 DE mV) mV) MIT CLS = OPEN (MIT CLS = OPEN (MIT CLS = OPEN NT LI 1 CLS = 0V VLI VLI RE R 100 100 U CLS = 0V CLS = 0V E C 0.1 V TI C A 50 50 0.01 0 10 20 30 40 50 –50 –25 0 25 50 75 100 0 100 200 300 400 500 600 VCC (V) TEMPERATURE (°C) SENSE VOLTAGE (VIN – VSENSE) (mV) 4226 G04 4226 G05 4226 G06 Gate Pull-Up Current vs Gate Voltage vs Gate Pull-Up Temperature Current Gate Voltage vs Supply Voltage –15 15 15 –10 10 10 (µA)GATE(UP) ∆V (V)GATE ∆V (V)GATE I –5 5 5 0 0 0 –50 –25 0 25 50 75 100 0 –5 –10 –15 0 10 20 30 40 50 TEMPERATURE (°C) IGATE(UP) (µA) VCC (V) 4226 G07 4226 G08 4226 G09 4226f 5

LTC4226 Typical perForMance characTerisTics T = 25°C, V = 12V, unless otherwise noted. A CC Gate Voltage vs Gate Pull-Down Gate Voltage vs Severe Fault Current Gate Pull-Down Current Gate Voltage vs Temperature 15 15 15 ON = 0V 10 10 10 V) V) V) (ATE (ATE (ATE G G G V V V ∆ ∆ ∆ 5 5 5 0 0 0 0 1 2 3 4 5 0 100 200 300 400 500 –50 –25 0 25 50 75 100 IGATE(DN) (mA) IGATE(DN) (mA) TEMPERATURE (°C) 4226 G10 4226 G11 4226 G12 Circuit Breaker Timer Current vs Current Limit Timer Current vs Fault Output Low Voltage vs Temperature Temperature Current –2.6 –110 5 –2.4 –90 4 CLS = 3V –2.2 µA) µA) –70 3 I (FTMR(CB) ––21..08 I (FTMR(CL) –50 V (V)OL 2 CLS = OPEN –30 1 –1.6 CLS = 0V –1.4 –10 0 –50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 0 2 4 6 8 10 TEMPERATURE (°C) TEMPERATURE (°C) IOL (mA) 4226 G13 4226 G14 4226 G15 Fault Input Threshold Voltage vs Supply Undervoltage Lockout vs Temperature Temperature ON Turn-On Time vs Temperature 0.8 4.0 15 0.7 3.8 13 VCC(UVL) V (V)FAULT 00..65 V (V)CC(UVL) 33..64 VCC(UVL) – ∆VCC(HYST) t (ms)ON(ON) 119 0.4 3.2 7 0.3 3.0 5 –50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 4226 G16 4226 G17 4226 G18 4226f 6

LTC4226 pin FuncTions CLS: Three-State Current Limit Select Input. Tying this pin GATE1, GATE2: Gate Drive for External MOSFET. The gate low enables 1.5× current limit; opening this pin enables 2× driver controls the external N-channel MOSFET switch current limit and tying this pin high (above 2V) enables 3× by applying a voltage across the GATE and OUT pins current limit. A higher current limit selection permits larger which connect to the MOSFET gate and source pins. A current transients to pass without invoking current limiting. charge pump sources 9µA at the GATE pin to turn on the The CLS pin permits dynamic current limit selection. The external MOSFET. When the MOSFET is on, the GATE pin three input states configure the preset current limit volt- voltage is clamped at ∆V above the OUT pin. During GATE age V to approximately 1.5×, 2× or 3× of 1.15 • V . turn-off, the GATE pin is discharged by a 3mA pull-down LIMIT CB with about 2.85mA of current flowing to the OUT pin. In Exposed Pad: The exposed pad may be left open or con- a severe fault, the GATE pin is discharged to the OUT pin nected to device ground. with a minimum of 100mA. When the MOSFET is off, FAULT1, FAULT2: FAULT Input/Output Status. When the the GATE pin is pulled towards ground with 150µA and FTMR pin has reached the VFTMR(H) threshold, the fault a voltage clamps limits the GATE voltage to a diode drop status is set active and the FAULT pin output pulls low. below the OUT pin. When fault is inactive, a 10µA current source pulls this GND: Device ground pin up to a diode below its internal supply voltage. Pulling the FAULT pin low turns off the external MOSFET without ON1, ON2: ON Control Inputs. The ON pins have a 1.23V affecting the FTMR pin status. The FAULT pin is not latched. threshold with 50mV of hysteresis. A high input turns on the external MOSFET with a 10ms delay. A low input turns FTMR1, FTMR2: Fault Timer. A capacitor sets the dual- off the external MOSFET and resets circuit breaker faults. rate fault timer durations: circuit breaker CB timeout and current limit CL timeout. The FTMR pin pulls up with OUT1, OUT2: Gate Drive Return. Connect this pin to the I when the sense resistor voltage is between V source of the external N-channel MOSFET switch. This pin FTMR(CB) CB and V . The FTMR pin pulls up with I when provides a return for the gate pull-down circuit. When the LIMIT FTMR(CL) the sense resistor voltage is at or above V . FTMR GATE pin is below the OUT pin, the internal clamp diode LIMIT pulls low with I when the sense resistor volt- draws current from this OUT pin. FTMR(DEF) age falls below V . When the FTMR voltage reaches the CB SENSE1, SENSE2: Current Sense Negative Input. The V threshold, the fault status is activated. To reset FTMR(H) circuit breaker comparator and the current limit amplifier FTMR, the ON pin can be pulled low or the correspond- monitor the voltage across the sense resistor. The current ing supply voltage can be pulled below the undervoltage limiting amplifier controls the GATE of the external MOSFET lockout threshold. The capacitor on the FTMR pin is pulled to keep the sense resistor voltage at V . The current LIMIT to GND with I to clear the fault status. For the FTMR(RST) limit is set higher than the circuit breaker to accommodate LTC4226-1 latchoff option, the MOSFET remains off until noisy loads that momentarily exceed the circuit breaker faults are cleared by cycling the ON pin or by an under- comparator threshold. voltage condition on the corresponding supply. For the LTC4226-2 auto-retry option, after a tD(COOL) delay, FTMR VCC1, VCC2: Supply Voltage and Current Sense Positive is reset, the fault status is cleared, and the GATE begins Input. An undervoltage lockout circuit disables the MOS- to ramp up. The LTC4226-2 can be forced to restart by FET switch until VCC is above the lockout voltage VCC(UVL) cycling the ON pin or by an undervoltage condition on the for 50ms. corresponding supply. 4226f 7

LTC4226 FuncTional block DiagraM VCC1 SENSE1 UVLO + + VCB – VLIMIT – ON1 CHARGE + – + – + PUMP ON CB CL 9µA GATE1 VREF – 12V OUT1 IFTMR(CB) IFTMR(CL) 10µA CB CL FTMR1 FAULT1 + FTMR(H) DEF RST LOGIC VREF – IFTMR(DEF) IFTMR(RST) + CHANNEL 1 FTMR(L) 0.1V – CLS GND IFTMR(CB) IFTMR(CL) CHANNEL 2 10µA CB CL FAULT2 FTMR2 + FTMR(H) DEF RST LOGIC VREF – IFTMR(DEF) IFTMR(RST) + FTMR(L) CHARGE 0.1V – PUMP ON2 + 9µA GATE2 ON VREF – 12V OUT2 CB CL – + – + – – VCB + VLIMIT + UVLO VCC2 SENSE2 4226 BD 4226f 8

LTC4226 operaTion The LTC4226 controls two independent Hot Swap channels. current limit is not activated and a shorter current limit It is designed to turn each supply voltage on and off in a (CL) timeout with a higher current I ramp up if FTMR(CL) controlled manner, allowing live insertion into a powered current limit is active. The CLS input state sets the higher connector or backplane. current I at 20μA when CLS = 0V; 36μA when FTMR(CL) CLS = open; 80μA when CLS > 2V. The LTC4226 powers-up the output of a channel when that channel’s V pin has remained above the 3.7V undervolt- During current limit, the sense voltage is at V . There CC LIMIT age lockout threshold V for more than 50ms and can be significant MOSFET power dissipation while in cur- CC(UVL) its ON pin has remained above the V threshold for more rent limit due to the substantial drain-to-source voltage. ON than 10ms. During normal operation, a charge pump turns The CL timeout duration should be selected based on the on the external N-channel MOSFET providing power to external MOSFET safe-operating-area to prevent MOSFET the load. Each channel’s charge pump derives its power damage. The CL timeout is set by the FTMR capacitor C T from its own V supply pin. To protect the MOSFET, the and the I pull-up to the V threshold. Setting CC FTMR(CL) FTMR(H) GATE voltage is clamped at about 12V above the OUT pin. the current limit higher than the circuit breaker threshold It is also clamped a diode voltage below the OUT pin and allows momentary current load spikes as long as the a diode voltage below GND. average current remains below the circuit breaker limit. The current flowing through the MOSFET is measured by Both channels share a common current limit select, CLS the external sense resistor. The sense voltage across the pin. This pin has three input states: low, open and high. sense resistor is measured between the V and SENSE The three input states configure the preset current limit CC pins. The LTC4226 has a circuit breaker (CB) comparator V to approximately 1.5×, 2× or 3× of 1.15 • V . LIMIT CB to detect the sense current above circuit breaker thresh- After a fault timeout, the auto-retry (LTC4266-2) version old and a current limit (CL) amplifier to actively clamp waits 0.5 seconds before resetting FTMR. After the FTMR the sense current at the current limit threshold. Both the capacitor is discharged, the GATE pin is free to ramp up CB comparator and the CL amplifier monitor the sense again after the FAULT pin resets high. For the latchoff resistor voltage between the V and SENSE pins. When CC (LTC4266-1) version, there is no 0.5 second restart delay. the sense voltage exceeds V but is below V , the CB LIMIT For both versions, FTMR can be reset by cycling the ON CB comparator enables a 2μA I current source FTMR(CB) pin low and then high or by cycling V below and then CC that ramps up the voltage on the FTMR pin. If the sense above UVLO. resistor voltage exceeds V , the CL amplifier limits LIMIT the current in the MOSFET by reducing the GATE-to-OUT The FAULT pin pulls low when active with a 5mA current voltage with an active control loop. The fast response CL limit. The pin can drive a low-current 2mA LED with a amplifier can quickly gain control of the GATE-to-OUT series resistor connected to VCC. The FAULT pin has an voltage in the event of an OUT-to-GND short circuit. The internal 10μA pull-up current to a diode below its internal FTMR pin is ramped up by the larger IFTMR(CL) current VCC when signaling no fault. Pulling the FAULT pin below source during active current limiting. If the sense voltage the VFAULT threshold causes the external MOSFET to turn falls below V , the FTMR is ramped down by the default off without affecting FTMR status. The FAULT pin can be CB 2μA I pull-down current. wire-OR’ed with other open-drain outputs. FTMR(DEF) A fault timeout occurs when an overcurrent condition The output voltage of the Hot Swap circuit is ramped persists above VCB that causes the FTMR pin to ramp to down when the ON pin transitions low or VCC falls below the V threshold. When this occurs, the MOSFET the 3.7V undervoltage lockout. The gate driver discharges FTMR(H) is turned off and the FAULT pin asserts low. The FTMR the GATE pin with 3mA (including 2.85mA to the OUT pin) has two timeout durations: a longer circuit breaker (CB) when GATE > OUT and 150µA to GND when GATE < OUT. timeout with a lower current I ramp up when the FTMR(CB) 4226f 9

LTC4226 applicaTions inForMaTion The typical LTC4226 application is in high availability At start-up, the switch current is typically dominated by systems that distribute positive voltage supplies between the current charging the load capacitor, C . If the sense L1 4.5V to 44V to hot-swappable ports or cards. It can also voltage reaches V , the current limit amplifier controls LIMIT be used in daisy chain port applications like FireWire to the gate of the MOSFET in a closed loop. This keeps the provide instant current limit. start-up inrush current at the current limit. The basic two channel applications are shown in Figure 1 Several conditions must be present before the external and Figure 2. Figure 1 shows the LTC4226 in a card resident MOSFET can be turned on. The fault timer FTMR is reset application with an upstream connector. Figure 2 shows the by either UVLO or ON low status. The external supply V CC LTC4226 on a backplane or motherboard with a downstream must exceed its undervoltage lockout level V for CC(UVL) connector. Each Hot Swap channel has a power path con- more than 50ms. The ON pin must be high for more than trolled by an external MOSFET switch and a sense resistor 10ms and the FAULT pin must be high before the external for monitoring current. MOSFET turns on with no additional delay. If the channel is not in UVLO, the ON pin low to high asser- Turn-On Sequence tion delay is 10ms. The FAULT pin must be high before the During turn-on, a 9µA current charges the gate of the external switch turns on. When the channel is not in UVLO MOSFET switch: Q1 for channel 1. The current limit am- and the ON pin is high, there is no delay from the FAULT plifier monitors the current in the channel 1 power path low to high transition to turn on of the external switch. by sensing the voltage across the resistor, R . S1 CONNECTOR CONNECTOR Q1 2 1 RS1 FDMS86500DC 5mΩ OR Si7164DP 12V 12V 8.9A + Z1 CL1 OUT R1 R2 C1 SMCJ15A 100µF 720k 100k 470pF ON1 GND R6 FAULT1 1k VCC1 SENSE1 GATE1 OUT1 CLS ON1 FTMR1 1R05k FAULT1 3C3T1nF CLS LTC4226-1 GND C3 FAULT2 CT2 R7 22nF 33nF ON2 FTMR2 1k FAULT2 VCC2 SENSE2 GATE2 OUT2 ON2 R4 C2 R3 100k 470pF 240k 5V 5V 4.45A BACKPLANE PLUG-IN ZS2MCJ7V0A 10RmS2Ω FDMS8Q62500DC + C22L20µF OUT CARD OR Si7164DP 4226 F01 Figure 1. 2-Channel Card Resident Controller with Upstream Connector 4226f 10

LTC4226 applicaTions inForMaTion CONNECTOR CONNECTOR 1 2 C1 R2 Q1 470pF 100k R1 RS1 FDMS86500DC 720k 5mΩ OR Si7164DP 12V 12V 8.9A Z1 OUT SMCJ15A + VCC1 SENSE1 GATE1 OUT1 CL1 ON1 ON1 FTMR1 100µF FAULT1 FAULT1 CT1 33nF CLS CLS LTC4226-1 GND GND FAULT2 FAULT2 CT2 33nF ON2 ON2 FTMR2 CL2 VCC2 SENSE2 GATE2 OUT2 +220µF 5V 5V 4.45A C2 R4 ZS2MCJ7V0A R2420k 10RmS2Ω FODRM SSi8Q761256040DDPC OUT 470pF 100k 4226 F02 MOTHERBOARD PLUG-IN OR BACKPLANE CARD Figure 2. 2-Channel Backplane Resident Controller with Downstream Connector CONNECTOR CONNECTOR 1 2 Q1 R1 RS1 FDMS86500DC 720k 5mΩ OR Si7164DP 12V 12V 8.9A Z1 OUT SMCJ15A + VCC1 SENSE1 GATE1 OUT1 CL1 ON1 FTMR1 100µF FAULT1 CT1 33nF CLS CLS LTC4226-1 GND GND FAULT FAULT2 CT2 33nF ON2 ON2 FTMR2 CL2 C1 R2 VCC2 SENSE2 GATE2 OUT2 +220µF 470pF 100k 5V 5V 4.45A Z2 RS2 Q2 OUT SMCJ7V0A 10mΩ FDMS86500DC MOTHERBOARD PLUG-IN OR Si7164DP CARD 4226 F03 Figure 3. 2-Channel Controller with a Common ON/OFF Connection 4226f 11

LTC4226 applicaTions inForMaTion Q1 CONNECTOR CONNECTOR RS1 FDMS86500DC 1 2 5mΩ OR Si7164DP 12V 12V + 8.9A C1 Z1 RG1 OUT 100µF SMCJ15A 10Ω CG1 + 10nF CL1 VCC1 SENSE1 GATE1 OUT1 100µF ON1 FTMR1 FAULT1 CT1 33nF CLS CLS LTC4226-1 GND GND FAULT FAULT2 CT2 33nF ON2 ON2 FTMR2 VCC2 SENSE2 GATE2 OUT2 RG2 CL2 10Ω +220µF CG1 10nF 5V 5V + 4.45A C2 Z2 RS2 Q2 OUT 220µF SMCJ7V0A 10mΩ FDMS86500DC MOTHERBOARD PLUG-IN OR Si7164DP CONNECTOR CARD OR 4226 F04 CONNECTOR Figure 4. 2-Channel Controller with Inrush Current Control but without Connector Enable Turn-Off Sequence during current limit while preserving the fast pull-down of the gate. The capacitor C should be sized to limit the The MOSFET switch can be turned off by a variety of con- G inrush current below the circuit breaker trip current. For ditions. A normal turn-off is initiated by the ON pin going leaded MOSFET with heatsink, an additional 10Ω resistor low. Additionally, a circuit breaker/current limit timeout will (as shown with R1 in Figure 13) can be added close to the cause the MOSFET to turn off, as will V dropping below CC MOSFET gate pin to prevent possible parasitic oscillation its undervoltage lockout potential V . Alternatively, CC(UVL) due to more trace/wire inductance and capacitance. the FAULT pin can be externally pulled low to force the gate shutdown. Under any of these conditions, the MOSFET is The MOSFET is turned on by a 9µA current source charging turned off with a 3mA current pulling down from GATE. up the GATE. When the GATE voltage reaches the MOSFET About 2.85mA of that current flows from GATE to OUT threshold voltage, the MOSFET turns on and the SOURCE and the remainder flows to GND. When the GATE voltage voltage follows the GATE voltage as it increases. The GATE is below the OUT pin, the GATE is pulled towards GND by voltage rises with a slope 9µA/C and the supply inrush G a 150µA current source. current is: C Inrush Current Control I = L •9µA (1) INRUSH C G In most applications, keeping the inrush current at current limit is an acceptable start-up method if it does not trip the Note that the voltage across the MOSFET switch can be fault timer FTMR and the MOSFET has an adequate safe large during inrush current control. If the inrush current is operating margin. To keep the inrush sense resistor voltage below the circuit breaker threshold, the fault timer FTMR below the circuit breaker threshold voltage VCB, a resistor is not activated. In some applications like Firewire where RG and a capacitor CG can be inserted between the GATE a large supply voltage step up transient can occur, the pin and ground as shown in Figure 4. The capacitor CG with current limit amplifier is momentarily activated and the a grounded terminal and interconnect inductance can lead GATE is partially discharged. Once the switch current falls to parasitic MOSFET oscillations. A resistor RG between below the current limit, the GATE will continue to charge 10Ω and 100Ω is typically adequate to prevent parasitic up at the supply inrush control rate. oscillation. R also allows C to act as a charge reservoir G G 4226f 12

LTC4226 applicaTions inForMaTion Overcurrent Fault ILIM The LTC4226 manages overcurrent faults by differentiat- ICB ing between circuit breaker faults and current limit faults. Typical applications have a load capacitor to filter the load IOUT current. A large load capacitor is an effective filter, but it can increase MOSFET switch power dissipation at start-up MOSFET FTMR OFF or during step up supply transients. VOUT When the MOSFET is fully enhanced and the current is MODEST OVERLOAD SEVERE OVERLOAD below the current limit, the MOSFET power dissipation is IGNORED SHUTS OFF low and is determined by the R and the switch cur- 4226 F05 DSON Figure 5. Dual-Rate Fault Timing rent. If the current is above the circuit breaker threshold but below current limit, the circuit breaker CB comparator duced. The MOSFET will turn off in a fault condition where activates a I pull-up current source at the FTMR pin. FTMR(CB) the average current is above the circuit breaker threshold, When the channel current exceeds the current limit, the but the dual-rate timer extends the allowable duration for CL amplifier activates the gate driver pull-down in a closed peak currents that remain below the current limit level. loop manner. The excess GATE overdrive voltage is abruptly The FTMR pin has comparators and four current sources discharged to the OUT pin until the sense voltage between connected to an external capacitor C . The four current T V and SENSE drops below V . This brief interval is CC LIMIT sources are: the default pull-down current I , FTMR(DEF) kept short by the fast responding amplifier to reduce the the circuit breaker pull-up current source I , the FTMR(CB) excessive channel current. Next the CL amplifier servos higher current limit pull-up current source I and FTMR(CL) the GATE pin to maintain the sense voltage at V . LIMIT the reset pull-down current source I . When the FTMR(RST) During this current limit interval, the power dissipation FTMR pin voltage exceeds the V threshold, the FTMR(H) in the MOSFET increases. The worst case switch power FTMR comparator signals a fault timeout. dissipation occurs during a load short where the current is set by the current limit with the entire supply voltage The FTMR pin is held low in default normal mode whenever appearing across the MOSFET. During active current limit- the circuit breaker comparator, the current limit amplifier ing, the FTMR pin is pulled up with I . and the reset are all inactive. The default mode has the FTMR(CL) I pull-down current source activated. When the FTMR(DEF) Dual-Rate Fault Timer sense voltage exceeds the circuit breaker threshold V but CB is below V , the circuit breaker comparator enables the The fault timer pin FTMR, as illustrated in Figure 5 timing LIMIT I pull-up current source and disables the I waveforms, has a dual-rate fault pull-up that extends the FTMR(CB) FTMR(DEF) current source. When the sense voltage reaches the V allowable duration of peak currents that are above the LIMIT threshold, the current limit amplifier activates the higher circuit breaker threshold but below the current limit level. I pull-up current source. When the load current exceeds the current limit threshold, FTMR(CL) the power dissipation in the MOSFET may be high due When the FTMR pin ramps up to V , the FTMR(H) FTMR(H) to the potentially large drain-to-source voltage. In this comparator trips. The FAULT pin is asserted low and the condition, the FTMR pull-up current increases to reduce GATE to OUT voltage is discharged to turn off the MOSFET. the fault timer duration. When the load current is below For the Auto-Retry option, the Auto-Retry internal timing the current limit threshold, the power dissipation in the is initiated. The FTMR pin is asserted high at V FTMR(H) MOSFET is less since the MOSFET is fully enhanced and until the FTMR(L) comparator is reset low at V by FTMR(L) the drain-to-source voltage is small. Therefore, when the the I pull-down source, which is activated by ON FTMR(RST) current is below the current limit threshold but above the low or UVLO or at the end of the Auto-Retry interval of circuit breaker threshold, the FTMR pull-up current is re- typically 0.5s. The FAULT pin goes high when the FTMR 4226f 13

LTC4226 applicaTions inForMaTion pin is pulled below V . The GATE to OUT voltage event of a load short. Proper choice of the MOSFET must FTMR(L) can ramp up for Auto-Retry mode if the ON pin is high accommodate high MOSFET power dissipation under the and V is not in UVLO. worst case short-circuit. There are three I , each CC FTMR(CL) corresponds with a V selected by the CLS input. The When the MOSFET current exceeds the circuit breaker LIMIT typical MOSFET SOA (safe operating area) has a constant threshold but remains below the current limit the fault P2t characteristic for single narrow (<10ms) pulse dissipa- time is given by: tion. An increase in current (V ) for constant MOSFET LIMIT 1.23V drain/source voltage results in square reduction in allowed t =C • (2) CB T I stress duration t (or square increase in I ). FTMR(CB) LIMIT FTMR(CL) The CLS pin is internally pulled to 1.23V. If it is driven When the current limit is active the fault time is given by: by a three-state output, the maximum allowable open- 1.23V circuit leakage is ±2µA. The driving output must source t =C • (3) LIMIT T I or sink more than 10µA in the high or low state. If the FTMR(CL) CLS trace crosses noisy digital signal lines, an RC filter During active current limiting, a large MOSFET drain to close to the CLS pin will filter noise pickup (as shown in source voltage can appear, and t should be selected Figure 1: R5/C3). LIMIT appropriately based on the worst MOSFET safe-operating- Auto-Retry vs Latchoff area with the OUT pin shorted to ground. The LTC4226-2 (automatic retry) version resets the FTMR A I pull-down source is active when resetting FTMR(RST) pin after a 0.5 second delay following a FTMR(H) com- the fault status. The current sources at the FTMR pin can parator timeout if the V voltage remains above the 4V be overdriven externally. The FTMR pin can be pulled high CC undervoltage lockout threshold V and the ON pin externally above V to force a fault status or the FTMR CC(UVL) FTMR(H) remains above its 1.23V V threshold. This retry delay pin can be pulled low externally towards ground to force ON can be terminated to force a 50ms delay restart by cycling a reset status. Both the FAULT and GATE pins behave the V below the V undervoltage threshold or a 10ms same way for externally driven FTMR as described above CC CC(UVL) delay restart by cycling the ON pin below the V threshold. for internal mode. A prolonged external pull-down is not ON The latchoff option (LTC4226-1) does not reset FTMR(L) recommended as it may mask normal FTMR operation. comparator automatically. It requires voltage cycling at Selecting Current Limit to Circuit Breaker Ratio either the ON pin or the VCC pin to reset FTMR pin. The ratio of the current limit voltage V and circuit LIMIT Resetting Faults breaker voltage V can be configured to allow low duty CB The circuit breaker fault can be reset by cycling the ON pin cycle, high crest factor load events like hard drive spin below and then above the ON comparator threshold. There up to operate above the maximum average load current is a turn on delay of 10ms after the ON pin transitions high. without invoking current limit. Avoiding current limit events is a good practice as the load voltage is not glitched un- Alternatively, the V pin can be cycled below and then CC necessarily by the current limit amplifier and the MOSFET above the undervoltage lockout threshold to reset faults. power dissipation is kept low. The unlatched CLS pin has There is a turn on delay of 50ms after the V pin exits CC three input states (low, open and high). This pin config- the undervoltage lockout. ures both Hot Swap channels simultaneously the preset The FTMR pin reset begins with the FTMR pin pulled down current limit voltage V to approximately 1.5×, 2× or LIMIT with 100µA to ground. This is followed by a start-up with 3× of 1.15 • V . However, higher current limit settings CB a 10µA FAULT pin pull-up and a 9µA GATE pin pull-up. will result in higher MOSFET power dissipation in the 4226f 14

LTC4226 applicaTions inForMaTion Fault Status used as FAULT indicators with resistors to reduce power dissipation at the FAULT pins. The FAULT status pin is active low with a 10µA current source pull-up to a diode below its internal supply volt- V Overvoltage Detection CC age, typically 5V for any V >7V. When a fault occurs, CC the FAULT pin pulls to ground with a 5mA limit. Although The FTMR pin can be used to detect a VCC overvoltage the FAULT pin has the same voltage rating as the supply condition with a Zener diode Z2 as shown in Figure 6. pin, sinking LED current as in Figure 9 requires a series Resistor R5 and Zener Z3 protect the FTMR pin from resistor to reduce pin power dissipation. excessive voltage while R6 provides a ground path. An overvoltage at V beyond 35V will pull the FTMR pin CC The FAULT pin is also an unlatched input to synchronize above 1.23V through diode D2A and force a fault status. the MOSFET GATE. Pulling this pin externally below 0.3V If V has a transient suppressor as shown in Figure 10, CC causes the GATE to shutoff immediately. This pin can the overvoltage threshold should be set at 35V which optionally be wire-ORed with other LTC4226's FAULT is below the transient suppressor SMCJ33A minimum pins to turn off their GATEs when one of the LTC4226 breakdown voltage of 36.7V. has a circuit breaker fault with the FTMR pin asserted at V . The other LTC4226's FTMR pin is unaffected by FTMR(H) VCC the low external FAULT input. When the LTC4226 with fault Z2 is reset (see section on auto-retry and resetting faults), the 33V R5 D2A wire-ORed FAULT pins return high and the GATEs revert 1k 1N4148 to their prior states. It is not recommended to connect an FTMR Z3 R6 LED to wire-ORed FAULT pins. 3V 1M 4226 F06 Daisy Chained Ports Figure 6. V Overvoltage Detection CC Figure 7, illustrates FireWire power distribution with Supply Transient Protection LTC4226 Hot Swap circuits and supply diode-ORing. The Firewire devices can be power providers or power All pins on the LTC4226 are tested for 44V operation with consumers and can be daisy chained together. the exception of FTMR and GATE. The GATE pins are volt- age clamped either to OUT or GND while the FTMR pins In Figure 8, a 2-port device allows either port to be powered are low voltage. If greater than 44V supply transients are internally through diode D1 or to be powered from the op- possible, 33V transient suppressors are highly recom- posite port. The higher voltage source delivers power to the mended at the V pins to clamp the voltage below the external port devices and the internal FireWire controller CC 55V absolute maximum voltage rating of the pins. interface. This permits the host power to be shutdown while the FireWire controller remains active with external power Output Positive Overvoltage Isolation provided by the port. The port can relay actively current limited power as long as there are power sources in the Transient voltage suppressors are adequate for clamping chain. More than two ports per device are possible permit- short overvoltage pulses at the ports, but they may over- ting power consumption or distribution among multiple heat if forced to sink large currents for extended periods. ports. The ports allow live plugging and unplugging with Figure 10 shows how series MOSFETs can be used to port load capacitances as large as 1mF at 33V for Figure 8. isolate positive port voltages up to the MOSFET VBVDSS. The output port step up surge current is actively limited. Q3 and Q4 are turned off when the overvoltage detection Zener Z2 pulls both FTMR1 and FTMR2 high through D2A Figure 9 shows a 12V host power source application that and D2B. The resistors R7 and R8 with MOSFETs Q5 and can drive a remote load capacitance up to 100µF with a Q6 facilitate restart by pulling up through the body diodes small MOSFET like the Si2318DS. 2mA rated LEDs can be of Q1 and Q2, respectively. 4226f 15

LTC4226 applicaTions inForMaTion NODE B NODE A 1394 1394 1394 1394 SOCKET PLUG PLUG SOCKET LTC4226 1394 POWER CONSUMER SOCKET POWER PATH POWER 1394 SOURCE SOCKET NODE C LTC4226 1394 1394 1394 1394 SOCKET PLUG PLUG SOCKET POWER PROVIDER (MASTER) POWER PATH LTC4226 NODE D 1394 1394 1394 1394 SOCKET PLUG PLUG SOCKET POWER LTC4226 1394 POWER CONSUMER SOURCE SOCKET 4226 F07 ALTERNATE POWER PROVIDER (SLAVE) Figure 7. FireWire Power Distribution Example PORT 1 Q1 SSD31P5 30RmS1Ω FODRM SSi876156040DDPC SO13C9K4ET P1L3U94G OPTIONAL 7V TO 33V V REG R1 R3 150k 150k VCC1 SENSE1 GATE1 OUT1 1.5A PHY ON1 FTMR1 FAULT1 CT1 220nF OPTIONAL CLS LTC4226-2 GND CONTROLLER FAULT2 CT2 220nF ON2 FTMR2 R2 R4 VCC2 SENSE2 GATE2 OUT2 PORT 2 50k 50k 1394 1394 SOCKET PLUG + C1 ZS1MCJ33A 30RmS2Ω FDMS8Q62500DC 10µF OR Si7164DP 1.5A 4226 F08 Figure 8. 2-Port FireWire Master or Slave Application 4226f 16

LTC4226 applicaTions inForMaTion PORT 1 SSD31P5 33RmS1Ω Si23Q181CDS SO13C9K4ET P1L3U94G OPTIONAL 12V FAULT INDICATORS VCC1 SENSE1 GATE1 OUT1 1.35A R1 LED1 ON1 FTMR1 4.7k FAULT1 CT1 15nF CLS LTC4226-2 GND FAULT2 CT2 15nF R2 ON2 FTMR2 4.7k LED2 VCC2 SENSE2 GATE2 OUT2 PORT 2 1394 1394 SOCKET PLUG Z1 RS2 Q2 DFLT15A 33mΩ Si2318CDS 1.35A 4226 F09 Figure 9. 12V FireWire Ports with LED Fault Indicators R7 Q5 1k BSS139 PORT 1 SSD31P5 30RmS1Ω FODRM SSi8Q761156040DDPC OFRD SMiQ7S1327627D2P SO13C9K4ET P1L3U94G OPTIONAL RG1 7V TO 33V V REG 10Ω R1 R3 1.5A 150k 150k D2A VCC1 SENSE1 GATE1 OUT1 MMBD4148CA PHY ON1 FTMR1 FAULT1 CT1 220nF OPTIONAL CLS LTC4226-2 GND CONTROLLER FAULT2 CT2 220nF ON2 FTMR2 R502k R504k VCC2 SENSE2 GATE2 OUT2 1R0GΩ2 MMBD414D8C2BA PORT 2 1394 1394 SOCKET PLUG Z2 R353V + C1 ZS1MCJ33A 30RmS2Ω FDMS8Q62500DC FDMQS42672 1k 10µF OR Si7164DP OR Si7172DP 1.5A 4226 F10 R8 Q5 1k BSS139 Z3 R6 3V 1M Figure 10. 2 FireWire Ports with Positive Overvoltage Isolation 4226f 17

LTC4226 applicaTions inForMaTion Design Example Setting the current limit fault timeout at about 14ms gives: As a design example, take the following specifications for t •20µA C = LIMIT =228nF Figure 8 with a load capacitor COUT of 1mF (not shown on T 1.23V schematic) at the cable end of port 1: Choose a standard value of 220nF. The resulting FTMR The channel is rated for a maximum V of 33V at 1.5A, CC timeout in current limit is: C  = 1mF and current limit at 1.5× of circuit breaker OUT current. tLIMIT = 13.5ms Circuit breaker current plus a 15% margin: The FTMR circuit breaker timeout is: ICB = 1.5A • 1.15 = 1.725A, tCB = 135ms Sense resistor: The resistor pair R1 and R2 sets the ON threshold voltage for both channels. In this case R1 = 150k, R2 = 50k: 50mV RS= ≈29mΩ (R1+R2)•1.23 1.5A • 1.15 V ON Threshold= =4.92V CC R2 Start-up in current limit with CLS low, V = 1.5 • 1.15 • V Layout Considerations LIMIT CB and To achieve accurate current sensing, Kelvin connections for the sense resistor are recommended. The PCB layout I = 1.5 • 1.15 • I ≈ 2.98A LIMIT CB of Kelvin sensing traces should be balanced, symmetrical Calculate the time it takes to charge up C in current limit: and minimized to reduce error. In addition, the PCB layout OUT for the sense resistors and the power MOSFETs should C •V t = OUT CC ≈11ms include good thermal management techniques for device CHARGE I LIMIT power dissipation such as vias and wide metal area. A recommended PCB layout for the sense resistor and power During a normal start-up where all of the current charges MOSFET is illustrated in Figure 11. To avoid the need for C , the average power dissipation in the MOSFET is OUT the additional MOSFET GATE pin resistor (R1 in Figure 13), given by: the GATE trace over ground plane should have minimized V •I trace length and capacitance. CC LIMIT P = =49.2W DISS 2 Q2 RG2 RS2 If the output is shorted to ground, the average power dissipation in MOSFET doubles: P = V • I = 98.4W DISS CC LIMIT The SOA (safe operating area) curve for the FDMS86500DC LTC4226 MOSFET shows 100W for 35ms. During a normal start- 1 up the MOSFET dissipates 49.2W for 11ms at 33V with RG1 adequate SOA margin. RS1 Q1 4226 F11 Figure 11. Recommended Layout 4226f 18

LTC4226 applicaTions inForMaTion In Hot Swap applications where load currents can be 5A, resistors. Separate resistors allow different current limit narrow PCB tracks exhibit more resistances than wide in each direction to be set. The transient suppressor at the tracks and operate at elevated temperatures. The mini- sense pins allow the circuit breaker to trip when either the mum trace width for 1oz copper foil is 0.02" per amp to input or output voltage exceeds the suppressor breakdown make sure the trace stays at a reasonable temperature. voltage. When the OUT voltage exceeds the suppressor Using 0.03" per amp or wider is recommended. Note that breakdown, GATE2 shuts down after FTMR2 time-out and 1oz copper exhibits a sheet resistance of about 0.5mΩ/ this can prevent suppressor blow out. The timing capacitor square. The use of vias allow multi-copper planes to be at FTMR2 can be selected to keep the suppressor within used to improve both electrical conduction and thermal safe operating area. dissipation. Thicker top and bottom copper such as 3oz or more can improve electrical conduction and reduce High Current Applications PCB trace dissipation. Figure 13 and Figure 14 show 44A and 89A continuous It is important to minimize noise pickup on PCB traces current applications for bus power distribution. The bus for ON, FTMR, FAULT, CLS and GATE. If an R resistor is connection inductance causes a supply dip at the sense G used, place the resistor as close to the MOSFET gate as resistor when there is a load transient. The worst transient possible to limit the parasitic trace capacitance that leads is a short at the output or the sudden connection of an to MOSFET self-oscillation. uncharged load capacitor. Without capacitors C1 and C2 for channel 1, V voltage can dip below the LTC4226 CC1 Bidirectional Current Limiting undervoltage lockout threshold resulting in a channel 1 UVLO reset. The low ESR electrolytic capacitor C1 and Figure 16 shows an application with bidirectional current ceramic capacitor C2 should be placed very close to the limiting with a common sense resistor. Figure 12 shows sense resistor V terminal and the ground plane to an asymmetric bidirectional current limiter for operating CC1 minimize inductance. voltage between 7V and 30V using two separate sense FDMS86500DC FDMS86500DC VIN 30mΩ 50mΩ OR Si7164DP OR Si7164DP OUT 7V TO 30V RANGE 7V TO 30V RANGE SMCJ33A 1.48A/0.89A VCC1 SENSE1 SENSE2 VCC2 GATE1 OUT1 OUT2 GATE2 ON1 FTMR1 FAULT1 FAULT1 220nF LTC4226-2 CLS CLS GND FAULT2 FAULT2 220nF ON2 FTMR2 4226 F12 Figure 12. 7V to 30V Asymmetric Bidirectional Current-Limiter 4226f 19

LTC4226 applicaTions inForMaTion RS1 Q1 1mΩ IRF2804S-7PPBF OUTPUT1 12V R1 R2 + C10100µF C222µF 1R0GΩ1 1C0Gn1F 12V, 44A 10k 10k 25V ×10 25V X5R VCC1 SENSE1 GATE1 OUT1 ON1 ON1 FTMR1 FAULT1 FAULT1 CT1 10nF CLS LTC4226-2 GND FAULT2 FAULT2 CT2 10nF ON2 ON2 FTMR2 VCC2 SENSE2 GATE2 OUT2 RG2 10Ω CG2 10nF OUTPUT2 + 12V, 44A Z1 C3 C4 RS2 Q2 SM6S15AHE3/2D 1000µF 22µF 1mΩ IRF2804S-7PPBF 25V ×10 4226 F13 25V X5R Figure 13. Dual Continuous 44A Typical Output At the occurrence of severe load transient, the GATE1 across R and R respectively. In the event of a current S1 S2 voltage undershoots the voltage needed for current limit fault, one channel may time out earlier than the adjacent regulation. The R and C network between GATE1 and channel due to mismatch. If FAULT1 and FAULT2 are kept G1 CG1 OUT1 help restore GATE1 voltage quickly to the voltage separate, the current in the channel of the first fault is needed for current limit regulation. When a heatsink is a diverted to the adjacent channel with a second fault time used and gate interconnect has significant capacitance and out occurring later. inductance, optional resistors R1 and R2 can be inserted Now consider the case where FAULT1 and FAULT2 are tied close to the MOSFET’s gate to prevent parasitic oscillation. together during a current fault. First fault channel FAULT1 The product of R1 and MOSFET C add delay to the cur- ISS pulls low and this causes an input low at FAULT2 with rent limit response. For short PCB gate interconnection, GATE2 pulling low immediately. FTMR2 does not time out these optional resistors are not needed. due to the common FAULT connection with GATE2 disabled Two Hot Swap channels with identical sense resistors earlier than the case of separate FAULT connection. The and MOSFETs can have their outputs connected together MOSFET Q1 where the first occurrence of current fault to almost double the current output capability without occurs would not be stressed as much as Q2 since the significant improvement in MOSFET’s SOA. OUTPUT1 in fully enhanced Q2 determines the parallel channels V CC Figure 14 can be connected to OUTPUT2 to give 178A. and OUT voltage drop. Common ON pin connections are FTMR1 and FTMR2 should be kept separate as capaci- preferred for parallel channel applications. tors C and C individually monitor the sense voltages T1 T2 4226f 20

LTC4226 applicaTions inForMaTion RS1 Q1 0.5mΩ IRF1324S-7PPBF OUTPUT1 +12V + 12V, 89A C1 C2 R3 R4 1000µF 22µF 10k 10k ×252V ×252V0 1R01Ω* 1R0GΩ1 1C0Gn1F X5R VCC1 SENSE1 GATE1 OUT1 ON1 ON1 FTMR1 FAULT1 FAULT1 CT1 1nF CLS LTC4226-2 GND FAULT2 FAULT2 CT2 1nF ON2 ON2 FTMR2 VCC2 SENSE2 GATE2 OUT2 R2* 1R0GΩ2 CG2 10Ω 10nF OUTPUT2 + 12V, 89A Z1 C3 C4 RS2 Q2 SM8S15AHE3/2D 1000µF 22µF 0.5mΩ IRF1324S-7PPBF ×2 ×20 4226 F14 25V 25V CONNECTION OPTION TO SHARE MOSFET SOA X5R *OPTIONAL Figure 14. Dual Continuous 89A Typical Output One drawback of the separate FTMR scheme for parallel one of the channels is in current limit mode, the clamp channels is that one timer may ramp up in current limit from the other channel will slow down the current limited mode before the other channel, resulting in shorter circuit channel’s FTMR ramp rate as shown in Figure 15’s accom- breaker timer duration and/or a reduction in the combined panying waveforms. This scheme assumes common V CC circuit breaker current threshold due to R mismatch. and ON pins, and both channels should be on the same DS(ON) These issues are solved by using two cross-coupled PNP chip. Channel to channel matching is 6% for V , 6% CB clamps connected between the FTMR pins as shown in Fig- for V , and GATE high skew delay timing for both ON LIMIT ure 15. The FAULT pins are shorted together and connected and V are 10%. The GATE pins must be synchronized CC to an external open drain pull-down which is controlled by by asserting the FAULT inputs low to mask out t ON(UVL) a gate synchronization signal. The PNPs prevent a current skew. Asserting the FAULT pins low for at least 100ms at limited channel’s FTMR from ramping up too fast while power-up will ensure that the MOSFETs turn on together. the other channel is still in circuit breaker mode. If only LTC4226 FTMR2 FTMR1 FAULT1 FAULT2 FTMR2 FAULT FTMR FTMR1 DELAYED 0.5V/DIV OFF ON IOUT TOTAL OUTPUT CURRENT Q3 Q4 5A/DIV 2N3906 2N3906 FAULT CT1 CT2 FAULT 10nF 10nF 5V/DIV 1ms/DIV 4226 F15 Figure 15. PNP Connected FTMR for 2 Parallel Channels 4226f 21

LTC4226 package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UD Package 16-Lead Plastic QFN (3mm × 3mm) (Reference LTC DWG # 05-08-1700 Rev A) Exposed Pad Variation AA 0.70 ±0.05 3.50 ±0.05 1.65 ±0.05 2.10 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW—EXPOSED PAD R = 0.115 PIN 1 NOTCH R = 0.20 TYP 3.00 ±0.10 0.75 ±0.05 TYP OR 0.25 × 45° CHAMFER (4 SIDES) 15 16 PIN 1 0.40 ±0.10 TOP MARK (NOTE 6) 1 1.65 ±0.10 2 (4-SIDES) (UD16 VAR A) QFN 1207 REV A 0.200 REF 0.25 ±0.05 0.00 – 0.05 0.50 BSC NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-4) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4226f 22

LTC4226 package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 16-Lead Plastic MSOP (Reference LTC DWG # 05-08-1669 Rev Ø) 0.889 ± 0.127 (.035 ± .005) 5.23 3.20 – 3.45 (.206) (.126 – .136) MIN 4.039 ± 0.102 0.305 ± 0.038 0.50 (.159 ± .004) (.0120 ± .0015) (.0197) (NOTE 3) 0.280 ± 0.076 TYP BSC 16151413121110 9 (.011 ± .003) RECOMMENDED SOLDER PAD LAYOUT REF DETAIL “A” 3.00 ± 0.102 0.254 4.90 ± 0.152 (.118 ± .004) (.010) 0° – 6° TYP (.193 ± .006) (NOTE 4) GAUGE PLANE 0.53 ± 0.152 1234567 8 (.021 ± .006) 1.10 0.86 (.043) (.034) DETAIL “A” MAX REF 0.18 (.007) SEATING PLANE 0.17 – 0.27 0.1016 ± 0.0508 (.007 – .011) (.004 ± .002) TYP 0.50 NOTE: (.0197) MSOP (MS16) 1107 REV Ø 1. DIMENSIONS IN MILLIMETER/(INCH) BSC 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 4226f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 23 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC4226 Typical applicaTion Si7164DP 30mΩ Si7164DP VIN OUT 7V TO 30V 7V TO 30V SMCJ33A 1.48A OUT2 GATE2 SENSE2 VCC1 VCC2 SENSE1 GATE1 OUT1 ON1 FTMR1 FAULT1 FAULT1 220nF LTC4226-2 CLS CLS GND FAULT2 FAULT2 220nF ON2 FTMR2 4226 F16 Figure 16. Bidirectional Current-Limiter relaTeD parTs PART NUMBER DESCRIPTION COMMENTS LTC1421 Dual Channel Hot Swap Controller Operates from 3V to 12V, Supports –12V LTC1422 Single Channel Hot Swap Controller Operates from 2.7V to 12V LTC1645 Dual Channel Hot Swap Controller Operates from 3V to 12V, Power Sequencing, LTC1647 Dual Channel Hot Swap Controller Operates from 2.7V to 16.5V LTC4210 Single Channel Hot Swap Controller Operates from 2.7V to 16.5V, Active Current Limiting LTC4211 Single Channel Hot Swap Controller Operates from 2.5V to 16.5V, Multifunction Current Control LTC4215 Single Hot Swap Controller with ADC and I2C Interface Operates from 2.9V to 15V, Monitors Voltage and Current with 8-Bit ADC LTC4216 Single Channel Hot Swap Controller Operates from 0V to 6V LTC4218 Single Channel Hot Swap Controller Operates from 2.9V to 26.5V, Adjustable, 5% Accurate (15mV) Current Limit LTC4222 Dual Hot Swap Controller with ADC and I2C Interface Operates from 2.9V to 29V, Digitally Monitors Voltage and Current with 10-Bit ADC LTC4224 Dual Channel Hot Swap Controller Operates from 1V to 6V LTC4227 Dual Ideal Diode and Single Hot Swap Controller Operates from 2.9V to 18V LTC4228 Dual Ideal Diode and Hot Swap Controller Operates from 2.9V to 18V LTC4230 Triple Channel Hot Swap Controller Operates from 1.7V to 16V, Multifunction Current Control LTC4280 Single Hot Swap Controller with ADC and I2C Interface Operates from 2.9V to 15V, Monitors Voltage and Current with 8-Bit ADC LTC4352 Ideal Diode Controller with Monitoring Operates from 0V to 18V, UV, OV LTC4364 Surge Stopper/Hot Swap Controller with Ideal Diode Operates from 4V to 80V, –40V Reverse Input 4226f 24 Linear Technology Corporation LT 1012 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2012