LTC3859AL Triple Output, Buck/Buck/Boost Synchronous Controller with 28µA Burst Mode I Q FEATURES DESCRIPTION n Low Operating I : 28μA (One Channel On) The LTC®3859AL is a high performance triple output (buck/ Q n Dual Buck Plus Single Boost Synchronous Controllers buck/boost) synchronous DC/DC switching regulator n Outputs Remain in Regulation Through Cold Crank controller that drives all N-channel power MOSFET stages. Down to 2.5V Constant frequency current mode architecture allows n Wide Bias Input Voltage Range: 4.5V to 38V a phase-lockable switching frequency of up to 850kHz. The LTC3859AL operates from a wide 4.5V to 38V input n Buck Output Voltage Range: 0.8V ≤ V ≤ 24V OUT supply range. When biased from the output of the boost n Boost Output Voltage Up to 60V converter or another auxiliary supply, the LTC3859AL can n R or DCR Current Sensing SENSE operate from an input supply as low as 2.5V after start-up. n 100% Duty Cycle for Boost Synchronous MOSFET Even in Burst Mode® Operation The 28μA no-load quiescent current extends operating n Phase-Lockable Frequency (75kHz to 850kHz) runtime in battery powered systems. OPTI-LOOP com- n Programmable Fixed Frequency (50kHz to 900kHz) pensation allows the transient response to be optimized n Selectable Continuous, Pulse-Skipping or Low Ripple over a wide range of output capacitance and ESR values. The LTC3859AL features a precision 0.8V reference for Burst Mode Operation at Light Loads the bucks, 1.2V reference for the boost and a power good n Very Low Buck Dropout Operation: 99% Duty Cycle output indicator. The PLLIN/MODE pin selects among n Adjustable Output Voltage Soft-Start or Tracking Burst Mode operation, pulse-skipping mode, or continu- n Low Shutdown I : 10μA Q ous inductor current mode at light loads. n Small 38-Lead 5mm × 7mm QFN and TSSOP Packages Compared to the LTC3859 and the LTC3859A, the APPLICATIONS LTC3859AL is fully pin-compatible, but with lower Burst n Automotive Always-On and Start-Stop Systems Mode operation I (28µA with one channel on). Q n Battery Operated Digital Devices L, LT, LTC, LTM, Burst Mode, OPTI-LOOP and µModule are registered trademarks and n Distributed DC Power Systems No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5705919, n Multioutput Buck-Boost Applications 5929620, 6144194, 6177787, 6580258. TYPICAL APPLICATION VOUT3 REGULATED AT 10V WHEN VIN < 10V 220µF 1µF Efficiency and Power Loss vs FOLLOWS VIN WHEN VIN > 10V 499k VFB3 VBIAS Output Current 68.1k TG1 100 10000 4.9µH 6mΩ VOUT1 90 VIN = 12V (START-UP2 .A5BVO TVOE 35V8VIVN) 2mΩ 1.2µH T SGW33 LTC3859AL SBWG11 55VA 7800 EVFOFUITC1I E=N BCUYRST 1000P 220µF BG3 %) OW SSINEETNNVSSCEEC33–+ SSEENNSSVEEF11B+–1 68.1k 357k 220µF EFFICIENCY (53640000 11000ER LOSS (mW) 4.7µF RUN1, 2, 3 VOUT1 = BURST LOSS BOOST1, 2, 3 EXTVCC VOUT1 20 1 0.1µF 10 SW1, 2, 3 TG2 6.5µH 8mΩ VOUT2 0 0.1 ITH1, 2, 3 SW2 8.5V 0.0001 0.001 0.01 0.1 1 10 BG2 3A OUTPUT CURRENT (A) 3859al TA01b SENSE2+ TRACK/SS1, 2 SENSE2– 0.1µF SS3 VFB2 PGND SGND 68.1k 649k 68µF 3859al TA01a 3859alfa 1 For more information www.linear.com/LTC3859AL

LTC3859AL ABSOLUTE MAXIMUM RATINGS (Note 1) Bias Input Supply Voltage (V ) ..............–0.3V to 40V SENSE1+, SENSE2+, SENSE1– BIAS Buck Top Side Driver Voltages SENSE2– Voltages .....................................–0.3V to 28V (BOOST1, BOOST2) .............................–0.3V to 46V SENSE3+, SENSE3– Voltages .....................–0.3V to 40V Boost Top Side Driver Voltages FREQ Voltages ......................................–0.3V to INTV CC (BOOST3) ............................................–0.3V to 76V EXTV ......................................................–0.3V to 14V CC Buck Switch Voltage (SW1, SW2) ................–5V to 40V I , I , I , V , V , V Voltages ....–0.3V to 6V TH1 TH2 TH3 FB1 FB2 FB3 Boost Switch Voltage (SW3) ........................–5V to 70V PLLIN/MODE, PGOOD1, OV3 Voltages ........–0.3V to 6V INTV , (BOOST1–SW1), TRACK/SS1, TRACK/SS2, SS3 Voltages .....–0.3V to 6V CC (BOOST2–SW2), (BOOST3–SW3) ...........–0.3V to 6V Operating Junction Temperature Range (Notes 2, 3) RUN1, RUN2, RUN3 ....................................–0.3V to 8V LTC3859ALE, LTC3859ALI ................–40°C to 125°C Maximum Current Sourced Into Pin LTC3859ALH .....................................–40°C to 150°C from Source >8V ..............................................100µA LTC3859ALMP ...................................–55°C to 150°C Storage Temperature Range ..............–65°C to 150°C PIN CONFIGURATION TOP VIEW TOP VIEW ITH1 1 38 TRACK/SS1 S1 SENSVEF1B1+ 23 3376 PTGG1OOD1 –SENSE1+SENSE1 VFB1 ITH1 TRACK/S PGOOD1 TG1 SENSE1– 4 35 SW1 38 37 36 35 34 33 32 FREQ 5 34 BOOST1 FREQ 1 31 SW1 PLLIN/MODE 6 33 BG1 PLLIN/MODE 2 30 BOOST1 SS3 3 29 BG1 SS3 7 32 SW3 SENSE3+ 8 31 TG3 SENSE3+ 4 28 SW3 SENSE3– 5 27 TG3 SENSE3– 9 30 BOOST3 VFB3 10 PG3N9D 29 BG3 VITFHB33 76 PG3N9D 2256 BBOGO3ST3 ITH3 11 28 VBIAS SGND 8 24 VBIAS SGND 12 27 EXTVCC RUN1 9 23 EXTVCC RUN1 13 26 INTVCC RUN2 10 22 INTVCC RUN2 14 25 BG2 RUN3 11 21 BG2 RUN3 15 24 BOOST2 SENSE2– 12 20 BOOST2 SENSE2– 16 23 SW2 13 14 15 16 17 18 19 SENSVEF2B+2 1178 2221 TOGV23 +SENSE2 VFB2 ITH2 ACK/SS2 OV3 TG2 SW2 ITH2 19 20 TRACK/SS2 TR UHF PACKAGE FE PACKAGE 38-LEAD (5mm × 7mm) PLASTIC QFN 38-LEAD PLASTIC TSSOP TJMAX = 150°C, qJA = 34.7°C/W TJMAX = 150°C, qJA = 25°C/W EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB 3859alfa 2 For more information www.linear.com/LTC3859AL

LTC3859AL ORDER INFORMATION http://www.linear.com/product/LTC3859AL#orderinfo LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3859ALEFE#PBF LTC3859ALEFE#TRPBF LTC3859ALFE 38-Lead Plastic TSSOP –40°C to 125°C LTC3859ALIFE#PBF LTC3859ALIFE#TRPBF LTC3859ALFE 38-Lead Plastic TSSOP –40°C to 125°C LTC3859ALHFE#PBF LTC3859ALHFE#TRPBF LTC3859ALFE 38-Lead Plastic TSSOP –40°C to 150°C LTC3859ALMPFE#PBF LTC3859ALMPFE#TRPBF LTC3859ALFE 38-Lead Plastic TSSOP –55°C to 150°C LTC3859ALEUHF#PBF LTC3859ALEUHF#TRPBF 3859AL 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C LTC3859ALIUHF#PBF LTC3859ALIUHF#TRPBF 3859AL 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C LTC3859ALHUHF#PBF LTC3859ALHUHF#TRPBF 3859AL 38-Lead (5mm × 7mm) Plastic QFN –40°C to 150°C LTC3859ALMPUHF#PBF LTC3859ALMPUHF#TRPBF 3859AL 38-Lead (5mm × 7mm) Plastic QFN –55°C to 150°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at T = 25°C. V = 12V, V = 5V, EXTV = 0V unless otherwise A BIAS RUN1,2,3 CC noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Bias Input Supply Operating Voltage 4.5 38 V BIAS Range V Buck Regulated Feedback Voltage (Note 4); I Voltage = 1.2V FB1,2 TH1,2 0°C to 85°C, All Grades 0.792 0.800 0.808 V LTC3859ALE, LTC3859ALI l 0.788 0.800 0.812 V LTC3859ALH, LTC3859ALMP l 0.786 0.800 0.812 V V Boost Regulated Feedback Voltage (Note 4); I Voltage = 1.2V FB3 TH3 0°C to 85°C, All Grades 1.183 1.200 1.214 V LTC3859ALE, LTC3859ALI l 1.181 1.200 1.218 V LTC3859ALH, LTC3859ALMP l 1.176 1.200 1.218 V I Feedback Current (Note 4) –2 ±50 nA FB1,2,3 V Reference Voltage Line Regulation (Note 4); V = 4V to 38V 0.002 0.02 %/V REFLNREG IN V Output Voltage Load Regulation (Note 4) LOADREG Measured in Servo Loop; l 0.01 0.1 % DITH Voltage = 1.2V to 0.7V Measured in Servo Loop; l –0.01 –0.1 % DITH Voltage = 1.2V to 2V g Transconductance Amplifier g (Note 4); I = 1.2V; 2 mmho m1,2,3 m TH1,2,3 Sink/Source 5µA 3859alfa 3 For more information www.linear.com/LTC3859AL

LTC3859AL ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at T = 25°C. V = 12V, V = 5V, EXTV = 0V unless otherwise A BIAS RUN1,2,3 CC noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I Input DC Supply Current (Note 5) Q Pulse-Skipping or RUN1 = 5V and RUN2,3 = 0V or 1.5 mA Forced Continuous Mode RUN2 = 5V and RUN1,3 = 0V or (One Channel On) RUN3 = 5V and RUN1,2 = 0V V ON = 0.83V (No Load) FB1, 2 V = 1.25V FB3 Pulse-Skipping or RUN1,2,3 = 5V, 3 mA Forced Continuous Mode V = 0.83V (No Load) FB1,2 (All Channels On) V = 1.25V FB3 Sleep Mode RUN1 = 5V and RUN2,3 = 0V or l 28 48 µA (One Channel On, Buck) RUN2 = 5V and RUN1,3 = 0V l 35 59 V = 0.83V (No Load) FB,ON Sleep Mode RUN3 = 5V and RUN1,2 = 0V 33 53 µA (One Channel On, Boost) V = 1.25V FB3 Sleep Mode RUN1 = 5V and RUN2 = 0V or 33 46 µA (Buck and Boost Channel On) RUN2 = 5V and RUN1 = 0V 40 59 RUN3 = 5V V = 0.83V (No Load) FB1,2 V = 1.25V FB3 Sleep Mode RUN1,2,3 = 5V, 38 56 µA (All Three Channels On) V = 0.83V (No Load) FB1,2 V = 1.25V FB3 Shutdown RUN1,2,3 = 0V 10 20 µA UVLO Undervoltage Lockout INTV Ramping Up l 4.15 4.5 V CC INTV Ramping Down l 3.5 3.8 4.0 V CC V Buck Feedback Overvoltage Protection Measured at V Relative to 7 10 13 % OVL1,2 FB1,2 Regulated V FB1,2 I + SENSE+ Pin Current Bucks (Channels 1 and 2) ±1 µA SENSE1,2 I + SENSE+ Pin Current Boost (Channel 3) 170 µA SENSE3 I – SENSE– Pin Current Bucks (Channels 1 and 2) SENSE1,2 V < V – 0.5V ±2 µA OUT1,2 INTVCC V > V + 0.5V 700 µA OUT1,2 INTVCC I – SENSE– Pin Current Boost (Channel 3) ±1 µA SENSE3 V +, V – = 12V SENSE3 SENSE3 DF Maximum Duty Factor for TG Bucks (Channels 1,2) in Dropout, FREQ = 0V 98 99 % MAX,TG Boost (Channel 3) in Overvoltage 100 % DF Maximum Duty Factor for BG Bucks (Channels 1,2) in Overvoltage 100 % MAX,BG Boost (Channel 3) 96 % I Soft-Start Charge Current V = 0V 3 5 8 µA TRACK/SS1,2 TRACK/SS1,2 I Soft-Start Charge Current V = 0V 3 5 8 µA SS3 SS3 V ON RUN1 Pin Threshold V Rising l 1.18 1.24 1.32 V RUN1 RUN1 V ON RUN2,3 Pin Threshold V Rising l 1.21 1.27 1.33 V RUN2,3 RUN2,3 V Hyst RUN Pin Hysteresis 70 mV RUN1,2,3 V Maximum Current Sense Threshold V = 0.7V, V – = 3.3V l 43 50 57 mV SENSE1,2,3(MAX) FB1,2 SENSE1,2 V = 1.1V, V + = 12V FB1,2,3 SENSE3 V SENSE3 Pins Common Mode Range 2.5 38 V SENSE3(CM) (BOOST Converter Input Supply Voltage) 3859alfa 4 For more information www.linear.com/LTC3859AL

LTC3859AL ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at T = 25°C. V = 12V, V = 5V, EXTV = 0V unless otherwise A BIAS RUN1,2,3 CC noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Gate Driver TG1,2 Pull-Up On-Resistance 2.5 Ω Pull-Down On-Resistance 1.5 Ω BG1,2 Pull-Up On-Resistance 2.4 Ω Pull-Down On-Resistance 1.1 Ω TG3 Pull-Up On-Resistance 1.2 Ω Pull-Down On-Resistance 1.0 Ω BG3 Pull-Up On-Resistance 1.2 Ω Pull-Down On-Resistance 1.0 Ω TG Transition Time: (Note 6) TG1,2,3 t Rise Time C = 3300pF 25 ns r LOAD TG1,2,3 t Fall Time C = 3300pF 16 ns f LOAD BG Transition Time: (Note 6) BG1,2,3 t Rise Time C = 3300pF 28 ns r LOAD BG1,2,3 t Fall Time C = 3300pF 13 ns f LOAD TG/BG t Top Gate Off to Bottom Gate On Delay C = 3300pF Each Driver Bucks (Channels 1, 2) 30 ns 1D LOAD Synchronous Switch-On Delay Time Boost (Channel 3) 70 ns BG/TG t Bottom Gate Off to Top Gate On Delay C = 3300pF Each Driver Bucks (Channels 1, 2) 30 ns 1D LOAD Top Switch-On Delay Time Boost (Channel 3) 70 ns t Buck Minimum On-Time (Note 7) 95 ns ON(MIN)1,2 t Boost Minimum On-Time (Note 7) 120 ns ON(MIN)3 INTV Linear Regulator CC V Internal V Voltage 6V < V < 38V, V = 0V, I = 0mA 5.0 5.4 5.6 V INTVCCVBIAS CC BIAS EXTVCC INTVCC V INTV Load Regulation I = 0mA to 50mA, V = 0V 0.7 2 % LDOVBIAS CC CC EXTVCC V Internal V Voltage 6V < V < 13V, I = 0mA 5.0 5.4 5.6 V INTVCCEXT CC EXTVCC INTVCC V INTV Load Regulation I = 0mA to 50mA, V = 8.5V 0.7 2 % LDOEXT CC CC EXTVCC V EXTV Switchover Voltage EXTV Ramping Positive 4.5 4.7 V EXTVCC CC CC V EXTV Hysteresis 200 mV LDOHYS CC Oscillator and Phase-Locked Loop f Programmable Frequency R = 25k; PLLIN/MODE = DC Voltage 115 kHz 25k FREQ f Programmable Frequency R = 65k; PLLIN/MODE = DC Voltage 440 kHz 65k FREQ f Programmable Frequency R = 105k; PLLIN/MODE = DC Voltage 835 kHz 105k FREQ f Low Fixed Frequency V = 0V PLLIN/MODE = DC Voltage 320 350 380 kHz LOW FREQ f High Fixed Frequency V = INTV ; PLLIN/MODE = DC Voltage 485 535 585 kHz HIGH FREQ CC f Synchronizable Frequency PLLIN/MODE = External Clock l 75 850 kHz SYNC PGOOD1 Output V PGOOD1 Voltage Low I = 2mA 0.2 0.4 V PGL1 PGOOD1 I PGOOD1 Leakage Current V = 5V ±1 µA PGOOD1 PGOOD1 V PGOOD1 Trip Level V with Respect to Set Regulated Voltage PG1 FB1 V Ramping Negative –13 –10 –7 % FB1 Hysteresis 2.5 % V Ramping Positive 7 10 13 % FB1 Hysteresis 2.5 % 3859alfa 5 For more information www.linear.com/LTC3859AL

LTC3859AL ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at T = 25°C. V = 12V, V = 5V, EXTV = 0V unless otherwise A BIAS RUN1,2,3 CC noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS T Delay For Reporting a Fault 40 µs PG1 OV3 Boost Overvoltage Indicator Output V OV3 Voltage Low I = 2mA 0.2 0.4 V OV3L OV3 I OV3 Leakage Current V = 5V ±1 µA OV3 OV3 V OV3 Trip Level V Ramping Positive with Respect to Set 6 10 13 % OV FB3 Regulated Voltage Hysteresis 1.5 % BOOST3 Charge Pump I BOOST3 Charge Pump Available Output V = 16V; V = 12V; 65 µA BST3 BOOST3 SW3 Current Forced Continuous Mode Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: This IC includes overtermperature protection that is intended to may cause permanent damage to the device. Exposure to any Absolute protect the device during momentary overload conditions. The maximum Maximum Rating condition for extended periods may affect device rated junction temperature will be exceeded when this protection is active. reliability and lifetime. Continuous operation above the specified absolute maximum operating Note 2: The LTC3859AL is tested under pulsed load conditions such that junction temperature may impair device reliability or permanently damage T ≈ T . The LTC3859ALE is guaranteed to meet performance the device. J A specifications from 0°C to 85°C. Specifications over the –40°C to Note 4: The LTC3859AL is tested in a feedback loop that servos V ITH1,2,3 125°C operating junction temperature range are assured by design, to a specified voltage and measures the resultant V . The specification at FB characterization and correlation with statistical process controls. The 85°C is not tested in production and is assured by design, characterization LTC3859ALI is guaranteed over the –40°C to 125°C operating junction and correlation to production testing at other temperatures (125°C for the temperature range, the LTC3859ALH is guaranteed over the –40°C to LTC3859ALE/LTC3859ALI, 150°C for the LTC3859ALH/LTC3859ALMP). 150°C operating junction temperature range and the LTC3859ALMP For the LTC3859ALI and LTC3859ALH, the specification at 0°C is not is tested and guaranteed over the –55°C to 150°C operating junction tested in production and is assured by design, characterization and temperature range. High junction temperatures degrade operating correlation to production testing at –40°C. For the LTC3859ALMP, the lifetimes; operating lifetime is derated for junction temperatures greater specification at 0°C is not tested in production and is assured by design, than 125°C. Note that the maximum ambient temperature consistent with characterization and correlation to production testing at –55°C. these specifications is determined by specific operating conditions in Note 5: Dynamic supply current is higher due to the gate charge being conjunction with board layout, the rated package thermal impedance and delivered at the switching frequency. See the Applications Information other environmental factors. TJ is calculated from the ambient temperature section. T and power dissipation P according to the following formula: T = T + A D J A Note 6: Rise and fall times are measured using 10% and 90% levels. Delay (PD • qJA), where qJA = 34.7°C/W for the QFN package and qJA = 25°C/W times are measured using 50% levels. for the TSSOP package. Note 7: The minimum on-time condition is specified for an inductor peak-to-peak ripple current ≥ 40% of I (See the Minimum On-Time MAX Considerations in the Applications Information section). 3859alfa 6 For more information www.linear.com/LTC3859AL

LTC3859AL TYPICAL PERFORMANCE CHARACTERISTICS Efficiency and Power Loss Efficiency vs Output Current (Buck) vs Output Current (Buck) Efficiency vs Input Voltage (Buck) 100 10000 100 100 FIGURE 12 CIRCUIT 90 90 VIN = 10V 99 VOUT = 5V 80 1000 80 VIN = 20V ILOAD = 4A 98 70 P 70 %) OW %) %)97 Y (60 100ER Y (60 Y ( NC50 LO NC50 NC96 EFFICIE40 FPCUMLS EEF-FSIKCIIPEPNICNYG 10 SS (mW EFFICIE40 EFFICIE95 30 EFFICIENCY ) 30 BURST LOSS 94 20 BURST EFFICIENCY 1 20 10 FPCUMLS LEO-SSKSIPPING 10 FIGURE 12 CIRCUIT 93 LOSS VOUT = 5V 0 0.1 0 92 0.0001 0.001 0.01 0.1 1 10 0.0001 0.001 0.01 0.1 1 10 0 5 10 15 20 25 30 35 40 OUTPUT CURRENT (A) OUTPUT CURRENT (A) INPUT VOLTAGE (V) FIGURE 12 CIRCUIT 3859al G01 3859al G02 3859al G03 VIN = 10V, VOUT = 5V Load Step (Buck) Load Step (Buck) Load Step (Buck) Burst Mode Operation Pulse-Skipping Mode Forced Continuous Mode 100mVV/ODUIVT VOUT VOUT 100mV/DIV 100mV/DIV AC-COUPLED AC-COUPLED AC-COUPLED IL IL IL 2A//DIV 2A//DIV 2A//DIV 50µs/DIV 3859al G04 50µs/DIV 3859al G05 50µs/DIV 3859al G06 VIN = 12V VIN = 12V VIN = 12V VOUT = 5V VOUT = 5V VOUT = 5V FIGURE 12 CIRCUIT FIGURE 12 CIRCUIT FIGURE 12 CIRCUIT Inductor Current at Light Load Buck Regulated Feedback Voltage (Buck) Soft Start-Up (Buck) vs Temperature 808 FORCED V)806 CONTINUOUS m MODE VOUT2 AGE (804 2V/DIV LT Burst Mode VO802 OPERATION VOUT1 CK 1A/DIV 2V/DIV BA800 D RUN1/ E PULSE- RUN2 D FE798 SKIPMPOINDGE 5V/DIV LATE796 U G 2µs/DIV 3859al G07 5ms/DIV 3859al G08 E794 VVIONU =T =1 05VV VFIIGN U=R 1E2 1V2 CIRCUIT R792 ILOAD = 1mA –75 –50 –25 0 25 50 75 100 125 150 FIGURE 12 CIRCUIT TEMPERATURE (°C) 3859al G09 3859alfa 7 For more information www.linear.com/LTC3859AL

LTC3859AL TYPICAL PERFORMANCE CHARACTERISTICS Efficiency and Power Loss Efficiency Efficiency vs Input Voltage vs Output Current (Boost) vs Output Current (Boost) (Boost) 100 10000 100 100 VIN = 8V FIGURE 12 CIRCUIT 90 90 VIN = 5V 99 VBIAS = VIN 80 1000 80 98 VOUT = 10V ILOAD = 2A 70 P 70 97 %) OW %) %) Y (60 100 ER Y (60 Y ( 96 EFFICIENC5400 FPECFUFMLICS EIEEF-NFSICKCYIIPENPICNYG 10 LOSS (mW EFFICIENC5400 EFFICIENC 9954 30 BURST LOSS ) 30 93 BURST 20 EFFICIENCY 1 20 92 FIGURE 12 CIRCUIT FCM LOSS 10 PULSE-SKIPPING 10 VBIAS = VIN 91 LOSS VOUT = 10V 0 0.1 0 90 0.0001 0.001 0.01 0.1 1 10 0.0001 0.001 0.01 0.1 1 10 2 3 4 5 6 7 8 9 10 OUTPUT CURRENT (A) OUTPUT CURRENT (A) INPUT VOLTAGE (V) FIGURE 12 CIRCUIT 3859al G10 3859al G11 3859al G12 VIN = 5V, VOUT = 10V, VBIAS = VIN Load Step (Boost) Load Step (Boost) Load Step (Boost) Burst Mode Operation Pulse-Skipping Mode Forced Continuous Mode 100VmOUVT/ VOUT VOUT 100mV/DIV 100mV/DIV DIV AC-COUPLED AC-COUPLED AC- COUPLED IL IL IL 5A/DIV 5A/DIV 5A/DIV 200µs/DIV 3859al G13 200µs/DIV 3859al G14 200µs/DIV 3859al G15 VOUT = 10V VOUT = 10V VOUT = 10V VIN = 5V VIN = 5V VIN = 5V FIGURE 12 CIRCUIT FIGURE 12 CIRCUIT FIGURE 12 CIRCUIT Inductor Current at Light Load Boost Regulated Feedback (Boost) Soft Start-Up (Boost) Voltage vs Temperature 1.212 CONTFINOMUROOCUEDDSE AGE (V)11..220096 LT O Burst Mode VOUT3 K V1.203 OPERATION 2V/DIV AC B1.200 5A/DIV D RUN3 EE PULSE- 5V/DIV D F1.197 SKIPMPOINDGE GND LATE1.194 U G 2µs/DIV 3859al G16 5ms/DIV 3859al G17 RE1.191 VOUT = 10V VIN = 5V VIN = 7V FIGURE 12 CIRCUIT 1.188 ILOAD = 1mA –75 –50 –25 0 25 50 75 100 120 150 FIGURE 12 CIRCUIT TEMPERATURE (°C) 3859al G18 3859alfa 8 For more information www.linear.com/LTC3859AL

LTC3859AL TYPICAL PERFORMANCE CHARACTERISTICS INTV and EXTV EXTV Switchover and INTV CC CC CC CC INTV Line Regulation vs Load Current Voltages vs Temperature CC 5.5 5.6 6.0 5.4 EXTVCC = 0V 5.8 5.4 5.2 EXTVCC = 8.5V GE (V) 5.6 INTVCC GE (V) 5.3 GE (V) 5.0 VOLTA 55..42 INTV VOLTACC 55..21 INTV VOLTACC 444...684 EXTVCC = 5V XTV AND INTV CCCC 4445....4680 EXETXVTCVCC CFA RLILSIINNGG 4.2 E 4.2 VBIAS = 12V 5.0 4.0 4.0 0 5 10 15 20 25 30 35 40 0 20 40 60 80 100 –75 –50 –25 0 25 50 75 100 125 150 INPUT VOLTAGE (V) LOAD CURRENT (mA) TEMPERATURE (°C) 3859al G19 3859al G20 3859al G21 SENSE Pins Total Input Current Buck SENSE– Pin Input Bias Boost SENSE Pin Total Input vs V Voltage Current vs Temperature Current vs Temperature SENSE 800 900 200 VIN = 12V 700 SENSE1, 2 PINS 800 180 700 VOUT > INTVCC + 0.5V 160 SENSE3+ PIN 600 A) A) A) 140 µ µ 600 µ NT ( 500 NT ( NT ( 120 E E 500 E R R R R 400 R R 100 CU CU 400 CU SE 300 SE SE 80 N N 300 N E E E 60 S 200 SENSE3 PIN S S 200 40 100 100 20 VOUT < INTVCC – 0.5V SENSE3– PIN 0 0 0 0 5 10 15 20 25 30 35 40 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 VSENSE COMMON MODE VOLTAGE (V) TEMPERATURE (°C) TEMPERATURE (°C) 3859al G22 3859al G23 3859al G24 Maximum Current Sense Maximum Current Sense TRACK/SS Pull-Up Current Threshold vs Duty Cycle Threshold vs I Voltage vs Temperature TH 80 60 6.00 V) V) M CURRENT SENSE VOLTAGE (m673425000000 BUCK BOOST M CURRENT SENSE VOLTAGE (m–4513210000000 TRACK/SS CURRENT (µA) 555454......720557550005 MU MU PULSE-SKIPPING XI10 XI–20 FORCED CONTINUOUS 4.25 A A M M Burst Mode OPERATION 0 –30 4.00 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 –75 –50 –25 0 25 50 75 100 125 150 DUTY CYCLE (%) ITH (V) TEMPERATURE (°C) 3859al G25 3859al G26 3859al G27 3859alfa 9 For more information www.linear.com/LTC3859AL

LTC3859AL TYPICAL PERFORMANCE CHARACTERISTICS Shutdown Current Shutdown Current vs Temperature vs Input Voltage Quiescent Current vs Temperature 20 25 80 VBIAS = 12V 18 70 20 RRENT (µA) 1164 RRENT (µA) 15 RRENT (µA) 5600 ALL CHANNELS ON CU 12 CU CU 40 N N T HUTDOW 108 HUTDOW 10 UIESCEN 2300 CHANNEL 1 ON S S 5 Q 6 10 4 0 0 –75 –50 –25 0 25 50 75 100 125 150 5 10 15 20 25 30 35 40 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) VBIAS INPUT VOLTAGE (V) TEMPERATURE (°C) 3859al G28 3859al G29 3859al G30 Oscillator Frequency Undervoltage Lockout Threshold Buck Foldback Current Limit vs Temperature vs Temperature 70 600 4.4 V) 65 m 4.3 AGE ( 6505 550 FREQ = INTVCC 4.2 RISING CURRENT SENSE VOLT 52344230000555 FREQUENCY (kHz)544005000 INTV VOLTAGE (V)CC34334.....80791 FALLING UM 15 FREQ = GND 3.6 M 350 MAXI 105 3.5 0 300 3.4 0 100 200 300 400 500 600 700 800 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 FEEDBACK VOLTAGE (mV) TEMPERATURE (°C) TEMPERATURE (°C) 3859al G31 3859al G32 3859al G33 Shutdown (RUN) Threshold Charge Pump Charging Current Charge Pump Charging Current vs Temperature vs Operating Frequency vs Switch Voltage 1.40 100 100 1.35 NT (µA) 8900 VVBSOWO3S =T 31 =2 V16V –55°C NT (µA) 8900 VBOOST3 – VSW3 = 4V FREQ = 0V N VOLTAGE (V)111...322005 RRUUNNR22U,,3N3 1FRA RILSILISNIINNGGG HARGING CURRE 675000 25°C HARGING CURRE 675000 FREQ = INTVCC RUN PI1.15 RUN1 FALLING UMP C 3400 150°C UMP C 3400 1.10 P P GE 20 GE 20 1.05 HAR 10 HAR 10 C C 1.00 0 0 –75 –50 –25 0 25 50 75 100 125 150 100 200 300 400 500 600 700 800 5 10 15 20 25 30 35 40 TEMPERATURE (°C) OPERATING FREQUENCY (kHz) SWITCH VOLTAGE (V) 3859al G34 3859al G35 3859al G36 3859alfa 10 For more information www.linear.com/LTC3859AL

LTC3859AL PIN FUNCTIONS (QFN/TSSOP) FREQ (Pin 1/Pin 5): The Frequency Control Pin for the INTV (Pin 22/Pin 26): Output of the Internal Linear CC Internal VCO. Connecting the pin to GND forces the VCO Low Dropout Regulator. The driver and control circuits to a fixed low frequency of 350kHz. Connecting the pin are powered from this voltage source. Must be decoupled to INTV forces the VCO to a fixed high frequency of to PGND with a minimum of 4.7µF ceramic or tantalum CC 535kHz. Other frequencies between 50kHz and 900kHz can capacitor. be programmed using a resistor between FREQ and GND. EXTV (Pin 23/Pin 27): External Power Input to an Inter- CC The resistor and an internal 20µA source current create a nal LDO Connected to INTV . This LDO supplies INTV CC CC voltage used by the internal oscillator to set the frequency. power, bypassing the internal LDO powered from V BIAS PLLIN/MODE (Pin 2/Pin 6): External Synchronization whenever EXTV is higher than 4.7V. See EXTV Con- CC CC Input to Phase Detector and Forced Continuous Mode nection in the Applications Information section. Do not Input. When an external clock is applied to this pin, the float or exceed 14V on this pin. phase-locked loop will force the rising TG1 signal to be V (Pin 24/Pin 28): Main Bias Input Supply Pin. A BIAS synchronized with the rising edge of the external clock, bypass capacitor should be tied between this pin and the and the regulators operate in forced continuous mode. SGND pin. When not synchronizing to an external clock, this input, which acts on all three controllers, determines how the BG1, BG2, BG3 (Pins 29, 21, 25/Pins 33, 25, 29): High LTC3859AL operates at light loads. Pulling this pin to Current Gate Drives for Bottom (Synchronous) N-Channel ground selects Burst Mode operation. An internal 100k MOSFETs. Voltage swing at these pins is from ground to resistor to ground also invokes Burst Mode operation INTVCC. when the pin is floated. Tying this pin to INTV forces CC BOOST1, BOOST2, BOOST3 (Pins 30, 20, 26/Pins 34, continuous inductor current operation. Tying this pin to 24, 30): Bootstrapped Supplies to the Top Side Floating a voltage greater than 1.2V and less than INTV – 1.3V CC Drivers. Capacitors are connected between the BOOST and selects pulse-skipping operation. This can be done by SW pins and Schottky diodes are tied between the BOOST connecting a 100k resistor from this pin to INTV . CC and INTV pins. Voltage swing at the BOOST pins is from CC SGND (Pin 8/Pin 12): Small Signal Ground common to INTVCC to (VIN + INTVCC). all three controllers, must be routed separately from high SW1, SW2, SW3 (Pins 31, 19, 28/Pins 35, 23, 32): current grounds to the common (–) terminals of the C IN Switch Node Connections to Inductors. capacitors. TG1, TG2, TG3 (Pins 32, 18, 27/Pins 36, 22, 31): High RUN1, RUN2, RUN3 (Pins 9, 10, 11/Pins 13, 14, 15): Current Gate Drives for Top N-Channel MOSFETs. These are Digital Run Control Inputs for Each Controller. Forcing the outputs of floating drivers with a voltage swing equal RUN1 below 1.17V and RUN2/RUN3 below 1.20V shuts to INTV superimposed on the switch node voltage SW. CC down that controller. Forcing all of these pins below 0.7V PGOOD1 (Pin 33/Pin 37): Open-Drain Logic Output. shuts down the entire LTC3859AL, reducing quiescent PGOOD1 is pulled to ground when the voltage on the V current to approximately 10µA. FB1 pin is not within ±10% of its set point. OV3 (Pin 17/Pin 21): Overvoltage Open-Drain Logic Output for the Boost Regulator. OV3 is pulled to ground when the voltage on the V pin is under 110% of its set FB3 point, and becomes high impedance when V goes over FB3 110% of its set point. 3859alfa 11 For more information www.linear.com/LTC3859AL

LTC3859AL PIN FUNCTIONS (QFN/TSSOP) TRACK/SS1, TRACK/SS2, SS3 (Pins 34, 16, 3/Pins 38, V , V , V (Pins 36, 14, 6/Pins 2, 18, 10): Receives FB1 FB2 FB3 20, 7): External Tracking and Soft-Start Input. For the buck the remotely sensed feedback voltage for each controller channels, the LTC3859AL regulates the V voltage to from an external resistive divider across the output. FB1,2 the smaller of 0.8V, or the voltage on the TRACK/SS1,2 SENSE1+, SENSE2+, SENSE3+ (Pins 37, 13, 4/Pins 3, 17, 8): pin. For the boost channel, the LTC3859AL regulates the The (+) Input to the Differential Current Comparators. V voltage to the smaller of 1.2V, or the voltage on the FB3 The I pin voltage and controlled offsets between the TH SS3 pin. An internal 5µA pull-up current source is con- SENSE– and SENSE+ pins in conjunction with R SENSE nected to this pin. A capacitor to ground at this pin sets the set the current trip threshold. For the boost channel, the ramp time to final regulated output voltage. Alternatively, a SENSE3+ pin supplies current to the current comparator. resistor divider on another voltage supply connected to the TRACK/SS pins of the buck channels allow the LTC3859AL SENSE1–, SENSE2–, SENSE3– (Pins 38, 12, 5/Pins 4, buck outputs to track the other supply during start-up. 16, 9): The (–) Input to the Differential Current Compara- tors. When SENSE1,2– for the buck channels is greater I , I , I (Pins 35, 15, 7/Pins 1, 19, 11): Error TH1 TH2 TH3 than INTV , then SENSE1,2– pin supplies current to the CC Amplifier Outputs and Switching Regulator Compensation current comparator. Points. Each associated channel’s current comparator trip point increases with this control voltage. PGND (Exposed Pad Pin 39): Driver Power Ground. Con- nects to the sources of bottom N-channel MOSFETs and the (–) terminal(s) of C . The exposed pad must be soldered IN to the PCB for rated electrical and thermal performance. 3859alfa 12 For more information www.linear.com/LTC3859AL

LTC3859AL FUNCTIONAL DIAGRAM 2 UT1, O V UT O CIN C SENSE RC R B 2 D R RA CC C2 N1, C VI L C DB CB CSS C V T N I BOOST TG SW BG PGND +SENSE –SENSE VFB ITH ACK/SS 3859al BD C R VC S T T S IN VCK/ V TOP BOT 0.80TRA 0.88 5µA SWITCHINGLOGIC IR+ – –+EA+ +OV – SHDN OUTBOTT TOPON SHDN +SLEEP – –++– 3mV OLDBACK PE F OD DR Q Q P+ – MP M O ELS 1 AND 2 S R IC 2.8V0.65V SLOPE C 7µA CH1160nA CH2 SHDNRST2(V)FB11V N N N A U H R C K C U B V 8 6. 2 1 K K +0.88V –VFB1+ –0.72V CLVCOCL PFDCLP SYNCDET 5.4V LDO EN INTVGNDCC S V O PGOOD1 20µA 100k 5.4 LD EN E D FREQ PLLIN/MO VBIAS EXTVCC + –4.7V 3859alfa 13 For more information www.linear.com/LTC3859AL

LTC3859AL FUNCTIONAL DIAGRAM VIN3 VOUT3 N COUT CI SENSE RC R UT3 RB RA CC CC2 O V L C DB CB CSS C V T N I OOST3 TG3 SW3 BG3 PGND –NSE3 +NSE3 VFB3 ITH3 SS3 3859al BD B C SE SE C V T N I V TOP BOT 1.2VSS3 1.32 G SWITCHINLOGIC IR+ – + –2V –+EA+ +OV – N N EEP +– 2mV O BOTO SHD SL LO 5µA SNSL + NS + – – S SQ RQ 0.425V ICMP+ – E COMP SHDN HANNEL 3 2.8V0.7V SLOP 160nA 11V RUN3 C T S O O B 1 E K D L O C M N/ LI L P V 1.32 VFB3 + – 3 V O 3859alfa 14 For more information www.linear.com/LTC3859AL

LTC3859AL OPERATION (Refer to Functional Diagram) Main Control Loop Each top MOSFET driver is biased from the floating boot- strap capacitor C , which normally recharges during each The LTC3859AL uses a constant frequency, current mode B cycle through an external diode when the switch voltage step-down architecture. The two buck controllers, chan- goes low. nels 1 and 2, operate 180 degrees out of phase with each other. The boost controller, channel 3, operates in phase For buck channels 1 and 2, if the buck’s input voltage with channel 1. During normal operation, the external decreases to a voltage close to its output, the loop may top MOSFET for the buck channels (the external bottom enter dropout and attempt to turn on the top MOSFET con- MOSFET for the boost channel) is turned on when the tinuously. The dropout detector detects this and forces the clock for that channel sets the RS latch, and is turned off top MOSFET off for about one twelfth of the clock period when the main current comparator, ICMP, resets the RS every tenth cycle to allow C to recharge. B latch. The peak inductor current at which ICMP trips and resets the latch is controlled by the voltage on the I pin, Shutdown and Start-Up (RUN1, RUN2, RUN3 and TH which is the output of the error amplifier EA. The error TRACK/SS1, TRACK/SS2, SS3 Pins) amplifier compares the output voltage feedback signal at The three channels of the LTC3859AL can be independently the V pin, (which is generated with an external resistor FB shut down using the RUN1, RUN2 and RUN3 pins. Pulling divider connected across the output voltage, V , to OUT RUN1 below 1.17V and RUN2/RUN3 below 1.20V shuts ground) to the internal 0.800V reference voltage for the down the main control loop for that channel. Pulling all bucks (1.2V reference voltage for the boost). When the three pins below 0.7V disables all controllers and most load current increases, it causes a slight decrease in V FB internal circuits, including the INTV LDOs. In this state, CC relative to the reference, which causes the EA to increase the LTC3859AL draws only 10µA of quiescent current. the I voltage until the average inductor current matches TH Releasing a RUN pin allows a small internal current to pull the new load current. up the pin to enable that controller. The RUN1 pin has a After the top MOSFET for the bucks (the bottom MOSFET 7µA pull-up current while the RUN2 and RUN3 pins have for the boost) is turned off each cycle, the bottom MOSFET a smaller 160nA. The 7µA current on RUN1 is designed is turned on (the top MOSFET for the boost) until either to be large enough so that the RUN1 pin can be safely the inductor current starts to reverse, as indicated by the floated (to always enable the controller) without worry current comparator IR, or the beginning of the next clock of condensation or other small board leakage pulling the cycle. pin down. This is ideal for always-on applications where one or more controllers are enabled continuously and INTV /EXTV Power CC CC never shut down. Power for the top and bottom MOSFET drivers and most Each RUN pin may also be externally pulled up or driven other internal circuitry is derived from the INTV pin. CC directly by logic. When driving a RUN pin with a low imped- When the EXTV pin is left open or tied to a voltage less CC ance source, do not exceed the absolute maximum rating than 4.7V, the V LDO (low dropout linear regulator) BIAS of 8V. Each RUN pin has an internal 11V voltage clamp supplies 5.4V from V to INTV . If EXTV is taken BIAS CC CC that allows the RUN pin to be connected through a resistor above 4.7V, the V LDO is turned off and an EXTV BIAS CC to a higher voltage (for example, V ), so long as the BIAS LDO is turned on. Once enabled, the EXTV LDO supplies CC maximum current in the RUN pin does not exceed 100µA. 5.4V from EXTV to INTV . Using the EXTV pin allows CC CC CC the INTVCC power to be derived from a high efficiency The start-up of each channel’s output voltage VOUT is con- external source such as one of the LTC3859AL switching trolled by the voltage on the TRACK/SS pin (TRACK/SS1 for regulator outputs. channel 1, TRACK/SS2 for channel 2, SS3 for channel 3). When the voltage on the TRACK/SS pin is less than the 3859alfa 15 For more information www.linear.com/LTC3859AL

LTC3859AL OPERATION 0.8V internal reference for the bucks and the 1.2V internal rent. If channels 1 and 3 are in sleep mode and channel 2 reference for the boost, the LTC3859AL regulates the V is shut down, it draws only 33µA of quiescent current. If all FB voltage to the TRACK/SS pin voltage instead of the cor- three controllers are enabled in sleep mode, the LTC3859AL responding reference voltage. This allows the TRACK/SS draws only 38µA of quiescent. In sleep mode, the load pin to be used to program a soft-start by connecting an current is supplied by the output capacitor. As the output external capacitor from the TRACK/SS pin to SGND. An voltage decreases, the EA’s output begins to rise. When the internal 5µA pull-up current charges this capacitor creating output voltage drops enough, the I pin is reconnected TH a voltage ramp on the TRACK/SS pin. As the TRACK/SS to the output of the EA, the sleep signal goes low, and the voltage rises linearly from 0V to 0.8V/1.2V (and beyond controller resumes normal operation by turning on the top up to INTV ), the output voltage V rises smoothly external MOSFET on the next cycle of the internal oscillator. CC OUT from zero to its final value. When a controller is enabled for Burst Mode operation, Alternatively the TRACK/SS pins for buck channels 1 and 2 the inductor current is not allowed to reverse. The reverse can be used to cause the start-up of V to track that of current comparator (IR) turns off the bottom external OUT another supply. Typically, this requires connecting to the MOSFET (the top external MOSFET for the boost) just TRACK/SS pin an external resistor divider from the other before the inductor current reaches zero, preventing it supply to ground (see the Applications Information section). from reversing and going negative. Thus, the controller operates in discontinuous operation. Light Load Current Operation (Burst Mode Operation, In forced continuous operation or clocked by an external Pulse-Skipping, or Continuous Conduction) clock source to use the phase-locked loop (see the Fre- (PLLIN/MODE Pin) quency Selection and Phase-Locked Loop section), the The LTC3859AL can be enabled to enter high efficiency inductor current is allowed to reverse at light loads or Burst Mode operation, constant frequency pulse-skipping under large transient conditions. The peak inductor cur- mode or forced continuous conduction mode at low load rent is determined by the voltage on the ITH pin, just as currents. To select Burst Mode operation, tie the PLLIN/ in normal operation. In this mode, the efficiency at light MODE pin to ground. To select forced continuous opera- loads is lower than in Burst Mode operation. However, tion, tie the PLLIN/MODE pin to INTV . To select pulse- continuous operation has the advantage of lower output CC skipping mode, tie the PLLIN/MODE pin to a DC voltage voltage ripple and less interference to audio circuitry. In greater than 1.2V and less than INTV – 1.3V. forced continuous mode, the output ripple is independent CC of load current. When a controller is enabled for Burst Mode operation, the minimum peak current in the inductor is set to approxi- When the PLLIN/MODE pin is connected for pulse-skipping mately 25% of the maximum sense voltage (30% for the mode, the LTC3859AL operates in PWM pulse-skipping boost) even though the voltage on the I pin indicates a mode at light loads. In this mode, constant frequency TH lower value. If the average inductor current is higher than operation is maintained down to approximately 1% of the load current, the error amplifier EA will decrease the designed maximum output current. At very light loads, the current comparator ICMP may remain tripped for several voltage on the I pin. When the I voltage drops below TH TH cycles and force the external top MOSFET to stay off for 0.425V, the internal sleep signal goes high (enabling sleep the same number of cycles (i.e., skipping pulses). The mode) and both external MOSFETs are turned off. The I TH inductor current is not allowed to reverse (discontinuous pin is then disconnected from the output of the EA and operation). This mode, like forced continuous operation, parked at 0.450V. exhibits low output ripple as well as low audio noise and In sleep mode, much of the internal circuitry is turned off, reduced RF interference as compared to Burst Mode reducing the quiescent current that the LTC3859AL draws. operation. It provides higher low current efficiency than If channel 1 is in sleep mode and the other two are shut forced continuous mode, but not nearly as high as Burst down, the LTC3859AL draws only 28µA of quiescent cur- Mode operation. 3859alfa 16 For more information www.linear.com/LTC3859AL

LTC3859AL OPERATION Frequency Selection and Phase-Locked Loop Boost Controller Operation When V > V IN OUT (FREQ and PLLIN/MODE Pins) When the input voltage to the boost channel rises above The selection of switching frequency is a tradeoff between its regulated V voltage, the controller can behave dif- OUT efficiency and component size. Low frequency opera- ferently depending on the mode, inductor current and tion increases efficiency by reducing MOSFET switching V voltage. In forced continuous mode, the loop works IN losses, but requires larger inductance and/or capacitance to keep the top MOSFET on continuously once VIN rises to maintain low output ripple voltage. above VOUT. An internal charge pump delivers current to the boost capacitor from the BOOST3 pin to maintain a The switching frequency of the LTC3859AL’s controllers sufficiently high TG voltage. (The amount of current the can be selected using the FREQ pin. charge pump can deliver is characterized by two curves If the PLLIN/MODE pin is not being driven by an external in the Typical Performance Characteristics section.) clock source, the FREQ pin can be tied to SGND, tied to In pulse-skipping mode, if V is between 100% and IN INTV , or programmed through an external resistor. CC 110% of the regulated V voltage, TG3 turns on if the OUT Tying FREQ to SGND selects 350kHz while tying FREQ to inductor current rises above approximately 3% of the INTV selects 535kHz. Placing a resistor between FREQ CC programmed I current. If the part is programmed in LIM and SGND allows the frequency to be programmed between Burst Mode operation under this same V window, then IN 50kHz and 900kHz. TG3 turns on at the same threshold current as long as A phase-locked loop (PLL) is available on the LTC3859AL the chip is awake (one of the buck channels is awake and to synchronize the internal oscillator to an external clock switching). If both buck channels are asleep or shut down source that is connected to the PLLIN/MODE pin. The in this VIN window, then TG3 will remain off regardless of the inductor current. LTC3859AL’s phase detector adjusts the voltage (through an internal lowpass filter) of the VCO input to align the If V rises above 110% of the regulated V voltage in IN OUT turn-on of controller 1’s external top MOSFET to the ris- any mode, the controller turns on TG3 regardless of the ing edge of the synchronizing signal. Thus, the turn-on inductor current. In Burst Mode operation, however, the of controller 2’s external top MOSFET is 180 degrees out internal charge pump turns off if the entire chip is asleep of phase to the rising edge of the external clock source. (the two buck channels are asleep or shut down). With the charge pump off, there would be nothing to prevent The VCO input voltage is pre-biased to the operating the boost capacitor from discharging, resulting in an frequency set by the FREQ pin before the external clock insufficient TG voltage needed to keep the top MOSFET is applied. If prebiased near the external clock frequency, completely on. The charge pump turns back on when the the PLL loop only needs to make slight changes to the chip wakes up, and it remains on as long as one of the VCO input in order to synchronize the rising edge of the buck channels is actively switching. external clock’s to the rising edge of TG1. The ability to pre-bias the loop filter allows the PLL to lock in rapidly Boost Controller at Low SENSE Pin Common Voltage without deviating far from the desired frequency. The current comparator of the boost controller is powered The typical capture range of the LTC3859AL’s phase- directly from the SENSE3+ pin and can operate to voltages locked loop is from approximately 55kHz to 1MHz, with a as low as 2.5V. Since this is lower than the V UVLO of BIAS guarantee over all manufacturing variations to be between the chip, V can be connected to the output of the boost BIAS 75kHz and 850kHz. In other words, the LTC3859AL’s PLL controller, as illustrated in the typical application circuit is guaranteed to lock to an external clock source whose in Figure 12. This allows the boost controller to handle frequency is between 75kHz and 850kHz. input voltage transients down to 2.5V while maintaining The typical input clock thresholds on the PLLIN/MODE output voltage regulation. If the SENSE3+ rises back pin are 1.6V (rising) and 1.2V (falling). above 2.5V, the SS3 pin will be released initiating a new soft-start sequence. 3859alfa 17 For more information www.linear.com/LTC3859AL

LTC3859AL OPERATION Buck Controller Output Overvoltage Protection Buck Foldback Current The two buck channels have an overvoltage comparator When the buck output voltage falls to less than 70% of that guards against transient overshoots as well as other its nominal level, foldback current limiting is activated, more serious conditions that may overvoltage their outputs. progressively lowering the peak current limit in proportion When the V pin rises by more than 10% above its to the severity of the overcurrent or short-circuit condition. FB1,2 regulation point of 0.800V, the top MOSFET is turned off Foldback current limiting is disabled during the soft-start and the bottom MOSFET is turned on until the overvoltage interval (as long as the V voltage is keeping up with FB condition is cleared. the TRACK/SS1,2 voltage). There is no foldback current limiting for the boost channel. Channel 1 Power Good (PGOOD1) Channel 1 has a PGOOD1 pin that is connected to an open THEORY AND BENEFITS OF 2-PHASE OPERATION drain of an internal N-channel MOSFET. The MOSFET Why the need for 2-phase operation? Up until the 2-phase turns on and pulls the PGOOD1 pin low when the V pin FB1 family, constant-frequency dual switching regulators voltage is not within ±10% of the 0.8V reference voltage operated both channels in phase (i.e., single-phase for the buck channel. The PGOOD1 pin is also pulled low operation). This means that both switches turned on at when the RUN1 pin is low (shut down). When the V FB1 the same time, causing current pulses of up to twice the pin voltage is within the ±10% requirement, the MOSFET amplitude of those for one regulator to be drawn from the is turned off and the pin is allowed to be pulled up by an input capacitor and battery. These large amplitude current external resistor to a source no greater than 6V. pulses increased the total RMS current flowing from the input capacitor, requiring the use of more expensive input Boost Overvoltage Indicator (OV3) capacitors and increasing both EMI and losses in the input The OV3 pin is an overvoltage indicator that signals whether capacitor and battery. the output voltage of the channel 3 boost controller goes With 2-phase operation, the two buck controllers of the over its programmed regulated voltage. The pin is con- LTC3859AL are operated 180 degrees out of phase. This nected to an open drain of an internal N-channel MOSFET. effectively interleaves the current pulses drawn by the The MOSFET turns on and pulls the OV3 pin low when the switches, greatly reducing the overlap time where they add V pin voltage is less than 110% of the 1.2V reference FB3 together. The result is a significant reduction in total RMS voltage for the boost channel. The OV3 pin is also pulled input current, which in turn allows less expensive input low when the RUN3 pin is low (shut down). When the V FB3 capacitors to be used, reduces shielding requirements for pin voltage goes higher than 110% of the 1.2V reference, EMI and improves real world operating efficiency. the MOSFET is turned off and the pin is allowed to be pulled up by an external resistor to a source no greater than 6V. 3859alfa 18 For more information www.linear.com/LTC3859AL

LTC3859AL OPERATION 5V SWITCH 20V/DIV 3.3V SWITCH 20V/DIV INPUT CURRENT 5A/DIV INPUT VOLTAGE 500mV/DIV IIN(MEAS) = 2.53ARMS IIN(MEAS) = 1.55ARMS 3859al F01a 3859al F01b (a) (b) Figure 1. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the 2-Phase Regulator Allows Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency Figure 1 compares the input waveforms for a representative It can readily be seen that the advantages of 2-phase op- single-phase dual switching regulator to the 2-phase dual eration are not just limited to a narrow operating range, buck controllers of the LTC3859AL. An actual measure- for most applications is that 2-phase operation will reduce ment of the RMS input current under these conditions the input capacitor requirement to that for just one chan- shows that 2-phase operation dropped the input current nel operating at maximum current and 50% duty cycle. from 2.53A to 1.55A . While this is an impressive RMS RMS The schematic on the first page is a basic LTC3859AL reduction in itself, remember that the power losses are application circuit. External component selection is driven proportional to I , meaning that the actual power wasted RMS2 by the load requirement, and begins with the selection of is reduced by a factor of 2.66. The reduced input ripple R and the inductor value. Next, the power MOSFETs SENSE voltage also means less power is lost in the input power are selected. Finally, C and C are selected. IN OUT path, which could include batteries, switches, trace/con- nector resistances and protection circuitry. Improvements 3.0 in both conducted and radiated EMI also directly accrue SINGLE-PHASE as a result of the reduced RMS input current and voltage. 2.5 DUAL CONTROLLER A) Of course, the improvement afforded by 2-phase opera- NT ( 2.0 E R tion is a function of the dual switching regulator’s relative R U C 1.5 duty cycles which, in turn, are dependent upon the input MS 2-PHASE R DUAL CONTROLLER voltage VIN (Duty Cycle = VOUT/VIN). Figure 2 shows how UT 1.0 P the RMS input current varies for single-phase and 2-phase IN 0.5 operation for 3.3V and 5V regulators over a wide input VO1 = 5V/3A VO2 = 3.3V/3A voltage range. 0 0 10 20 30 40 INPUT VOLTAGE (V) 3859al F02 Figure 2. RMS Input Current Comparison 3859alfa 19 For more information www.linear.com/LTC3859AL

LTC3859AL APPLICATIONS INFORMATION The Typical Application on the first page is a basic Filter components mutual to the sense lines should be LTC3859AL application circuit. LTC3859AL can be config- placed close to the LTC3859AL, and the sense lines should ured to use either DCR (inductor resistance) sensing or low run close together to a Kelvin connection underneath the value resistor sensing. The choice between the two current current sense element (shown in Figure 3). Sensing cur- sensing schemes is largely a design trade-off between rent elsewhere can effectively add parasitic inductance cost, power consumption, and accuracy. DCR sensing and capacitance to the current sense element, degrading is becoming popular because it saves expensive current the information at the sense terminals and making the sensing resistors and is more power efficient, especially programmed current limit unpredictable. If DCR sensing in high current applications. However, current sensing is used (Figure 4b), sense resistor R1 should be placed resistors provide the most accurate current limits for the close to the switching node, to prevent noise from coupling controller. Other external component selection is driven into sensitive small-signal nodes. by the load requirement, and begins with the selection of R (if R is used) and inductor value. Next, the TO SENSE FILTER SENSE SENSE NEXT TO THE CONTROLLER power MOSFETs and Schottky diodes are selected. Finally, input and output capacitors are selected. SENSE+ and SENSE– Pins CURRENT FLOW The SENSE+ and SENSE– pins are the inputs to the cur- INDUCTOR OR RSENSE 3859al F03 rent comparators. Figure 3. Sense Lines Placement with Inductor or Sense Resistor Buck Controllers (SENSE1+/SENSE1–,SENSE2+/SENSE2–): The common mode voltage range on these pins is 0V to Low Value Resistor Current Sensing 28V (absolute maximum), enabling the LTC3859AL to A typical sensing circuit using a discrete resistor is shown regulate buck output voltages up to a nominal 24V (al- in Figure 4a. R is chosen based on the required lowing margin for tolerances and transients). The SENSE+ SENSE output current. pin is high impedance over the full common mode range, drawing at most ±1µA. This high impedance allows the The current comparators have a maximum threshold current comparators to be used in inductor DCR sensing. VSENSE(MAX) of 50mV. The current comparator threshold The impedance of the SENSE– pin changes depending on sets the peak of the inductor current, yielding a maximum the common mode voltage. When SENSE– is less than average output current, IMAX, equal to the peak value less INTVCC–0.5V, a small current of less than 1µA flows out half the peak-to-peak ripple current, DIL. To calculate the of the pin. When SENSE– is above INTV +0.5V, a higher sense resistor value, use the equation: CC current (≈700µA) flows into the pin. Between INTV –0.5V CC V SENSE(MAX) and INTV +0.5V, the current transitions from the smaller R = CC SENSE DI current to the higher current. I + L MAX 2 Boost Controller (SENSE3+/SENSE3–): The common mode input range for these pins is 2.5V to 38V, allowing the boost When using the buck controllers in very low dropout converter to operate from inputs over this full range. The conditions, the maximum output current level will be SENSE3+ pin also provides power to the current compara- reduced due to the internal compensation required to tor and draws about 170µA during normal operation (when meet stability criterion for buck regulators operating at not shut down or asleep in Burst Mode operation). There is greater than 50% duty factor. A curve is provided in the a small bias current of less than 1µA that flows out of the Typical Performance Characteristics section to estimate SENSE3– pin. This high impedance on the SENSE3– pin allows this reduction in peak output current level depending upon the current comparator to be used in inductor DCR sensing. the operating duty factor. 3859alfa 20 For more information www.linear.com/LTC3859AL

LTC3859AL APPLICATIONS INFORMATION VIN1,2 across the external capacitor is equal to the drop across INTVCC (VOUT3) the inductor DCR multiplied by R2/(R1 + R2). R2 scales the voltage across the sense terminals for applications where BOOST the DCR is greater than the target sense resistor value. TG To properly dimension the external filter components, the LTC3859ALSW RSENSE VOUT1,2 DCR of the inductor must be known. It can be measured (VIN3) using a good RLC meter, but the DCR tolerance is not BG always the same and varies with temperature; consult SENSE1,2+ the manufacturers’ data sheets for detailed information. (SENSE3–) CAP SENSE1, 2– PLACED NEAR SENSE PINS Using the inductor ripple current value from the Inductor (SENSE3+) Value Calculation section, the target sense resistor value is: SGND V 3859al F04a SENSE(MAX) R = (EQUIV) 4a. Using a Resistor to Sense Current DI I + L MAX 2 VIN1,2 INTVCC (VOUT3) To ensure that the application will deliver full load cur- rent over the full operating temperature range, determine BOOST R , keeping in mind that the maximum current SENSE(EQUIV) INDUCTOR TG sense threshold (V ) for the LTC3859AL is fixed SENSE(MAX) LTC3859AL L DCR VOUT1,2 at 50mV. SW (VIN3) BG Next, determine the DCR of the inductor. Where provided, use the manufacturer’s maximum value, usually given at SENSE1, 2+ R1 (SENSE3–) 20°C. Increase this value to account for the temperature C1* R2 coefficient of resistance, which is approximately 0.4%/°C. SENSE1, 2– (SENSE3+) A conservative value for T is 100°C. L(MAX) SGND To scale the maximum inductor DCR to the desired sense 3859al F04b (R1||R2) • C1 = L/DCR resistor value, use the divider ratio: *PLACE C1 NEAR SENSE PINS RSENSE(EQ) = DCR(R2/(R1+R2)) R 4b. Using the Inductor DCR to Sense Current SENSE(EQUIV) R = D DCR atT Figure 4. Current Sensing Methods MAX L(MAX) C1 is usually selected to be in the range of 0.1µF to 0.47µF. Inductor DCR Sensing This forces R1||R2 to around 2k, reducing error that might For applications requiring the highest possible efficiency at have been caused by the SENSE+ pin’s ±1µA current. high load currents, the LTC3859AL is capable of sensing the The equivalent resistance R1||R2 is scaled to the room voltage drop across the inductor DCR, as shown in Figure 4b. temperature inductance and maximum DCR: The DCR of the inductor represents the small amount of DC winding resistance of the copper, which can be less L R1R2= than 1mΩ for today’s low value, high current inductors. (DCR at20°C)•C1  In a high current application requiring such an inductor, conduction loss through a sense resistor would cost several The sense resistor values are: points of efficiency compared to DCR sensing. R1R2 R1•R R1= ; R2= D If the external R1||R2 • C1 time constant is chosen to be exactly equal to the L/DCR time constant, the voltage drop  RD 1−RD 3859alfa 21 For more information www.linear.com/LTC3859AL

LTC3859AL APPLICATIONS INFORMATION The maximum power loss in R1 is related to duty cycle. Accepting larger values of DI allows the use of low L For the buck controllers, the maximum power loss will inductances, but results in higher output voltage ripple occur in continuous mode at the maximum input voltage: and greater core losses. A reasonable starting point for setting ripple current is DI = 0.3(I ). The maximum L MAX (V −V )• V IN(MAX) OUT OUT DI occurs at the maximum input voltage for the bucks P R1= L LOSS R1 and VIN = 1/2•VOUT for the boost. For the boost controller, the maximum power loss in R1 The inductor value also has secondary effects. The tran- will occur in continuous mode at V = 1/2•V : sition to Burst Mode operation begins when the average IN OUT inductor current required results in a peak current below (V −V )• V OUT(MAX) IN IN 25% of the current limit (30% for the boost) determined P R1= LOSS R1 by RSENSE. Lower inductor values (higher DIL) will cause this to occur at lower load currents, which can cause a dip Ensure that R1 has a power rating higher than this value. in efficiency in the upper range of low current operation. In If high efficiency is necessary at light loads, consider this Burst Mode operation, lower inductance values will cause power loss when deciding whether to use DCR sensing or the burst frequency to decrease. sense resistors. Light load power loss can be modestly higher with a DCR network than with a sense resistor, Inductor Core Selection due to the extra switching losses incurred through R1. However, DCR sensing eliminates a sense resistor, reduces Once the value for L is known, the type of inductor must conduction losses and provides higher efficiency at heavy be selected. High efficiency converters generally cannot loads. Peak efficiency is about the same with either method. afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy Inductor Value Calculation cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance The operating frequency and inductor selection are inter- selected. As inductance increases, core losses go down. related in that higher operating frequencies allow the use Unfortunately, increased inductance requires more turns of smaller inductor and capacitor values. So why would of wire and therefore copper losses will increase. anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher Ferrite designs have very low core loss and are preferred frequency generally results in lower efficiency because at high switching frequencies, so design goals can con- of MOSFET gate charge losses. In addition to this basic centrate on copper loss and preventing saturation. Ferrite trade-off, the effect of inductor value on ripple current and core material saturates “hard,” which means that induc- low current operation must also be considered. tance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor The inductor value has a direct effect on ripple current. ripple current and consequent output voltage ripple. Do The inductor ripple current DI decreases with higher L not allow the core to saturate! inductance or frequency. For the buck controllers, DI L increases with higher V : IN 1 ⎛ V ⎞ DIL = VOUT⎜1− OUT⎟ (f)(L) ⎝ VIN ⎠ For the boost controller, the inductor ripple current DI L increases with higher V : OUT 1 ⎛ V ⎞ DI = V ⎜1− IN ⎟ L IN (f)(L) ⎝ VOUT⎠ 3859alfa 22 For more information www.linear.com/LTC3859AL

LTC3859AL APPLICATIONS INFORMATION Power MOSFET and Schottky Diode The MOSFET power dissipations at maximum output (Optional) Selection current are given by: Two external power MOSFETs must be selected for each V 2 P = OUT (I ) (1+δ)R + controller in the LTC3859AL: one N-channel MOSFET for MAIN_BUCK OUT(MAX) DS(ON) V IN the top switch (main switch for the buck, synchronous ⎛I ⎞ for the boost), and one N-channel MOSFET for the bot- 2 OUT(MAX) (V ) ⎜ ⎟(R )(C )• IN DR MILLER tom switch (main switch for the boost, synchronous for ⎝ 2 ⎠ the buck). ⎡ 1 1 ⎤ The peak-to-peak drive levels are set by the INTV voltage. ⎢ + ⎥(f) This voltage is typically 5.4V during start-up (sCeCe EXTV ⎣VINTVCC −VTHMIN VTHMIN⎦ CC Pin Connection). Consequently, logic-level threshold P = VIN −VOUT (I )2(1+δ)R SYNC_BUCK OUT(MAX) DS(ON) MOSFETs must be used in most applications. Pay close V IN attention to the BV specification for the MOSFETs as DSS well; many of the logic level MOSFETs are limited to 30V P = (VOUT −VIN)VOUT (I )2 • or less. MAIN_BOOST 2 OUT(MAX) V IN Selection criteria for the power MOSFETs include the on-resistance RDS(ON), Miller capacitance CMILLER, input (1+δ)RDS(ON)+⎛⎜⎜VOUT3⎞⎟⎟⎛⎜IOUT(MAX)⎞⎟• voltage and maximum output current. Miller capacitance, ⎝ VIN ⎠⎝ 2 ⎠ C , can be approximated from the gate charge curve MILLER ⎡ 1 1 ⎤ usually provided on the MOSFET manufacturers’ data (RDR)(CMILLER)•⎢ + ⎥(f) sheet. C is equal to the increase in gate charge ⎣VINTVCC−VTHMIN VTHMIN⎦ MILLER along the horizontal axis while the curve is approximately V 2 P = IN (I ) (1+δ)R flat divided by the specified change in V . This result is SYNC_BOOST OUT(MAX) DS(ON) DS V OUT then multiplied by the ratio of the application applied V DS to the gate charge curve specified VDS. When the IC is where z is the temperature dependency of RDS(ON) and operating in continuous mode the duty cycles for the top RDR (approximately 2Ω) is the effective driver resistance and bottom MOSFETs are given by: at the MOSFET’s Miller threshold voltage. V is the THMIN typical MOSFET minimum threshold voltage. V Buck Main Switch Duty Cycle = OUT Both MOSFETs have I2R losses while the main N-channel V IN equations for the buck and boost controllers include an V −V Buck Sync Switch Duty Cycle = IN OUT additional term for transition losses, which are highest at VIN high input voltages for the bucks and low input voltages for Boost Main Switch Duty Cycle= VOUT −VIN the boost. For VIN < 20V (high VIN for the boost) the high current efficiency generally improves with larger MOSFETs, V OUT while for V > 20V (low V for the boost) the transition IN IN V Boost Sync Switch Duty Cycle= IN losses rapidly increase to the point that the use of a higher VOUT RDS(ON) device with lower CMILLER actually provides higher 3859alfa 23 For more information www.linear.com/LTC3859AL

LTC3859AL APPLICATIONS INFORMATION efficiency. The synchronous MOSFET losses for the buck In a boost converter, the output has a discontinuous current, controllers are greatest at high input voltage when the top so C must be capable of reducing the output voltage OUT switch duty factor is low or during a short-circuit when ripple. The effects of ESR (equivalent series resistance) and the synchronous switch is on close to 100% of the period. the bulk capacitance must be considered when choosing The synchronous MOSFET losses for the boost control- the right capacitor for a given output ripple voltage. The ler are greatest when the input voltage approaches the steady ripple due to charging and discharging the bulk output voltage or during an overvoltage event when the capacitance is given by: synchronous switch is on 100% of the period. I •(V −V ) OUT(MAX) OUT IN(MIN) The term (1+ z) is generally given for a MOSFET in the Ripple= V C • V • f form of a normalized RDS(ON) vs Temperature curve, but OUT OUT z = 0.005/°C can be used as an approximation for low where C is the output filter capacitor. OUT voltage MOSFETs. The steady ripple due to the voltage drop across the ESR The optional Schottky diodes D4, D5, and D6 shown in is given by: Figure 13 conduct during the dead-time between the conduction of the two power MOSFETs. This prevents DVESR = IL(MAX) • ESR the body diode of the synchronous MOSFET from turning Multiple capacitors placed in parallel may be needed to on, storing charge during the dead-time and requiring a meet the ESR and RMS current handling requirements. reverse recovery period that could cost as much as 3% Dry tantalum, special polymer, aluminum electrolytic in efficiency at high VIN. A 1A to 3A Schottky is generally and ceramic capacitors are all available in surface mount a good compromise for both regions of operation due to packages. Ceramic capacitors have excellent low ESR the relatively small average current. Larger diodes result characteristics but can have a high voltage coefficient. in additional transition losses due to their larger junction Capacitors are now available with low ESR and high ripple capacitance. current ratings such as OS-CON and POSCAP. Boost C , C Selection Buck C , C Selection IN OUT IN OUT The input ripple current in a boost converter is relatively The selection of C for the two buck controllers is simplified IN low (compared with the output ripple current), because by the 2-phase architecture and its impact on the worst- this current is continuous. The boost input capacitor C case RMS current drawn through the input network (bat- IN voltage rating should comfortably exceed the maximum tery/fuse/capacitor). It can be shown that the worst-case input voltage. Although ceramic capacitors can be relatively capacitor RMS current occurs when only one controller tolerant of overvoltage conditions, aluminum electrolytic is operating. The controller with the highest (V )(I ) OUT OUT capacitors are not. Be sure to characterize the input voltage product needs to be used in the formula shown in Equa- for any possible overvoltage transients that could apply tion (1) to determine the maximum RMS capacitor current excess stress to the input capacitors. requirement. Increasing the output current drawn from the other controller will actually decrease the input RMS The value of C is a function of the source impedance, and IN ripple current from its maximum value. The out-of-phase in general, the higher the source impedance, the higher the technique typically reduces the input capacitor’s RMS required input capacitance. The required amount of input ripple current by a factor of 30% to 70% when compared capacitance is also greatly affected by the duty cycle. High to a single phase power supply solution. output current applications that also experience high duty cycles can place great demands on the input supply, both in terms of DC current and ripple current. 3859alfa 24 For more information www.linear.com/LTC3859AL

LTC3859AL APPLICATIONS INFORMATION In continuous mode, the source current of the top MOSFET A small (0.1µF to 1µF) bypass capacitor between the chip is a square wave of duty cycle (V )/(V ). To prevent V pin and ground, placed close to the LTC3859AL, is also OUT IN IN large voltage transients, a low ESR capacitor sized for the suggested. A small (1Ω to 10Ω) resistor placed between maximum RMS current of one channel must be used. The C (C1) and the V pin provides further isolation between IN IN maximum RMS capacitor current is given by: the two channels. IMAX 1/2 The selection of COUT is driven by the effective series CIN Required IRMS ≈ ⎡⎣(VOUT)(VIN −VOUT)⎤⎦ (1) resistance (ESR). Typically, once the ESR requirement V IN is satisfied, the capacitance is adequate for filtering. The This formula has a maximum at VIN = 2VOUT, where IRMS output ripple (DVOUT) is approximated by: = I /2. This simple worst-case condition is commonly OUT ⎛ 1 ⎞ used for design because even significant deviations do not DV ≈ DI ⎜ESR+ ⎟ OUT L offer much relief. Note that capacitor manufacturers’ ripple ⎝ 8fCOUT⎠ current ratings are often based on only 2000 hours of life. where f is the operating frequency, C is the output This makes it advisable to further derate the capacitor, or OUT capacitance and DI is the ripple current in the inductor. to choose a capacitor rated at a higher temperature than L The output ripple is highest at maximum input voltage required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high since DIL increases with input voltage. operating frequency of the LTC3859AL, ceramic capacitors Setting Output Voltage can also be used for C . Always consult the manufacturer IN if there is any question. The LTC3859AL output voltages are each set by an external feedback resistor divider carefully placed across the output, The benefit of the LTC3859AL 2-phase operation can be as shown in Figure 5. The regulated output voltages are calculated by using Equation (1) for the higher power con- determined by: troller and then calculating the loss that would have resulted if both controller channels switched on at the same time. ⎛ R ⎞ The total RMS power lost is lower when both controllers V =0.8V⎜1+ B ⎟ OUT,BUCK are operating due to the reduced overlap of current pulses ⎝ RA ⎠ required through the input capacitor’s ESR. This is why ⎛ R ⎞ the input capacitor’s requirement calculated above for the VOUT,BOOST =1.2V⎜1+ B ⎟ worst-case controller is adequate for the dual controller ⎝ RA ⎠ design. Also, the input protection fuse resistance, battery To improve the frequency response, a feedforward ca- resistance, and PC board trace resistance losses are also pacitor, C , may be used. Great care should be taken to FF reduced due to the reduced peak currents in a 2-phase route the V line away from noise sources, such as the FB system. The overall benefit of a multiphase design will inductor or the SW line. only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. VOUT The drains of the top MOSFETs should be placed within 1cm of each other and share a common C (s). Separat- ing the drains and C may produce undeIsNirable voltage 1/3 LTC3859AL RB CFF IN and current resonances at V . VFB IN RA 3859al F05 Figure 5. Setting Output Voltage 3859alfa 25 For more information www.linear.com/LTC3859AL

LTC3859AL APPLICATIONS INFORMATION Tracking and Soft-Start 1/3 LTC3859AL (TRACK/SS1, TRACK/SS2, SS3 Pins) TRACK/SS The start-up of each V is controlled by the voltage on CSS OUT SGND the respective TRACK/SS pin (TRACK/SS1 for channel 1, 3859al F06 TRACK/SS2 for channel 2, SS3 for channel 3). When the voltage on the TRACK/SS pin is less than the internal Figure 6. Using the TRACK/SS Pin to Program Soft-Start 0.8V reference (1.2V reference for the boost channel), the LTC3859AL regulates the V pin voltage to the voltage FB on the TRACK/SS pin instead of the internal reference. VX(MASTER) Likewise, the TRACK/SS pin for the buck channels can be used to program an external soft-start function or to allow )UT O V VOUT to track another supply during start-up. UT ( TP VOUT(SLAVE) U Soft-start is enabled by simply connecting a capacitor O from the TRACK/SS pin to ground, as shown in Figure 6. An internal 5µA current source charges the capacitor, providing a linear ramping voltage at the TRACK/SS pin. TIME 3859al F07a 7a. Coincident Tracking The LTC3859AL will regulate the V pin (and hence V ) FB OUT according to the voltage on the TRACK/SS pin, allowing V to rise smoothly from 0V to its final regulated value. OUT VX(MASTER) The total soft-start time will be approximately: )UT O 0.8V V tSS_BUCK =CSS • 5µA TPUT ( VOUT(SLAVE) U O 1.2V t =C • SS_BOOST SS 5µA TIME 3859al F07b Alternatively, the TRACK/SS1 and TRACK/SS2 pins for the 7b. Ratiometric Tracking two buck controllers can be used to track two (or more) sup- plies during start-up, as shown qualitatively in Figures 7a Figure 7. Two Different Modes of Output Voltage Tracking and 7b. To do this, a resistor divider should be connected from the master supply (V ) to the TRACK/SS pin of the X VOUT slave supply (V ), as shown in Figure 8. During start-up OUT VOUT will track VX according to the ratio set by the resis- RB LTC3859AL tor divider: VFB1,2 VX = RA • RTRACKA +RTRACKB VX RA V R R +R OUT TRACKA A B RTRACKB For coincident tracking (V = V during start-up), OUT X TRACK/SS1,2 RA = RTRACKA RTRACKA R = R B TRACKB 3859al F08 Figure 8. Using the TRACK/SS Pin for Tracking 3859alfa 26 For more information www.linear.com/LTC3859AL

LTC3859AL APPLICATIONS INFORMATION INTV Regulators To prevent the maximum junction temperature from being CC exceeded, the input supply current must be checked while The LTC3859AL features two separate internal P-channel operating in continuous conduction mode (PLLIN/MODE low dropout linear regulators (LDO) that supply power = INTV ) at maximum V . at the INTV pin from either the V supply pin or the CC IN CC BIAS EXTV pin depending on the connection of the EXTV When the voltage applied to EXTV rises above 4.7V, the CC CC CC pin. INTV powers the gate drivers and much of the V LDO is turned off and the EXTV LDO is enabled. CC BIAS CC LTC3859AL’s internal circuitry. The V LDO and the The EXTV LDO remains on as long as the voltage applied BIAS CC EXTV LDO regulate INTV to 5.4V. Each of these must to EXTV remains above 4.5V. The EXTV LDO attempts CC CC CC CC be bypassed to ground with a minimum of 4.7µF ceramic to regulate the INTV voltage to 5.4V, so while EXTV CC CC capacitor. No matter what type of bulk capacitor is used, an is less than 5.4V, the LDO is in dropout and the INTV CC additional 1µF ceramic capacitor placed directly adjacent voltage is approximately equal to EXTV . When EXTV CC CC to the INTV and PGND IC pins is highly recommended. is greater than 5.4V, up to an absolute maximum of 14V, CC Good bypassing is needed to supply the high transient INTV is regulated to 5.4V. CC currents required by the MOSFET gate drivers and to Using the EXTV LDO allows the MOSFET driver and CC prevent interaction between the channels. control power to be derived from one of the LTC3859AL’s High input voltage applications in which large MOSFETs switching regulator outputs (4.7V ≤ V ≤ 14V) dur- OUT are being driven at high frequencies may cause the maxi- ing normal operation and from the V LDO when the BIAS mum junction temperature rating for the LTC3859AL to be output is out of regulation (e.g., startup, short-circuit). If exceeded. The INTV current, which is dominated by the more current is required through the EXTV LDO than CC CC gate charge current, may be supplied by either the V is specified, an external Schottky diode can be added BIAS LDO or the EXTV LDO. When the voltage on the EXTV between the EXTV and INTV pins. In this case, do CC CC CC CC pin is less than 4.7V, the V LDO is enabled. Power not apply more than 6V to the EXTV pin and make sure BIAS CC dissipation for the IC in this case is highest and is equal to that EXTV ≤ V . CC BIAS V • I . The gate charge current is dependent BIAS INTVCC Significant efficiency and thermal gains can be realized on operating frequency as discussed in the Efficiency by powering INTV from the buck output, since the V CC IN Considerations section. The junction temperature can be current resulting from the driver and control currents will estimated by using the equations given in Note 2 of the be scaled by a factor of (Duty Cycle)/(Switcher Efficiency). Electrical Characteristics. For example, the LTC3859AL For 5V to 14V regulator outputs, this means connecting INTV current is limited to less than 40mA from a 40V CC the EXTV pin directly to V . Tying the EXTV pin to CC OUT CC supply when not using the EXTV supply at a 70°C ambi- CC a 8.5V supply reduces the junction temperature in the ent temperature in the QFN package: previous example from 125°C to: T = 70°C + (40mA)(40V)(34°C/W) = 125°C J T = 70°C + (40mA)(8.5V)(34°C/W) = 82°C J However, for 3.3V and other low voltage outputs, additional circuitry is required to derive INTV power from the output. CC 3859alfa 27 For more information www.linear.com/LTC3859AL

LTC3859AL APPLICATIONS INFORMATION The following list summarizes the four possible connec- 3. EXTV connected to an external supply. If an external CC tions for EXTV : supply is available in the 5V to 14V range, it may be CC used to power EXTV providing it is compatible with 1. EXTV grounded. This will cause INTV to be powered CC CC CC the MOSFET gate drive requirements. Ensure that from the internal 5.4V regulator resulting in an efficiency EXTV ≤ V . penalty of up to 10% at high input voltages. CC BIAS 4. EXTV connected to an output-derived boost network 2. EXTV connected directly to the output voltage of one CC CC off one of the buck regulators. For 3.3V and other low of the buck regulators. This is the normal connection voltage buck regulators, efficiency gains can still be for a 5V to 14V regulator and provides the highest ef- realized by connecting EXTV to an output-derived ficiency. CC voltage that has been boosted to greater than 4.7V. This can be done with the capacitive charge pump shown in Figure 9. Ensure that EXTV ≤ V . CC BIAS VIN1,2 BAT85 BAT85 C1 LTC3859AL MTOP BAT85 TG EXTVCC L RSENSE SW VOUT1,2 MBOT BG PGND 3859al F09 Figure 9. Capacitive Charge Pump for EXTV CC 3859alfa 28 For more information www.linear.com/LTC3859AL

LTC3859AL APPLICATIONS INFORMATION Topside MOSFET Driver Supply (C , D ) top MOSFET on continuously during dropout/overvolt- B B age conditions. The Schottky/silicon diode selected for External bootstrap capacitors C connected to the BOOST B the boost topside driver should have a reverse leakage pins supply the gate drive voltages for the topside MOS- less than the available output current the charge pump FETs. Capacitor C in the Functional Diagram is charged B can supply. Curves displaying the available charge pump though external diode D from INTV when the SW pin B CC current under different operating conditions can be found is low. When one of the topside MOSFETs is to be turned in the Typical Performance Characteristics section. on, the driver places the C voltage across the gate-source B of the desired MOSFET. This enhances the MOSFET and A leaky diode D in the boost converter can not only B turns on the topside switch. The switch node voltage, prevent the top MOSFET from fully turning on but it can SW, rises to V for the buck channels (V for the boost also completely discharge the bootstrap capacitor C and IN OUT B channel) and the BOOST pin follows. With the topside create a current path from the input voltage to the BOOST3 MOSFET on, the boost voltage is above the input supply: pin to INTV . This can cause INTV to rise if the diode CC CC V = V + V (V = V + V for the leakage exceeds the current consumption on INTV . This BOOST IN INTVCC BOOST OUT INTVCC CC boost controller). The value of the boost capacitor C is particularly a concern in Burst Mode operation where B needs to be 100 times that of the total input capacitance the load on INTV can be very small. There is an internal CC of the topside MOSFET(s). The reverse breakdown of the voltage clamp on INTV that prevents the INTV voltage CC CC external Schottky diode must be greater than V for from running away, but this clamp should be regarded IN(MAX) the buck channels and V for the boost channel. as a failsafe only. The external Schottky or silicon diode OUT(MAX) should be carefully chosen such that INTV never gets The external diode D can be a Schottky diode or silicon CC B charged up much higher than its normal regulation voltage. diode, but in either case it should have low leakage and fast recovery. Pay close attention to the reverse leakage at high Care should also be taken when choosing the external temperatures where it generally increases substantially. diode D for the buck converters. A leaky diode not only B increases the quiescent current of the buck converter, but The topside MOSFET driver for the boost channel includes it can also cause a similar leakage path to INTV from an internal charge pump that delivers current to the CC V for applications with output voltages greater than bootstrap capacitor from the BOOST3 pin. This charge OUT the INTV voltage (~5.4V). current maintains the bias voltage required to keep the CC 1000 900 800 Hz) 700 Y (k 600 C N 500 E U Q 400 E R F 300 200 100 0 15 25 35 45 55 65 75 85 95 105115125 FREQ PIN RESISTOR (kΩ) 3859al F10 Figure 10. Relationship Between Oscillator Frequency and Resistor Value at the FREQ Pin 3859alfa 29 For more information www.linear.com/LTC3859AL

LTC3859AL APPLICATIONS INFORMATION Fault Conditions: Buck Current Limit and Current A shorted top MOSFET for the buck channel will result in Foldback a high current condition which will open the system fuse. The switching regulator will regulate properly with a leaky The LTC3859AL includes current foldback for the buck top MOSFET by altering the duty cycle to accommodate channels to help limit load current when the output is the leakage. shorted to ground. If the buck output falls below 70% of its nominal output level, then the maximum sense volt- Fault Conditions: Over Temperature Protection age is progressively lowered from 100% to 40% of its maximum selected value. Under short-circuit conditions At higher temperatures, or in cases where the internal with very low duty cycles, the buck channel will begin power dissipation causes excessive self heating on chip cycle skipping in order to limit the short-circuit current. (such as INTVCC short to ground), the over temperature In this situation the bottom MOSFET will be dissipating shutdown circuitry will shut down the LTC3859AL. When most of the power but less than in normal operation. The the junction temperature exceeds approximately 170°C, the short-circuit ripple current is determined by the minimum over temperature circuitry disables the INTVCC LDO, caus- on-time tON(MIN) of the LTC3859AL (≈95ns), the input ing the INTVCC supply to collapse and effectively shutting voltage and inductor value: down the entire LTC3859AL chip. Once the junction tem- perature drops back to approximately 155°C, the INTV CC DI = t (V /L) L(SC) ON(MIN) IN LDO turns back on. Long term overstress (T > 125°C) J The resulting average short-circuit current is: should be avoided as it can degrade the performance or shorten the life of the part. 1 I = 40% •I − DI SC LIM(MAX) L(SC) 2 Phase-Locked Loop and Frequency Synchronization Fault Conditions: Buck Overvoltage Protection (Crowbar) The LTC3859AL has an internal phase-locked loop (PLL) comprised of a phase frequency detector, a lowpass filter, The overvoltage crowbar is designed to blow a system and a voltage-controlled oscillator (VCO). This allows the input fuse when the output voltage of the one of the buck turn-on of the top MOSFET of controller 1 to be locked to regulators rises much higher than nominal levels. The the rising edge of an external clock signal applied to the crowbar causes huge currents to flow, that blow the fuse PLLIN/MODE pin. The turn-on of controller 2’s top MOSFET to protect against a shorted top MOSFET if the short oc- is thus 180 degrees out of phase with the external clock. curs while the controller is operating. The phase detector is an edge sensitive digital type that A comparator monitors the buck output for overvoltage provides zero degrees phase shift between the external conditions. The comparator detects faults greater than and internal oscillators. This type of phase detector does 10% above the nominal output voltage. When this condi- not exhibit false lock to harmonics of the external clock. tion is sensed, the top MOSFET of the buck controller is If the external clock frequency is greater than the inter- turned off and the bottom MOSFET is turned on until the nal oscillator’s frequency, f , then current is sourced OSC overvoltage condition is cleared. The bottom MOSFET continuously from the phase detector output, pulling up remains on continuously for as long as the overvoltage the VCO input. When the external clock frequency is less condition persists; if V returns to a safe level, normal OUT than f , current is sunk continuously, pulling down the OSC operation automatically resumes. 3859alfa 30 For more information www.linear.com/LTC3859AL

LTC3859AL APPLICATIONS INFORMATION VCO input. If the external and internal frequencies are the Minimum On-Time Considerations same but exhibit a phase difference, the current sources Minimum on-time t is the smallest time duration that ON(MIN) turn on for an amount of time corresponding to the phase the LTC3859AL is capable of turning on the top MOSFET difference. The voltage at the VCO input is adjusted until (bottom MOSFET for the boost controller). It is determined the phase and frequency of the internal and external os- by internal timing delays and the gate charge required to cillators are identical. At the stable operating point, the turn on the top MOSFET. Low duty cycle applications may phase detector output is high impedance and the internal approach this minimum on-time limit and care should be filter capacitor, CLP, holds the voltage at the VCO input. taken to ensure that Note that the LTC3859AL can only be synchronized to V an external clock whose frequency is within range of the t < OUT ON(MIN)_BUCK LTC3859AL’s internal VCO, which is nominally 55kHz to VIN(f) 1MHz. This is guaranteed to be between 75kHz and 850kHz. V −V t < OUT IN ON(MIN)_BOOST Typically, the external clock (on PLLIN/MODE pin) input VOUT(f) high threshold is 1.6V, while the input low threshold is 1.2V. If the duty cycle falls below what can be accommodated Rapid phase-locking can be achieved by using the FREQ by the minimum on-time, the controller will begin to skip pin to set a free-running frequency near the desired cycles. The output voltage will continue to be regulated, synchronization frequency. The VCO’s input voltage is but the ripple voltage and current will increase. prebiased at a frequency correspond to the frequency The minimum on-time for the LTC3859AL is approximately set by the FREQ pin. Once prebiased, the PLL only needs 95ns for the bucks and 120ns for the boost. However, as to adjust the frequency slightly to achieve phase-lock the peak sense voltage decreases the minimum on-time and synchronization. Although it is not required that the gradually increases up to about 130ns. This is of particu- free-running frequency be near external clock frequency, lar concern in forced continuous applications with low doing so will prevent the operating frequency from pass- ripple current at light loads. If the duty cycle drops below ing through a large range of frequencies as the PLL locks. the minimum on-time limit in this situation, a significant Table 1 summarizes the different states in which the FREQ amount of cycle skipping can occur with correspondingly pin can be used. larger current and voltage ripple. Table 1 FREQ PIN PLLIN/MODE PIN FREQUENCY 0V DC Voltage 350kHz INTV DC Voltage 535kHz CC Resistor to SGND DC Voltage 50kHz to 900kHz Any of the Above External Clock Phase-Locked to External Clock 3859alfa 31 For more information www.linear.com/LTC3859AL

LTC3859AL APPLICATIONS INFORMATION Efficiency Considerations 3. I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, current sense resis- The percent efficiency of a switching regulator is equal to tor, and input and output capacitor ESR. In continuous the output power divided by the input power times 100%. mode the average output current flows through L and It is often useful to analyze individual losses to determine R , but is “chopped” between the topside MOSFET what is limiting the efficiency and which change would SENSE and the synchronous MOSFET. If the two MOSFETs have produce the most improvement. Percent efficiency can approximately the same R , then the resistance be expressed as: DS(ON) of one MOSFET can simply be summed with the resis- %Efficiency = 100% – (L1 + L2 + L3 + ...) tances of L, R and ESR to obtain I2R losses. For SENSE example, if each R = 30mΩ, R = 50mΩ, R where L1, L2, etc. are the individual losses as a percent- DS(ON) L SENSE = 10mΩ and R = 40mΩ (sum of both input and age of input power. ESR output capacitance losses), then the total resistance Although all dissipative elements in the circuit produce is 130mΩ. This results in losses ranging from 3% to losses, four main sources usually account for most of 13% as the output current increases from 1A to 5A for the losses in LTC3859AL circuits: 1) IC V current, BIAS a 5V output, or a 4% to 20% loss for a 3.3V output. 2) INTV regulator current, 3) I2R losses, 4) Topside CC Efficiency varies as the inverse square of V for the OUT MOSFET transition losses. same external components and output power level. The 1. The V current is the DC supply current given in the combined effects of increasingly lower output voltages BIAS Electrical Characteristics table, which excludes MOS- and higher currents required by high performance digital FET driver and control currents. V current typically systems is not doubling but quadrupling the importance BIAS results in a small (<0.1%) loss. of loss terms in the switching regulator system! 2. INTV current is the sum of the MOSFET driver and 4. Transition losses apply only to the top MOSFET(s) (bot- CC control currents. The MOSFET driver current results tom MOSFET for the boost), and become significant only from switching the gate capacitance of the power when operating at high input voltages (typically 15V or MOSFETs. Each time a MOSFET gate is switched from greater). Transition losses can be estimated from: low to high to low again, a packet of charge, dQ, moves Transition Loss = (1.7)V 2 • I • C • f IN O(MAX) RSS from INTV to ground. The resulting dQ/dt is a current CC Other hidden losses such as copper trace and internal out of INTV that is typically much larger than the CC battery resistances can account for an additional 5% control circuit current. In continuous mode, I GATECHG to 10% efficiency degradation in portable systems. It is = f(Q + Q ), where Q and Q are the gate charges of T B T B very important to include these “system” level losses the topside and bottom side MOSFETs. during the design phase. The internal battery and fuse Supplying INTV from an output-derived source power CC resistance losses can be minimized by making sure that through EXTV will scale the V current required for CC IN C has adequate charge storage and very low ESR at IN the driver and control circuits by a factor of (Duty Cycle)/ the switching frequency. A 25W supply will typically (Efficiency). For example, in a 20V to 5V application, require a minimum of 20µF to 40µF of capacitance 10mA of INTV current results in approximately 2.5mA CC having a maximum of 20mΩ to 50mΩ of ESR. The of V current. This reduces the mid-current loss from IN LTC3859AL 2-phase architecture typically halves this 10% or more (if the driver was powered directly from input capacitance requirement over competing solu- V ) to only a few percent. IN tions. Other losses including Schottky conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. 3859alfa 32 For more information www.linear.com/LTC3859AL

LTC3859AL APPLICATIONS INFORMATION Checking Transient Response used to determine phase margin. This is why it is better to look at the I pin signal which is in the feedback loop The regulator loop response can be checked by looking at TH and is the filtered and compensated control loop response. the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) The gain of the loop will be increased by increasing RC load current. When a load step occurs, V shifts by an and the bandwidth of the loop will be increased by de- OUT amount equal to DI , where ESR is the effective creasing CC. If RC is increased by the same factor that LOAD(ESR) series resistance of C . DI also begins to charge or CC is decreased, the zero frequency will be kept the same, OUT LOAD discharge C generating the feedback error signal that thereby keeping the phase shift the same in the most OUT forces the regulator to adapt to the current change and critical frequency range of the feedback loop. The output return V to its steady-state value. During this recovery voltage settling behavior is related to the stability of the OUT time V can be monitored for excessive overshoot or closed-loop system and will demonstrate the actual overall OUT ringing, which would indicate a stability problem. OPTI- supply performance. LOOP compensation allows the transient response to be A second, more severe transient is caused by switching optimized over a wide range of output capacitance and in loads with large (>1µF) supply bypass capacitors. The ESR values. The availability of the I pin not only allows TH discharged bypass capacitors are effectively put in parallel optimization of control loop behavior, but it also provides with C , causing a rapid drop in V . No regulator can OUT OUT a DC coupled and AC filtered closed loop response test alter its delivery of current quickly enough to prevent this point. The DC step, rise time and settling at this test sudden step change in output voltage if the load switch point truly reflects the closed loop response. Assuming a resistance is low and it is driven quickly. If the ratio of predominantly second order system, phase margin and/ C to C is greater than 1:50, the switch rise time LOAD OUT or damping factor can be estimated using the percentage should be controlled so that the load rise time is limited of overshoot seen at this pin. The bandwidth can also be to approximately 25 • C . Thus a 10µF capacitor would LOAD estimated by examining the rise time at the pin. The I TH require a 250µs rise time, limiting the charging current external components shown in Figure 16 will provide an to about 200mA. adequate starting point for most applications. The I series RC-CC filter sets the dominant pole-zero Buck Design Example TH loop compensation. The values can be modified slightly As a design example for one of the buck channels channel, (from 0.5 to 2 times their suggested values) to optimize assume V = 12V , V = 22V , V = 3.3V, IN (NOMINAL) IN (MAX) OUT transient response once the final PC layout is done and I = 6A, V = 50mV, and f = 350kHz. MAX SENSE(MAX) the particular output capacitor type and value have been The inductance value is chosen first based on a 30% ripple determined. The output capacitors need to be selected current assumption. The highest value of ripple current because the various types and values determine the loop occurs at the maximum input voltage. Tie the FREQ pin gain and phase. An output current pulse of 20% to 80% to GND, generating 350kHz operation. The minimum of full-load current having a rise time of 1µs to 10µs will inductance for 30% ripple current is: produce output voltage and I pin waveforms that will TH give a sense of the overall loop stability without breaking ⎛ ⎞ V V the feedback loop. DI = OUT ⎜1− OUT ⎟ L ⎜ ⎟ (f)(L) V Placing a power MOSFET directly across the output ca- ⎝ IN(NOMINAL)⎠ pacitor and driving the gate with an appropriate signal A 3.9µH inductor will produce 29% ripple current. The generator is a practical way to produce a realistic load step peak inductor current will be the maximum DC value plus condition. The initial output voltage step resulting from one half the ripple current, or 6.88A. Increasing the ripple the step change in output current may not be within the current will also help ensure that the minimum on-time bandwidth of the feedback loop, so this signal cannot be 3859alfa 33 For more information www.linear.com/LTC3859AL

LTC3859AL APPLICATIONS INFORMATION of 95ns is not violated. The minimum on-time occurs at ESR of 0.02Ω for low output ripple. The output ripple in maximum V : continuous mode will be highest at the maximum input volt- IN age. The output voltage ripple due to ESR is approximately: V 3.3V t = OUT = = 429ns ON(MIN) V = R (DI ) = 0.02Ω(1.75A) = 35mV V (f) 22V(350kHz) ORIPPLE ESR L P-P IN(MAX) PC Board Layout Checklist The R resistor value can be calculated by using the SENSE minimum value for the maximum current sense threshold When laying out the printed circuit board, the following (43mV): checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the 43mV R ≤ =0.006Ω layout diagram of Figure 11. Figure 12 illustrates the current SENSE 6.88A waveforms present in the various branches of the 2-phase Choosing 1% resistors: R = 25k and R = 80.6k yields synchronous buck regulators operating in the continuous A B an output voltage of 3.33V. mode. Check the following in your layout: The power dissipation on the top side MOSFET can be easily 1. Are the top N-channel MOSFETs MTOP1 and MTOP2 estimated. Choosing a Fairchild FDS6982S dual MOSFET located within 1cm of each other with a common drain results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF. connection at CIN? Do not attempt to split the input At maximum input voltage with T(estimated) = 50°C: decoupling for the two channels as it can cause a large resonant loop. 3.3V 2 PMAIN = (6A) {1+(0.005)(50°C−25°C)} 2. Are the signal and power grounds kept separate? The 22V combined IC signal ground pin and the ground return 5A (0.035Ω)+(22V)26 (2.5Ω)(215pF)• of CINTVCC must return to the combined COUT (–) termi- 2 nals. The path formed by the top N-channel MOSFET, ⎧ 1 1 ⎫ Schottky diode and the C capacitor should have short ⎨ + ⎬(350kHz)= 433mW IN ⎩5V−2.3V 2.3V⎭ leads and PC trace lengths. The output capacitor (–) terminals should be connected as close as possible A short-circuit to ground will result in a folded back cur- to the (–) terminals of the input capacitor by placing rent of: the capacitors next to each other and away from the Schottky loop described above. 20mV 1⎧95ns(22V)⎫ I = − ⎨ ⎬=3.07A SC 3. Do the LTC3859AL V pins’ resistive dividers con- 0.006Ω 2⎩ 3.9µH ⎭ FB nect to the (+) terminals of C ? The resistive divider OUT with a typical value of R and z = (0.005/°C)(25°C) must be connected between the (+) terminal of C DS(ON) OUT = 0.125. The resulting power dissipated in the bottom and signal ground. The feedback resistor connections MOSFET is: should not be along the high current input feeds from 2 the input capacitor(s). P =(2.23A) (1.125)(0.022Ω)=233mW SYNC 4. Are the SENSE– and SENSE+ leads routed together with which is less than under full-load conditions. minimum PC trace spacing? The filter capacitor between The input capacitor to the buck regulator CIN is chosen SENSE+ and SENSE– should be as close as possible for an RMS current rating of at least 3A at temperature to the IC. Ensure accurate current sensing with Kelvin assuming only this channel is on. COUT is chosen with an connections at the sense resistor. 3859alfa 34 For more information www.linear.com/LTC3859AL

LTC3859AL APPLICATIONS INFORMATION 5. Is the INTV decoupling capacitor connected close the loop can be used to tame a poor PC layout if regulator CC to the IC, between the INTV and the power ground bandwidth optimization is not required. Only after each CC pins? This capacitor carries the MOSFET drivers’ cur- controller is checked for its individual performance should rent peaks. An additional 1µF ceramic capacitor placed both controllers be turned on at the same time. A particularly immediately next to the INTV and PGND pins can help difficult region of operation is when one controller channel CC improve noise performance substantially. is nearing its current comparator trip point when the other channel is turning on its top MOSFET. This occurs around 6. Keep the switching nodes (SW1, SW2, SW3), top gate 50% duty cycle on either channel due to the phasing of nodes (TG1, TG2, TG3), and boost nodes (BOOST1, the internal clocks and may cause minor duty cycle jitter. BOOST2, BOOST3) away from sensitive small-signal nodes, especially from the opposites channel’s voltage Reduce V from its nominal level to verify operation of IN and current sensing feedback pins. All of these nodes the regulator in dropout. Check the operation of the un- have very large and fast moving signals and therefore dervoltage lockout circuit by further lowering V while IN should be kept on the output side of the LTC3859AL monitoring the outputs to verify operation. and occupy minimum PC trace area. Investigate whether any problems exist only at higher out- 7. Use a modified star ground technique: a low impedance, put currents or only at higher input voltages. If problems large copper area central grounding point on the same coincide with high input voltages and low output currents, side of the PC board as the input and output capacitors look for capacitive coupling between the BOOST, SW, TG, with tie-ins for the bottom of the INTV decoupling and possibly BG connections and the sensitive voltage CC capacitor, the bottom of the voltage feedback resistive and current pins. The capacitor placed across the current divider and the SGND pin of the IC. sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the PC Board Layout Debugging effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with Start with one controller on at a time. It is helpful to use high current output loading at lower input voltages, look a DC-50MHz current probe to monitor the current in the for inductive coupling between C , Schottky and the top inductor while testing the circuit. Monitor the output switch- IN MOSFET components to the sensitive current and voltage ing node (SW pin) to synchronize the oscilloscope to the sensing traces. In addition, investigate common ground internal oscillator and probe the actual output voltage as path voltage pickup between these components and the well. Check for proper performance over the operating SGND pin of the IC. voltage and current range expected in the application. The frequency of operation should be maintained over the An embarrassing problem, which can be missed in an input voltage range down to dropout and until the output otherwise properly working switching regulator, results load drops below the low current operation threshold— when the current sensing leads are hooked up backwards. typically 25% of the maximum designed current level in The output voltage under this improper hookup will still Burst Mode operation. be maintained but the advantages of current mode control will not be realized. Compensation of the voltage loop will The duty cycle percentage should be maintained from cycle be much more sensitive to component selection. This to cycle in a well-designed, low noise PCB implementation. behavior can be investigated by temporarily shorting out Variation in the duty cycle at a subharmonic rate can sug- the current sensing resistor—don’t worry, the regulator gest noise pickup at the current or voltage sensing inputs will still maintain control of the output voltage. or inadequate loop compensation. Overcompensation of 3859alfa 35 For more information www.linear.com/LTC3859AL

LTC3859AL APPLICATIONS INFORMATION SW1 L1 RSENSE1 VOUT1 D1 COUT1 RL1 VIN RIN CIN SW2 L2 RSENSE2 VOUT2 BOLD LINES INDICATE D2 COUT2 RL2 HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH. 3859al F11 Figure 11. Branch Current Waveforms for Bucks 3859alfa 36 For more information www.linear.com/LTC3859AL

LTC3859AL TYPICAL APPLICATIONS VOUT1 RA1 OPT RB1 68.1k 357k LTC3859AL VFB1 SENSE1– CITH1A C1 100pF 1nF CITH1 RITH1 SENSE1+ 1500pF 15k 100k ITH1 PGOOD1 C1 0C.S1Sµ1F TG1 MTOP1 10µF4.L91µH RS6EmNΩSE1 VOUT1 5V TRACK/SS1 SW1 CB1 5A 0.1µF FREQ BOOST1 COUT1 PLLIN/MODE BG1 MBOT1 220µF SGND D1 RUN1 VBIAS VOUT2 RUN2 C10BµIAFS RA2 10pF RB2 RUN3 PGND 68.1k 649k VFB2 2C.I2THnF2 R1IT5Hk2 C4.I7NµT1F C2 10µF CITH2A ITH2 INTVCC 68pF D2 0C.1SµSF2 TG2 C0.B12µF MTOP2 6.L52µH RS8EmNΩSE2 VOUT2 TRACK/SS2 BOOST2 8.5V 3A VOUT3 SW2 COUT2 RA3 OPT RB3 BG2 MBOT2 68µF 68.1k 499k VFB3 0C.0IT1Hµ3F RITH3 SENSE2+ 3.6k C2 CITH3A ITH3 1nF 820pF SENSE2– VOUT3 10V* CSS3 D3 0.1µF SS3 TG3 MTOP3 L3 RSENSE2 C22O0UµTF3 1.2µH 2mΩ SW3 VIN CB3 2.5V TO 38V OV3 BOOST3 0.1µF (START-UP ABOVE 5V) MTOP1, MTOP2: BSZ097NO4LS MMBTOOPT13,: MBSBCO0T227:N BOS4ZL0S97NO4LS VOUT1 EXTVCC BG3 MBOT3 C22IN0µF MBOT3: BSCO1BN04LS SENSE3– L1: WÜRTH 744314490 L2: WÜRTH 744314650 C3 L3: WÜRTH 744325120 1nF CCCOOINUU, TTC12O:: USSTAA3NN: YYSOOA N61YT0OPTPB 5C2026C08EMM22L0LX SEN3S85E93al +F12 * FVOOLULT3O WISS 1 0VVIN W WHHEENN V VININ < > 1 100VV, D1, D2: CMDH-4E D3: BAS140W Figure 12. High Efficiency Wide Input Range Dual 5V/8.5V Converter 3859alfa 37 For more information www.linear.com/LTC3859AL

LTC3859AL TYPICAL APPLICATIONS VOUT1 RA1 33pF RB1 34k 475k LTC3859AL VFB1 SENSE1– CITH1A C1 100pF 1nF 6C8I0THpF1 R1IT0Hk1 SENSE1+ 100k ITH1 PGOOD1 C1 0C.S1Sµ1F TG1 MTOP1 10µF8.L81µH RS9EmNΩSE1 VOUT1 12V TRACK/SS1 SW1 CB1 3A 0.1µF FREQ BOOST1 COUT1 PLLIN/MODE BG1 MBOT1 47µF SGND D1 RUN1 VBIAS VOUT2 RUN2 C10BµIAFS RA2 15pF RB2 RUN3 PGND 68.1k 215k VFB2 8C2IT0Hp2F R1IT5Hk2 C4.I7NµT1F C2 10µF CITH2A ITH2 INTVCC 150pF D2 0C.1SµSF2 TG2 C0.B12µF MTOP2 3.L22µH RS6EmNΩSE2 VOUT2 TRACK/SS2 BOOST2 3.3V 5A VOUT3 SW2 COUT2 RA3 OPT RB3 BG2 MBOT2 150µF 68.1k 787k VFB3 0C.0IT1Hµ3F RITH3 SENSE2+ 3.6k C2 CITH3A ITH3 1nF 820pF SENSE2– VOUT3 15V* CSS3 D3 0.1µF SS3 TG3 MTOP3 L3 RSENSE2 C22O0UµTF3 100k 1.2µH 2mΩ INTVCC OV3 SW3 VIN CB3 2.5V TO 38V BOOST3 0.1µF (START-UP ABOVE 5V) MTOP1, MTOP2: VISHAY Si7848DP MMBTOOPT13,: MBSBCO0T227:N VOIS4HLSAY Si7848DP EXTVCC BG3 MBOT3 C22IN0µF MBOT3: BSCO1BN04LS SENSE3– L1: SUMIDA CDEP105-8R8M L2: SUMIDA CDEP105-3R2M C3 L3: WÜRTH 744325120 1nF CCCOOINUU, TTC12O:: UKSTEA3MN: YSEOTA NT4Y5T2OP5E 5D1045C70E6M2M2O0L1X6E035 SEN3S85E93al +F13 * FVOOLULT3O WISS 1 5VVIN W WHHEENN V VININ < > 1 155VV, D1, D2: CMDH-4E D3: BAS140W Figure 13. High Efficiency Wide Input Range Dual 12V/3.3V Converter 3859alfa 38 For more information www.linear.com/LTC3859AL

LTC3859AL TYPICAL APPLICATIONS VOUT1 RA1 56pF RB1 115k 28.7k LTC3859AL VFB1 SENSE1– CITH1A C1 200pF 1nF CITH1 RITH1 SENSE1+ 1000pF 3.93k 100k ITH1 PGOOD1 C1 0C.0S1Sµ1F TG1 MTOP1 10µF L1 RSENSE1 0.47µH 3.5mΩ VOUT1 TRACK/SS1 SW1 1V CB1 8A 0.1µF FREQ BOOST1 COUT1 PLLIN/MODE BG1 MBOT1 220µF ×2 SGND D1 RUN1 VBIAS VOUT2 RUN2 C10BµIAFS RA2 56pF RB2 RUN3 PGND 115k 57.6k VFB2 1C0I0T0Hp2F R3.I9T3Hk2 C4.I7NµT1F C2 10µF CITH2A ITH2 INTVCC 200pF D2 0.C01SµSF2 TG2 C0.B12µF MTOP2 0.4L72µH R3S.5ENmSΩE2 VOUT2 TRACK/SS2 BOOST2 1.2V 8A VOUT3 SW2 COUT2 RA3 OPT RB3 BG2 MBOT2 220µF 12.1k 232k ×2 VFB3 C1I5TnHF3 RITH3 SENSE2+ 8.66k C2 CITH3A ITH3 1nF 220pF SENSE2– VOUT3 24V CSS3 D3 COUT3 5A 0.01µF SS3 TG3 MTOP3 L3 RSENSE2 220µF 3.3µH 4mΩ OV3 SW3 VIN CB3 12V 0.1µF MTOP1, MTOP2: RENESAS RJK0305 BOOST3 CIN MMBTOOPT13,, MMBBOOTT23:: RREENNEESSAASS RHJAKT02312689H EXTVCC BG3 MBOT3 220µF L1, L2: SUMIDA CDEP105-0R4 SENSE3– L3: PULSE PA1494.362NL COUT1, COUT2: SANYO 2R5TPE220M C3 CIN, COUT3: SANYO 50CE220AX 1nF D1, D2: CMDH-4E SENSE3+ D3: BAS140W 3859al F14 Figure 14. High Efficiency Triple 24V/1V/1.2V Converter from 12V V IN 3859alfa 39 For more information www.linear.com/LTC3859AL

LTC3859AL TYPICAL APPLICATIONS VOUT1 RA1 RB1 115k 57.6k LTC3859AL VFB1 SENSE1– CITH1A C1 100pF 1nF 2C.I2THnF1 R5I.T6Hk1 SENSE1+ 100k ITH1 PGOOD1 C1 0C.S1Sµ1F TG1 MTOP1 10µF L1 RSENSE1 2.2µH 9mΩ VOUT1 TRACK/SS1 SW1 CB1 13.A2V 0.1µF FREQ BOOST1 COUT1 PLLIN/MODE BG1 MBOT1 220µF SGND D1 RUN1 VBIAS VOUT2 RUN2 C10BµIAFS RA2 RB2 RUN3 PGND 115k 357k VFB2 3C.I3THnF2 R9I.T1Hk2 C4.I7NµT1F C2 10µF CITH2A ITH2 INTVCC 100pF D2 0C.1SµSF2 TG2 C0.B12µF MTOP2 6.L52µH RS9EmNΩSE2 VOUT2 TRACK/SS2 BOOST2 3.3V 3A VOUT3 SW2 COUT2 RA3 RB3 BG2 MBOT2 220µF 115k 887k VFB3 1C0IT0Hn3F RITH3 SENSE2+ 13k C2 CITH3A ITH3 1nF 10pF SENSE2– D3 VOUT3 CSS3 10.5V 0.1µF SS3 TG3 C27O0UµTF3 1.2A C3 • OV3 SW3 10µF RSENSE2 MMMTBBOOOPTT113,,: MMBSTBZOO0PT9227::N BBOSS4ZZL009977NNOO44LLSS EXTVCC BOOBSGT33 MB5O0TV3•10Lµ3H 9mΩ C22IN0µV5F.I8NV TO 34V L1: WURTH 744311220 SENSE3– L2: WURTH 744314650 L3: COOPER BUSSMANN DRQ125-100 C3 COUT1: SANYO 2R5TPE220MAFB 1nF COUT2: SANYO 4TPE220MAZB SENSE3+ COUT3: SANYO SVPC270M CIN: SANYO 50CE220LX 3859al F15 D1, D2: CMDH-4E D3: DIODES INC B360A-13-F Figure 15. High Efficiency 1.2V/3.3V Step-Down Converter with 10.5V SEPIC Converter 3859alfa 40 For more information www.linear.com/LTC3859AL

LTC3859AL PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC3859AL#packaging for the most recent package drawings. FE Package 38-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1772 Rev C) Exposed Pad Variation AA 4.75 REF 9.60 – 9.80* (.378 – .386) 4.75 REF (.187) 38 20 6.60 ±0.10 2.74 REF 4.50 REF SEE NOTE 4 6.40 2.74 0.315 ±0.05 REF(.252) (.108) BSC 1.05 ±0.10 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT 1 19 1.20 4.30 – 4.50* (.047) (.169 – .177) 0.25 MAX REF 0° – 8° 0.50 0.09 – 0.20 0.50 – 0.75 (.0196) 0.05 – 0.15 (.0035 – .0079) (.020 – .030) BSC (.002 – .006) 0.17 – 0.27 (.0067 – .0106) FE38 (AA) TSSOP REV C 0910 TYP NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE 2. DIMENSIONS ARE INMILLIMETERS FOR EXPOSED PAD ATTACHMENT (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH 3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3859alfa 41 For more information www.linear.com/LTC3859AL

LTC3859AL PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC3859AL#packaging for the most recent package drawings. UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701 Rev C) 0.70 ±0.05 5.50 ±0.05 5.15 ±0.05 4.10 ±0.05 3.00 REF 3.15 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 5.5 REF 6.10 ±0.05 7.50 ±0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 NOTCH R = 0.30 TYP OR 0.75 ±0.05 3.00 REF 0.35 × 45° CHAMFER 5.00 ±0.10 0.00 – 0.05 37 38 0.40 ±0.10 PIN 1 TOP MARK 1 (SEE NOTE 6) 2 5.15 ±0.10 7.00 ±0.10 5.50 REF 3.15 ±0.10 (UH) QFN REF C 1107 0.200 REF 0.25 ±0.05 R = 0.125 R = 0.10 TYP TYP 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE OUTLINE M0-220 VARIATION WHKD MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 2. DRAWING NOT TO SCALE 5. EXPOSED PAD SHALL BE SOLDER PLATED 3. ALL DIMENSIONS ARE IN MILLIMETERS 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3859alfa 42 For more information www.linear.com/LTC3859AL

LTC3859AL REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 06/16 Modified Buck Block Diagram 13 Corrected P equation 23 MAIN_BOOST Modified points #3 and #4 28 Reversed N-FET in Figure 9 28 3859alfa 43 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnFeocrti omn oorf eit si ncifrocrumitsa atsio dne swcrwibwed.l hineereainr. cwoilml n/oLtT inCf3rin8g5e9 oAnL existing patent rights.

LTC3859AL TYPICAL APPLICATION High Efficiency Wide Input Range Dual 3.3V/8.5V Converter VOUT1 6R8A.11k 15pF R21B51k VFB1 LTC3859SAELNSE1– CITH1A C1 150pF 1nF CITH1 RITH1 SENSE1+ 820pF 15k 100k ITH1 PGOOD1 C1 0C.S1Sµ1F TG1 MTOP1 10µF L1 RSENSE1 3.2µH 6mΩ VOUT1 TRACK/SS1 SW1 CB1 35.A3V FREQ BOOST1 0.1µF COUT1 PLLIN/MODE BG1 MBOT1 150µF SGND D1 RUN1 VBIAS VOUT2 RUN2 C10BµIAFS 6R8A.12k 10pF R64B92k RUN3 PGND VFB2 2C.I2THnF2 R1IT5Hk2 C4.I7NµT1F C102µF CITH2A ITH2 INTVCC 68pF D2 0C.1SµSF2 TG2 C0.B12µF MTOP2 6.L52µH RS8EmNΩSE2 VOUT2 TRACK/SS2 BOOST2 8.5V 3A VOUT3 SW2 COUT2 6R8A.13k OPT R49B93k BG2 MBOT2 68µF VFB3 0C.0IT1Hµ3F RITH3 SENSE2+ 3.6k C2 CITH3A ITH3 1nF 820pF SENSE2– VOUT3 10V* CSS3 D3 0.1µF SS3 TG3 MTOP31.L23µH RS2EmNΩSE2 C22O0UµTF3 MMTBOOPT11,, MMTBOOPT22:: VBISSZH0A9Y7 NSOi748L4S8DP OV3 BOOSSWT33 C0.B13µF 2(VS.I5NTVA RTTO- U3P8 VABOVE 5V) MMTBOOPT33:: BBSSCC0O217BNNO044LLSS VOUT2 EXTVCC BG3 MBOT3 C22IN0µF LL12:: SWUÜMRITDHA 7 C4D4E3P1140655-03R2M SENSE3– L3: WÜRTH 744325120 C3 COUT1: SANYO 6TPB220ML 1nF CCDOI1NU,, TDC22O: :US CTAM3N: DYSHOA- N44YTEOPE 5105C0EM220LX SEN38S59Eal3 TA+02 * FVOOLULT3O WISS 1 0VVIN W WHHEENN V VININ < > 1 100VV, D3: BAS140W RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3786 Low I Synchronous Step-Up DC/DC Controller 4.5V (Down to 2.5V after Start-Up) ≤ V ≤ 38V, V Up to 60V, I = 55µA Q IN OUT Q PLL Fixed Frequency 50kHz to 900kHz, 3mm × 3mm QFN-16, MSOP-16E LTC3787 Low I , Multiphase, Dual Channel Single Output 4.5V (Down to 2.5V after Start-Up) ≤ V ≤ 38V, V up to 60V, PLL Fixed Q IN OUT Synchronous Step-Up DC/DC Controller Frequency 50kHz to 900kHz, I = 135µA Q LTC3826/ Low I , Dual Output 2-Phase Synchronous Step-Down PLL Fixed Frequency 50kHz to 900kHz, 4V≤ V ≤ 36V, 0.8V ≤ V ≤ 10V, Q IN OUT LTC3826-1 DC/DC Controllers with 99% Duty Cycle I = 30µA Q LTC3890/ 60V, Low I , Dual 2-Phase Synchronous Step-Down DC/DC PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V, 0.8V ≤ V ≤ 24V, Q IN OUT LTC3890-1/ Controller with 99% Duty Cycle I = 50µA Q LTC3890-2 LTC3891 60V, Low I , Synchronous Step-Down DC/DC Controller PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V, 0.8V ≤ V ≤ 24V, Q IN OUT with 99% Duty Cycle I = 50µA Q LTC3864 60V, Low I , High Voltage DC/DC Controller with 100% Fixed Frequency 50kHz to 850kHz, 3.5V≤ V ≤ 60V, 0.8V ≤ V ≤ V , Q IN OUT IN Duty Cycle IQ = 40µA, MSOP-12E, 3mm × 4mm DFN-12 LTC3789 4-Switch High Efficiency Buck-Boost DC/DC Controller 4V≤ V ≤ 38V, 0.8V ≤ V ≤ 38V IN OUT 3859alfa 44 Linear Technology Corporation LT 0616 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC3859AL (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3859AL © LINEAR TECHNOLOGY CORPORATION 2013