LTC3855 Dual, Multiphase Synchronous DC/DC Controller with Differential Remote Sense FeaTures DescripTion n Dual, 180° Phased Controllers Reduce Required The LTC®3855 is a dual PolyPhase® current mode synchro- Input Capacitance and Power Supply Induced Noise nous step-down switching regulator controller that drives n High Efficiency: Up to 95% all N-channel power MOSFET stages. It includes a high n RSENSE or DCR Current Sensing speed differential remote sense amplifier. The maximum n Programmable DCR Temperature Compensation current sense voltage is programmable for either 30mV, n ±0.75% 0.6V Output Voltage Accuracy 50mV or 75mV, allowing the use of either the inductor DCR n Phase-Lockable Fixed Frequency 250kHz to 770kHz or a discrete sense resistor as the sensing element. n True Remote Sensing Differential Amplifier The LTC3855 features a precision 0.6V reference and can n Dual N-Channel MOSFET Synchronous Drive produce output voltages up to 12.5V. A wide 4.5V to 38V n Wide V Range: 4.5V to 38V IN input supply range encompasses most intermediate bus n V Range: 0.6V to 12.5V without Differential Amplifier OUT voltages and battery chemistries. Power loss and supply n V Range: 0.6V to 3.3V with Differential Amplifier OUT noise are minimized by operating the two controller output n Clock Input and Output for Up to 12-Phase Operation stages out of phase. Burst Mode® operation, continuous n Adjustable Soft-Start or V Tracking OUT or pulse-skipping modes are supported. n Foldback Output Current Limiting n Output Overvoltage Protection The LTC3855 can be configured for up to 12-phase op- n 40-Pin (6mm × 6mm) QFN and 38-Lead FE Packages eration, has DCR temperature compensation, two power good signals and two current limit set pins. The LTC3855 applicaTions is available in low profile 40-pin 6mm × 6mm QFN and 38-lead exposed pad FE packages. n Computer Systems L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode and PolyPhase are registered n Telecom Systems trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620, 6100678, n Industrial and Medical Instruments 6144194, 6177787, 6304066, 6580258. n DC Power Distribution Systems Typical applicaTion High Efficiency Dual 1.8V/1.2V Step-Down Converter VIN Load Step + 4.5V TO 4.7µF 1µF 22µF 20V (Forced Continuous Mode) VIN INTVCC TG1 TG2 0.1µF 0.1µF ILOAD 0.56µH BOOST1 BOOST2 0.4µH 5A/DIV SW1 SW2 300mA TO 5A BG1 BG2 IL PGND1 LTC3855 PGND2 5A/DIV FREQ SENSE1+ SENSE2+ VOUT1 SENSE1– SDEIFNFSOEU2T– 20k VOUT2 100mVV/ODUIVT 1.8V VFB1 VFB2 1.2V AC-COUPLED 15A 40.2k ITH1 ITH2 15A + 470pF TK/SS1DIFFP SGNDDIFFNTK/SS2 470pF + 3×320µF 20k 15k 0.1µF 0.1µF 100k 7.5k20k 3×320µF VIN = 12V 50µs/DIV 3855TA01a VOUT = 1.8V 3855TA01 3855f 

LTC3855 absoluTe MaxiMuM raTings (Note 1) Input Supply Voltage (V ) .........................–0.3V to 40V DIFFP, DIFFN ..........................................–0.3V to INTV IN CC Top Side Driver Voltages ITEMP1, ITEMP2 Voltages ....................–0.3V to INTV CC BOOST1, BOOST2 ..................................–0.3V to 46V I , I , V , V Voltages ..............–0.3V to INTV TH1 TH2 FB1 FB2 CC Switch Voltage (SW1, SW2) .........................–5V to 40V INTV Peak Output Current (Note 8) ..................100mA CC INTV , RUN1, RUN2, PGOOD(s), EXTV , Operating Junction Temperature Range (Notes 2, 3) CC CC (BOOST1-SW1), (BOOST2-SW2) .............–0.3V to 6V LTC3855 .............................................–40°C to 125°C SENSE1+, SENSE2+, SENSE1–, Storage Temperature Range ...................–65°C to 125°C SENSE2– Voltages .................................–0.3V to 13V Lead Temperature (Soldering, 10 sec) MODE/PLLIN, I , I , TK/SS1, TK/SS2, FREQ, (FE Package) .....................................................300°C LIM1 LIM2 DIFFOUT, PHASMD Voltages .............–0.3V to INTV CC pin conFiguraTion TOP VIEW ITEMP2 1 38 FREQ TOP VIEW ITEMP1 2 37 MODE/PLLIN N LI SSEENNRSSUEEN111+– 345 333654 PCSHLWKA1OSUMTD –4SENSE10 +3SENSE19 3RUN18 3ITEMP17 3ITEMP26 3FREQ5 3MODE/PL4 3PHASMD3 3CLKOUT2 3SW11 TK/SS1 6 33 TG1 TK/SS1 1 30 TG1 ITH1 7 32 BOOST1 ITH1 2 29 BOOST1 VFB1 8 31 PGND1 VFB1 3 28 PGND1 VFB2 9 30 BG1 SGND 4 27 BG1 39 ITH2 10 SGND 29 VIN VFB2 5 41 26 VIN TK/SS2 11 28 INTVCC ITH2 6 SGND 25 INTVCC SENSE2+ 12 27 EXTVCC TK/SS2 7 24 EXTVCC SENSE2– 13 26 BG2 SENSE2+ 8 23 BG2 DIFFP 14 25 PGND2 SENSE2– 9 22 PGND2 DIFFP 10 21 BOOST2 DIFFN 15 24 BOOST2 11 12 13 14 15 16 17 18 19 20 DIFFOUT 16 23 TG2 RILUINM21 1178 2221 SPWGO2OD2 DIFFN DIFFOUT RUN2 ILIM1 ILIM2 PGOOD1 PGOOD2 NC SW2 TG2 ILIM2 19 20 PGOOD1 UJ PACKAGE 40-LEAD (6mm (cid:115) 6mm) PLASTIC QFN FE PACKAGE TJMAX = 125°C, θJA = 33°C/W 38-LEAD PLASTIC SSOP EXPOSED PAD (PIN 41) IS SGND, MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 25°C/W EXPOSED PAD (PIN 39) IS SGND, MUST BE SOLDERED TO PCB 3855f 

LTC3855 orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3855EFE#PBF LTC3855EFE#TRPBF LTC3855FE 38-Lead Plastic TSSOP –40°C to 85°C LTC3855IFE#PBF LTC3855IFE#TRPBF LTC3855FE 38-Lead Plastic TSSOP –40°C to 125°C LTC3855EUJ#PBF LTC3855EUJ#TRPBF LTC3855UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C LTC3855IUJ#PBF LTC3855IUJ#TRPBF LTC3855UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ elecTrical characTerisTics The l denotes the specifications which apply over the full operating junction temperature range (E-Grade), otherwise specifications are at T = 25°C. V = 15V, V = 5V unless otherwise noted. A IN RUN1,2 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loops V Input Voltage Range 4.5 38 V IN V Output Voltage Range 0.6 12.5 V OUT V Regulated Feedback Voltage I Voltage = 1.2V (Note 4) l 0.5955 0.600 0.6045 V FB1,2 TH1,2 I Voltage = 1.2V (Note 4), T = 125°C l 0.594 0.600 0.606 V TH1,2 A I Feedback Current (Note 4) –15 –50 nA FB1,2 V Reference Voltage Line Regulation V = 4.5V to 38V (Note 4) 0.002 0.02 %/V REFLNREG IN V Output Voltage Load Regulation (Note 4) LOADREG Measured in Servo Loop; ∆I Voltage = 1.2V to 0.7V l 0.01 0.1 % TH Measured in Servo Loop; ∆I Voltage = 1.2V to 1.6V l –0.01 –0.1 % TH g Transconductance Amplifier g I = 1.2V; Sink/Source 5µA; (Note 4) 2 mmho m1,2 m TH1,2 I Input DC Supply Current (Note 5) Q Normal Mode V = 15V 3.5 mA IN Shutdown V = 0V 30 50 µA RUN1,2 DF Maximum Duty Factor In Dropout, f = 500kHz 94 95 % MAX OSC UVLO Undervoltage Lockout V Ramping Down l 3.0 3.2 3.4 V INTVCC UVLO UVLO Hysteresis 0.6 V HYS V Feedback Overvoltage Lockout Measured at V l 0.64 0.66 0.68 V OVL1,2 FB1,2 I Sense Pins Bias Current (Each Channel); V = 3.3V l ±1 ±2 µA SENSE1,2 SENSE1,2 I DCR Tempco Compensation Current V = 0.2V l 9 10 11 µA TEMP1,2 ITEMP1,2 I Soft-Start Charge Current V = 0V l 1 1.2 1.4 µA TK/SS1,2 TK/SS1,2 V RUN Pin ON Threshold V , V Rising l 1.1 1.22 1.35 V RUN1,2 RUN1 RUN2 V RUN Pin ON Hysteresis 80 mV RUN1,2HYS V Maximum Current Sense Threshold V = 0.5V, V = 3.3V, I = 0V l 25 30 35 mV SENSE(MAX) FB1,2 SENSE1,2 LIM V = 0.5V, V = 3.3V, I = Float l 45 50 55 mV FB1,2 SENSE1,2 LIM V = 0.5V, V = 3.3V, I = INTV l 68 75 82 mV FB1,2 SENSE1,2 LIM CC TG1, 2 t TG Transition Time: (Note 6) r TG1, 2 t Rise Time C = 3300pF 25 ns f LOAD Fall Time C = 3300pF 25 ns LOAD BG1, 2 t BG Transition Time: (Note 6) r BG1, 2 t Rise Time C = 3300pF 25 ns f LOAD Fall Time C = 3300pF 25 ns LOAD 3855f 

LTC3855 elecTrical characTerisTics The l denotes the specifications which apply over the full operating junction temperature range (E-Grade), otherwise specifications are at T = 25°C. V = 15V, V = 5V unless otherwise noted. A IN RUN1,2 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS TG/BG t Top Gate Off to Bottom Gate On Delay C = 3300pF Each Driver 30 ns 1D LOAD Synchronous Switch-On Delay Time BG/TG t Bottom Gate Off to Top Gate On Delay C = 3300pF Each Driver 30 ns 2D LOAD Top Switch-On Delay Time t Minimum On-Time (Note 7) 90 ns ON(MIN) INTV Linear Regulator CC V Internal V Voltage 6V < V < 38V 4.8 5 5.2 V INTVCC CC IN V INT INTV Load Regulation I = 0mA to 20mA 0.5 2 % LDO CC CC V EXTV Switchover Voltage EXTV Ramping Positive l 4.5 4.7 V EXTVCC CC CC V EXT EXTV Voltage Drop I = 20mA, V = 5V 50 100 mV LDO CC CC EXTVCC V EXTV Hysteresis 200 mV LDOHYS CC Oscillator and Phase-Locked Loop f Nominal Frequency V = 1.2V 450 500 550 kHz NOM FREQ f Lowest Frequency V = 0V 210 250 290 kHz LOW FREQ f Highest Frequency V ≥ 2.4V 700 770 850 kHz HIGH FREQ R MODE/PLLIN Input Resistance 250 kΩ MODE/PLLIN I Frequency Setting Current 9 10 11 µA FREQ CLKOUT Phase (Relative to Controller 1) PHASMD = GND 60 Deg PHASMD = Float 90 Deg PHASMD = INTV 120 Deg CC CLK Clock High Output Voltage 4 5 V HIGH CLK Clock Low Output Voltage 0 0.2 V LOW PGOOD Output V PGOOD Voltage Low I = 2mA 0.1 0.3 V PGL PGOOD I PGOOD Leakage Current V = 5V ±2 µA PGOOD PGOOD V PGOOD Trip Level, Either Controller V with Respect to Set Output Voltage PG FB V Ramping Negative –10 % FB V Ramping Positive 10 % FB Differential Amplifier A Gain l 0.998 1 1.002 V/V DA R Input Resistance Measured at DIFFP Input 80 kΩ IN V Input Offset Voltage V = V = 1.5V, I = 100µA 2 mV OS DIFFP DIFFOUT DIFFOUT PSRR Power Supply Rejection Ratio 5V < V < 38V 100 dB OA IN I Maximum Output Current 2 3 mA CL V Maximum Output Voltage I = 300µA V – 1.4 V – 1.1 V OUT(MAX) DIFFOUT INTVCC INTVCC GBW Gain Bandwidth Product (Note 8) 3 MHz Slew Rate Differential Amplifier Slew Rate (Note 8) 2 V/µs 3855f 

LTC3855 elecTrical characTerisTics The l denotes the specifications which apply over the full operating junction temperature range (E-Grade), otherwise specifications are at T = 25°C. V = 15V, V = 5V unless otherwise noted. A IN RUN/SS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS On Chip Driver TG R TG Pull-Up R TG High 2.6 Ω UP DS(ON) TG R TG Pull-Down R TG Low 1.5 Ω DOWN DS(ON) BG R BG Pull-Up R BG High 2.4 Ω UP DS(ON) BG R BG Pull-Down R BG Low 1.1 Ω DOWN DS(ON) Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 4: The LTC3855 is tested in a feedback loop that servos V to a ITH1,2 may cause permanent damage to the device. Exposure to any Absolute specified voltage and measures the resultant VFB1,2. Maximum Rating condition for extended periods may affect device Note 5: Dynamic supply current is higher due to the gate charge being reliability and lifetime. delivered at the switching frequency. See Applications Information. Note 2: The LTC3855E is guaranteed to meet performance specifications Note 6: Rise and fall times are measured using 10% and 90% levels. Delay from 0°C to 85°C. Specifications over the –40°C to 85°C operating times are measured using 50% levels. junction temperature range are assured by design, characterization and Note 7: The minimum on-time condition is specified for an inductor correlation with statistical process controls. The LTC3855I is guaranteed peak-to-peak ripple current ≥40% of IMAX (see Minimum On-Time to meet performance specifications over the full –40°C to 125°C operating Considerations in the Applications Information section). junction temperature range. Note 8: Guaranteed by design. Note 3: T is calculated from the ambient temperature T and power J A dissipation P according to the following formulas: D LTC3855UJ: T = T + (P • 33°C/W) J A D LTC3855FE: T = T + (P • 25°C/W) J A D Typical perForMance characTerisTics Efficiency vs Output Current Efficiency vs Output Current Full Load Efficiency and Power and Mode and Mode Loss vs Input Voltage 100 100 90 5 1.8V 90 90 Burst Mode EFFICIENCY 80 OPERATION 80 Burst Mode OPERATION 1.2V 70 70 NCY (%) 5600 DCM VIN = 12V NCY (%) 5600 DCM VIN = 12V NCY (%) 85 4 POWER L EFFICIE 40 CCM VOUT = 1.8V EFFICIE 40 CCM VOUT = 1.2V EFFICIE 80 POWER LOS1S.8V 3 OSS (W 30 30 ) 1.2V 20 20 10 10 CIRCUIT OF FIGURE 19 CIRCUIT OF FIGURE 19 CIRCUIT OF FIGURE 19 0 0 75 2 0.01 0.1 1 10 100 0.01 0.1 1 10 100 5 10 15 20 LOAD CURRENT (A) LOAD CURRENT (A) INPUT VOLTAGE (V) 3855 G23 3855 G24 3855G24 3855f 

LTC3855 Typical perForMance characTerisTics Load Step Load Step (Burst Mode Operation) (Forced Continuous Mode) ILOAD 5AIL/ODAIVD 5A/DIV 300mA TO 5A 300mA TO 5A IL IL 5A/DIV 5A/DIV VOUT VOUT 100mV/DIV 100mV/DIV AC-COUPLED AC-COUPLED 50µs/DIV 3855G01 50µs/DIV 3855G02 VIN = 12V VIN = 12V VOUT = 1.8V VOUT = 1.8V Load Step (Pulse-Skipping Mode) Inductor Current at Light Load ILOAD 5A/DIV FORCED 300mA TO 5A CONTINUOUS MODE 5A/DIV IL Burst Mode 5A/DIV OPERATION VOUT 5A/DIV 100mV/DIV PULSE-SKIPPING AC-COUPLED MODE 5A/DIV 50µs/DIV 3855G03 1µs/DIV 3855G04 VIN = 12V VIN = 12V VOUT = 1.8V VOUT = 1.8V ILOAD = 400mA Prebiased Output at 2V Coincident Tracking VOUT RUN 2V/DIV 2V/DIV VOUT1 VFB 500mTVK/D/SISV VVOOUUTT12 VOUT2 1V/DIV 500mV/DIV 2ms/DIV 3855G05 5ms/DIV 3855G06 VIN = 12V VOUT1 = 1.8V, 1.5Ω LOAD VOUT = 3.3V VOUT2 = 1.2V, 1Ω LOAD 3855f 

LTC3855 Typical perForMance characTerisTics Tracking Up and Down Quiescent Current with External Ramp vs Temperature without EXTV INTV Line Regulation CC CC 4.5 5.5 TK/SS1 4.0 TK/SS2 5.0 2V/DIV VOUT1 A) 3.5 500mVVAOO/DUUTTIV12 VVIONU =T1 1 =2 V1.8V, 1.5Ω1 0LVmOOAsU/DDT2IV 3855G07 QUIESCENT CURRENT (m 32121.....00055 INTV VOLTAGE (V)CC4433....5005 VOUT2 = 1.2V, 1Ω LOAD 0.5 2.5 0 2.0 –50 –25 0 25 50 75 100 125 0 10 20 30 40 TEMPERATURE (°C) INPUT VOLTAGE (V) 3855G08 3855G09 Maximum Current Sense Current Sense Threshold Threshold vs Common Mode Maximum Current Sense vs I Voltage Voltage Threshold vs Duty Cycle TH 80 80 80 ILIM = INTVCC 60 mV) 70 ILIM = INTVCC mV) 70 ILIM = INTVCC D ( 60 D ( 60 L L 40 ILIM = FLOAT HO HO (mV)SENSE 20 ILIM = GND NSE THRES 4500 ILIM = FLOAT NSE THRES 4500 ILIM = FLOAT V 0 T SE 30 ILIM = GND T SE 30 ILIM = GND N N E 20 E 20 R R –20 UR UR C 10 C 10 –40 0 0 0 0.5 1 1.5 2 0 2 4 6 8 10 12 0 20 40 60 80 100 VITH (V) VSENSE COMMON MODE VOLTAGE (V) DUTY CYCLE (%) 3855G10 3855G11 3855G12 Maximum Current Sense Voltage vs Feedback Voltage (Current TK/SS Pull-Up Current Foldback) vs Temperature V) 90 1.6 m D ( 80 ILIM = INTVCC L O H 70 S RE A) NSE TH 6500 ILIM = FLOAT RENT (µ 1.4 RRENT SE 4300 ILIM = GND K/SS CUR 1.2 U T C M 20 U XIM 10 A M 0 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 –50 –25 0 25 50 75 100 125 FEEDBACK VOLTAGE (V) TEMPERATURE (°C) 3855G13 3855G14 3855f 

LTC3855 Typical perForMance characTerisTics Shutdown (RUN) Threshold Regulated Feedback Voltage Oscillator Frequency vs Temperature vs Temperature vs Temperature 1.26 612 900 1.24 mV) 610 800 RUN PIN THRESHOLD (V) 11111.....2211120486 OOFNF ULATED FEEDBACK VOLTAGE ( 666665500000998642068 FREQUENCY (kHz) 756234000000000000 VVVFFRFRREEQEQQ == = I1 NG.T2NVVDCC G 1.12 RE 594 100 1.10 592 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3855G15 3855G16 3855G17 Undervoltage Lockout Threshold Oscillator Frequency Shutdown Current (INTV ) vs Temperature vs Input Voltage vs Input Voltage CC 4.1 520 60 3.9 RISING A) 50 µ 3.7 510 T ( ESHOLD (V) 33..53 FALLING NCY (kHz)500 UT CURREN 4300 R E P H U N VLO T 3.1 FREQ OWN I 20 U 2.9 490 TD U H 10 2.7 S 2.5 480 0 –40 –20 0 20 40 60 80 100 5 10 15 20 25 30 35 40 5 10 15 20 25 30 35 40 TEMPERATURE (°C) INPUT VOLTAGE (V) INPUT VOLTAGE (V) 3855G18 3855G19 3855G20 Shutdown Current Quiescent Current vs Temperature vs Input Voltage without EXTV CC 60 4.5 4.3 50 RENT (µA) 40 NT (mA) 433...179 N CUR 30 CURRE 3.5 W Y 3.3 O L UTD 20 UPP 3.1 H S S 2.9 10 2.7 0 2.5 –50 –25 0 25 50 75 100 125 5 10 15 20 25 30 35 40 TEMPERATURE (°C) INPUT VOLTAGE (V) 3855G21 3855G22 3855f 

LTC3855 pin FuncTions (FE38/UJ40) ITEMP1, ITEMP2 (Pin 2, Pin 1/Pin 37, Pin 36): Inputs of DIFFP (Pin 14/Pin 10): Positive Input of Remote Sens- the temperature sensing comparators. Connect each of ing Differential Amplifier. Connect this to the remote load these pins to external NTC resistors placed near induc- voltage of one of the two channels directly. tors. Floating these pins disables the DCR temperature DIFFN (Pin 15/Pin 11): Negative Input of Remote Sensing compensation function. Differential Amplifier. Connect this to the negative terminal RUN1, RUN2 (Pin 3, Pin 17/Pin 38, Pin 13): Run Control of the output capacitors. Inputs. A voltage above 1.2V on either pin turns on the IC. DIFFOUT (Pin 16/Pin 12): Output of Remote Sensing Dif- However, forcing either of these pins below 1.2V causes ferential Amplifier. Connect this to V or V through FB1 FB2 the IC to shut down the circuitry required for that particular a resistive divider. channel. There are 1µA pull-up currents for these pins. Once the Run pin rises above 1.2V, an additional 4.5µA ILIM1, ILIM2 (Pin 18, Pin 19/Pin 14, Pin 15): Current pull-up current is added to the pin. Comparator Sense Voltage Range Inputs. This pin can be tied to SGND, tied to INTV or left floating to set the SENSE1+, SENSE2+ (Pin 4, Pin 12/Pin 39, Pin 8): Current CC maximum current sense threshold for each comparator. Sense Comparator Inputs. The (+) inputs to the current comparators are normally connected to DCR sensing PGOOD1, PGOOD2 (Pin 20, Pin 21/Pin 16, Pin 17): Power networks or current sensing resistors. Good Indicator Output for Each Channel. Open drain logic out that is pulled to ground when either channel output SENSE1–, SENSE2– (Pin 5, Pin 13/Pin 40, Pin 9): Current exceeds ±10% regulation window, after the internal 20µs Sense Comparator Inputs. The (–) inputs to the current power bad mask timer expires. comparators are connected to the outputs. EXTV (Pin 27/Pin 24): External Power Input to an Inter- CC TK/SS1, TK/SS2 (Pin 6, Pin 11/Pin 1, Pin 7): Output Volt- nal Switch Connected to INTV . This switch closes and CC age Tracking and Soft-Start Inputs. When one particular supplies the IC power, bypassing the internal low dropout channel is configured to be the master of two channels, regulator, whenever EXTV is higher than 4.7V. Do not CC a capacitor to ground at this pin sets the ramp rate for exceed 6V on this pin. the master channel’s output voltage. When the channel is configured to be the slave of two channels, the VFB INTVCC (Pin 28/Pin 25): Internal 5V Regulator Output. The voltage of the master channel is reproduced by a resistor control circuits are powered from this voltage. Decouple divider and applied to this pin. Internal soft-start currents this pin to PGND with a minimum of 4.7µF low ESR tan- of 1.2µA are charging these pins. talum or ceramic capacitor. ITH1, ITH2 (Pin 7, Pin 10/Pin 2, Pin 6): Current Control VIN (Pin 29/Pin 26): Main Input Supply. Decouple this pin Thresholds and Error Amplifier Compensation Points. to PGND with a capacitor (0.1µF to 1µF). Each associated channels’ current comparator tripping BG1, BG2 (Pin 30, Pin 26/Pin 27, Pin 23): Bottom Gate threshold increases with its I control voltage. TH Driver Outputs. These pins drive the gates of the bottom VFB1, VFB2 (Pin 8, Pin 9/Pin 3, Pin 5): Error Amplifier N-Channel MOSFETs between PGND and INTVCC. Feedback Inputs. These pins receive the remotely sensed PGND1, PGND2 (Pin 31, Pin 25/Pin 28, Pin 22): Power feedback voltages for each channel from external resistive Ground Pin. Connect this pin closely to the sources of the dividers across the outputs. bottom N-channel MOSFETs, the (–) terminal of C and VCC the (–) terminal of C . IN 3855f 

LTC3855 pin FuncTions (FE38/UJ40) BOOST1, BOOST2 (Pin 32, Pin 24/Pin 29, Pin 21): Boosted MODE/PLLIN (Pin 37/Pin 34): This is a dual purpose pin. Floating Driver Supplies. The (+) terminal of the bootstrap When external frequency synchronization is not used, capacitors connect to these pins. These pins swing from a this pin selects the operating mode. The pin can be tied diode voltage drop below INTV up to V + INTV . to SGND, tied to INTV or left floating. SGND enables CC IN CC CC forced continuous mode. INTV enables pulse-skipping TG1, TG2 (Pin 33, Pin 23/Pin 30, Pin 20): Top Gate CC mode. Floating enables Burst Mode operation. For external Driver Outputs. These are the outputs of floating drivers sync, apply a clock signal to this pin. Both channels will with a voltage swing equal to INTV superimposed on CC go into forced continuous mode and the internal PLL will the switch nodes voltages. synchronize the internal oscillator to the clock. The PLL SW1, SW2 (Pin 34, Pin 22/Pin 31, Pin 19): Switch Node compensation network is integrated into the IC. Connections to Inductors. Voltage swing at these pins FREQ (Pin 38/Pin 35): There is a precision 10µA current is from a Schottky diode (external) voltage drop below flowing out of this pin. A resistor to ground sets a voltage ground to V . IN which in turn programs the frequency. Alternatively, this PHASMD (Pin 36/Pin 33): This pin can be tied to SGND, pin can be driven with a DC voltage to vary the frequency tied to INTVCC or left floating. This pin determines the of the internal oscillator. relative phases between the internal controllers as well SGND (Exposed Pad Pin 39/ Pin 4, Exposed Pad Pin 41): as the phasing of the CLKOUT signal. See Table 1 in the Signal Ground. All small-signal components and com- Operation section. pensation components should connect to this ground, CLKOUT (Pin 35/Pin 32): Clock output with phase change- which in turn connects to PGND at one point. Exposed able by PHASMD to enable usage of multiple LTC3855 in pad must be soldered to PCB, providing a local ground multiphase systems. for the control components of the IC, and be tied to the PGND pin under the IC. 3855f 0

LTC3855 FuncTional block DiagraM FREQ MODE/PLLIN PHASMD ITEMP EXTVCC VIN VIN 4.7V + – + CIN TEMPSNS F MODE/SYNC 0.6V 5V DETECT REG PLL-SYNC – + INTVCC F INTVCC BOOST CLKOUT OSC S BURSTEN TG CB R Q FCNT M1 SW L1 3k ON SWITCH VOUT + – LOANGDIC SENSE+ DB ICMP IREV SAHNOTOI-T – + THROUGH SENSE– + RUN COUT BG OV M2 CVCC ILIM SLOPE COMPENSATION PGND PGOOD DIFFP INTVCC UVLO 40k + 0.54V + 511k SLAOCPTEIV REE CCLOAVMEPRY UV VFB R2 DIFFAMP 40k – – ITHB + 40k 40k DIFFN VIN SLEEP R1 OV – 0.66V 0.6V – SS + –RUN + SGND REF EA 1.2µA – + + + – 0.5V 1.2V 0.55V 1µA ITH RC CC1 RUN TK/SS CSS 3855FBD DIFFOUT 3855f 

LTC3855 operaTion Main Control Loop Shutdown and Start-Up (RUN1, RUN2 and TK/SS1, TK/SS2 Pins) The LTC3855 is a constant-frequency, current mode step- down controller with two channels operating 180 degrees The two channels of the LTC3855 can be independently out-of-phase. During normal operation, each top MOSFET shut down using the RUN1 and RUN2 pins. Pulling either is turned on when the clock for that channel sets the RS of these pins below 1.2V shuts down the main control latch, and turned off when the main current comparator, loop for that controller. Pulling both pins low disables both I , resets the RS latch. The peak inductor current at controllers and most internal circuits, including the INTV CMP CC which I resets the RS latch is controlled by the voltage regulator. Releasing either RUN pin allows an internal CMP on the I pin, which is the output of each error ampli- 1µA current to pull up the pin and enable that controller. TH fier EA. The V pin receives the voltage feedback signal, Alternatively, the RUN pin may be externally pulled up FB which is compared to the internal reference voltage by the or driven directly by logic. Be careful not to exceed the EA. When the load current increases, it causes a slight Absolute Maximum Rating of 6V on this pin. decrease in V relative to the 0.6V reference, which in FB The start-up of each controller’s output voltage V is OUT turn causes the I voltage to increase until the average TH controlled by the voltage on the TK/SS1 and TK/SS2 pins. inductor current matches the new load current. After the When the voltage on the TK/SS pin is less than the 0.6V top MOSFET has turned off, the bottom MOSFET is turned internal reference, the LTC3855 regulates the V voltage FB on until either the inductor current starts to reverse, as to the TK/SS pin voltage instead of the 0.6V reference. This indicated by the reverse current comparator I , or the REV allows the TK/SS pin to be used to program the soft-start beginning of the next cycle. period by connecting an external capacitor from the TK/SS pin to SGND. An internal 1.2µA pull-up current charges INTV /EXTV Power CC CC this capacitor, creating a voltage ramp on the TK/SS pin. Power for the top and bottom MOSFET drivers and most As the TK/SS voltage rises linearly from 0V to 0.6V (and other internal circuitry is derived from the INTVCC pin. When beyond), the output voltage VOUT rises smoothly from zero the EXTVCC pin is left open or tied to a voltage less than to its final value. Alternatively the TK/SS pin can be used 4.7V, an internal 5V linear regulator supplies INTVCC power to cause the start-up of VOUT to “track” that of another from VIN. If EXTVCC is taken above 4.7V, the 5V regulator is supply. Typically, this requires connecting to the TK/SS turned off and an internal switch is turned on connecting pin an external resistor divider from the other supply to EXTVCC. Using the EXTVCC pin allows the INTVCC power ground (see the Applications Information section). When to be derived from a high efficiency external source such the corresponding RUN pin is pulled low to disable a as one of the LTC3855 switching regulator outputs. controller, or when INTV drops below its undervoltage CC lockout threshold of 3.2V, the TK/SS pin is pulled low by Each top MOSFET driver is biased from the floating an internal MOSFET. When in undervoltage lockout, both bootstrap capacitor C , which normally recharges during B controllers are disabled and the external MOSFETs are each off cycle through an external diode when the top held off. MOSFET turns off. If the input voltage V decreases to IN a voltage close to V , the loop may enter dropout and OUT Light Load Current Operation (Burst Mode Operation, attempt to turn on the top MOSFET continuously. The Pulse-Skipping, or Continuous Conduction) dropout detector detects this and forces the top MOSFET off for about one-twelfth of the clock period plus 100ns The LTC3855 can be enabled to enter high efficiency Burst every third cycle to allow C to recharge. However, it is Mode operation, constant-frequency pulse-skipping mode, B recommended that a load be present or the IC operates or forced continuous conduction mode. To select forced at low frequency during the drop-out transition to ensure continuous operation, tie the MODE/PLLIN pin to a DC C is recharged. B 3855f 

LTC3855 operaTion voltage below 0.6V (e.g., SGND). To select pulse-skipping Multichip Operations (PHASMD and CLKOUT Pins) mode of operation, tie the MODE/PLLIN pin to INTV . To CC The PHASMD pin determines the relative phases between select Burst Mode operation, float the MODE/PLLIN pin. the internal controllers as well as the CLKOUT signal as When a controller is enabled for Burst Mode operation, shown in Table 1. The phases tabulated are relative to the peak current in the inductor is set to approximately zero phase being defined as the rising edge of the clock one-third of the maximum sense voltage even though of phase 1. the voltage on the I pin indicates a lower value. If the TH average inductor current is higher than the load current, Table 1. the error amplifier EA will decrease the voltage on the ITH PHASMD GND FLOAT INTVcc pin. When the ITH voltage drops below 0.5V, the internal Phase1 0° 0° 0° sleep signal goes high (enabling sleep mode) and both Phase2 180° 180° 240° external MOSFETs are turned off. CLKOUT 60° 90° 120° In sleep mode, the load current is supplied by the output The CLKOUT signal can be used to synchronize additional capacitor. As the output voltage decreases, the EA’s output power stages in a multiphase power supply solution feeding begins to rise. When the output voltage drops enough, the a single, high current output or separate outputs. Input sleep signal goes low, and the controller resumes normal capacitance ESR requirements and efficiency losses are operation by turning on the top external MOSFET on the substantially reduced because the peak current drawn from next cycle of the internal oscillator. When a controller is the input capacitor is effectively divided by the number enabled for Burst Mode operation, the inductor current is of phases used and power loss is proportional to the not allowed to reverse. The reverse current comparator RMS current squared. A two stage, single output voltage (I ) turns off the bottom external MOSFET just before REV implementation can reduce input path power loss by 75% the inductor current reaches zero, preventing it from and radically reduce the required RMS current rating of reversing and going negative. Thus, the controller oper- the input capacitor(s). ates in discontinuous operation. In forced continuous operation, the inductor current is allowed to reverse at Single Output Multiphase Operation light loads or under large transient conditions. The peak inductor current is determined by the voltage on the I The LTC3855 can be used for single output multiphase TH pin. In this mode, the efficiency at light loads is lower than converters by making these connections in Burst Mode operation. However, continuous mode has • Tie all of the I pins together TH the advantages of lower output ripple and less interference • Tie all of the V pins together with audio circuitry. FB • Tie all of the TK/SS pins together When the MODE/PLLIN pin is connected to INTV , the CC LTC3855 operates in PWM pulse-skipping mode at light • Tie all of the RUN pins together loads. At very light loads, the current comparator I may CMP • Tie all of the ITEMP pins together remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles (i.e., • Tie all of the I pins together, or tie the I pins to LIM LIM skipping pulses). The inductor current is not allowed to the same potential reverse (discontinuous operation). This mode, like forced For three or more phases, tie the inputs of the unused dif- continuous operation, exhibits low output ripple as well as ferential amplifier(s) to ground. Examples of single output low audio noise and reduced RF interference as compared multiphase converters are shown in Figures 20 to 23. to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. 3855f 

LTC3855 operaTion Sensing the Output Voltage with a Differential Where: Amplifier V is the maximum adjusted current sense SENSEMAX(ADJ) The LTC3855 includes a low offset, unity gain, high band- threshold. width differential amplifier for applications that require true V is the maximum current sense threshold SENSE(MAX) remote sensing. Sensing the load across the load capaci- specified in the electrical characteristics table. It is typi- tors directly greatly benefits regulation in high current, low cally 75mV, 50mV, or 30mV depending on the setting voltage applications, where board interconnection losses I pins. LIM can be a significant portion of the total error budget. V is the voltage of ITEMP pin. ITEMP The LTC3855 differential amplifier has a typical output slew rate of 2V/μs. The amplifier is configured for unity gain, The valid voltage range for DCR temperature compensa- meaning that the difference between DIFFP and DIFFN is tion on the ITEMP pin is between 0.5V to 0.2V, with 0.5V translated to DIFFOUT, relative to SGND. or above being no DCR temperature correction and 0.2V the maximum correction. However, if the duty cycle of the Care should be taken to route the DIFFP and DIFFN PCB controller is less than 25%, the ITEMP range is extended traces parallel to each other all the way to the terminals from 0.5V to 0V. of the output capacitor or remote sensing points on the board. In addition, avoid routing these sensitive traces An NTC resistor has a negative temperature coefficient, near any high speed switching nodes in the circuit. Ideally, that means that its value decreases as temperature rises. the DIFFP and DIFFN traces should be shielded by a low The VITEMP voltage, therefore, decreases as temperature impedance ground plane to maintain signal integrity. increases and in turn the VSENSEMAX(ADJ) will increase to compensate the DCR temperature coefficient. The NTC Inductor DCR Sensing Temperature Compensation and resistor, however, is non-linear and user can linearize its the ITEMP Pins value by building a resistor network with regular resis- tors. Consult the NTC manufacture datasheets for detailed Inductor DCR current sensing provides a lossless method information. of sensing the instantaneous current. Therefore, it can provide higher efficiency for applications of high output Another use for the ITEMP pins, in addition to NTC com- currents. However the DCR of a copper inductor typically pensated DCR sensing, is adjusting V to values SENSE(MAX) has a positive temperature coefficient. As the temperature between the nominal values of 30mV, 50mV and 75mV for of the inductor rises, its DCR value increases. The current a more precise current limit. This is done by applying a limit of the controller is therefore reduced. voltage less than 0.5V to the ITEMP pin. V will SENSE(MAX) be varied per the above equation and the same duty cycle LTC3855 offers a method to counter this inaccuracy by limitations will apply. The current limit can be adjusted using allowing the user to place an NTC temperature sensing this method either with a sense resistor or DCR sensing. resistor near the inductor. ITEMP pin, when left floating, is at a voltage around 5V and DCR temperature compensa- For more information see the NTC Compensated DCR Sens- tion is disabled. ITEMP pin has a constant 10µA precision ing paragraph in the Applications Information section. current flowing out the pin. By connecting an NTC resistor from ITEMP pin to SGND, the maximum current sense Frequency Selection and Phase-Locked Loop threshold can be varied over temperature according the (FREQ and MODE/PLLIN Pins) following equation: The selection of switching frequency is a trade-off between 1.8–V efficiency and component size. Low frequency opera- V =V • ITEMP SENSEMAX(ADJ) SENSE(MAX) tion increases efficiency by reducing MOSFET switching 1.3 losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching 3855f 

LTC3855 operaTion frequency of the LTC3855’s controllers can be selected Power Good (PGOOD Pins) using the FREQ pin. If the MODE/PLLIN pin is not being When V pin voltage is not within ±10% of the 0.6V refer- driven by an external clock source, the FREQ pin can be FB ence voltage, the PGOOD pin is pulled low. The PGOOD used to program the controller’s operating frequency from pin is also pulled low when the RUN pin is below 1.2V or 250kHz to 770kHz. when the LTC3855 is in the soft-start or tracking phase. There is a precision 10µA current flowing out of the FREQ The PGOOD pin will flag power good immediately when pin, so the user can program the controller’s switching the V pin is within the ±10% of the reference window. FB frequency with a single resistor to SGND. A curve is However, there is an internal 20µs power bad mask when provided later in the application section showing the V goes out the ±10% window. Each channel has its own FB relationship between the voltage on the FREQ pin and PGOOD and only responds to its own channel signals. switching frequency. The PGOOD pins are allowed to be pulled up by external resistors to sources of up to 6V. A phase-locked loop (PLL) is integrated on the LTC3855 to synchronize the internal oscillator to an external clock Output Overvoltage Protection source that is connected to the MODE/PLLIN pin. The controller is operating in forced continuous mode when An overvoltage comparator, OV, guards against transient it is synchronized. overshoots (>10%) as well as other more serious condi- tions that may overvoltage the output. In such cases, the The PLL loop filter network is integrated inside the LTC3855. top MOSFET is turned off and the bottom MOSFET is turned The phase-locked loop is capable of locking any frequency on until the overvoltage condition is cleared. within the range of 250kHz to 770kHz. The frequency setting resistor should always be present to set the controller’s initial switching frequency before locking to the external clock. applicaTions inForMaTion The Typical Application on the first page is a basic LTC3855 for the maximum current sense threshold will be 30mV, application circuit. LTC3855 can be configured to use either 50mV or 75mV, respectively. The maximum current sense DCR (inductor resistance) sensing or low value resistor threshold will be adjusted to values between these settings sensing. The choice between the two current sensing by applying a voltage less than 0.5V to the ITEMP pin. See schemes is largely a design trade-off between cost, power the Operation section for more details. consumption, and accuracy. DCR sensing is becoming Which setting should be used? For the best current limit popular because it saves expensive current sensing resis- accuracy, use the 75mV setting. The 30mV setting will tors and is more power efficient, especially in high current allow for the use of very low DCR inductors or sense applications. However, current sensing resistors provide resistors, but at the expense of current limit accuracy. the most accurate current limits for the controller. Other The 50mV setting is a good balance between the two. For external component selection is driven by the load require- single output dual phase applications, use the 50mV or ment, and begins with the selection of R (if R is SENSE SENSE 75mV setting for optimal current sharing. used) and inductor value. Next, the power MOSFETs are se- lected. Finally, input and output capacitors are selected. SENSE+ and SENSE– Pins Current Limit Programming The SENSE+ and SENSE– pins are the inputs to the current comparators. The common mode input voltage range of The I pin is a tri-level logic input which sets the maxi- LIM the current comparators is 0V to 12.5V. Both SENSE pins mum current limit of the controller. When I is either LIM are high impedance inputs with small base currents of grounded, floated or tied to INTV , the typical value CC 3855f 

LTC3855 applicaTions inForMaTion less than 1µA. When the SENSE pins ramp up from 0V to Because of possible PCB noise in the current sensing loop, 1.4V, the small base currents flow out of the SENSE pins. the AC current sensing ripple of ∆V = ∆I • R also SENSE L SENSE When the SENSE pins ramp down from 12.5V to 1.1V, needs to be checked in the design to get a good signal-to- the small base currents flow into the SENSE pins. The noise ratio. In general, for a reasonably good PCB layout, a high impedance inputs to the current comparators allow 10mV ∆V voltage is recommended as a conservative SENSE accurate DCR sensing. However, care must be taken not number to start with, either for R or DCR sensing SENSE to float these pins during normal operation. applications, for duty cycles less than 40%. Filter components mutual to the sense lines should be For previous generation current mode controllers, the placed close to the LTC3855, and the sense lines should maximum sense voltage was high enough (e.g., 75mV for run close together to a Kelvin connection underneath the the LTC1628 / LTC3728 family) that the voltage drop across current sense element (shown in Figure 1). Sensing cur- the parasitic inductance of the sense resistor represented rent elsewhere can effectively add parasitic inductance a relatively small error. For today’s highest current density and capacitance to the current sense element, degrading solutions, however, the value of the sense resistor can the information at the sense terminals and making the be less than 1mΩ and the peak sense voltage can be as programmed current limit unpredictable. If DCR sensing low as 20mV. In addition, inductor ripple currents greater is used (Figure 2b), sense resistor R1 should be placed than 50% with operation up to 1MHz are becoming more close to the switching node, to prevent noise from coupling common. Under these conditions the voltage drop across into sensitive small-signal nodes. The capacitor C1 should the sense resistor’s parasitic inductance is no longer neg- be placed close to the IC pins. ligible. A typical sensing circuit using a discrete resistor is shown in Figure 2a. In previous generations of controllers, a small RC filter placed near the IC was commonly used to TO SENSE FILTER, NEXT TO THE CONTROLLER reduce the effects of capacitive and inductive noise coupled inthe sense traces on the PCB. A typical filter consists of COUT two series 10Ω resistors connected to a parallel 1000pF RSENSE 3855F01 capacitor, resulting in a time constant of 20ns. Figure 1. Sense Lines Placement with Sense Resistor This same RC filter, with minor modifications, can be used to extract the resistive component of the current sense Low Value Resistors Current Sensing signal in the presence of parasitic inductance. For example, A typical sensing circuit using a discrete resistor is shown Figure 3 illustrates the voltage waveform across a 2mΩ in Figure 2a. RSENSE is chosen based on the required sense resistor with a 2010 footprint for the 1.2V/15A output current. converter operating at 100% load. The waveform is the superposition of a purely resistive component and a The current comparator has a maximum threshold purely inductive component. It was measured using two V determined by the I setting. The input SENSE(MAX) LIM scope probes and waveform math to obtain a differential common mode range of the current comparator is 0V to measurement. Based on additional measurements of the 12.5V. The current comparator threshold sets the peak of inductor ripple current and the on-time and off-time of the inductor current, yielding a maximum average output the top switch, the value of the parasitic inductance was current I equal to the peak value less half the peak-to- MAX determined to be 0.5nH using the equation: peak ripple current, ∆I . To calculate the sense resistor L value, use the equation: V t •t ESL= ESL(STEP) ON OFF V ∆I t +t SENSE(MAX) L ON OFF R = SENSE ∆I I + L If the RC time constant is chosen to be close to the (MAX) 2 parasitic inductance divided by the sense resistor (L/R), 3855f 

LTC3855 applicaTions inForMaTion VIN VIN VIN VIN INTVCC INTVCC SENSE RESISTOR BOOST BOOST PLUS PARASITIC TG INDUCTOR TG INDUCTANCE OPTIONAL TEMP COMP SW L DCR VOUT LTC3855 SW RS ESL VOUT NETWORK LTC3855 ITEMP BG PGNBGD RF CCF A•PN O2CRLEFEL -≤LZ AEESRTILOO/RNS RS SEPNGSNED+ R1** SSEENNSSEE+– CF RNTC RP SENSE– C1* R2 SGND RF SGND 3855F02a PLFAICLETDER N CEAORM PSOENNSEEN TPSINS * * PINLDAUCCET RO1R NEXT TO * SPELNACSEE –C P1I NNESAR SENSE+, R1||R2× C1 = DCLR RSENSE(EQ) = DCR R1R +2 R2 3855F02b (2a) Using a Resistor to Sense Current (2b) Using the Inductor DCR to Sense Current Figure 2. Two Different Methods of Sensing Current the resulting waveform looks resistive again, as shown The above generally applies to high density/high current in Figure 4. For applications using low maximum sense applications where I >10A and low values of induc- (MAX) voltages, check the sense resistor manufacturer’s data tors are used. For applications where I <10A, set R (MAX) F sheet for information about parasitic inductance. In the to 10 Ohms and C to 1000pF. This will provide a good F absence of data, measure the voltage drop directly across starting point. the sense resistor to extract the magnitude of the ESL The filter components need to be placed close to the IC. step and use the equation above to determine the ESL. The positive and negative sense traces need to be routed However, do not over-filter. Keep the RC time constant less as a differential pair and Kelvin connected to the sense than or equal to the inductor time constant to maintain a resistor. high enough ripple voltage on V . RSENSE Inductor DCR Sensing For applications requiring the highest possible efficiency at high load currents, the LTC3855 is capable of sensing the voltage drop across the inductor DCR, as shown in Figure VESL(STEP) 2b. The DCR of the inductor represents the small amount VSENSE 20mV/DIV of DC winding resistance of the copper, which can be less than 1mΩ for today’s low value, high current inductors. 500ns/DIV 3855F03 In a high current application requiring such an inductor, Figure 3. Voltage Waveform Measured conduction loss through a sense resistor would cost sev- Directly Across the Sense Resistor. eral points of efficiency compared to DCR sensing. If the external R1||R2 • C1 time constant is chosen to be exactly equal to the L/DCR time constant, the voltage drop across the external capacitor is equal to the drop across the inductor DCR multiplied by R2/(R1 + R2). R2 scales the voltage across the sense terminals for applications where VSENSE 20mV/DIV the DCR is greater than the target sense resistor value. To properly dimension the external filter components, the 500ns/DIV 3855F04 DCR of the inductor must be known. It can be measured Figure 4. Voltage Waveform Measured After the using a good RLC meter, but the DCR tolerance is not Sense Resistor Filter. C = 1000pF, R = 100Ω. F F 3855f 

LTC3855 applicaTions inForMaTion always the same and varies with temperature; consult the ( ) V −V •V manufacturers’ datasheets for detailed information. IN(MAX) OUT OUT P R1= LOSS R1 Using the inductor ripple current value from the Inductor Value Calculation section, the target sense resistor value is: Ensure that R1 has a power rating higher than this value. If high efficiency is necessary at light loads, consider this V SENSE(MAX) R = power loss when deciding whether to use DCR sensing or SENSE(EQUIV) ∆I I + L sense resistors. Light load power loss can be modestly (MAX) 2 higher with a DCR network than with a sense resistor, due to the extra switching losses incurred through R1. However, To ensure that the application will deliver full load current DCR sensing eliminates a sense resistor, reduces conduc- over the full operating temperature range, choose the tion losses and provides higher efficiency at heavy loads. minimum value for the Maximum Current Sense Threshold Peak efficiency is about the same with either method. (V ) in the Electrical Characteristics table (25mV, SENSE(MAX) 45mV, or 68mV, depending on the state of the ILIM pin). To maintain a good signal to noise ratio for the current sense signal, use a minimum ∆V of 10mV for duty Next, determine the DCR of the inductor. Where provided, SENSE cycles less than 40%. For a DCR sensing application, the use the manufacturer’s maximum value, usually given at actual ripple voltage will be determined by the equation: 20°C. Increase this value to account for the temperature coefficient of resistance, which is approximately 0.4%/°C V −V V ∆V = IN OUT OUT or use LTC3855 DCR temperature compensation function. SENSE R1•C1 V •f A conservative value for T is 100°C. IN OSC L(MAX) To scale the maximum inductor DCR to the desired sense NTC Compensated DCR Sensing resistor value, use the divider ratio: For DCR sensing applications where a more accurate R current limit is required, a network consisting of an NTC SENSE(EQUIV) R = D DCR atT thermistor placed from the ITEMP pin to ground will (MAX) L(MAX) provide correction of the current limit over temperature. C1 is usually selected to be in the range of 0.047µF to Figure 2b shows this network. Resistors RS and RP will 0.47µF. This forces R1||R2 to around 2kΩ, reducing error linearize the impedance the ITEMP pin sees. To implement NTC compensated DCR sensing, design the DCR sense that might have been caused by the SENSE pins’ ±1µA filter network per the same procedure mentioned in the current. T is the maximum inductor temperature. L(MAX) previous selection, except calculate the divider components The equivalent resistance R1||R2 is scaled to the room using the room temperature value of the DCR. For a single temperature inductance and maximum DCR: output rail operating from one phase: L 1. Set the ITEMP pin resistance to 50k at 25°C. With R1||R2= (DCR at 20°C)•C1 10µA flowing out of the ITEMP pin, the voltage on the ITEMP pin will be 0.5V at room temperature. Current The sense resistor values are: limit correction will occur for inductor temperatures greater than 25°C. R1||R2 R1•R R1= ; R2= D R 1−R 2. Calculate the ITEMP pin resistance and the maximum D D inductor temperature which is typically 100°C. Use the The maximum power loss in R1 is related to duty cycle, following equations: and will occur in continuous mode at the maximum input voltage: 3855f 

LTC3855 applicaTions inForMaTion After determining the components for the temperature V RITEMP100C= ITEMP100C compensation network, check the results by plotting 10µA I versus inductor temperature using the following MAX equations: V =0.5V−1.3• ITEMP100C IMAX•DCR(MAX)•R2 (1100°C−25°C)•0.4 IMAX = • R1+R2 100 V −∆V SENSEMAX(ADJ) SENSE V SENSE(MAX) 2  ( ) 0.4 Calculate the values for RP and RS. A simple method is to DCR(MAX)at25°CC•1+ TL(MAX)−25°C •100 graph the following R versus R equations with R on S P S the y-axis and R on the x-axis. P where R = R – R ||R S ITEMP25C NTC25C P 1.8V−V V =V • ITEMP −A R = R – R ||R SENSEMAX(ADJ) SENSE(MAX) 1.3 S ITEMP100C NTC100C P Next, find the value of R that satisfies both equations P V = 10µA • (R + R ||R ) ITEMP S P NTC which will be the point where the curves intersect. Once Use typical values for V . Subtracting constant R is known, solve for R . SENSE(MAX) P S A will provide a minimum value for V . These SENSE(MAX) The resistance of the NTC thermistor can be obtained values are summarized in Table 2. from the vendor’s data sheet either in the form of graphs, tabulated data, or formulas. The approximate value for the Table 2. NTC thermistor for a given temperature can be calculated I GND FLOAT INTV LIM CC from the following equation: V TYP 30mV 50mV 75mV SENSE(MAX) A 5mV 5mV 7mV   1 1  R=R •exp B• − O  T+273 TO+273 The resulting current limit should be greater than or equal to I for inductor temperatures between 25°C MAX where and 100°C. R = Resistance at temperature T, which is in degrees C Typical values for the NTC compensation network are: R = Resistance at temperature T , typically 25°C • NTC R = 100k, B-constant = 3000 to 4000 O O O B = B-constant of the thermistor • R ≈ 20k S Figure 5 shows a typical resistance curve for a 100k therm- • R ≈ 50k P istor and the ITEMP pin network over temperature. Generating the I versus inductor temperature curve plot MAX Starting values for the NTC compensation network are: first using the above values as a starting point and then adjusting the R and R values as necessary is another • NTC R = 100k S P O approach. Figure 6 shows a typical curve of I versus MAX • RS = 20k inductor temperature. For PolyPhase applications, tie the ITEMP pins together and calculate for an ITEMP pin cur- • R = 50k P rent of 10µA • #phases. But, the final values should be calculated using the above The same thermistor network can be used to correct for equations and checked at 25°C and 100°C. temperatures less than 25°C. But make sure V is ITEMP 3855f 

LTC3855 applicaTions inForMaTion 10000 25 THERMISTOR RESISTANCE RO = 100k, TO = 25°C 20 1000 B = 4334 for 25°C/100°C Ω) CORRECTED IMAX SISTANCE (k 100 RITMP I (A)MAX1150 NOMINAL IMAX UNCORRECTED IMAX RE 10 RRSP == 2403k.2ΩkΩ RNRTSP C== T24H03Ek.2RΩkMΩISTOR: 100k NTC 5 RO = 100k TO = 25°C B = 4334 1 0 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 INDUCTOR TEMPERATURE (°C) INDUCTOR TEMPERATURE (°C) 3855F05 3855F06 Figure 5. Resistance Versus Temperature for Figure 6. Worst Case I Versus Inductor Temperature MAX ITEMP Pin Network and the 100k NTC Curve with and without NTC Temperature Compensation greater than 0.2V for duty cycles of 25% or more, oth- maximum inductor peak current to remain unaffected erwise temperature correction may not occur at elevated throughout all duty cycles. ambients. For the most accurate temperature detection, place the thermistors next to the inductors as shown in Inductor Value Calculation Figure 7. Take care to keep the ITEMP pins away from the Given the desired input and output voltages, the inductor switch nodes. value and operating frequency f directly determine the OSC inductor’s peak-to-peak ripple current: Slope Compensation and Inductor Peak Current V  V –V  Slope compensation provides stability in constant- I = OUT IN OUT RIPPLE   frequency architectures by preventing subharmonic oscil- V  f •L  IN OSC lations at high duty cycles. It is accomplished internally by Lower ripple current reduces core losses in the inductor, adding a compensating ramp to the inductor current signal ESR losses in the output capacitors, and output voltage at duty cycles in excess of 40%. Normally, this results in ripple. Thus, highest efficiency operation is obtained at a reduction of maximum inductor peak current for duty low frequency with a small ripple current. Achieving this, cycles >40%. However, the LTC3855 uses a scheme that however, requires a large inductor. counteracts this compensating ramp, which allows the CONNECT TO CONNECT TO ITEMP1 ITEMP2 NETWORK VOUT1 VOUT2 NETWORK VOUT RNTC1 RNTC2 L1 L2 L1 RNTC L2 GND GND SW1 SW2 SW1 SW2 3855F07a 3855F07b (7a) Dual Output Dual Phase DCR Sensing Application (7b) Single Output Dual Phase DCR Sensing Application Figure 7. Thermistor Locations. Place Thermistor Next to Inductor(s) for Accurate Sensing of the Inductor Temperature, but Keep the ITEMP Pins Away from the Switch Nodes and Gate Drive Traces 3855f 0

LTC3855 applicaTions inForMaTion A reasonable starting point is to choose a ripple current core material saturates “hard,” which means that induc- that is about 40% of I for a duty cycle less than tance collapses abruptly when the peak design current is OUT(MAX) 40%. Note that the largest ripple current occurs at the exceeded. This results in an abrupt increase in inductor highest input voltage. To guarantee that ripple current does ripple current and consequent output voltage ripple. Do not exceed a specified maximum, the inductor should be not allow the core to saturate! chosen according to: Power MOSFET and Schottky Diode V –V V L≥ IN OUT • OUT (Optional) Selection f •I V OSC RIPPLE IN Two external power MOSFETs must be selected for each controller in the LTC3855: one N-channel MOSFET for the For duty cycles greater than 40%, the 10mV current top (main) switch, and one N-channel MOSFET for the sense ripple voltage requirement is relaxed because the bottom (synchronous) switch. slope compensation signal aids the signal-to-noise ratio and because a lower limit is placed on the inductor value The peak-to-peak drive levels are set by the INTV CC to avoid subharmonic oscillations. To ensure stability for voltage. This voltage is typically 5V during start-up duty cycles up to the maximum of 95%, use the following (see EXTV Pin Connection). Consequently, logic-level CC equation to find the minimum inductance. threshold MOSFETs must be used in most applications. The only exception is if low input voltage is expected (V V IN L > OUT •1.4 < 5V); then, sub-logic level threshold MOSFETs (V MIN f •I GS(TH) SW LOAD(MAX) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic where level MOSFETs are limited to 30V or less. L is in units of µH MIN Selection criteria for the power MOSFETs include the f is in units of MHz on-resistance R , Miller capacitance C , input SW DS(ON) MILLER voltage and maximum output current. Miller capacitance, Inductor Core Selection C , can be approximated from the gate charge curve MILLER usually provided on the MOSFET manufacturers’ data Once the inductance value is determined, the type of in- sheet. C is equal to the increase in gate charge ductor must be selected. Core loss is independent of core MILLER along the horizontal axis while the curve is approximately size for a fixed inductor value, but it is very dependent flat divided by the specified change in V . This result is on inductance selected. As inductance increases, core DS then multiplied by the ratio of the application applied V losses go down. Unfortunately, increased inductance DS to the gate charge curve specified V . When the IC is requires more turns of wire and therefore copper losses DS operating in continuous mode the duty cycles for the top will increase. and bottom MOSFETs are given by: Ferrite designs have very low core loss and are preferred V at high switching frequencies, so design goals can con- MainSwitchDutyCycle= OUT centrate on copper loss and preventing saturation. Ferrite V IN V –V SynchronousSwitchDutyCycle= IN OUT V IN 3855f 

LTC3855 applicaTions inForMaTion The MOSFET power dissipations at maximum output the relatively small average current. Larger diodes result current are given by: in additional transition losses due to their larger junction capacitance. A Schottky diode in parallel with the bottom P =VOUT (I )2(1+d)R + FET may also provide a modest improvement in Burst MAIN MAX DS(ON) V IN Mode efficiency. (VIN)2IMAX(RDR)(CMILLER)• Soft-Start and Tracking  22  The LTC3855 has the ability to either soft-start by itself   1 1  + •f with a capacitor or track the output of another channel or OSC VINTVCC–VTH(MIN) VTTH(MIN) external supply. When one particular channel is configured to soft-start by itself, a capacitor should be connected to its TK/SS pin. This channel is in the shutdown state if its P =VIN–VOUT (I ))2(1+d)R RUN pin voltage is below 1.2V. Its TK/SS pin is actively SYNC MAX DS(ON) V pulled to ground in this shutdown state. IN Once the RUN pin voltage is above 1.2V, the channel pow- where d is the temperature dependency of R and DS(ON) ers up. A soft-start current of 1.2µA then starts to charge R (approximately 2Ω) is the effective driver resistance DR its soft-start capacitor. Note that soft-start or tracking is at the MOSFET’s Miller threshold voltage. V is the TH(MIN) achieved not by limiting the maximum output current of typical MOSFET minimum threshold voltage. the controller but by controlling the output ramp voltage Both MOSFETs have I2R losses while the topside N-channel according to the ramp rate on the TK/SS pin. Current equation includes an additional term for transition losses, foldback is disabled during this phase to ensure smooth which are highest at high input voltages. For V < 20V IN soft-start or tracking. The soft-start or tracking range is the high current efficiency generally improves with larger defined to be the voltage range from 0V to 0.6V on the MOSFETs, while for V > 20V the transition losses rapidly IN TK/SS pin. The total soft-start time can be calculated as: increase to the point that the use of a higher R device DS(ON) C with lower CMILLER actually provides higher efficiency. The t =0.6• SS SOFTSTART synchronous MOSFET losses are greatest at high input 1.2µA voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close Regardless of the mode selected by the MODE/PLLIN pin, to 100% of the period. the regulator will always start in pulse-skipping mode up to TK/SS = 0.5V. Between TK/SS = 0.5V and 0.54V, it The term (1 + d) is generally given for a MOSFET in the will operate in forced continuous mode and revert to the form of a normalized R vs Temperature curve, but DS(ON) selected mode once TK/SS > 0.54V. The output ripple d = 0.005/°C can be used as an approximation for low is minimized during the 40mV forced continuous mode voltage MOSFETs. window ensuring a clean PGOOD signal. The optional Schottky diodes conduct during the dead time When the channel is configured to track another supply, between the conduction of the two power MOSFETs. These the feedback voltage of the other supply is duplicated by prevent the body diodes of the bottom MOSFETs from turn- a resistor divider and applied to the TK/SS pin. Therefore, ing on, storing charge during the dead time and requiring the voltage ramp rate on this pin is determined by the a reverse recovery period that could cost as much as 3% ramp rate of the other supply’s voltage. Note that the small in efficiency at high V . A 1A to 3A Schottky is generally IN soft-start capacitor charging current is always flowing, a good compromise for both regions of operation due to 3855f 

LTC3855 applicaTions inForMaTion producing a small offset error. To minimize this error, select To implement the coincident tracking in Figure 8a, con- the tracking resistive divider value to be small enough to nect an additional resistive divider to V and connect OUT1 make this error negligible. its midpoint to the TK/SS pin of the slave channel. The ratio of this divider should be the same as that of the slave In order to track down another channel or supply after channel’s feedback divider shown in Figure 9a. In this the soft-start phase expires, the LTC3855 is forced into tracking mode, V must be set higher than V . To continuous mode of operation as soon as V is below the OUT1 OUT2 FB implement the ratiometric tracking in Figure 9b, the ratio of undervoltage threshold of 0.54V regardless of the setting the V divider should be exactly the same as the master on the MODE/PLLIN pin. However, the LTC3855 should OUT2 channel’s feedback divider shown in Figure 9b. By select- always be set in force continuous mode tracking down ing different resistors, the LTC3855 can achieve different when there is no load. After TK/SS drops below 0.1V, its modes of tracking including the two in Figure 8. channel will operate in discontinuous mode. So which mode should be programmed? While either Output Voltage Tracking mode in Figure 8 satisfies most practical applications, The LTC3855 allows the user to program how its output some tradeoffs exist. The ratiometric mode saves a pair of resistors, but the coincident mode offers better output ramps up and down by means of the TK/SS pins. Through regulation. these pins, the output can be set up to either coincidentally or ratiometrically track another supply’s output, as shown When the master channel’s output experiences dynamic in Figure 8. In the following discussions, VOUT1 refers to excursion (under load transient, for example), the slave the LTC3855’s output 1 as a master channel and VOUT2 channel output will be affected as well. For better output refers to the LTC3855’s output 2 as a slave channel. In regulation, use the coincident tracking mode instead of practice, though, either phase can be used as the master. ratiometric. VOUT1 VOUT1 E E G G A A T T L L O O V V T T U U TP VOUT2 TP VOUT2 U U O O TIME 3855F08a TIME 3855F08b (8a) Coincident Tracking (8b) Ratiometric Tracking Figure 8. Two Different Modes of Output Voltage Tracking VOUT1 VOUT2 VOUT1 VOUT2 R3 R1 R3 R1 R3 TO TO TO TO TO TK/SS2 VFB1 VFB2 TK/SS2 TO VFB2 PIN PIN PIN PIN VFB1 PIN R4 R2 R4 PIN R4 R2 3855F09 (9a) Coincident Tracking Setup (9b) Ratiometric Tracking Setup Figure 9. Setup for Coincident and Ratiometric Tracking 3855f 

LTC3855 applicaTions inForMaTion INTV Regulators and EXTV from the INTV when the output is out of regulation CC CC CC (e.g., start-up, short-circuit). If more current is required The LTC3855 features a true PMOS LDO that supplies through the EXTV than is specified, an external Schottky power to INTV from the V supply. INTV powers the CC CC IN CC diode can be added between the EXTV and INTV pins. gate drivers and much of the LTC3855’s internal circuitry. CC CC Do not apply more than 6V to the EXTV pin and make The linear regulator regulates the voltage at the INTV pin CC CC sure that EXTV < V . to 5V when V is greater than 5.5V. EXTV connects to CC IN IN CC INTV through a P-channel MOSFET and can supply the Significant efficiency and thermal gains can be realized by CC needed power when its voltage is higher than 4.7V. Each powering INTV from the output, since the V current CC IN of these can supply a peak current of 100mA and must resulting from the driver and control currents will be scaled be bypassed to ground with a minimum of 4.7µF ceramic by a factor of (Duty Cycle)/(Switcher Efficiency). capacitor or low ESR electrolytic capacitor. No matter Tying the EXTV pin to a 5V supply reduces the junction what type of bulk capacitor is used, an additional 0.1µF CC temperature in the previous example from 125°C to: ceramic capacitor placed directly adjacent to the INTV CC and PGND pins is highly recommended. Good bypassing T = 70°C + (44mA)(5V)(33°C/W) = 77°C J is needed to supply the high transient currents required However, for 3.3V and other low voltage outputs, addi- by the MOSFET gate drivers and to prevent interaction tional circuitry is required to derive INTV power from CC between the channels. the output. High input voltage applications in which large MOSFETs The following list summarizes the four possible connec- are being driven at high frequencies may cause the maxi- tions for EXTV : CC mum junction temperature rating for the LTC3855 to be exceeded. The INTV current, which is dominated by the 1. EXTV left open (or grounded). This will cause CC CC gate charge current, may be supplied by either the 5V linear INTV to be powered from the internal 5V regulator CC regulator or EXTV . When the voltage on the EXTV pin resulting in an efficiency penalty of up to 10% at high CC CC is less than 4.7V, the linear regulator is enabled. Power input voltages. dissipation for the IC in this case is highest and is equal 2. EXTV connected directly to V . This is the CC OUT to V • I . The gate charge current is dependent IN INTVCC normal connection for a 5V regulator and provides on operating frequency as discussed in the Efficiency the highest efficiency. Considerations section. The junction temperature can be estimated by using the equations given in Note 3 of the 3. EXTVCC connected to an external supply. If a 5V Electrical Characteristics. For example, the LTC3855 INTV external supply is available, it may be used to power CC current is limited to less than 44mA from a 38V supply in EXTVCC providing it is compatible with the MOSFET the UJ package and not using the EXTV supply: gate drive requirements. CC TJ = 70°C + (44mA)(38V)(33°C/W) = 125°C 4. EXTVCC connected to an output-derived boost net- work. For 3.3V and other low voltage regulators, To prevent the maximum junction temperature from being efficiency gains can still be realized by connecting exceeded, the input supply current must be checked while EXTV to an output-derived voltage that has been operating in continuous conduction mode (MODE/PLLIN = CC boosted to greater than 4.7V. SGND) at maximum V . When the voltage applied to EXT- IN V rises above 4.7V, the INTV linear regulator is turned For applications where the main input power is below 5V, CC CC off and the EXTV is connected to the INTV . The EXTV tie the V and INTV pins together and tie the combined CC CC CC IN CC remains on as long as the voltage applied to EXTV remains pins to the 5V input with a 1Ω or 2.2Ω resistor as shown CC above 4.5V. Using the EXTV allows the MOSFET driver in Figure 10 to minimize the voltage drop caused by the CC and control power to be derived from one of the LTC3855’s gate charge current. This will override the INTV linear CC switching regulator outputs during normal operation and regulator and will prevent INTV from dropping too low CC 3855f 

LTC3855 applicaTions inForMaTion due to the dropout voltage. Make sure the INTV voltage Another way to detect an undervoltage condition is to CC is at or exceeds the R test voltage for the MOSFET monitor the V supply. Because the RUN pins have a DS(ON) IN which is typically 4.5V for logic level devices. precision turn-on reference of 1.2V, one can use a resistor divider to V to turn on the IC when V is high enough. IN IN An extra 4.5µA of current flows out of the RUN pin once the RUN pin voltage passes 1.2V. One can program the LTC3855 VIN RVIN hysteresis of the run comparator by adjusting the values INTVCC 5V of the resistive divider. For accurate V undervoltage CINTVCC 1Ω + IN detection, V needs to be higher than 4.5V. 4.7µF CIN IN C and C Selection 3855F07 IN OUT Figure 10. Setup for a 5V Input The selection of C is simplified by the 2-phase architec- IN ture and its impact on the worst-case RMS current drawn Topside MOSFET Driver Supply (C , DB) B through the input network (battery/fuse/capacitor). It can be External bootstrap capacitors C connected to the BOOST shown that the worst-case capacitor RMS current occurs B pins supply the gate drive voltages for the topside MOSFETs. when only one controller is operating. The controller with Capacitor CB in the Functional Diagram is charged though the highest (VOUT)(IOUT) product needs to be used in the external diode DB from INTV when the SW pin is low. formula below to determine the maximum RMS capacitor CC When one of the topside MOSFETs is to be turned on, current requirement. Increasing the output current drawn the driver places the C voltage across the gate source from the other controller will actually decrease the input B of the desired MOSFET. This enhances the MOSFET and RMS ripple current from its maximum value. The out-of- turns on the topside switch. The switch node voltage, SW, phase technique typically reduces the input capacitor’s RMS rises to V and the BOOST pin follows. With the topside ripple current by a factor of 30% to 70% when compared IN MOSFET on, the boost voltage is above the input supply: to a single phase power supply solution. V = V + V . The value of the boost capacitor BOOST IN INTVCC In continuous mode, the source current of the top MOSFET C needs to be 100 times that of the total input capa- B is a square wave of duty cycle (V )/(V ). To prevent OUT IN citance of the topside MOSFET(s). The reverse break- large voltage transients, a low ESR capacitor sized for the down of the external Schottky diode must be greater maximum RMS current of one channel must be used. The than V . When adjusting the gate drive level, the IN(MAX) maximum RMS capacitor current is given by: final arbiter is the total input current for the regulator. If a change is made and the input current decreases, then C RequiredI ≈IMAX (V )(V –V )1/2 IN RMS  OUT IN OUT  the efficiency has improved. If there is no change in input V IN current, then there is no change in efficiency. This formula has a maximum at V = 2V , where I = IN OUT RMS Undervoltage Lockout I /2. This simple worst-case condition is commonly used OUT for design because even significant deviations do not of- The LTC3855 has two functions that help protect the fer much relief. Note that capacitor manufacturers’ ripple controller in case of undervoltage conditions. A precision current ratings are often based on only 2000 hours of life. UVLO comparator constantly monitors the INTV voltage CC This makes it advisable to further derate the capacitor, or to ensure that an adequate gate-drive voltage is present. It to choose a capacitor rated at a higher temperature than locks out the switching action when INTV is below 3.2V. CC required. Several capacitors may be paralleled to meet To prevent oscillation when there is a disturbance on the size or height requirements in the design. Due to the high INTV , the UVLO comparator has 600mV of precision CC operating frequency of the LTC3855, ceramic capacitors hysteresis. 3855f 

LTC3855 applicaTions inForMaTion can also be used for C . Always consult the manufacturer output, as shown in Figure 11. The regulated output IN if there is any question. voltage is determined by: The benefit of the LTC3855 2-phase operation can be cal-  R  V =0.6V• 1+ B culated by using the equation above for the higher power OUT    R  controller and then calculating the loss that would have A resulted if both controller channels switched on at the same To improve the frequency response, a feed-forward ca- time. The total RMS power lost is lower when both control- pacitor, C , may be used. Great care should be taken to FF lers are operating due to the reduced overlap of current route the V line away from noise sources, such as the FB pulses required through the input capacitor’s ESR. This is inductor or the SW line. why the input capacitor’s requirement calculated above for the worst-case controller is adequate for the dual controller VOUT design. Also, the input protection fuse resistance, battery resistance, and PC board trace resistance losses are also 1/2 LTC3855 RB CFF reduced due to the reduced peak currents in a 2-phase VFB system. The overall benefit of a multiphase design will RA only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. 3855 F11 The sources of the top MOSFETs should be placed within Figure 11. Setting Output Voltage 1cm of each other and share a common C (s). Separating IN Fault Conditions: Current Limit and Current Foldback the sources and C may produce undesirable voltage and IN current resonances at V . The LTC3855 includes current foldback to help limit load IN current when the output is shorted to ground. If the out- A small (0.1µF to 1µF) bypass capacitor between the chip put falls below 50% of its nominal output level, then the V pin and ground, placed close to the LTC3855, is also IN maximum sense voltage is progressively lowered from its suggested. A 2.2Ω to 10Ω resistor placed between C IN maximum programmed value to one-third of the maximum (C1) and the V pin provides further isolation between IN value. Foldback current limiting is disabled during the the two channels. soft-start or tracking up. Under short-circuit conditions The selection of C is driven by the effective series with very low duty cycles, the LTC3855 will begin cycle OUT resistance (ESR). Typically, once the ESR requirement skipping in order to limit the short-circuit current. In this is satisfied, the capacitance is adequate for filtering. The situation the bottom MOSFET will be dissipating most of output ripple (∆V ) is approximated by: the power but less than in normal operation. The short- OUT circuit ripple current is determined by the minimum on-  1  time t of the LTC3855 (≈ 90ns), the input voltage ∆V ≈I ESR+ ON(MIN) OUT RIPPLE 8fC  and inductor value: OUT V where f is the operating frequency, C is the output ∆I =t • IN OUT L(SC) ON(MIN) L capacitance and I is the ripple current in the induc- RIPPLE tor. The output ripple is highest at maximum input voltage The resulting short-circuit current is: since I increases with input voltage. RIPPLE 1/3V 1 SENSE(MAX) I = – ∆I Setting Output Voltage SC R 2 L(SC) SENSE The LTC3855 output voltages are each set by an external feedback resistive divider carefully placed across the 3855f 

LTC3855 applicaTions inForMaTion Phase-Locked Loop and Frequency Synchronization 900 800 The LTC3855 has a phase-locked loop (PLL) comprised of 700 an internal voltage-controlled oscillator (V ) and a phase CO detector. This allows the turn-on of the top MOSFET of Hz)600 k controller 1 to be locked to the rising edge of an external CY (500 N clock signal applied to the MODE/PLLIN pin. The turn-on UE400 Q E of controller 2’s top MOSFET is thus 180 degrees out- FR300 of-phase with the external clock. The phase detector is 200 an edge sensitive digital type that provides zero degrees 100 phase shift between the external and internal oscillators. 0 0 0.5 1 1.5 2 2.5 This type of phase detector does not exhibit false lock to FREQ PIN VOLTAGE (V) 3855F12 harmonics of the external clock. Figure 12. Relationship Between Oscillator Frequency and Voltage at the FREQ Pin The output of the phase detector is a pair of complementary current sources that charge or discharge the internal filter 2.4V 5V network. There is a precision 10µA of current flowing out RSET of FREQ pin. This allows the user to use a single resistor 10µA to SGND to set the switching frequency when no external FREQ clock is applied to the MODE/PLLIN pin. The internal switch MODE/ between FREQ pin and the integrated PLL filter network PLLIN DIGITAL EXTERNAL PHASE/ SYNC is ON, allowing the filter network to be pre-charged to the OSCILLATOR FREQUENCY DETECTOR VCO same voltage potential as the FREQ pin. The relationship between the voltage on the FREQ pin and the operating frequency is shown in Figure 12 and specified in the Elec- trical Characteristic table. If an external clock is detected on the MODE/PLLIN pin, the internal switch mentioned 3855 F13 above will turn off and isolate the influence of FREQ pin. Figure 13. Phase-Locked Loop Block Diagram Note that the LTC3855 can only be synchronized to an external clock whose frequency is within range of the Typically, the external clock (on MODE/PLLIN pin) LTC3855’s internal V . This is guaranteed to be between input high threshold is 1.6V, while the input low threshold CO 250kHz and 770kHz. A simplified block diagram is shown is 1V. It is not recommended to apply the external clock in Figure 13. when IC is in shutdown. If the external clock frequency is greater than the internal Minimum On-Time Considerations oscillator’s frequency, f , then current is sourced continu- OSC Minimum on-time t is the smallest time duration ously from the phase detector output, pulling up the filter ON(MIN) that the LTC3855 is capable of turning on the top MOSFET. network. When the external clock frequency is less than f , OSC It is determined by internal timing delays and the gate current is sunk continuously, pulling down the filter network. If charge required to turn on the top MOSFET. Low duty the external and internal frequencies are the same but exhibit cycle applications may approach this minimum on-time a phase difference, the current sources turn on for an amount limit and care should be taken to ensure that of time corresponding to the phase difference. The voltage on the filter network is adjusted until the phase and frequency of V the internal and external oscillators are identical. At the stable tON(MIN)< OUT V (f) operating point, the phase detector output is high impedance IN and the filter capacitor holds the voltage. 3855f 

LTC3855 applicaTions inForMaTion If the duty cycle falls below what can be accommodated from INTV to ground. The resulting dQ/dt is a cur- CC by the minimum on-time, the controller will begin to skip rent out of INTV that is typically much larger than the CC cycles. The output voltage will continue to be regulated, control circuit current. In continuous mode, I GATECHG but the ripple voltage and current will increase. = f(Q + Q ), where Q and Q are the gate charges of T B T B the topside and bottom side MOSFETs. The minimum on-time for the LTC3855 is approximately 90ns, with reasonably good PCB layout, minimum 30% Supplying INTV power through EXTV from an out- CC CC inductor current ripple and at least 10mV – 15mV ripple put-derived source will scale the V current required IN on the current sense signal. The minimum on-time can be for the driver and control circuits by a factor of (Duty affected by PCB switching noise in the voltage and current Cycle)/(Efficiency). For example, in a 20V to 5V applica- loop. As the peak sense voltage decreases the minimum tion, 10mA of INTV current results in approximately CC on-time gradually increases to 130ns. This is of particular 2.5mA of V current. This reduces the mid-current loss IN concern in forced continuous applications with low ripple from 10% or more (if the driver was powered directly current at light loads. If the duty cycle drops below the from V ) to only a few percent. IN minimum on-time limit in this situation, a significant 3. I2R losses are predicted from the DC resistances of the amount of cycle skipping can occur with correspondingly fuse (if used), MOSFET, inductor, current sense resistor. larger current and voltage ripple. In continuous mode, the average output current flows through L and R , but is “chopped” between the Efficiency Considerations SENSE topside MOSFET and the synchronous MOSFET. If the The percent efficiency of a switching regulator is equal to two MOSFETs have approximately the same R , DS(ON) the output power divided by the input power times 100%. then the resistance of one MOSFET can simply be It is often useful to analyze individual losses to determine summed with the resistances of L and R to ob- SENSE what is limiting the efficiency and which change would tain I2R losses. For example, if each R = 10mΩ, DS(ON) produce the most improvement. Percent efficiency can R = 10mΩ, R = 5mΩ, then the total resistance L SENSE be expressed as: is 25mΩ. This results in losses ranging from 2% to %Efficiency = 100% – (L1 + L2 + L3 + ...) 8% as the output current increases from 3A to 15A for a 5V output, or a 3% to 12% loss for a 3.3V output. where L1, L2, etc. are the individual losses as a percent- Efficiency varies as the inverse square of V for the OUT age of input power. same external components and output power level. The Although all dissipative elements in the circuit produce combined effects of increasingly lower output voltages losses, four main sources usually account for most of the and higher currents required by high performance digital losses in LTC3855 circuits: 1) IC V current, 2) INTV systems is not doubling but quadrupling the importance IN CC regulator current, 3) I2R losses, 4) Topside MOSFET of loss terms in the switching regulator system! transition losses. 4. Transition losses apply only to the topside MOSFET(s), 1. The V current is the DC supply current given in and become significant only when operating at high IN the Electrical Characteristics table, which excludes input voltages (typically 15V or greater). Transition MOSFET driver and control currents. V current typi- losses can be estimated from: IN cally results in a small (<0.1%) loss. Transition Loss = (1.7) V 2 I C f IN O(MAX) RSS 2. INTV current is the sum of the MOSFET driver and CC Other “hidden” losses such as copper trace and internal control currents. The MOSFET driver current results battery resistances can account for an additional 5% to from switching the gate capacitance of the power 10% efficiency degradation in portable systems. It is very MOSFETs. Each time a MOSFET gate is switched from important to include these “system” level losses during low to high to low again, a packet of charge dQ moves the design phase. The internal battery and fuse resistance 3855f 

LTC3855 applicaTions inForMaTion losses can be minimized by making sure that C has The I series R -C filter sets the dominant pole-zero IN TH C C adequate charge storage and very low ESR at the switch- loop compensation. The values can be modified slightly ing frequency. A 25W supply will typically require a (from 0.5 to 2 times their suggested values) to optimize minimum of 20µF to 40µF of capacitance having transient response once the final PC layout is done and a maximum of 20mΩ to 50mΩ of ESR. The LTC3855 the particular output capacitor type and value have been 2-phase architecture typically halves this input capacitance determined. The output capacitors need to be selected requirement over competing solutions. Other losses because the various types and values determine the loop including Schottky conduction losses during dead time gain and phase. An output current pulse of 20% to 80% and inductor core losses generally account for less than of full-load current having a rise time of 1µs to 10µs will 2% total additional loss. produce output voltage and I pin waveforms that will TH give a sense of the overall loop stability without break- Modest improvements in Burst Mode efficiency may be ing the feedback loop. Placing a power MOSFET directly realized by using a smaller inductor value, a lower switch- across the output capacitor and driving the gate with an ing frequency or for DCR sensing applications, making the appropriate signal generator is a practical way to produce DCR filter’s time constant smaller than the L/DCR time a realistic load step condition. The initial output voltage constant for the inductor. A small Schottky diode with a step resulting from the step change in output current may current rating equal to about 20% of the maximum load not be within the bandwidth of the feedback loop, so this current or less may yield minor improvements, too. signal cannot be used to determine phase margin. This Checking Transient Response is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated The regulator loop response can be checked by looking at control loop response. The gain of the loop will be in- the load current transient response. Switching regulators creased by increasing R and the bandwidth of the loop C take several cycles to respond to a step in DC (resistive) will be increased by decreasing C . If R is increased by C C load current. When a load step occurs, V shifts by an OUT the same factor that C is decreased, the zero frequency C amount equal to ∆I (ESR), where ESR is the effective LOAD will be kept the same, thereby keeping the phase shift the series resistance of C . ∆I also begins to charge or OUT LOAD same in the most critical frequency range of the feedback discharge C generating the feedback error signal that OUT loop. The output voltage settling behavior is related to the forces the regulator to adapt to the current change and stability of the closed-loop system and will demonstrate return V to its steady-state value. During this recovery OUT the actual overall supply performance. time V can be monitored for excessive overshoot or OUT ringing, which would indicate a stability problem. The A second, more severe transient is caused by switching availability of the I pin not only allows optimization of in loads with large (>1µF) supply bypass capacitors. The TH control loop behavior but also provides a DC coupled and discharged bypass capacitors are effectively put in parallel AC filtered closed loop response test point. The DC step, with C , causing a rapid drop in V . No regulator can OUT OUT rise time and settling at this test point truly reflects the alter its delivery of current quickly enough to prevent this closed loop response. Assuming a predominantly second sudden step change in output voltage if the load switch order system, phase margin and/or damping factor can be resistance is low and it is driven quickly. If the ratio of estimated using the percentage of overshoot seen at this C to C is greater than 1:50, the switch rise time LOAD OUT pin. The bandwidth can also be estimated by examining the should be controlled so that the load rise time is limited rise time at the pin. The ITH external components shown to approximately 25 • CLOAD. Thus a 10µF capacitor would in the Typical Application circuit will provide an adequate require a 250µs rise time, limiting the charging current starting point for most applications. to about 200mA. 3855f 

LTC3855 applicaTions inForMaTion PC Board Layout Checklist 6. Keep the switching nodes (SW1, SW2), top gate nodes (TG1, TG2), and boost nodes (BOOST1, BOOST2) away When laying out the printed circuit board, the following from sensitive small-signal nodes, especially from the checklist should be used to ensure proper operation of opposite channel’s voltage and current sensing feed- the IC. These items are also illustrated graphically in the back pins. All of these nodes have very large and fast layout diagram of Figure 14. Figure 15 illustrates the moving signals and therefore should be kept on the current waveforms present in the various branches of “output side” of the LTC3855 and occupy minimum the 2-phase synchronous regulators operating in the PC trace area. If DCR sensing is used, place the top continuous mode. Check the following in your layout: resistor (Figure 2b, R1) close to the switching node. 1. Are the top N-channel MOSFETs M1 and M3 located 7. Are DIFFP and DIFFN leads routed together and correctly within 1 cm of each other with a common drain con- Kelvin sensing the output voltage? nection at C ? Do not attempt to split the input de- IN coupling for the two channels as it can cause a large 8. Use a modified “star ground” technique: a low imped- resonant loop. ance, large copper area central grounding point on the same side of the PC board as the input and output 2. Are the signal and power grounds kept separate? The capacitors with tie-ins for the bottom of the INTV combined IC signal ground pin and the ground return CC decoupling capacitor, the bottom of the voltage feedback of C must return to the combined C (–) ter- INTVCC OUT resistive divider and the SGND pin of the IC. minals. The V and I traces should be as short as FB TH possible. The path formed by the top N-channel MOSFET, PC Board Layout Debugging Schottky diode and the C capacitor should have short IN leads and PC trace lengths. The output capacitor (–) Start with one controller at a time. It is helpful to use a terminals should be connected as close as possible DC-50MHz current probe to monitor the current in the to the (–) terminals of the input capacitor by placing inductor while testing the circuit. Monitor the output the capacitors next to each other and away from the switching node (SW pin) to synchronize the oscilloscope Schottky loop described above. to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating 3. Do the LTC3855 V pins’ resistive dividers connect to FB voltage and current range expected in the application. the (+) terminals of C ? The resistive divider must be OUT The frequency of operation should be maintained over connected between the (+) terminal of C and signal OUT the input voltage range down to dropout and until the ground. The feedback resistor connections should not output load drops below the low current operation be along the high current input feeds from the input threshold—typically 10% of the maximum designed cur- capacitor(s). rent level in Burst Mode operation. 4. Are the SENSE+ and SENSE– leads routed together with The duty cycle percentage should be maintained from minimum PC trace spacing? The filter capacitor between cycle to cycle in a well-designed, low noise PCB implemen- SENSE+ and SENSE– should be as close as possible tation. Variation in the duty cycle at a subharmonic rate to the IC. Ensure accurate current sensing with Kelvin can suggest noise pickup at the current or voltage sensing connections at the sense resistor or inductor, whichever inputs or inadequate loop compensation. Overcompensa- is used for current sensing. tion of the loop can be used to tame a poor PC layout if 5. Is the INTV decoupling capacitor connected close to regulator bandwidth optimization is not required. Only after CC the IC, between the INTV and the power ground pins? each controller is checked for its individual performance CC This capacitor carries the MOSFET drivers current peaks. should both controllers be turned on at the same time. An additional 1µF ceramic capacitor placed immediately A particularly difficult region of operation is when one next to the INTV and PGND pins can help improve controller channel is nearing its current comparator trip CC noise performance substantially. point when the other channel is turning on its top MOSFET. 3855f 0

LTC3855 applicaTions inForMaTion CLKOUT TK/SS1 RPU2 VPULL-UP ITH1 PGOOD PGOOD LTC3855 DIFFP VFB1 DIFFN DIFFOUT L1 RSENSE SENSE1+ TG1 VOUT1 SENSE1– SW1 CB1 M1 M2 FREQ BOOST1 D1 ILIM BG1 1µF fIN MODE/PLLIN VIN CERAMIC COUT1 RUN1 CVIN RIN + PGND RUN2 VIN + GND SGND EXTVCC CINTVCC CIN + SENSE2– INTVCC + 1µF COUT2 CERAMIC SENSE2+ BG2 M3 M4 VFB2 BOOST2 D2 CB2 ITH2 SW2 RSENSE TG2 VOUT2 TK/SS2 L2 3855F14 Figure 14. Recommended Printed Circuit Layout Diagram SW1 L1 RSENSE1 VOUT1 D1 COUT1 RL1 VIN RIN CIN SW2 L2 RSENSE2 VOUT2 BOLD LINES INDICATE D2 COUT2 RL2 HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH. 3855F15 Figure 15. Branch Current Waveforms 3855f 

LTC3855 applicaTions inForMaTion This occurs around 50% duty cycle on either channel due input voltage: to the phasing of the internal clocks and may cause minor   duty cycle jitter. VOUT VOUT L= 1−  Reduce V from its nominal level to verify operation f • ∆IL(MAX)  VIN(MAX) IN of the regulator in dropout. Check the operation of the Channel 1 will require 0.78µH, and channel 2 will require undervoltage lockout circuit by further lowering V while IN 0.54µH. The Vishay IHLP4040DZ-01, 0.56µH inductor is monitoring the outputs to verify operation. chosen for both rails. At the nominal input voltage (12V), Investigate whether any problems exist only at higher out- the ripple current will be: put currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, V  V  OUT OUT look for capacitive coupling between the BOOST, SW, TG, ∆IL(NOM)= 1−  f •L  VIN(NOM) and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current Channel 1 will have 6.8A (46%) ripple, and channel 2 will sensing pins needs to be placed immediately adjacent to have 4.8A (32%) ripple. The peak inductor current will be the pins of the IC. This capacitor helps to minimize the the maximum DC value plus one-half the ripple current, effects of differential noise injection due to high frequency or 18.4A for channel 1 and 17.4A for channel 2. capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look The minimum on-time occurs on channel 2 at the maximum for inductive coupling between CIN, Schottky and the top VIN, and should not be less than 90ns: MOSFET components to the sensitive current and voltage V 1.2V sensing traces. In addition, investigate common ground t = OUT = =150ns ON(MIN) V f 20V(400kHz) path voltage pickup between these components and the IN(MAX) SGND pin of the IC. With I floating, the equivalent R resistor value LIM SENSE can be calculated by using the minimum value for the Design Example maximum current sense threshold (45mV). As a design example for a two channel high current regula- V tor, assume VIN = 12V(nominal), VIN = 20V(maximum), R = SENSE(MIN) V = 1.8V, V = 1.2V, I = 15A, and f = 400kHz SENSE(EQUIV) ∆I OUT1 OUT2 MAX1,2 L(NOM) I + (see Figure 16). LOAD(MAX) 2 The regulated output voltages are determined by: The equivalent required R value is 2.4mΩ for chan- SENSE  R  nel 1 and 2.6mΩ for channel 2. The DCR of the 0.56µH V =0.6V• 1+ B OUT   inductor is 1.7mΩ typical and 1.8mΩ maximum for a  R  A 25°C ambient. At 100°C, the estimated maximum DCR Using 20k 1% resistors from both V nodes to ground, value is 2.3mΩ. The maximum DCR value is just slightly FB the top feedback resistors are (to the nearest 1% standard under the equivalent RSENSE values. Therefore, R2 is not value) 40.2k and 20k. required to divide down the signal. The frequency is set by biasing the FREQ pin to 1V (see For each channel, 0.1µF is selected for C1. Figure 12). L 0.56µH R1= = =3.11k The inductance values are based on a 35% maximum (DCR at25°C)•C1 1.8mΩ•0.1µF MAX ripple current assumption (5.25A for each channel). The highest value of ripple current occurs at the maximum Choose R1 = 3.09k 3855f 

LTC3855 applicaTions inForMaTion VIN + 4.5V TO 10µF 82µF 20V 2.2Ω 1µF 25V 25V (cid:115)2 4.7µF D3 D4 VIN PGOOD EXTVCCINTVCC M1 TG1 TG2 M3 0.1µF 0.1µF L1 L2 0.56µH BOOST1 BOOST2 0.56µH SW1 SW2 M2 BG1 LTC3855 BG2 M4 3.09k 3.09k CLKOUT 1% 1% MODE/PLLIN PGND ILIM1 FREQ ILIM2 SENSE1+ SENSE2+ 0.1µF 0.1µF SENSE1– SENSE2– ITEMP1 ITEMP2 DIFFP RUN2 DIFFN 40.2k 20k, 1% VOUT1 1% RUN1 DIFFOUT VOUT2 1.8V VFB1 VFB2 1.2V 15A ITH1 ITH2 15A 1nF 1nF + TK/SS1 SGND TK/SS2 + COUT1 20k 12.1k 150pF 100k 4.99k 150pF 20k COUT2 330µF 1% 1% 0.1µF 0.1µF 1% 1% 1% 330µF (cid:115)2 (cid:115)2 L1, L2: VISHAY IHLP4040DZ-01, 0.56µH 3855F16 M1, M3: RENESAS RJK0305DPB M2, M4: RENESAS RJK0330DPB Figure 16. High Efficiency Dual 400kHz 1.8V/1.2V Step-Down Converter The power loss in R1 at the maximum input voltage is: 95 5 P R1=(VIN(MAX)−VOUT)•VOUT VMION D=E 1 =2 VCCM 11..88VV RDSCERN SSEENSE LOSS R1 90 4 P Tanhde 7remsuWlt ifnogr cphoawnenre llo 2s.s for R1 is 11mW for channel 1 NCY (%) 85 EFFICIENCY 3 OWER L E O The sum of the sense resistor and DCR is 2.5mΩ (max) EFFICI 80 2 SS (W for the RSENSE application whereas the inductor DCR for POWER LOSS ) 75 1 the DCR sense application is 1.8mΩ (max). As a result of the lower conduction losses from the switch node to V , 1.2V RSENSE OUT 1.2V DCR SENSE 70 0 the DCR sensing application has higher efficiency. 0 2 4 6 8 10 12 14 16 LOAD CURRENT (A) The power dissipation on the topside MOSFET can be 3855F17 DCR SENSE APP: SEE FIGURE 16 easily estimated. Choosing a Renesas RJK0305DPB RSENSE APP: SEE FIGURE 19 Figure 17. DCR Sense Efficiency vs R Efficiency SENSE 3855f 

LTC3855 applicaTions inForMaTion MOSFET results in: R = 13mΩ (max), V = A Renesas RJK0330DPB, R = 3.9mΩ, is chosen for DS(ON) MILLER DS(ON) 2.6V, C ≅ 150pF. At maximum input voltage with T the bottom FET. The resulting power loss is: MILLER J (estimated) = 75°C: 20V–1.8V P = (15A)2 • 1.8V SYNC P = (15A)2[1+(0.005)(75°C–25°C)]• 20V MAIN 20V 1+(0.005)•(75°C–25°C)•0.0039Ω   (0.013Ω)+(20V)215A(2Ω)(150pF)•    2  PSYNC = 1W  1 1  C is chosen for an RMS current rating of at least 7.5A at + (400kHz) IN 5V–2.6V 2.6V temperature assuming only channel 1 or 2 is on. COUT is chosen with an equivalent ESR of 4.5mΩ for low output =329mW+288mW ripple. The output ripple in continuous mode will be highest =617mW at the maximum input voltage. The output voltage ripple due to ESR is approximately: For a 2mΩ sense resistor, a short-circuit to ground will result in a folded back current of: VORIPPLE = RESR (∆IL) = 0.0045Ω • 6.8A = 31mVP–P (1/3)50mV 190ns(20V) Further reductions in output voltage ripple can be made ISC = 0.002Ω –2 0.56µH  =6.7A by placing a 100µF ceramic across COUT. Typical applicaTions 20k 20k 0.1µF R1N0T0Ck2 49.9k R1N0T0Ck1 49.9k 86.6k VIN + 4.5V TO 10µF 24.9k 82µF 20V 0.1µF (cid:115)2 25V 20k 1nF 20k63.4k TITKH/1SS1–SENSE1+SENSE1 RUN1 ITEMP1 ITEMP2 FREQ MODE/PLLIN PHSASMDBCLKOUTOOTSGTSW111 0.1µF MRJ1K0305DPB 3.00.16Lk81µH (cid:115)C160.2O30UVµTF1 + C343VO0UµTF2 V21.5O5AUVT1 100pF VFB1 PGND1 CMDSH-3 (cid:115)2 M2 SGND BG1 2.2Ω RJK0330DPB 100pF 20k VFB2 LTC3855 VIN ITH2 INTVCC TK/SS2 EXTVCC 4.7µF 15k SENSE2+ BG2 0.1µF 1nF 0.1µF SENSE2– PGND2 DIFFP BOOST2 0.1µF UT D1 D2 40.2k DIFFN DIFFO RUN2 ILIM1 ILIM2 PGOO PGOO NC SW2 TG2 0.1µF CMDSH-3 M3 L2 RJK0305DPB 0.68µH VOUT2 + 1.8V PGOOD1 100k MRJ4K0330DPB 3.01k C160.O30UVµTF3 C343VO0UµTF4 15A PGOOD2 (cid:115)2 100k 24.9k L1, L2: VISHAY IHLP5050CE-01, 0.68µH 3855F18 COUT1, COUT3: MURATA GRM32ER60J107ME20 COUT2, COUT4: KEMET T520V337M004ATE009 RNTC1, RNTC2: MURATA NCP18WF104J03RB Figure 18. 2.5V, 15A and 1.8V, 15A Supply with NTC Temperature Compensated DCR Sensing, f = 350kHz SW 3855f 

LTC3855 Typical applicaTions 100Ω 1nF 100Ω 100k VIN + 4.5V TO 0.1µF 40.2k 1(cid:115)02µF 8225µVF 20V (cid:115)2 18k 1nF 20k TITKH/1SS1–SENSE1 +SENSE1 RUN1 ITEMP1 ITEMP2 FREQ MODE/PLLIN PHSASMDBCLKOUTOOTSGTSW111 0.1µF MRJ1K03005.L4D1µPHB 0.002Ω C160.O30UVµTF1 + C323.O50UVµTF2 V11.5O8AUVT1 150pF VFB1 PGND1 CMDSH-3 (cid:115)2 M2 SGND BG1 2.2Ω RJK0330DPB 150pF 20k VFB2 LTC3855 VIN ITH2 INTVCC TK/SS2 EXTVCC 4.7µF 5.49k SENSE2+ BG2 0.1µF 1.5nF 1nF SENSE2– PGND2 DIFFP BOOST2 0.1µF UT D1 D2 100Ω 100Ω 20k DIFFN DIFFO RUN2 ILIM1 ILIM2 PGOO PGOO NC SW2 TG2 0.1µF CMDSH-3 MRJ3K0305DPB L2 0.4µH 0.002Ω VOUT2 + 1.2V M4 COUT3 COUT4 15A 100k RJK0330DPB 100µF 330µF PGOOD1 6.3V 2.5V PGOOD2 (cid:115)2 100k L1, L2: VITEC 59PR9875 3855F19 COUT1, COUT3: MURATA GRM31CR60J107ME39L COUT2, COUT4: SANYO 2R5TPE330M9 Figure 19. 1.8V, 15A and 1.2V, 15A Supply, f = 400kHz SW 3855f 

LTC3855 Typical applicaTions 100Ω 1nF 100Ω RUN 250kHz + V4.I5NV TO 10µF 270µF 14V (cid:115)4 16V TK/SS1–SENSE1+SENSE1 RUN1 ITEMP1 ITEMP2 FREQ ODE/PLLIN PHSASMD CLKOUTTGSW11 0.1µF MRJ1K0L3105DPB 0.010%1Ω 0.1µF ITH1 M BOOST1 0.44µH VFB1 PGND1 CMDSH-3 M2 SGND BG1 RJK0330DPB 2.2Ω (cid:115)2 20k VFB2 LTC3855 VIN ITH2 INTVCC 100pF 2200pF TSKE/NSSSE22+ EXTBVGC2C 4.7µF 0.1µF C10O0UµTF1 + C33O0UµTF2 V14.0O2AUVT 20k 5.9k 1nF SENSE2– PGND2 6(cid:115).43V 2(cid:115).45V DIFFP BOOST2 UT D1 D2 DIFFN DIFFO RUN2 ILIM1 ILIM2 PGOO PGOO NC SW2 TG2 0.1µF CMDSH-3 MRJ3K0305DPB L2 0.001Ω 0.44µH 1% RUN M4 100Ω 100Ω 100k RJK0330DPB PGOOD (cid:115)2 L1, L2: PULSE PA0513.441NLT 3855F20 COUT1: MURATA GRM31CR60J107ME39L COUT2: SANYO 2R5TPE330M9 Figure 20. High Efficiency Dual Phase 1.2V, 40A Supply, f = 250kHz SW 3855f 

LTC3855 Typical applicaTions 0.1µF VIN + 4.5V TO 10µF 270µF 14V (cid:115)4 16V TK/SS1–SENSE1+SENSE1 RUN1 ITEMP1 ITEMP2 FREQ ODE/PLLIN PHSASMD CLKOUTTGSW11 0.1µF MRJ1K0305DPB 3.92Lk1 0.1µF ITH1 M BOOST1 0.47µH VFB1 PGND1 CMDSH-3 M2 SGND BG1 RJK0330DPB 2.2Ω (cid:115)2 20k VFB2 LTC3855 VIN ITH2 INTVCC 330pF 3300pF TSKE/NSSSE22+ EXTBVGC2C 4.7µF 1µF C10O0UµTF1 + C33O0UµTF2 V14.0O2AUVT 20k 10k 0.1µF SENSE2– PGND2 6(cid:115).43V 2(cid:115).45V DIFFP BOOST2 UT D1 D2 DIFFN DIFFO RUN2 ILIM1 ILIM2 PGOO PGOO NC SW2 TG2 0.1µF CMDSH-3 M3 L2 RJK0305DPB 0.47µH M4 100k RJK0330DPB PGOOD (cid:115)2 3.92k L1, L2: VISHAY IHLP5050FD-01, 0.47µH 3855F21 COUT1: MURATA GRM31CR60J107ME39L COUT2: SANYO 2R5TPE330M9 Figure 21. High Efficiency Dual Phase 1.2V, 40A Supply with DCR Sensing, f = 250kHz SW 3855f 

LTC3855 Typical applicaTions 100Ω 1nF 100Ω 400kHz VIN + 4.5V TO 100k 10µF 270µF 14V (cid:115)4 16V M1 RJK0305DPB TK/SS1–SENSE1+SENSE1 RUN1 ITEMP1 ITEMP2 FREQ ODE/PLLIN PHSASMD CLKOUTTGSW11 0.1µF (cid:115)2 L1 0.010%1Ω 0.1µF ITH1 M BOOST1 0.23µH VFB1 PGND1 CMDSH-3 M2 SGND BG1 RJK0330DPB 2.2Ω (cid:115)2 10k VFB2 LTC3855 VIN ITH2 INTVCC 220pF 2700pF TSKE/NSSSE22+ EXTBVGC2C 4.7µF 1µF C10O0UµTF1 + C33O0UµTF2 V05.0O9AUVT 20k 5.1k 1nF SENSE2– PGND2 6(cid:115).23V 2(cid:115).45V DIFFP BOOST2 UT D1 D2 DIFFN DIFFO RUN2 ILIM1 ILIM2 PGOO PGOO NC SW2 TG2 0.1µF CMDSH-3 MR(cid:115)2J3K0305DPB L2 0.001Ω 0.23µH 1% M4 100Ω 100Ω 100k RJK0330DPB PGOOD (cid:115)2 L1, L2: VITEC 59PR9873 3855F22 COUT1: MURATA GRM31CR60J107ME39L COUT2: SANYO 2R5TPE330M9 Figure 22. Small Size, Dual Phase 0.9V, 50A Supply, f = 400kHz SW 3855f 

LTC3855 Typical applicaTions 100Ω 1nF 100Ω VIN + 4.5V TO RUN1 100k 1(cid:115)03µF 21760VµF 14V M1 TK/SS1–SENSE1+SENSE1 RUN1 ITEMP1 ITEMP2 FREQ ODE/PLLIN PHSASMD CLKOUTTGSW11 0.1µF RJK0L3105DPB 0.010%2Ω M 0.3µH 0.1µF ITH1 BOOST1 VFB1 PGND1 CMDSH-3 M2 SGND BG1 2.2Ω RJK0330DPB 13.3k VFB2 LTC3855 VIN ITH2 INTVCC 4700pF TK/SS2 EXTVCC 4.7µF 1µF 330pF SENSE2+ BG2 20k 2k 1nF SENSE2– PGND2 DIFFP BOOST2 UT D1 D2 DIFFN DIFFO RUN2 ILIM1 ILIM2 PGOO PGOO NC SW2 TG2 0.1µF CMDSH-3 MRJ3K0305DPB L2 0.002Ω 0.3µH 1% RUN1 + 1VVOUT1 100Ω 100Ω MRJ4K0330DPB C10O0UµTF1 C47O0UµTF2 50A PGOOD1V 6.3V 2.5V 100k (cid:115)3 (cid:115)4 100Ω 1nF 100Ω 100k RUN1 M5 RJK0305DPB TK/SS1–SENSE1+SENSE1 RUN1 ITEMP1 ITEMP2 FREQ ODE/PLLIN PHSASMD CLKOUTTGSW11 0.1µF L3 0.010%2Ω M 0.3µH ITH1 BOOST1 VFB1 PGND1 CMDSH-3 M6 SGND BG1 RJK0330DPB 2.2Ω 90.9k VFB2 LTC3855 VIN ITH2 INTVCC TK/SS2 EXTVCC 4.7µF 1µF 20k 3300pF SENSE2+ BG2 0.1µF 100pF 10k 0.1µF SENSE2– PGND2 10µF DIFFP BOOST2 UT D1 D2 DIFFN DIFFO RUN2 ILIM1 ILIM2 PGOO PGOO NC SW2 TG2 0.1µF CMDSH-3 MS47816BDY L4 2.2µH VOUT2 RUN2 3.3V 100k C10O0UµTF3 5A PGOOD3.3V 2.49k 6.3V 4.99k 3855F23 L1, L2, L3: VITEC 59PR9874 L4: WURTH 744311220 COUT1, COUT3: TDK C3225X5R0J107M COUT2: KEMET T530D477M2R5ATE006 Figure 23. Triple Phase 1V, 50A Supply with Auxillary 3.3V, 5A Rail, f = 400kHz SW 3855f 

LTC3855 Typical applicaTions VIN 7V TO 2.2Ω 22µF 24V 50V 1µF Si4816BDY 4.7µF Si4816BDY D3 VIN PGOOD INTVCC D4 M1 M2 TG1 TG2 0.1µF 0.1µF L2 L2 2.2µH BOOST1 BOOST2 3.3µH SW1 SW2 LTC3855 BG1 BG2 CLKOUT MODE/PLLIN PGND 10Ω ILIM FREQ 10Ω SENSE1+ SENSE2+ 8mΩ 1000pF 1000pF 8mΩ SENSE1– SENSE2– 10Ω RUN1 10Ω 15pF DIFFP 10pF RUN2 DIFFN VOUT1 DIFFOUT EXTVCC VOUT2 3.3V VFB1 VFB2 5V 5A 90.9k ITH1 ITH2 147k 5A + C22O0U1µT%F1 210%k 110%1k000pF100pF 0.1µFTK/SS1 SGND TK/SS20.1µF 112%2k 115%1k000pF 100pF 210%1k% + C15O0UµTF2 3855F24 L1: TDK RLF 7030T-2R2M5R4 L2: TDK ULF10045T-3R3N6R9 COUT1: SANYO 4TPE220MF COUT2: SANYO 6TPE150MI Figure 24. 3.3V/5A, 5V/5A Converter Using Sense Resistors 3855f 0

LTC3855 Typical applicaTions 0.1µF VIN 0.1µF 383k 4(cid:115).67µF 24k + 15000VµF 1338VV TO 10k 5.6nF TK/SS1–SENSE1 +SENSE1 RUN1 ITEMP1 ITEMP2 FREQ MODE/PLLIN PHSASMD CLKOUTTGSW11 0.1µF MBS1C093N040LS 18k13Lµ1H + COUT1 V162AOVUT1 20k ITH1 BOOST1 3196µVF 47pF VFB1 PGND1 CMDSH-3 (cid:115)2 M2 SGND BG1 2.2Ω BSC093N040LS 47pF 20k VFB2 LTC3855 VIN ITH2 INTVCC 4.7µF TK/SS2 EXTVCC 4.99k SENSE2+ BG2 0.1µF 5.6nF 0.1µF SENSE2– PGND2 DIFFP BOOST2 0.1µF T 1 2 U D D 147k DIFFN DIFFO RUN2 ILIM1 ILIM2 PGOO PGOO NC SW2 TG2 0.1µF CMDSH-3 M3 L2 BSC093N040LS 3.7µH VOUT2 + 5V M4 COUT2 10A 100k BSC093N040LS 39µF PGOOD1 8.2k 16V PGOOD2 (cid:115)2 100k 24k 3855F25 L1: WURTH 7443551131 L2: WURTH 7443551370 COUT1, COUT2: SANYO 16SVPC39MV Figure 25. 12V, 6A and 5V, 10A Supply with DCR Sensing, f = 250kHz SW 3855f 

LTC3855 package DescripTion FE Package 38-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1772 Rev A) Exposed Pad Variation AA 4.75 REF 9.60 – 9.80* (.378 – .386) 4.75 REF (.187) 38 20 6.60 ±0.10 2.74 REF 4.50 REF SEE NOTE 4 6.40 2.74 0.315 ±0.05 REF(.252) (.108) BSC 1.05 ±0.10 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT 1 19 1.20 4.30 – 4.50* (.047) (.169 – .177) 0.25 MAX REF 0(cid:111) – 8(cid:111) 0.50 0.09 – 0.20 0.50 – 0.75 (.0196) 0.05 – 0.15 (.0035 – .0079) (.020 – .030) BSC (.002 – .006) 0.17 – 0.27 (.0067 – .0106) FE38 (AA) TSSOP 0608 REV A TYP NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE 2. DIMENSIONS ARE INMILLIMETERS FOR EXPOSED PAD ATTACHMENT (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH 3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3855f 

LTC3855 package DescripTion UJ Package 40-Lead Plastic QFN (6mm × 6mm) (Reference LTC DWG # 05-08-1728 Rev Ø) 0.70 ±0.05 6.50 ±0.05 5.10 ±0.05 4.42 ±0.05 4.50 ±0.05 (4 SIDES) 4.42 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 6.00 ± 0.10 0.75 ± 0.05 R = 0.115 (4 SIDES) R = 0.10 TYP 39 40 TYP 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2 PIN 1 NOTCH R = 0.45 OR 0.35(cid:115) 45° CHAMFER 4.42 ±0.10 4.50 REF (4-SIDES) 4.42 ±0.10 (UJ40) QFN REV Ø 0406 0.200 REF 0.25 ± 0.05 0.00 – 0.05 0.50 BSC NOTE: BOTTOM VIEW—EXPOSED PAD 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3855f Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC3855 relaTeD parTs PART NUMBER DESCRIPTION COMMENTS LTC3853 Triple Output, Multiphase Synchronous Step-Down DC/DC Phase-Lockable Fixed 250kHz to 750kHz Frequency, 4V ≤ V ≤ 24V, IN Controller, R or DCR Current Sensing and Tracking V Up to 13.5V SENSE OUT3 LTC3731 3-Phase Synchronous Controller, Expandable to 12 phases Phase-Lockable Fixed 250kHz to 600kHz Frequency, 0.6V ≤ V ≤ 5.25V, OUT Differential Amp, High Output Current 60A to 240A 4.5V ≤ V ≤ 32V, IN LTC3850/ Dual 2-Phase, High Efficiency Synchronous Step-Down DC/ Phase-Lockable Fixed 250kHz to 780kHz Frequency, 4V ≤ V ≤ 30V, IN LTC3850-1/ DC Controller, R or DCR Current Sensing and Tracking 0.8V ≤ V ≤ 5.25V SENSE OUT LTC3850-2 LTC3854 Small Footprint Wide V Range Synchronous Step-Down Fixed 400kHz Operating Frequency 4.5V ≤ V ≤ 38V, 0.8V ≤ V ≤ 5.25V, IN IN OUT DC/DC Controller, RSENSE or DCR Current Sensing 2mm × 3mm QFN-12 LTC3851A/ No R ™ Wide V Range Synchronous Step-Down DC/ Phase-Lockable Fixed 250kHz to 750kHz Frequency, 4V ≤ V ≤ 38V, SENSE IN IN LTC3851A-1 DC Controller, RSENSE or DCR Current Sensing and Tracking 0.8V ≤ VOUT ≤ 5.25V, MSOP-16E, 3mm × 3mm QFN-16, SSOP-16 LTC3878 No R Constant On-Time Synchronous Step-Down Very Fast Transient Response, t = 43ns, 4V ≤ V ≤ 38V, SENSE ON(MIN) IN DC/DC Controller, No R Required 0.8V ≤ V ≤ 0.9V , SSOP-16 SENSE OUT IN LTC3879 No R Constant On-Time Synchronous Step-Down Very Fast Transient Response, t = 43ns, 4V ≤ V ≤ 38V, SENSE ON(MIN) IN DC/DC Controller, No RSENSE Required 0.6V ≤ VOUT ≤ 0.9VIN, MSOP-16E, 3mm × 3mm QFN-16 LTM4600HV 10A DC/DC µModule® Complete Power Supply High Efficiency, Compact Size, Fast Transient Response 4.5V ≤ V ≤ 28V, IN 0.8V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.8mm LTM4601AHV 12A DC/DC µModule Complete Power Supply High Efficiency, Compact Size, Fast Transient Response 4.5V ≤ V ≤ 28V, IN 0.8V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.8mm LTC3610 12A, 1MHz, Monolithic Synchronous Step-Down DC/DC High Efficiency, Adjustable Constant On-Time 4V ≤ V ≤ 24V, IN Converter VOUT(MIN) 0.6V, 9mm × 9mm QFN-64 LTC3611 10A, 1MHz, Monolithic Synchronous Step-Down DC/DC High Efficiency, Adjustable Constant On-Time 4V ≤ V ≤ 32V, IN Converter VOUT(MIN) 0.6V, 9mm × 9mm QFN-64 LTC3857/ Low I , Dual Output 2-Phase Synchronous Step-Down Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz, Q LTC3857-1 DC/DC Controller with 99% Duty Cycle 4V ≤ V ≤ 38V, 0.8V ≤ V ≤ 24V, I = 50µA IN OUT Q LTC3868/ Low I , Dual Output 2-Phase Synchronous Step-Down Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz, Q LTC3868-1 DC/DC Controller with 99% Duty Cycle 4V ≤ V ≤ 24V, 0.8V ≤ V ≤ 14V, I = 170µA, IN OUT Q LT3845 Low I , High Voltage Synchronous Step-Down DC/DC Adjustable Fixed Operating Frequency 100kHz to 500kHz, Q Controller 4V ≤ V ≤ 60V, 1.23V ≤ V ≤ 36V, I = 30µA, TSSOP-16 IN OUT Q No R is a trademark of Linear Technology Corporation. µModule is a registered trademark of Linear Technology Corporation. SENSE 3855f  Linear Technology Corporation LT 1009 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2009