LTC3728L/LTC3728LX Dual, 550kHz, 2-Phase Synchronous Regulators FeaTures DescripTion n Dual, 180° Phased Controllers Reduce Required The LTC®3728L/LTC3728LX are dual high performance Input Capacitance and Power Supply Induced Noise step-down switching regulator controllers that drive all n OPTI-LOOP® Compensation Minimizes C N-channel synchronous power MOSFET stages. A constant- OUT n ±1% Output Voltage Accuracy (LTC3728LC) frequency, current mode architecture allows phase-lockable n Power Good Output Voltage Indicator frequency of up to 550kHz. Power loss and noise due to n Phase-Lockable Fixed Frequency 250kHz to 550kHz the ESR of the input capacitors are minimized by operating n Dual N-Channel MOSFET Synchronous Drive the two controller output stages out of phase. n Wide V Range: 4.5V to 28V Operation IN OPTI-LOOP compensation allows the transient response to n Very Low Dropout Operation: 99% Duty Cycle be optimized over a wide range of output capacitance and n Adjustable Soft-Start Current Ramping ESR values. The precision 0.8V reference and power good n Foldback Output Current Limiting output indicator are compatible with future microproces- n Latched Short-Circuit Shutdown with Defeat Option sor generations, and a wide 4.5V to 28V (30V maximum) n Output Overvoltage Protection input supply range encompasses all battery chemistries. n Low Shutdown I : 20µA Q n 5V and 3.3V Standby Regulators A RUN/SS pin for each controller provides both soft- n 3 Selectable Operating Modes: Constant-Frequency, start and optional timed, short-circuit shutdown. Current foldback limits MOSFET dissipation during short-circuit Burst Mode® Operation and PWM conditions when overcurrent latchoff is disabled. Output n 5mm × 5mm QFN and 28-Lead Narrow SSOP overvoltage protection circuitry latches on the bottom Packages MOSFET until V returns to normal. The FCB mode OUT applicaTions pin can select among Burst Mode, constant-frequency mode and continuous inductor current mode or regulate n Notebook and Palmtop Computers a secondary winding. The LTC3728L/LTC3728LX include n Telecom Systems a power good output pin that indicates when both outputs n Portable Instruments are within 7.5% of their designed set point. n Battery-Operated Digital Devices n DC Power Distribution Systems L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, OPTI-LOOP and PolyPhase are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical applicaTion VIN + 1µF CIN 5.2V TO 28V 4.7µF D3 VIN PGOOD INTVCC D4 CERAMIC 25C20EµVRFAMIC M1 TG1 TG2 M2 L1 L2 3.2µH CB1, 0.1µF BOOST1 BOOST2 CB2, 0.1µF 3.2µH SW1 SW2 LTC3728L/ D1 BG1 LTC3728LX BG2 D2 500kfHINz PLLIN PGND SENSE1+ SENSE2+ RSENSE1 1000pF 1000pF RSENSE2 0.01Ω 0.01Ω SENSE1– SENSE2– VOUT1 VOSENSE1 VOSENSE2 VOUT2 55VA + C46S7VOPµUFT1 11R0%52k R210%1k R15C2Ck21C01pF 0C.1SµSF1RITUHN1/SS1 SGND RUN/ISTHS22C0.S1Sµ2F 22C0pCR1F25Ck2 21R0%3k 613R%.44k C5O6S6UµVPFT + 35.A3V M1, M2: FDS6982S 3728 F01 Figure 1. High Efficiency Dual 5V/3.3V Step-Down Converter 3728lxff 1

LTC3728L/LTC3728LX absoluTe MaxiMuM raTings (Note 1) Input Supply Voltage (V ) ........................ 30V to –0.3V I I , V , V Voltages ...2.7V to –0.3V IN TH1, TH2 OSENSE1 OSENSE2 Topside Driver Voltages Peak Output Current <10µs (TG1, TG2, BG1, BG2) .... 3A (BOOST1, BOOST2) .............................. 36V to –0.3V INTV Peak Output Current ................................. 40mA CC Switch Voltage (SW1, SW2) ........................ 30V to –5V Operating Temperature Range (Note 7) INTV EXTV , RUN/SS1, RUN/SS2, LTC3728LC/LTC3728LXC ........................ 0°C to 85°C CC, CC (BOOST1-SW1), (BOOST2-SW2), PGOOD .... 7V to –0.3V LTC3728LE/LTC3728LI ........................ –40°C to 85°C SENSE1+, SENSE2+, SENSE1–, Junction Temperature (Note 2) ............................ 125°C SENSE2– Voltages ........................ (1.1)INTV to –0.3V Storage Temperature Range .................. –65°C to 125°C CC PLLIN, PLLFLTR, FCB Voltages ............ INTV to –0.3V Reflow Peak Body Temperature (UH Package) ..... 260°C CC Lead Temperature (Soldering, 10 sec) (GN Package) ....................................................300°C pin conFiguraTion TOP VIEW TOP VIEW RSUENNS/SES11+ 12 2287 PTGG1OOD NC–SENSE1+SENSE1 NC RUN/SS1 PGOOD TG1 SW1 SENSE1– 3 26 SW1 32 31 30 29 28 27 26 25 VOSENSE1 4 25 BOOST1 VOSENSE1 1 24 BOOST1 PLLFLTR 5 24 VIN PLLFLTR 2 23 VIN PLLIN 3 22 BG1 PLLIN 6 23 BG1 FCB 4 21 EXTVCC FCB 7 22 EXTVCC 33 ITH1 5 20 INTVCC ITH1 8 21 INTVCC SGND 6 19 PGND SGND 9 20 PGND 3.3VOUT 7 18 BG2 3.3VOUT 10 19 BG2 ITH2 8 17 BOOST2 ITH2 11 18 BOOST2 9 10 11 12 13 14 15 16 VSSOEESNNESSNEES22E2–+ 111234 111765 STRGWU2N2/SS2 VOSENSE2 NC–SENSE2+SENSE2 RUN/SS2 TG2 SW2 NC UH PACKAGE GN PACKAGE 32-LEAD (5mm × 5mm) PLASTIC QFN 28-LEAD NARROW PLASTIC SSOP TJMAX = 125°C, θJA = 34°C/W TJMAX = 125°C, θJA = 95°C/W EXPOSED PAD IS SGND (PIN 33), MUST BE SOLDERED TO PCB 3728lxff 2

LTC3728L/LTC3728LX orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3728LCGN#PBF LTC3728LCGN#TRPBF 28-Lead Narrow Plastic SSOP 0°C to 85°C LTC3728LEGN#PBF LTC3728LEGN#TRPBF 28-Lead Narrow Plastic SSOP –40°C to 85°C LTC3728LIGN#PBF LTC3728LIGN#TRPBF 28-Lead Narrow Plastic SSOP –40°C to 85°C LTC3728LCUH#PBF LTC3728LCUH#TRPBF 3728L 32-Lead (5mm × 5mm) Plastic QFN 0°C to 85°C LTC3728LEUH#PBF LTC3728LEUH#TRPBF 3728LE 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C LTC3728LIUH#PBF LTC3728LIUH#TRPBF 3728LI 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C LTC3728LXCUH#PBF LTC3728LXCUH#TRPBF 3728LX 32-Lead (5mm × 5mm) Plastic QFN 0°C to 85°C LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3728LCGN LTC3728LCGN#TR 28-Lead Narrow Plastic SSOP 0°C to 85°C LTC3728LEGN LTC3728LEGN#TR 28-Lead Narrow Plastic SSOP –40°C to 85°C LTC3728LIGN LTC3728LIGN#TR 28-Lead Narrow Plastic SSOP –40°C to 85°C LTC3728LCUH LTC3728LCUH#TR 3728L 32-Lead (5mm × 5mm) Plastic QFN 0°C to 85°C LTC3728LEUH LTC3728LEUH#TR 3728LE 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C LTC3728LIUH LTC3728LIUH#TR 3728LI 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C LTC3728LXCUH LTC3728LXCUH#TR 3728LX 32-Lead (5mm × 5mm) Plastic QFN 0°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3728lxff 3

LTC3728L/LTC3728LX elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 15V, V = 5V unless otherwise noted. A IN RUN/SS1, 2 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loops V Regulated Feedback Voltage (Note 3); I Voltage = 1.2V (LTC3728LC) ● 0.792 0.800 0.808 V OSENSE1, 2 TH1, 2 (Note 3); I Voltage = 1.2V ● 0.788 0.800 0.812 V TH1, 2 (LTC3728LE/LTC3728LX/LTC3728LI) I Feedback Current (Note 3) –5 –50 nA VOSENSE1, 2 V Reference Voltage Line Regulation V = 3.6V to 30V (Note 3) 0.002 0.02 %/V REFLNREG IN V Output Voltage Load Regulation (Note 3) LOADREG Measured in Servo Loop; ΔI Voltage = 1.2V to 0.7V ● 0.1 0.5 % TH Measured in Servo Loop; ΔI Voltage = 1.2V to 2.0V ● –0.1 –0.5 % TH g Transconductance Amplifier g I = 1.2V; Sink/Source 5µA (Note 3) 1.3 mmho m1, 2 m TH1, 2 g Transconductance Amplifier GBW I = 1.2V (Note 8) 3 MHz mGBW1, 2 TH1, 2 I Input DC Supply Current (Note 4) Q Normal Mode V = 15V; EXTV Tied to V ; V = 5V 450 µA IN CC OUT1 OUT1 Shutdown V = 0V 20 35 µA RUN/SS1, 2 V Forced Continuous Threshold ● 0.76 0.800 0.84 V FCB I Forced Continuous Pin Current V = 0.85V –0.50 –0.18 –0.1 µA FCB FCB V Burst Inhibit (Constant-Frequency) Measured at FCB Pin 4.3 4.8 V BINHIBIT Threshold UVLO Undervoltage Lockout V Ramping Down ● 3.5 4 V IN V Feedback Overvoltage Lockout Measured at V ● 0.84 0.86 0.88 V OVL OSENSE1, 2 I Sense Pins Total Source Current (Each Channel); V – –= V + += 0V –90 –60 µA SENSE SENSE1 , 2 SENSE1 , 2 DF Maximum Duty Factor In Dropout 98 99.4 % MAX I Soft-Start Charge Current V = 1.9V 0.5 1.2 µA RUN/SS1, 2 RUN/SS1, 2 V ON RUN/SS Pin ON Threshold V V Rising 1.0 1.5 2.0 V RUN/SS1, 2 RUN/SS1, RUN/SS2 V LT RUN/SS Pin Latchoff Arming V V Rising from 3V 4.1 4.75 V RUN/SS1, 2 RUN/SS1, RUN/SS2 Threshold I RUN/SS Discharge Current Soft-Short Condition V = 0.5V; 0.5 2 4 µA SCL1, 2 OSENSE1, 2 V = 4.5V RUN/SS1, 2 I Shutdown Latch Disable Current V = 0.5V 1.6 5 µA SDLHO OSENSE1, 2 VSENSE(MAX) Maximum Current Sense Threshold VOSENSE1, 2 = 0.7V, VSENSE1–, 2– = 5V 65 75 85 mV VOSENSE1, 2 = 0.7V, VSENSE1–, 2– = 5V ● 62 75 88 mV TG Transition Time: (Note 5) TG1, 2 t Rise Time C = 3300pF 55 100 ns r LOAD TG1, 2 t Fall Time C = 3300pF 55 100 ns f LOAD BG Transition Time: (Note 5) BG1, 2 t Rise Time C = 3300pF 45 100 ns r LOAD BG1, 2 t Fall Time C = 3300pF 45 90 ns f LOAD TG/BG t Top Gate Off to Bottom Gate On Delay 1D Synchronous Switch-On Delay Time C = 3300pF Each Driver 80 ns LOAD BG/TG t Bottom Gate Off to Top Gate On Delay 2D Top Switch-On Delay Time C = 3300pF Each Driver 80 ns LOAD t Minimum On-Time Tested with a Square Wave (Note 6) 100 ns ON(MIN) 3728lxff 4

LTC3728L/LTC3728LX elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 15V, V = 5V unless otherwise noted. A IN RUN/SS1, 2 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS INTV Linear Regulator CC V Internal V Voltage 6V < V < 30V, V = 4V 4.8 5.0 5.2 V INTVCC CC IN EXTVCC V INT INTV Load Regulation I = 0 to 20mA, V = 4V 0.2 2.0 % LDO CC CC EXTVCC V EXT EXTV Voltage Drop I = 20mA, V = 5V 100 200 mV LDO CC CC EXTVCC V EXTV Switchover Voltage I = 20mA, EXTV Ramping Positive ● 4.5 4.7 V EXTVCC CC CC CC V EXTV Hysteresis 0.2 V LDOHYS CC Oscillator and Phase-Locked Loop f Nominal Frequency V = 1.2V 360 400 440 kHz NOM PLLFLTR f Lowest Frequency V = 0V 230 260 290 kHz LOW PLLFLTR f Highest Frequency V ≥ 2.4V 480 550 590 kHz HIGH PLLFLTR R PLLIN Input Resistance 50 kΩ PLLIN I Phase Detector Output Current PLLFLTR Sinking Capability f < f –15 µA PLLIN OSC Sourcing Capability f > f 15 µA PLLIN OSC 3.3V Linear Regulator V 3.3V Regulator Output Voltage No Load ● 3.2 3.35 3.45 V 3.3OUT V 3.3V Regulator Load Regulation I = 0 to 10mA 0.5 2 % 3.3IL 3.3 V 3.3V Regulator Line Regulation 6V < V < 30V 0.05 0.2 % 3.3VL IN PGOOD Output V PGOOD Voltage Low I = 2mA 0.1 0.3 V PGL PGOOD I PGOOD Leakage Current V = 5V ±1 µA PGOOD PGOOD V PGOOD Trip Level, Either Controller V with Respect to Set Output Voltage PG OSENSE V Ramping Negative –6 –7.5 –9.5 % OSENSE V Ramping Positive 6 7.5 9.5 % OSENSE Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: Rise and fall times are measured using 10% and 90% levels. Delay may cause permanent damage to the device. Exposure to any Absolute times are measured using 50% levels. Maximum Rating condition for extended periods may affect device Note 6: The minimum on-time is tested under an ideal condition without reliability and lifetime. external power FETs. It can be larger when the IC is operating in an Note 2: T is calculated from the ambient temperature T and power actual circuit. See Minimum On-Time Considerations in the Applications J A dissipation P according to the following formulas: Information section. D LTC3728LUH/LTC3728LXUH: T = T + (P • 34°C/W) Note 7: The LTC3728LC/LTC3728LXC are guaranteed to meet performance J A D LTC3728LGN: T = T + (P • 95°C/W) specifications from 0°C to 85°C. The LTC3728LE is guaranteed to meet J A D performance specifications over the –40°C to 85°C operating temperature Note 3: The IC is tested in a feedback loop that servos V to a ITH1, 2 range as assured by design, characterization and correlation with statistical specified voltage and measures the resultant V OSENSE1, 2. process controls. The LTC3728LI is guaranteed to meet performance Note 4: Dynamic supply current is higher due to the gate charge being specifications over the –40°C to 85°C operating temperature range. delivered at the switching frequency. See the Applications Information Note 8: Guaranteed by design. section. 3728lxff 5

LTC3728L/LTC3728LX Typical perForMance characTerisTics Efficiency vs Output Current Efficiency vs Output Current Efficiency vs Input Voltage and Mode (Figure 13) (Figure 13) (Figure 13) 100 100 100 90 OBPuErsRtA MTIoOdNe VIN = 7V 80 90 90 70 VIN = 10V CY (%) 60 FCMOOORNDCTEEI ND(PUWOUMS) CY (%) 80 VIN = 15V CY (%) 80 EN 50 EN VIN = 20V EN CI CI CI FFI 40 CONSTANT FFI 70 FFI 70 E 30 FREQUENCY E E (BURST DISABLE) 20 60 60 10 fVV =ION U2 =T5 0=1k 55HVVz Vf =O U2T5 0=k 5HVz VIfO =OU U2TT 5= 0= 3k 5HAVz 0 50 50 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 5 15 25 35 OUTPUT CURRENT (A) OUTPUT CURRENT (A) INPUT VOLTAGE (V) 3728L G01 3728L G02 3728L G03 Supply Current vs Input Voltage INTV and EXTV Switch CC CC and Mode (Figure 13) EXTV Voltage Drop Voltage vs Temperature CC 1000 200 5.05 GE (V)5.00 INTVCC VOLTAGE 800 V) TA LY CURRENT (µA)640000 BCOOTNHTROLLERS ON VOLTAGE DROP (m 110500 TV SWITCH VOLCC444...899505 UPP V CC D EX4.80 S200 EXT 50 ANC EXTVCC SWITCHOVER THRESHOLD VC4.75 T SHUTDOWN IN 0 0 4.70 0 5 10 15 20 25 30 0 10 20 30 40 –50 –25 0 25 50 75 100 125 INPUT VOLTAGE (V) CURRENT (mA) TEMPERATURE (°C) 3728L G04 3728L G05 3728L G06 Maximum Current Sense Maximum Current Sense Threshold vs Percent of Nominal Internal 5V LDO Line Regulation Threshold vs Duty Factor Output Voltage (Foldback) 5.1 75 80 ILOAD = 1mA 5.0 70 60 V) 4.9 GE ( V) 50 V) 50 A 4.8 m m V VOLTCC 4.7 V (SENSE V (SENSE 4300 T 25 IN 4.6 20 4.5 10 4.4 0 0 0 5 10 15 20 25 30 0 20 40 60 80 100 0 25 50 75 100 INPUT VOLTAGE (V) DUTY FACTOR (%) PERCENT ON NOMINAL OUTPUT VOLTAGE (%) 3728L G07 3728L G08 3728L G09 3728lxff 6

LTC3728L/LTC3728LX Typical perForMance characTerisTics Maximum Current Sense Threshold Maximum Current Sense Threshold Current Sense Threshold vs V (Soft-Start) vs Sense Common Mode Voltage vs I Voltage RUN/SS TH 80 80 90 VSENSE(CM) = 1.6V 80 70 76 60 60 50 mV) mV) 72 mV) 40 (NSE 40 (NSE (NSE 30 VSE VSE 68 VSE 20 10 20 0 64 –10 –20 0 60 –30 0 1 2 3 4 5 6 0 1 2 3 4 5 0 0.5 1 1.5 2 2.5 VRUN/SS (V) COMMON MODE VOLTAGE (V) VITH (V) 3728L G10 3728L G11 3728L G12 Load Regulation V vs V SENSE Pins Total Source Current ITH RUN/SS 0.0 2.5 100 FCB = 0V VOSENSE = 0.7V VIN = 15V FIGURE 13 2.0 %)–0.1 50 MALIZED V (OUT–0.2 V (V)ITH 11..05 I (µA)SENSE 0 R O N–0.3 –50 0.5 –0.4 0 –100 0 1 2 3 4 5 0 1 2 3 4 5 6 0 2 4 6 LOAD CURRENT (A) VRUN/SS (V) VSENSE COMMON MODE VOLTAGE (V) 3728L G13 3728L G14 3728L G15 Maximum Current Sense Dropout Voltage vs Output Current Threshold vs Temperature (Figure 14) RUN/SS Current vs Temperature 80 4 1.8 VOUT = 5V 1.6 78 V (mV)SENSE 7764 OPOUT VOLTAGE (V) 32 RSENSE = 0.015Ω N/SS CURRENT (µA) 01110.....80246 R U D 1 R 72 0.4 RSENSE = 0.010Ω 0.2 70 0 0 –50 –25 0 25 50 75 100 125 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) OUTPUT CURRENT (A) TEMPERATURE (°C) 3728L G17 3728L G18 3728L G25 3728lxff 7

LTC3728L/LTC3728LX Typical perForMance characTerisTics Soft-Start Up (Figure 13) Load Step (Figure 13) Load Step (Figure 13) VOUT VOUT VOUT 5V/DIV 200mV/DIV 200mV/DIV VRUN/SS 5V/DIV IL IL 2A/DIV 2A/DIV IL 2A/DIV VIN = 15V 5ms/DIV 3728L G19 VIN = 15V 20µs/DIV 3728L G20 VIN = 15V 20µs/DIV 3728L G21 VOUT = 5V VOUT = 5V VOUT = 5V VPLLFLTR = 0V VPLLFLTR = 0V LOAD STEP = 0A TO 3A LOAD STEP = 0A TO 3A Burst Mode OPERATION CONTINUOUS MODE Input Source/Capacitor Constant-Frequency (Burst Inhibit) Instantaneous Current (Figure 13) Burst Mode Operation (Figure 13) Operation (Figure 13) IIN 2A/DIV VOUT VOUT 20mV/DIV 20mV/DIV VIN 200mV/DIV VSW1 10V/DIV IL VSW2 0.5A/DIV IL 10V/DIV 0.5A/DIV VIN = 15V 1µs/DIV 3728L G22 VIN = 15V 10µs/DIV 3728L G23 VIN = 15V 2µs/DIV 3728L G24 VOUT1 = 5V, VOUT2 = 3.3V VOUT = 5V VOUT = 5V VPLLFLTR = 0V VPLLFLTR = 0V VPLLFLTR = 0V IOUT5 = IOUT3.3 = 2A VFCB = OPEN VFCB = 5V IOUT = 20mA IOUT = 20mA 3728lxff 8

LTC3728L/LTC3728LX Typical perForMance characTerisTics Current Sense Pin Input Current EXTV Switch Resistance Oscillator Frequency CC vs Temperature vs Temperature vs Temperature 35 10 700 VOUT = 5V A) RRENT SENSE INPUT CURRENT (µ 32231973 EXTV SWITCH RESISTANCE (Ω)CC 6428 FREQUENCY (kHz) 432651000000000000 VVVPPPLLLLLLFFFLLLTTTRRR == = 21 0..42VVV U C 25 0 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3728L G26 3728L G27 3728L G28 Undervoltage Lockout Shutdown Latch Thresholds vs Temperature vs Temperature 3.50 4.5 LATCH ARMING V) 4.0 V)3.45 S ( T ( LD 3.5 U O LATCHOFF KO3.40 SH 3.0 THRESHOLD C E O R GE L3.35 H TH 2.5 OLTA LATC 2.0 ERV3.30 WN 1.5 D O N D 1.0 U3.25 UT SH 0.5 3.20 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) 3728L G29 3728L G30 3728lxff 9

LTC3728L/LTC3728LX pin FuncTions V , V : Error Amplifier Feedback Input. TG2, TG1: High Current Gate Drives for Top N-Channel OSENSE1 OSENSE2 Receives the remotely sensed feedback voltage for each MOSFETs. These are the outputs of floating drivers with controller from an external resistive divider across the a voltage swing equal to INTV – 0.5V superimposed on CC output. the switch node voltage SW. PLLFLTR: Filter Connection for Phase-Locked Loop. Alter- SW2, SW1: Switch Node Connections to Inductors. Voltage natively, this pin can be driven with an AC or DC voltage swing at these pins is from a Schottky diode (external) source to vary the frequency of the internal oscillator. voltage drop below ground to V . IN PLLIN: External Synchronization Input to Phase Detector. BOOST2, BOOST1: Bootstrapped Supplies to the Top- This pin is internally terminated to SGND with 50kΩ. The side Floating Drivers. Capacitors are connected between phase-locked loop will force the rising top gate signal of the boost and switch pins and Schottky diodes are tied controller 1 to be synchronized with the rising edge of between the boost and INTV pins. Voltage swing at the CC the PLLIN signal. boost pins is from INTV to (V + INTV ). CC IN CC FCB: Forced Continuous Control Input. This input acts BG2, BG1: High Current Gate Drives for Bottom (Synchro- on both controllers and is normally used to regulate a nous) N-Channel MOSFETs. Voltage swing at these pins secondary winding. Pulling this pin below 0.8V will force is from ground to INTV . CC continuous synchronous operation. PGND: Driver Power Ground. Connects to the sources I I : Error Amplifier Output and Switching Regulator of bottom (synchronous) N-channel MOSFETs, anodes TH1, TH2 Compensation Point. Each associated channels’ current of the Schottky rectifiers and the (–) terminal(s) of C . IN comparator trip point increases with this control voltage. INTV : Output of the Internal 5V Linear Low Dropout CC SGND: Small Signal Ground. Common to both con- Regulator and the EXTV Switch. The driver and control CC trollers, this pin must be routed separately from high circuits are powered from this voltage source. Must be current grounds to the common (–) terminals of the C decoupled to power ground with a minimum of 4.7µF OUT capacitors. tantalum or other low ESR capacitor. 3.3V : Linear Regulator Output. Capable of supplying EXTV : External Power Input to an Internal Switch OUT CC 10mA DC with peak currents as high as 50mA. Connected to INTV . This switch closes and supplies CC V power, bypassing the internallow dropout regulator, NC: No Connect. CC whenever EXTV is higher than 4.7V. See EXTV connec- CC CC SENSE2–, SENSE1–: The (–) Input to the Differential Cur- tion in Applications section. Do not exceed 7V on this pin. rent Comparators. V : Main Supply Pin. A bypass capacitor should be tied IN SENSE2+, SENSE1+: The (+) Input to the Differential Current between this pin and the signal ground pin. Comparators. The I pin voltage and controlled offsets TH PGOOD: Open-Drain Logic Output. PGOOD is pulled to between the SENSE– and SENSE+ pins in conjunction with ground when the voltage on either V pin is not R set the current trip threshold. OSENSE SENSE within ±7.5% of its set point. RUN/SS2, RUN/SS1: Combination of soft-start, run control Exposed Pad (UH Package Only): Signal Ground. Must inputs and short-circuit detection timers. A capacitor to be soldered to the PCB, providing a local ground for the ground at each of these pins sets the ramp time to full control components of the IC, and be tied to the PGND output current. Forcing either of these pins back below pin under the IC. 1.0V causes the IC to shut down the circuitry required for that particular controller. Latchoff overcurrent protection is also invoked via this pin as described in the Applications Information section. 3728lxff 10

LTC3728L/LTC3728LX FuncTional DiagraM UT O V + CIN COUT + D1 RSENSE 3728 FD/F02 C N R VI C DB CB R2 1 C CC2 CSS C R C V T N I BOOST TG SW BG PGND +SENSE –SENSE VOSENSE ITH RUN/SS C VC 0k 0k T 3 3 IN CC TOP TCHGIC BOT INTV VFB 0.80V 0.86V WIO SL – + + – FCB N HDN I2– + 45k 2.4V EA OV RUNSOFTSTART O S P – BOT TO mV 2 B + 3 HDNRSTV)FB re DROPOUTDET +V – + 45k S 4( Figu Q Q 0.55 +–– R SECONDCHANNEL S R I1 0.86V4(V)FB SLOPECOMP µA LICATE FOTROLLER 1.2 6V PN UO DC SE1 SE2 N N CLK1 CLK2 –0.86V +VOSE– +0.74V 0.86V– +VOSE– +0.74V BINH FCB VREF 5VLDOREG INTERNALSUPPLY – + + – PHASE DET OSCILLATOR 3V4.3V 0.8V+ – +4.7V – ACKAGE PAD) µA H P 8 U PLLIN FIN 50k PLLFLTR RLP CLP PGOOD INTVCC 0.1 R6FCB R5 3.3VOUT VIN VIN EXTVCC INTVCC5V+ SGND ( 3728lxff 11

LTC3728L/LTC3728LX operaTion (Refer to Functional Diagram) Main Control Loop Low Current Operation The IC uses a constant-frequency, current mode step-down The FCB pin is a multifunction pin providing two func- architecture with the two controller channels operating tions: 1) to provide regulation for a secondary winding by 180 degrees out of phase. During normal operation, each temporarily forcing continuous PWM operation on both top MOSFET is turned on when the clock for that channel controllers; and 2) to select between two modes of low sets the RS latch, and turned off when the main current current operation. When the FCB pin voltage is below comparator, I , resets the RS latch. The peak inductor 0.8V, the controller forces continuous PWM current mode 1 current at which I resets the RS latch is controlled by operation. In this mode, the top and bottom MOSFETs 1 the voltage on the I pin, which is the output of each are alternately turned on to maintain the output voltage TH error amplifier EA. The V pin receives the voltage independent of direction of inductor current. When the OSENSE feedback signal, which is compared to the internal refer- FCB pin is below V – 2V but greater than 0.8V, INTVCC ence voltage by the EA. When the load current increases, the controller enters Burst Mode operation. Burst Mode it causes a slight decrease in V relative to the 0.8V operation sets a minimum output current level before OSENSE reference, which in turn causes the I voltage to increase inhibiting the top switch and turns off the synchronous TH until the average inductor current matches the new load MOSFET(s) when the inductor current goes negative. This current. After the top MOSFET has turned off, the bottom combination of requirements will, at low currents, force MOSFET is turned on until either the inductor current the I pin below a voltage threshold that will temporarily TH starts to reverse, as indicated by current comparator I , inhibit turn-on of both output MOSFETs until the output 2 or the beginning of the next cycle. voltage drops. There is 60mV of hysteresis in the burst comparator B tied to the I pin. This hysteresis produces The top MOSFET drivers are biased from floating bootstrap TH output signals to the MOSFETs that turn them on for capacitor C , which normally is recharged during each off B several cycles, followed by a variable “sleep” interval cycle through an external diode when the top MOSFET depending upon the load current. The resultant output turns off. As V decreases to a voltage close to V , IN OUT voltage ripple is held to a very small value by having the the loop may enter dropout and attempt to turn on the hysteretic comparator after the error amplifier gain block. top MOSFET continuously. The dropout detector detects this and forces the top MOSFET off for about 400ns every Frequency Synchronization tenth cycle to allow C to recharge. B The phase-locked loop allows the internal oscillator to The main control loop is shut down by pulling the RUN/SS be synchronized to an external source via the PLLIN pin. pin low. Releasing RUN/SS allows an internal 1.2µA cur- The output of the phase detector at the PLLFLTR pin is rent source to charge soft-start capacitor C . When C SS SS also the DC frequency control input of the oscillator that reaches 1.5V, the main control loop is enabled with the I TH operates over a 260kHz to 550kHz range corresponding voltage clamped at approximately 30% of its maximum to a DC voltage input from 0V to 2.4V. When locked, the value. As C continues to charge, the I pin voltage is SS TH PLL aligns the turn on of the top MOSFET to the rising gradually released allowing normal, full-current operation. edge of the synchronizing signal. When PLLIN is left When both RUN/SS1 and RUN/SS2 are low, all control- open, the PLLFLTR pin goes low, forcing the oscillator to ler functions are shut down, including the 5V and 3.3V minimum frequency. regulators. 3728lxff 12

LTC3728L/LTC3728LX operaTion (Refer to Functional Diagram) Constant-Frequency Operation Power Good (PGOOD) Pin When the FCB pin is tied to INTV , Burst Mode opera- The PGOOD pin is connected to an open drain of an internal CC tion is disabled and the forced minimum output current MOSFET. The MOSFET turns on and pulls the pin low when requirement is removed. This provides constant-frequency, either output is not within ±7.5% of the nominal output discontinuous current (preventing reverse inductor cur- level as determined by the resistive feedback divider. When rent) operation over the widest possible output current both outputs meet the ±7.5% requirement, the MOSFET is range. This constant-frequency operation is not as efficient turned off within 10µs and the pin is allowed to be pulled as Burst Mode operation, but does provide a lower noise, up by an external resistor to a source of up to 7V. constant-frequency operating mode down to approximately 1% of the designed maximum output current. Foldback Current, Short-Circuit Detection and Short-Circuit Latchoff Continuous Current (PWM) Operation The RUN/SS capacitors are used initially to limit the inrush Tying the FCB pin to ground will force continuous current current of each switching regulator. After the controller operation. This is the least efficient operating mode, but has been started and been given adequate time to charge may be desirable in certain applications. The output can up the output capacitors and provide full load current, the source or sink current in this mode. When sinking current RUN/SS capacitor is used in a short-circuit time-out circuit. while in forced continuous operation, current will be forced If the output voltage falls to less than 70% of its nominal back into the main power supply potentially boosting the output voltage, the RUN/SS capacitor begins discharging input supply to dangerous voltage levels—BEWARE! on the assumption that the output is in an overcurrent and/ or short-circuit condition. If the condition lasts for a long INTVCC/EXTVCC Power enough period as determined by the size of the RUN/SS capacitor, the controller will be shut down until the RUN/ Power for the top and bottom MOSFET drivers and most SS pin(s) voltage(s) are recycled. This built-in latchoff can other internal circuitry is derived from the INTV pin. When CC be overridden by providing a >5µA pull-up at a compliance the EXTV pin is left open, an internal 5V low dropout CC of 5V to the RUN/SS pin(s). This current shortens the soft linear regulator supplies INTV power. If EXTV is taken CC CC start period but also prevents net discharge of the RUN/ above 4.7V, the 5V regulator is turned off and an internal SS capacitor(s) during an overcurrent and/or short-circuit switch is turned on connecting EXTV to INTV . This al- CC CC condition. Foldback current limiting is also activated when lows the INTV power to be derived from a high efficiency CC the output voltage falls below 70% of its nominal level external source such as the output of the regulator itself whether or not the short-circuit latchoff circuit is enabled. or a secondary winding, as described in the Applications Even if a short is present and the short-circuit latchoff is Information section. not enabled, a safe, low output current is provided due to Output Overvoltage Protection internal current foldback and actual power wasted is low due to the efficient nature of the current mode switching An overvoltage comparator, OV, guards against transient regulator. overshoots (>7.5%) as well as other more serious condi- tions that may overvoltage the output. In this case, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. 3728lxff 13

LTC3728L/LTC3728LX operaTion (Refer to Functional Diagram) THEORY AND BENEFITS OF 2-PHASE OPERATION This effectively interleaves the current pulses drawn by the switches, greatly reducing the overlap time where The LTC1628 and the LTC3728L family of dual high effi- they add together. The result is a significant reduction ciency DC/DC controllers brings the considerable benefits in total RMS input current, which in turn allows less of 2-phase operation to portable applications for the first expensive input capacitors to be used, reduces shielding time. Notebook computers, PDAs, handheld terminals requirements for EMI and improves real world operating and automotive electronics will all benefit from the lower efficiency. input filtering requirement, reduced electromagnetic in- terference (EMI) and increased efficiency associated with Figure 3 compares the input waveforms for a representa- 2-phase operation. tive single-phase dual switching regulator to the LTC1628 2-phase dual switching regulator. An actual measurement of Why the need for 2-phase operation? Up until the the RMS input current under these conditions shows that 2-phase family, constant-frequency dual switching regula- 2-phase operation dropped the input current from 2.53A RMS tors operated both channels in phase (i.e., single-phase to 1.55A . While this is an impressive reduction in itself, RMS operation). This means that both switches turned on at remember that the power losses are proportional to I 2, RMS the same time, causing current pulses of up to twice the meaning that the actual power wasted is reduced by a fac- amplitude of those for one regulator to be drawn from the tor of 2.66. The reduced input ripple voltage also means input capacitor and battery. These large amplitude current less power is lost in the input power path, which could pulses increased the total RMS current flowing from the include batteries, switches, trace/connector resistances input capacitor, requiring the use of more expensive input and protection circuitry. Improvements in both conducted capacitors and increasing both EMI and losses in the input and radiated EMI also directly accrue as a result of the capacitor and battery. reduced RMS input current and voltage. With 2-phase operation, the two channels of the dual- Of course, the improvement afforded by 2-phase opera- switching regulator are operated 180 degrees out of phase. tion is a function of the dual switching regulator’s relative 5V SWITCH 20V/DIV 3.3V SWITCH 20V/DIV INPUT CURRENT 5A/DIV INPUT VOLTAGE 500mV/DIV IIN(MEAS) = 2.53ARMS DC236 F03a IIN(MEAS) = 2.53ARMS DC236 F03b (a) (b) Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the LTC1628 2-Phase Regulator Allows Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency 3728lxff 14

LTC3728L/LTC3728LX operaTion (Refer to Functional Diagram) duty cycles which, in turn, are dependent upon the input channels becomes more critical with 2-phase operation voltage V (Duty Cycle = V /V ). Figure 4 shows how because switch transitions in one channel could potentially IN OUT IN the RMS input current varies for single-phase and 2-phase disrupt the operation of the other channel. operation for 3.3V and 5V regulators over a wide input These 2-phase parts are proof that these hurdles have voltage range. been surmounted. They offer unique advantages for the It can readily be seen that the advantages of 2-phase opera- ever expanding number of high efficiency power supplies tion are not just limited to a narrow operating range, but required in portable electronics. in fact extend over a wide region. A good rule of thumb for most applications is that 2-phase operation will reduce 3.0 the input capacitor requirement to that for just one chan- SINGLE PHASE nel operating at maximum current and 50% duty cycle. 2.5 DUAL CONTROLLER A) A final question: If 2-phase operation offers such an ad- NT ( 2.0 E vantage over single-phase operation for dual switching RR U C 1.5 regulators, why hasn’t it been done before? The answer MS 2-PHASE is that, while simple in concept, it is hard to implement. UT R 1.0 DUAL CONTROLLER Constant-frequency, current mode switching regulators NP I require an oscillator derived slope compensation signal 0.5 VO1 = 5V/3A to allow stable operation of each regulator at over 50% VO2 = 3.3V/3A 0 duty cycle. This signal is relatively easy to derive in 0 10 20 30 40 INPUT VOLTAGE (V) single-phase dual switching regulators, but required the 3728 F04 development of a new and proprietary technique to allow 2-phase operation. In addition, isolation between the two Figure 4. RMS Input Current Comparison 3728lxff 15

LTC3728L/LTC3728LX applicaTions inForMaTion Figure 1 on the first page is a basic LTC3728L/LTC3728LX 2.5 application circuit. External component selection is driven 2.0 by the load requirement, and begins with the selection of V) E ( R and the inductor value. Next, the power MOSFETs G SENSE TA 1.5 L and D1 are selected. Finally, C and C are selected. O IN OUT N V The circuit shown in Figure 1 can be configured for R PI 1.0 T operation up to an input voltage of 28V (limited by the LFL L external MOSFETs). P 0.5 0 RSENSE Selection for Output Current 200 300 400 500 600 OPERATING FREQUENCY (kHz) R is chosen based on the required output current. The SENSE 3728 F05 current comparator has a maximum threshold of 75mV/ Figure 5. PLLFLTR Pin Voltage vs Frequency R and an input common mode range of SGND to SENSE and Frequency Synchronization in the Applications Infor- 1.1(INTV ). The current comparator threshold sets the CC mation section for additional information. peak of the inductor current, yielding a maximum average output current I equal to the peak value less half the A graph for the voltage applied to the PLLFLTR pin vs MAX peak-to-peak ripple current, ΔI . frequency is given in Figure 5. As the operating frequency L is increased the gate charge losses will be higher, reducing Allowing a margin for variations in the IC and external efficiency (see Efficiency Considerations). The maximum component values yields: switching frequency is approximately 550kHz. 50mV R = SENSE I Inductor Value Calculation MAX The operating frequency and inductor selection are inter- Because of possible PCB layout-induced noise in the related in that higher operating frequencies allow the use current sensing loop, the AC current sensing ripple of of smaller inductor and capacitor values. So why would ΔV = ΔI • R also needs to be checked in the SENSE SENSE anyone ever choose to operate at lower frequencies with design to get good signal-to-noise ratio. In general, for larger components? The answer is efficiency. A higher a reasonably good PCB layout, a 15mV ΔVSENSE voltage frequency generally results in lower efficiency because is recommended as a conservative design starting point. of MOSFET gate charge losses. In addition to this basic When using the controller in very low dropout conditions, trade-off, the effect of inductor value on ripple current and the maximum output current level will be reduced due to the low current operation must also be considered. internal compensation required to meet stability criterion The inductor value has a direct effect on ripple current. for buck regulators operating at greater than 50% duty The inductor ripple current ΔI decreases with higher L factor. A curve is provided to estimate this reduction in inductance or frequency and increases with higher V : IN peak output current level depending upon the operating duty factor. 1  V  ∆I = V 1– OUT L OUT  (f)(L)  V  Operating Frequency IN The IC uses a constant-frequency, phase-lockable ar- Accepting larger values of ΔIL allows the use of low in- chitecture with the frequency determined by an internal ductances, but results in higher output voltage ripple and capacitor. This capacitor is charged by a fixed current plus greater core losses. A reasonable starting point for setting an additional current which is proportional to the voltage ripple current is ΔI = 30% of maximum output current or applied to the PLLFLTR pin. Refer to Phase-Locked Loop higher for good load transient response and sufficient ripple current signal in the current loop. 3728lxff 16

LTC3728L/LTC3728LX applicaTions inForMaTion The inductor value also has secondary effects. The tran- The peak-to-peak drive levels are set by the INTV CC sition to Burst Mode operation begins when the average voltage. This voltage is typically 5V during start-up inductor current required results in a peak current below (see EXTV Pin Connection). Consequently, logic-level CC 25% of the current limit determined by R . Lower threshold MOSFETs must be used in most applications. SENSE inductor values (higher ΔI ) will cause this to occur at The only exception is if low input voltage is expected (V L IN lower load currents, which can cause a dip in efficiency in < 5V); then, sublogic level threshold MOSFETs (V GS(TH) the upper range of low current operation. In Burst Mode < 3V) should be used. Pay close attention to the BV DSS operation, lower inductance values will cause the burst specification for the MOSFETs as well; most of the logic frequency to decrease. level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the Inductor Core Selection on-resistance R , Miller capacitance C , input DS(ON) MILLER Once the value for L is known, the type of inductor must voltage and maximum output current. Miller capacitance, be selected. High efficiency converters generally cannot C , can be approximated from the gate charge curve MILLER afford the core loss found in low cost powdered iron cores, usually provided on the MOSFET manufacturers’ data forcing the use of more expensive ferrite, molypermalloy, sheet. C is equal to the increase in gate charge MILLER or Kool Mµ® cores. Actual core loss is independent of core along the horizontal axis while the curve is approximately size for a fixed inductor value, but it is very dependent flat divided by the specified change in V . This result is DS on inductance selected. As inductance increases, core then multiplied by the ratio of the application applied V DS losses go down. Unfortunately, increased inductance to the gate charge curve specified V . When the IC is DS requires more turns of wire and, therefore, copper losses operating in continuous mode the duty cycles for the top will increase. and bottom MOSFETs are given by: V Ferrite designs have very low core loss and are preferred MainSwitchDutyCycle= OUT at high switching frequencies, so design goals can con- V IN centrate on copper loss and preventing saturation. Ferrite V –V core material saturates hard, which means that induc- SynchronousSwitchDutyCycle= IN OUT V tance collapses abruptly when the peak design current is IN exceeded. This results in an abrupt increase in inductor The MOSFET power dissipations at maximum output ripple current and consequent output voltage ripple. Do current are given by: not allow the core to saturate! V P = OUT (I )2(1+d)R + Molypermalloy (from Magnetics, Inc.) is a very good, low MAIN MAX DS(ON) V IN loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same (V )2IMAX(R )(C )• IN  2  DR MILLER manufacturer is Kool Mµ. Toroids are very space efficient, especially when using several layers of wire. Because  1 1  they generally lack a bobbin, mounting is more difficult.  + (f) V –V V However, designs for surface mount are available that do  INTVCC THMIN THMIN not increase the height significantly. P = VIN –VOUT (I )2(1+d)R SYNC MAX DS(ON) V Power MOSFET and D1 Selection IN Two external power MOSFETs must be selected for each controller in the LTC3728L/LTC3728LX: One N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. 3728lxff 17

LTC3728L/LTC3728LX applicaTions inForMaTion where d is the temperature dependency of R and factor of 30% to 70% when compared to a single phase DS(ON) R (approximately 4Ω) is the effective driver resistance power supply solution. DR at the MOSFET’s Miller threshold voltage. V is the TH(MIN) The type of input capacitor, value and ESR rating have typical MOSFET minimum threshold voltage. efficiency effects that need to be considered in the selec- Both MOSFETs have I2R losses while the topside N-channel tion process. The capacitance value chosen should be equation includes an additional term for transition losses, sufficient to store adequate charge to keep high peak which are highest at high input voltages. For V < 20V battery currents down. 20µF to 40µF is usually sufficient IN the high current efficiency generally improves with larger for a 25W output supply operating at 200kHz. The ESR of MOSFETs, while for V > 20V the transition losses rapidly the capacitor is important for capacitor power dissipation IN increase to the point that the use of a higher RDS(ON) device as well as overall battery efficiency. All of the power (RMS with lower CMILLER actually provides higher efficiency. The ripple current • ESR) not only heats up the capacitor but synchronous MOSFET losses are greatest at high input wastes power from the battery. voltage when the top switch duty factor is low or during Medium voltage (20V to 35V) ceramic, tantalum, OS-CON a short-circuit when the synchronous switch is on close and switcher-rated electrolytic capacitors can be used to 100% of the period. as input capacitors, but each has drawbacks: ceramic The term (1 + d) is generally given for a MOSFET in the voltage coefficients are very high and may have audible form of a normalized RDS(ON) vs Temperature curve, but piezoelectric effects; tantalums need to be surge-rated; d = 0.005/°C can be used as an approximation for low OS-CONs suffer from higher inductance, larger case size voltage MOSFETs. and limited surface-mount applicability; electrolytics’ higher ESR and dryout possibility require several to be The Schottky diode, D1, shown in Figure 1 conducts during the dead time between the conduction of the two power used. Multiphase systems allow the lowest amount of MOSFETs. This prevents the body diode of the bottom capacitance overall. As little as one 22µF or two to three MOSFET from turning on, storing charge during the dead 10µF ceramic capacitors are an ideal choice in a 20W to time and requiring a reverse-recovery period that could 35W power supply due to their extremely low ESR. Even cost as much as 3% in efficiency at high V . A 1A to 3A though the capacitance at 20V is substantially below their IN Schottky is generally a good compromise for both regions rating at zero-bias, very low ESR loss makes ceramics of operation due to the relatively small average current. an ideal candidate for highest efficiency battery operated Larger diodes result in additional transition losses due to systems. Also consider parallel ceramic and high quality their larger junction capacitance. electrolytic capacitors as an effective means of achieving ESR and bulk capacitance goals. C and C Selection IN OUT In continuous mode, the source current of the top N-channel The selection of C is simplified by the multiphase ar- MOSFET is a square wave of duty cycle V /V . To prevent IN OUT IN chitecture and its impact on the worst-case RMS current large voltage transients, a low ESR input capacitor sized drawn through the input network (battery/fuse/capacitor). for the maximum RMS current of one channel must be It can be shown that the worst-case RMS current occurs used. The maximum RMS capacitor current is given by: when only one controller is operating. The controller 1/2 V (V −V ) with the highest (VOUT)(IOUT) product needs to be used CINRequiredIRMS ≈IMAX  OUT IN OUT  V in the subsequent formula to determine the maximum IN RMS current requirement. Increasing the output current, drawn from the other out-of-phase controller, will actually This formula has a maximum at V = 2V , where I IN OUT RMS decrease the input RMS ripple current from this maximum = I /2. This simple worst-case condition is commonly OUT value (see Figure 4). The out-of-phase technique typically used for design because even significant deviations do not reduces the input capacitor’s RMS ripple current by a offer much relief. Note that capacitor manufacturer’s ripple 3728lxff 18

LTC3728L/LTC3728LX applicaTions inForMaTion current ratings are often based on only 2000 hours of life. The first condition relates to the ripple current into the ESR This makes it advisable to further derate the capacitor, or of the output capacitance while the second term guarantees to choose a capacitor rated at a higher temperature than that the output capacitance does not significantly discharge required. Several capacitors may also be paralleled to meet during the operating frequency period due to ripple current. size or height requirements in the design. Always consult The choice of using smaller output capacitance increases the manufacturer if there is any question. the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low ESR to The benefit of the LTC3728L/LTC3728LX multiphase clock- maintain the ripple voltage at or below 50mV. The I pin ing can be calculated by using the equation above for the TH OPTI-LOOP compensation components can be optimized higher power controller and then calculating the loss that to provide stable, high performance transient response would have resulted if both controller channels switched regardless of the output capacitors selected. on at the same time. The total RMS power lost is lower when both controllers are operating due to the interleav- Manufacturers such as Nichicon, United Chemi-Con and ing of current pulses through the input capacitor’s ESR. Sanyo can be considered for high performance through- This is why the input capacitor’s requirement calculated hole capacitors. The OS-CON semiconductor dielectric in the previous equation for the worst-case controller is capacitor available from Sanyo has the lowest (ESR) adequate for the dual controller design. Remember that (size) product of any aluminum electrolytic at a somewhat input protection fuse resistance, battery resistance and higher price. An additional ceramic capacitor in parallel PC board trace resistance losses are also reduced due to with OS-CON capacitors is recommended to reduce the the reduced peak currents in a multiphase system. The inductance effects. overall benefit of a multiphase design will only be fully In surface mount applications, multiple capacitors may realized when the source impedance of the power supply/ need to be used in parallel to meet ESR, RMS cur- battery is included in the efficiency testing. The drains of rent handling and load step requirements. Aluminum the two top MOSFETs should be placed within 1cm of each electrolytic, dry tantalum and special polymer capaci- other and share a common C (s). Separating the drains IN tors are available in surface mount packages. Special and C may produce undesirable voltage and current IN polymer surface mount capacitors offer very low ESR resonances at V . IN but have lower storage capacity per unit volume than The selection of C is driven by the required effective other capacitor types. These capacitors offer a very OUT series resistance (ESR). Typically once the ESR require- cost-effective output capacitor solution and are an ideal ment is satisfied the capacitance is adequate for filtering. choice when combined with a controller having high The output ripple (ΔV ) is determined by: loop bandwidth. Tantalum capacitors offer the highest OUT capacitance density and are often used as output capaci-  1  ∆V ≈∆I ESR+ tors for switching regulators having controlled soft-start. OUT L   8fCOUT Several excellent surge-tested choices are the AVX TPS, AVX TPSV or the KEMET T510 series of surface mount Where f = operating frequency, C = output capacitance, OUT tantalums, available in case heights ranging from 2mm and ΔI = ripple current in the inductor. The output ripple L to 4mm. Aluminum electrolytic capacitors can be used is highest at maximum input voltage since ΔI increases L in cost-driven applications providing that consideration with input voltage. With ΔI = 0.3I the output L OUT(MAX) is given to ripple current ratings, temperature and long ripple will typically be less than 50mV at the maximum term reliability. A typical application will require several V assuming: IN to many aluminum electrolytic capacitors in parallel. A C Recommended ESR < 2 R combination of the aforementioned capacitors will often OUT SENSE result in maximizing performance and minimizing overall and C > 1/(8fR ) OUT SENSE cost. Other capacitor types include Nichicon PL series, 3728lxff 19

LTC3728L/LTC3728LX applicaTions inForMaTion Panasonic SP, NEC Neocap, Cornell Dubilier ESRE and current drawn from the internal 3.3V linear regulator. To Sprague 595D series. Consult manufacturers for other prevent maximum junction temperature from being ex- specific recommendations. ceeded, the input supply current must be checked operating in continuous mode at maximum V . IN INTV Regulator CC EXTV Connection An internal P-channel low dropout regulator produces CC 5V at the INTVCC pin from the VIN supply pin. INTVCC The IC contains an internal P-channel MOSFET switch powers the drivers and internal circuitry within the IC. connected between the EXTV and INTV pins. When CC CC The INTVCC pin regulator can supply a peak current of the voltage applied to EXTVCC rises above 4.7V, the internal 50mA and must be bypassed to ground with a minimum regulator is turned off and the switch closes, connecting of 4.7µF tantalum, 10µF special polymer, or low ESR type the EXTV pin to the INTV pin, thereby supplying internal CC CC electrolytic capacitor. A 1µF ceramic capacitor placed di- power. The switch remains closed as long as the voltage rectly adjacent to the INTVCC and PGND IC pins is highly applied to EXTVCC remains above 4.5V. This allows the recommended. Good bypassing is necessary to supply MOSFET driver and control power to be derived from the the high transient currents required by the MOSFET gate output during normal operation (4.7V < V < 7V) and OUT drivers and to prevent interaction between channels. from the internal regulator when the output is out of regu- lation (start-up, short-circuit). If more current is required Higher input voltage applications in which large MOSFETs through the EXTV switch than is specified, an external are being driven at high frequencies may cause the maxi- CC Schottky diode can be added between the EXTV and mum junction temperature rating for the IC to be exceeded. CC INTV pins. Do not apply greater than 7V to the EXTV The system supply current is normally dominated by the CC CC pin and ensure that EXTV < V . gate charge current. Additional external loading of the CC IN INTVCC and 3.3V linear regulators also needs to be taken Significant efficiency gains can be realized by powering into account for the power dissipation calculations. The INTV from the output, since the V current resulting CC IN total INTVCC current can be supplied by either the 5V in- from the driver and control currents will be scaled by a ternal linear regulator or by the EXTVCC input pin. When factor of (Duty Cycle)/(Efficiency). For 5V regulators this the voltage applied to the EXTVCC pin is less than 4.7V, all supply means connecting the EXTVCC pin directly to VOUT. of the INTVCC current is supplied by the internal 5V linear However, for 3.3V and other lower voltage regulators, regulator. Power dissipation for the IC in this case is high- additional circuitry is required to derive INTV power CC est: (VIN)(IINTVCC), and overall efficiency is lowered. The from the output. gate charge current is dependent on operating frequency The following list summarizes the four possible connec- as discussed in the Efficiency Considerations section. tions for EXTV : The junction temperature can be estimated by using the CC equations given in Note 2 of the Electrical Characteristics. 1. EXTV Left Open (or Grounded). This will cause CC For example, the IC V current is thermally limited to less INTV to be powered from the internal 5V regulator IN CC than 67mA from a 24V supply when not using the EXTV resulting in an efficiency penalty of up to 10% at high CC pin as follows: input voltages. T = 70°C + (67mA)(24V)(34°C/W) = 125°C 2. EXTV Connected Directly to V . This is the normal J CC OUT connection for a 5V regulator and provides the highest Use of the EXTV input pin reduces the junction tem- CC efficiency. perature to: 3. EXTV Connected to an External Supply. If an external T = 70°C + (67mA)(5V)(34°C/W) = 81°C CC J supply is available in the 5V to 7V range, it may be used The absolute maximum rating for the INTV pin is 40mA. to power EXTV providing it is compatible with the CC CC Dissipation should be calculated to also include any added MOSFET gate drive requirements. 3728lxff 20

LTC3728L/LTC3728LX applicaTions inForMaTion 4. EXTV Connected to an Output-Derived Boost Network. Output Voltage CC For 3.3V and other low voltage regulators, efficiency The output voltages are each set by an external feedback gains can still be realized by connecting EXTV to an CC resistive divider carefully placed across the output capaci- output-derived voltage that has been boosted to greater tor. The resultant feedback signal is compared with the than 4.7V. This can be done with either the inductive internal precision 0.800V voltage reference by the error boost winding as shown in Figure 6a or the capacitive amplifier. The output voltage is given by the equation: charge pump shown in Figure 6b. The charge pump has the advantage of simple magnetics.  R2 VOUT =0.8V1+ R1 Topside MOSFET Driver Supply (C , D ) B B External bootstrap capacitors C connected to the BOOST where R1 and R2 are defined in Figure 2. B pins supply the gate drive voltages for the topside MOS- SENSE+/SENSE– Pins FETs. Capacitor C in the Functional Diagram is charged B though external diode DB from INTVCC when the SW pin The common mode input range of the current comparator is low. When one of the topside MOSFETs is to be turned sense pins is from 0V to (1.1)INTV . Continuous linear CC on, the driver places the CB voltage across the gate-source operation is guaranteed throughout this range allowing of the desired MOSFET. This enhances the MOSFET and output voltage setting from 0.8V to 7.7V, depending upon turns on the topside switch. The switch node voltage, SW, the voltage applied to EXTV . A differential NPN input CC rises to VIN and the BOOST pin follows. With the topside stage is biased with internal resistors from an internal 2.4V MOSFET on, the boost voltage is above the input supply: source, as shown in the Functional Diagram. This requires VBOOST = VIN + VINTVCC. The value of the boost capacitor that current either be sourced or sunk from the SENSE CB needs to be 100 times that of the total input capacitance pins depending on the output voltage. If the output voltage of the topside MOSFET(s). The reverse breakdown of the is below 2.4V, current will flow out of both SENSE pins to external Schottky diode must be greater than VIN(MAX). the main output. The output can be easily preloaded by When adjusting the gate drive level, the final arbiter is the the V resistive divider to compensate for the current OUT total input current for the regulator. If a change is made comparator’s negative input bias current. The maximum and the input current decreases, then the efficiency has current flowing out of each pair of SENSE pins is: improved. If there is no change in input current, then there I + + I – = (2.4V – V )/24k is no change in efficiency. SENSE SENSE OUT + VIN VIN 1µF OPTIONAL EXTVCC CONNECTION + + 5V < VSEC < 7V CIN CIN BAT 85 BAT85 0.22µF BAT85 VIN VSEC VIN LTC3728L/ + LTC3728L/ LTC3728LX 1µF LTC3728LX VN2222LL BAT85 TG1 TG1 RSENSE RSENSE N-CH VOUT N-CH VOUT EXTVCC SW T1 EXTVCC SW L1 1:N R6 + + FCB BG1 COUT BG1 COUT R5 N-CH N-CH SGND PGND PGND 3728 F06a 3728 F06b Figure 6a. Secondary Output Loop and EXTV Connection Figure 6b. Capacitive Charge Pump for EXTV CC CC 3728lxff 21

LTC3728L/LTC3728LX applicaTions inForMaTion Since V is servoed to the 0.8V reference voltage, Each RUN/SS pin has an internal 6V Zener clamp (see the OSENSE we can choose R1 in Figure 2 to have a maximum value Functional Diagram). to absorb this current. VIN  0.8V  3.3V OR 5V RUN/SS R1(MAX) =24k2.4V–V  D1 RSS* OUT CSS for V < 2.4V OUT Regulating an output voltage of 1.8V, the maximum value *OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF of R1 should be 32k. Note that for an output voltage above 3728 F07 2.4V, R1 has no maximum value necessary to absorb the sense currents; however, R1 is still bounded by the V Figure 7. RUN/SS Pin Interfacing OSENSE feedback current. Fault Conditions: Overcurrent Latchoff Soft-Start/Run Function The RUN/SS pins also provide the ability to latch off the controller(s) when an overcurrent condition is detected. The RUN/SS1 and RUN/SS2 pins are multipurpose pins The RUN/SS capacitor, C , is used initially to turn on that provide a soft-start function and a means to shut down SS and limit the inrush current. After the controller has been the LTC3728L/LTC3728LX. Soft-start reduces the input started and been given adequate time to charge up the power source’s surge currents by gradually increasing the output capacitor and provide full load current, the RUN/SS controller’s current limit (proportional to V ). This pin ITH capacitor is used for a short-circuit timer. If the regulator’s can also be used for power supply sequencing. output voltage falls to less than 70% of its nominal value An internal 1.2µA current source charges up the CSS after CSS reaches 4.1V, CSS begins discharging on the as- capacitor. When the voltage on RUN/SS1 (RUN/SS2) sumption that the output is in an overcurrent condition. If reaches 1.5V, the particular controller is permitted to start the condition lasts for a long enough period as determined operating. As the voltage on RUN/SS increases from 1.5V by the size of the C and the specified discharge current, SS to 3.0V, the internal current limit is increased from 25mV/ the controller will be shut down until the RUN/SS pin volt- R to 75mV/R . The output current limit ramps up age is recycled. If the overload occurs during start-up, the SENSE SENSE slowly, taking an additional 1.25s/µF to reach full cur- time can be approximated by: rent. The output current thus ramps up slowly, reducing t ≈ [C (4.1 – 1.5 + 4.1 – 3.5)]/(1.2µA) the starting surge current required from the input power LO1 SS supply. If RUN/SS has been pulled all the way to ground = 2.7 • 106 (C ) SS there is a delay before starting of approximately: If the overload occurs after start-up the voltage on C will SS 1.5V begin discharging from the Zener clamp voltage: t = C =(1.25s/µF)C DELAY SS SS 1.2µA tLO2 ≈ [CSS (6 – 3.5)]/(1.2µA) = 2.1 • 106 (CSS) This built-in overcurrent latchoff can be overridden by 3V−1.5V t = C =(1.25s/µF)C providing a pull-up resistor to the RUN/SS pin, as shown IRAMP SS SS 1.2µA in Figure 7. This resistance shortens the soft-start period and prevents the discharge of the RUN/SS capacitor By pulling both RUN/SS pins below 1V, the IC is put into during an over current condition. Tying this pull-up resis- low current shutdown (I = 20µA). The RUN/SS pins Q tor to V , as in Figure 7, defeats overcurrent latchoff. can be driven directly from logic, as shown in Figure 7. IN Diode, D1, in Figure 7 reduces the start delay but allows Why should you defeat overcurrent latchoff? During the C to ramp up slowly providing the soft-start function. prototyping stage of a design, there may be a problem SS 3728lxff 22

LTC3728L/LTC3728LX applicaTions inForMaTion with noise pickup or poor layout causing the protection Fault Conditions: Overvoltage Protection (Crowbar) circuit to latch off. Defeating this feature will easily allow The overvoltage crowbar is designed to blow a system troubleshooting of the circuit and PC layout. The internal input fuse when the output voltage of the regulator rises short-circuit and foldback current limiting still remains much higher than nominal levels. The crowbar causes huge active, thereby protecting the power supply system from currents to flow, that blow the fuse to protect against a failure. After the design is complete, a decision can be shorted top MOSFET if the short occurs while the controller made whether to enable the latchoff feature. is operating. The value of the soft-start capacitor C may need to be SS A comparator monitors the output for overvoltage con- scaled with output voltage, output capacitance and load ditions. The comparator (OV) detects overvoltage faults current characteristics. The minimum soft-start capaci- greater than 7.5% above the nominal output voltage. When tance is given by: this condition is sensed, the top MOSFET is turned off CSS > (COUT )(VOUT) (10–4) (RSENSE) and the bottom MOSFET is turned on until the overvolt- age condition is cleared. The output of this comparator The minimum recommended soft-start capacitor of C = SS is only latched by the overvoltage condition itself and 0.1µF will be sufficient for most applications. will, therefore, allow a switching regulator system hav- Fault Conditions: Current Limit and Current Foldback ing a poor PC layout to function while the design is being debugged. The bottom MOSFET remains on continuously The current comparators have a maximum sense volt- for as long as the OV condition persists. If V returns OUT age of 75mV resulting in a maximum MOSFET current to a safe level, normal operation automatically resumes. A of 75mV/R . The maximum value of current limit SENSE shorted top MOSFET will result in a high current condition generally occurs with the largest V at the highest ambi- IN which will open the system fuse. The switching regulator ent temperature, conditions that cause the highest power will regulate properly with a leaky top MOSFET by altering dissipation in the top MOSFET. the duty cycle to accommodate the leakage. Each controller includes current foldback to help further limit load current when the output is shorted to ground. Phase-Locked Loop and Frequency Synchronization The foldback circuit is active even when the overload The IC has a phase-locked loop comprised of an internal shutdown latch previously described is overridden. If the voltage controlled oscillator and phase detector. This al- output falls below 70% of its nominal output level, then lows the top MOSFET turn-on to be locked to the rising the maximum sense voltage is progressively lowered from edge of an external source. The frequency range of the 75mV to 25mV. Under short-circuit conditions with very voltage controlled oscillator is ±50% around the center low duty cycles, the controller will begin cycle skipping frequency f . A voltage applied to the PLLFLTR pin of 1.2V O in order to limit the short-circuit current. In this situation, corresponds to a frequency of approximately 400kHz. The the bottom MOSFET will be dissipating most of the power nominal operating frequency range of the IC is 260kHz to but less than in normal operation. The short-circuit ripple 550kHz. current is determined by the minimum on-time t ON(MIN) The phase detector used is an edge-sensitive digital type of each controller (typically 100ns), the input voltage and which provides zero degrees phase shift between the ex- inductor value: ternal and internal oscillators. This type of phase detector ΔI = t (V /L) L(SC) ON(MIN) IN will not lock up on input frequencies close to the harmonics The resulting short-circuit current is: of the VCO center frequency. The PLL hold-in range, ΔfH, is equal to the capture range, Δf C: 25mV 1 I = – ∆I SC L(SC) Δf = Δf = ±0.5 f (260kHz-550kHz) R 2 H C O SENSE 3728lxff 23

LTC3728L/LTC3728LX applicaTions inForMaTion The output of the phase detector is a complementary pair If the duty cycle falls below what can be accommodated of current sources charging or discharging the external by the minimum on-time, the controller will begin to skip filter network on the PLLFLTR pin. cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. If the external frequency (f ) is greater than the os- PLLIN cillator frequency, f , current is sourced continuously, The typical tested minimum on-time is 100ns under an ideal 0SC pulling up the PLLFLTR pin. When the external frequency is condition without switching noise. However, the minimum less than f , current is sunk continuously, pulling down on-time can be affected by PCB switching noise in the 0SC the PLLFLTR pin. If the external and internal frequencies voltage and current loops. With a reasonably good PCB are the same but exhibit a phase difference, the current layout, a minimum 30% inductor current ripple, approxi- sources turn on for an amount of time corresponding to mately 15mV sensing ripple voltage and 200ns minimum the phase difference. Thus, the voltage on the PLLFLTR pin on-time are conservative estimates for starting a design. is adjusted until the phase and frequency of the external and internal oscillators are identical. At this stable operat- FCB Pin Operation ing point, the phase comparator output is open and the The FCB pin can be used to regulate a secondary winding filter capacitor C holds the voltage. The IC’s PLLIN pin LP or as a logic-level input. Continuous operation is forced must be driven from a low impedance source such as a on both controllers when the FCB pin drops below 0.8V. logic gate located close to the pin. When using multiple During continuous mode, current flows continuously in ICs for a phase-locked system, the PLLFLTR pin of the the transformer primary. The secondary winding(s) draw master oscillator should be biased at a voltage that will current only when the bottom, synchronous switch is on. guarantee the slave oscillator(s) ability to lock onto the When primary load currents are low and/or the V /V IN OUT master’s frequency. A DC voltage of 0.7V to 1.7V applied ratio is low, the synchronous switch may not be on for a to the master oscillator’s PLLFLTR pin is recommended sufficient amount of time to transfer power from the output in order to meet this requirement. The resultant operating capacitor to the secondary load. Forced continuous opera- frequency can range from 300kHz to 500kHz. tion will support secondary windings providing there is The loop filter components (C , R ) smooth out the sufficient synchronous switch duty factor. Thus, the FCB LP LP current pulses from the phase detector and provide a input pin removes the requirement that power must be stable input to the voltage controlled oscillator. The filter drawn from the inductor primary in order to extract power components, C and R , determine how fast the loop from the auxiliary windings. With the loop in continuous LP LP acquires lock. Typically, R = 10kΩ and C is 0.01µF mode, the auxiliary outputs may nominally be loaded LP LP to 0.1µF. without regard to the primary output load. The secondary output voltage, V , is normally set as SEC Minimum On-Time Considerations shown in Figure 6a by the turns ratio N of the transformer: Minimum on-time, t , is the smallest time dura- ON(MIN) V @ (N + 1) V SEC OUT tion that each controller is capable of turning on the top MOSFET. It is determined by internal timing delays and the However, if the controller goes into Burst Mode operation gate charge required to turn on the top MOSFET. Low duty and halts switching due to a light primary load current, cycle applications may approach this minimum on-time then VSEC will droop. An external resistive divider from limit and care should be taken to ensure that: VSEC to the FCB pin sets a minimum voltage VSEC(MIN): V  R6 tON(MIN) < VOU(Tf) VSEC(MIN) ≈0.8V1+R5 IN where R5 and R6 are shown in Figure 2. 3728lxff 24

LTC3728L/LTC3728LX applicaTions inForMaTion If V drops below this level, the FCB voltage forces The resistive load reduces the DC loop gain while main- SEC temporary continuous switching operation until V is taining the linear control range of the error amplifier. The SEC again above its minimum. maximum output voltage deviation can theoretically be reduced to half, or alternatively the amount of output In order to prevent erratic operation if no external connec- capacitance can be reduced for a particular application. tions are made to the FCB pin, the FCB pin has a 0.18µA A complete explanation is included in Design Solutions internal current source pulling the pin high. Include this 10 (see www.linear.com). current when choosing resistor values R5 and R6. The following table summarizes the possible states avail- Efficiency Considerations able on the FCB pin: The percent efficiency of a switching regulator is equal to Table 1 the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine FCB Pin Condition what is limiting the efficiency and which change would 0V to 0.75V Forced Continuous Both Controllers (Current Reversal Allowed— Burst Inhibited) produce the most improvement. Percent efficiency can 0.85V < V < 4.3V Minimum Peak Current Induces be expressed as: FCB Burst Mode Operation No Current Reversal Allowed %Efficiency = 100% – (L1 + L2 + L3 + ...) Feedback Resistors Regulating a Secondary Winding where L1, L2, etc. are the individual losses as a percent- >4.8V Burst Mode Operation Disabled age of input power. Constant-Frequency Mode Enabled No Current Reversal Allowed Although all dissipative elements in the circuit produce No Minimum Peak Current losses, four main sources usually account for most of the Voltage Positioning losses in LTC3728L/LTC3728LX circuits: 1) IC VIN current (including loading on the 3.3V internal regulator), 2) IN- Voltage positioning can be used to minimize peak-to-peak TV regulator current, 3) I2R losses, 4) Topside MOSFET CC output voltage excursions under worst-case transient transition losses. loading conditions. The open-loop DC gain of the control loop is reduced depending upon the maximum load step 1. The VIN current has two components: the first is the specifications. Voltage positioning can easily be added DC supply current given in the Electrical Characteristics to either or both controllers by loading the I pin with table, which excludes MOSFET driver and control cur- TH a resistive divider having a Thevenin equivalent voltage rents; the second is the current drawn from the 3.3V source equal to the midpoint operating voltage range of linear regulator output. VIN current typically results in the error amplifier, or 1.2V (see Figure 8). a small (<0.1%) loss. 2. INTV current is the sum of the MOSFET driver and CC control currents. The MOSFET driver current results from INTVCC switching the gate capacitance of the power MOSFETs. RT2 Each time a MOSFET gate is switched from low to high ITH LTC3728L/ to low again, a packet of charge dQ moves from INTV RT1 RC LTC3728LX CC to ground. The resulting dQ/dt is a current out of INTV CC CC that is typically much larger than the control circuit 3728 F08 current. In continuous mode, I = f(Q + Q ), GATECHG T B where Q and Q are the gate charges of the topside T B Figure 8. Active Voltage Positioning and bottom side MOSFETs. Applied to the LTC3728L/LTC3728LX 3728lxff 25

LTC3728L/LTC3728LX applicaTions inForMaTion Supplying INTV power through the EXTV switch losses can be minimized by making sure that C has ad- CC CC IN input from an output-derived source will scale the V equate charge storage and very low ESR at the switching IN current required for the driver and control circuits by frequency. A 25W supply will typically require a minimum a factor of (Duty Cycle)/(Efficiency). For example, in a of 20µF to 40µF of capacitance having a maximum of 20mΩ 20V to 5V application, 10mA of INTV current results to 50mΩ of ESR. The LTC3728L 2-phase architecture CC in approximately 2.5mA of V current. This reduces the typically halves this input capacitance requirement over IN mid-current loss from 10% or more (if the driver was competing solutions. Other losses, including Schottky con- powered directly from V ) to only a few percent. duction losses during dead time and inductor core losses, IN generally account for less than 2% total additional loss. 3. I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor, current sense resis- Checking Transient Response tor, and input and output capacitor ESR. In continuous mode the average output current flows through L and The regulator loop response can be checked by looking at R , but is “chopped” between the topside MOSFET the load current transient response. Switching regulators SENSE and the synchronous MOSFET. If the two MOSFETs have take several cycles to respond to a step in DC (resistive) approximately the same RDS(ON), then the resistance of load current. When a load step occurs, VOUT shifts by an one MOSFET can simply be summed with the resistances amount equal to ΔILOAD (ESR), where ESR is the effective of L, RSENSE and ESR to obtain I2R losses. For example, series resistance of COUT. ΔILOAD also begins to charge or if each RDS(ON) = 30mΩ, RL = 50mΩ, RSENSE = 10mΩ discharge COUT generating the feedback error signal that and R = 40mΩ (sum of both input and output ca- forces the regulator to adapt to the current change and ESR pacitance losses), then the total resistance is 130mΩ. return VOUT to its steady-state value. During this recovery This results in losses ranging from 3% to 13% as the time, VOUT can be monitored for excessive overshoot or output current increases from 1A to 5A for a 5V output, ringing, which would indicate a stability problem. OPTI- or a 4% to 20% loss for a 3.3V output. Efficiency var- LOOP compensation allows the transient response to be ies as the inverse square of V for the same external optimized over a wide range of output capacitance and OUT components and output power level. The combined ESR values. The availability of the ITH pin not only allows effects of increasingly lower output voltages and higher optimization of control loop behavior but also provides currents required by high performance digital systems a DC coupled and AC filtered closed loop response test is not doubling, but quadrupling, the importance of loss point. The DC step, rise time and settling at this test terms in the switching regulator system! point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/ 4. Transition losses apply only to the topside MOSFET(s), or damping factor can be estimated using the percentage and become significant only when operating at high input of overshoot seen at this pin. The bandwidth can also be voltages (typically 15V or greater). Transition losses can estimated by examining the rise time at the pin. The I TH be estimated from: external components shown in the Figure 1 circuit will Transition Loss = (V )2 •IMAX(R )• provide an adequate starting point for most applications. IN  2  DR The I series R -C filter sets the dominant pole-zero TH C C  1 1  loop compensation. The values can be modified slightly (C )(f) + MILLER 5V–V V  (from 0.5 to 2 times their suggested values) to optimize TH TH transient response once the final PC layout is done and Other “hidden” losses such as copper trace and internal the particular output capacitor type and value have been battery resistances can account for an additional 5% to determined. The output capacitors need to be selected 10% efficiency degradation in portable systems. It is very because the various types and values determine the loop important to include these system level losses during the gain and phase. An output current pulse of 20% to 80% design phase. The internal battery and fuse resistance of full-load current having a rise time of 1µs to 10µs will 3728lxff 26

LTC3728L/LTC3728LX applicaTions inForMaTion produce output voltage and I pin waveforms that will Automotive Considerations: Plugging into the TH give a sense of the overall loop stability without break- Cigarette Lighter ing the feedback loop. Placing a power MOSFET directly As battery-powered devices go mobile, there is a natural across the output capacitor and driving the gate with an interest in plugging into the cigarette lighter in order to appropriate signal generator is a practical way to produce conserve or even recharge battery packs during operation. a realistic load step condition. The initial output voltage But before you connect, be advised: you are plugging step resulting from the step change in output current may into the supply from hell. The main power line in an not be within the bandwidth of the feedback loop, so this automobile is the source of a number of nasty potential signal cannot be used to determine phase margin. This transients, including load-dump, reverse-battery and is why it is better to look at the I pin signal, which is TH double-battery. in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be in- Load-dump is the result of a loose battery cable. When the creased by increasing R and the bandwidth of the loop cable breaks connection, the field collapse in the alterna- C will be increased by decreasing C . If R is increased by tor can cause a positive spike as high as 60V which takes C C the same factor that C is decreased, the zero frequency several hundred milliseconds to decay. Reverse-battery is C will be kept the same, thereby keeping the phase shift the just what it says, while double-battery is a consequence of same in the most critical frequency range of the feedback tow truck operators finding that a 24V jump start cranks loop. The output voltage settling behavior is related to the cold engines faster than 12V. stability of the closed-loop system and will demonstrate The network shown in Figure 9 is the most straightforward the actual overall supply performance. approach to protect a DC/DC converter from the ravages of A second, more severe transient is caused by switching an automotive power line. The series diode prevents current in loads with large (>1µF) supply bypass capacitors. The from flowing during reverse-battery, while the transient discharged bypass capacitors are effectively put in parallel suppressor clamps the input voltage during load-dump. with C , causing a rapid drop in V . No regulator can Note that the transient suppressor should not conduct OUT OUT alter its delivery of current quickly enough to prevent this during double-battery operation, but must still clamp the sudden step change in output voltage if the load switch input voltage below breakdown of the converter. Although resistance is low and it is driven quickly. If the ratio of the LTC3728L/LTC3728LX have a maximum input voltage C to C is greater than 1:50, the switch rise time of 30V, most applications will also be limited to 30V by LOAD OUT should be controlled so that the load rise time is limited the MOSFET BVD . SS to approximately 25 • C . Thus a 10µF capacitor would LOAD require a 250µs rise time, limiting the charging current to about 200mA. 50A IPK RATING VIN 12V LTC3728L/ LTC3728LX TRANSIENT VOLTAGE SUPPRESSOR GENERAL INSTRUMENT 1.5KA24A 3728 F09 Figure 9. Automotive Application Protection 3728lxff 27

LTC3728L/LTC3728LX applicaTions inForMaTion Design Example Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields an output voltage of 1.816V. As a design example for one channel, assume V = 12V IN (nominal), V = 22V(max), V = 1.8V, I = 5A and The power dissipation on the topside MOSFET can be easily IN OUT MAX f = 300kHz. estimated. Choosing a Fairchild FDS6982S dual MOSFET results in: R = 0.035Ω/0.022Ω, C = 215pF. At The inductance value is chosen first based on a 30% ripple DS(ON) MILLER maximum input voltage with T(estimated) = 50°C: current assumption. The highest value of ripple current occurs at the maximum input voltage. Tie the PLLFLTR P = 1.8V(5)2[1+(0.005)(50°C–25°C)]• MAIN pin to a resistive divider from the INTV pin, generating 22V CC 03.07%V froiprp 3le0 0ckuHrrze onpt eisr:ation. The minimum inductance for (0.035Ω)+(22V)25A(4Ω)(215pF)•  2  ∆IL = VOUT 1– VOUT  1 + 1 (300kHz)=332mW (f)(L) VIN  5–2.3 2.3 A 4.7µH inductor will produce 23% ripple current and a A short-circuit to ground will result in a folded back 3.3µH will result in 33%. The peak inductor current will be current of: the maximum DC value plus one half the ripple current, or 5.84A, for the 3.3µH value. Increasing the ripple current will 25mV 1120ns(22V) I = – =2.1A also help ensure that the minimum on-time of 200ns is not SC 0.01Ω 2 3.3µH  violated. The minimum on-time occurs at maximum V : IN with a typical value of R and d = (0.005/°C)(20) = 0.1. V 1.8V DS(ON) t = OUT = =273ns The resulting power dissipated in the bottom MOSFET is: ON(MIN) V f 22V(300kHz) IN(MAX) P = 22V–1.8V(2.1A)2(1.125)(0.022Ω) SYNC 22V The R resistor value can be calculated by using the SENSE maximum current sense voltage specification with some =100mW accommodation for tolerances: which is less than under full-load conditions. 60mV C is chosen for an RMS current rating of at least 3A at R ≤ ≈0.01Ω IN SENSE 5.84A temperature assuming only this channel is on. COUT is chosen with an ESR of 0.02Ω for low output ripple. The Since the output voltage is below 2.4V, the output resistive output ripple in continuous mode will be highest at the divider will need to be sized to not only set the output voltage maximum input voltage. The output voltage ripple due to but also to absorb the SENSE pin’s specified input current. ESR is approximately:  0.8V  V = R (ΔI ) = 0.02Ω(1.67A) = 33mV ORIPPLE ESR L P–P R1 =24k (MAX)   2.4V–V  OUT  0.8V  =24k  =32k 2.4V–1.8V 3728lxff 28

LTC3728L/LTC3728LX applicaTions inForMaTion PC Board Layout Checklist 4. Are the SENSE– and SENSE+ leads routed together with minimum PC trace spacing? The filter capacitor When laying out the printed circuit board, the following between SENSE+ and SENSE– should be as close as checklist should be used to ensure proper operation of possible to the IC. Ensure accurate current sensing the IC. These items are also illustrated graphically in the with Kelvin connections at the SENSE resistor. layout diagram of Figure 10. Figure 11 illustrates the cur- rent waveforms present in the various branches of the 5. Is the INTV decoupling capacitor connected close to CC 2-phase synchronous regulators operating in the continu- the IC, betweenthe INTV and the power ground pins? CC ous mode. Check the following in your layout: This capacitor carries the MOSFET drivers current peaks. An additional 1µF ceramic capacitor placed immediately 1. Are the top N-channel MOSFETs M1 and M3 located with- next to the INTV and PGND pins can help improve in 1cm of each other with a common drain connection CC noise performance substantially. at C ? Do not attempt to split the input decoupling for IN the two channels as it can cause a large resonant loop. 6. Keep the switching nodes (SW1, SW2), top gate nodes (TG1, TG2), and boost nodes (BOOST1, BOOST2) away 2. Are the signal and power grounds kept separate? The from sensitive small-signal nodes, especially from the combined IC signal ground pin and the ground return opposites channel’s voltage and current sensing feed- of C must return to the combined C (–) termi- INTVCC OUT back pins. All of these nodes have very large and fast nals. The path formed by the top N-channel MOSFET, moving signals and therefore should be kept on the Schottky diode and the C capacitor should have short IN output side of the LTC3728L/LTC3728LX and occupy leads and PC trace lengths. The output capacitor (–) minimum PC trace area. terminals should be connected as close as possible to the (–) terminals of the input capacitor by placing 7. Use a modified “star ground” technique: a low imped- the capacitors next to each other and away from the ance, large copper area central grounding point on Schottky loop just described. the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTV 3. Do the LTC3728L/LTC3728LX V pins’ resistive CC OSENSE decoupling capacitor, the bottom of the voltage feedback dividers connect to the (+) terminals of C ? The resis- OUT resistive divider and the SGND pin of the IC. tive divider must be connected between the (+) terminal of C and signal ground. The R2 and R4 connections OUT should not be along the high current input feeds from the input capacitor(s). 3728lxff 29

LTC3728L/LTC3728LX applicaTions inForMaTion RPU VPULL-UP (<7V) RUN/SS1 PGOOD PGOOD L1 RSENSE SENSE1+ TG1 VOUT1 R2 SENSE1– SW1 R1 CB1 M1 M2 VOSENSE1 BOOST1 D1 PLLFLTR VIN fIN PLLIN BG1 1µF COUT1 RIN CERAMIC + INTVCC FCB EXTVCC LTC3728L/LTC3728LX CVIN GND + ITH1 INTVCC + VIN CIN + CINTVCC SGND PGND 1µF COUT2 CERAMIC 3.3V 3.3VOUT BG2 M3 M4 ITH2 BOOST2 D2 CB2 VOSENSE2 SW2 R3 R4 RSENSE SENSE2– TG2 VOUT2 L2 SENSE2+ RUN/SS2 3728 F10 Figure 10. LTC3728L/LTC3728LX Recommended Printed Circuit Layout Diagram 3728lxff 30

LTC3728L/LTC3728LX applicaTions inForMaTion SW1 L1 RSENSE1 VOUT1 + D1 COUT1 RL1 CERAMIC VIN RIN + CIN SW2 L2 RSENSE2 VOUT2 + BOLD LINES INDICATE D2 COUT2 RL2 HIGH SWITCHING CERAMIC CURRENT. KEEP LINES TO A MINIMUM LENGTH. 3728 F11 Figure 11. Branch Current Waveforms 3728lxff 31

LTC3728L/LTC3728LX applicaTions inForMaTion PC Board Layout Debugging Reduce V from its nominal level to verify operation of IN the regulator in dropout. Check the operation of the un- Start with one controller on at a time. It is helpful to use dervoltage lockout circuit by further lowering V while a DC-50MHz current probe to monitor the current in the IN monitoring the outputs to verify operation. inductor while testing the circuit. Monitor the output switch- ing node (SW pin) to synchronize the oscilloscope to the Investigate whether any problems exist only at higher out- internal oscillator and probe the actual output voltage as put currents or only at higher input voltages. If problems well. Check for proper performance over the operating coincide with high input voltages and low output currents, voltage and current range expected in the application. The look for capacitive coupling between the BOOST, SW, TG, frequency of operation should be maintained over the input and possibly BG connections and the sensitive voltage voltage range down to dropout and until the output load and current pins. The capacitor placed across the current drops below the low current operation threshold—typically sensing pins needs to be placed immediately adjacent to 10% to 20% of the maximum designed current level in the pins of the IC. This capacitor helps to minimize the Burst Mode operation. effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with The duty cycle percentage should be maintained from cycle high current output loading at lower input voltages, look to cycle in a well designed, low noise PCB implementation. for inductive coupling between C , Schottky and the top Variation in the duty cycle at a subharmonic rate can sug- IN MOSFET components to the sensitive current and voltage gest noise pickup at the current or voltage sensing inputs sensing traces. In addition, investigate common ground or inadequate loop compensation. Overcompensation of path voltage pickup between these components and the the loop can be used to tame a poor PC layout if regulator SGND pin of the IC. bandwidth optimization is not required. Only after each controller is checked for its individual performance should An embarrassing problem, which can be missed in an both controllers be turned on at the same time. A particularly otherwise properly working switching regulator, results difficult region of operation is when one controller channel when the current sensing leads are hooked up backwards. is nearing its current comparator trip point when the other The output voltage under this improper hookup will still channel is turning on its top MOSFET. This occurs around be maintained but the advantages of current mode control 50% duty cycle on either channel due to the phasing of will not be realized. Compensation of the voltage loop will the internal clocks and may cause minor duty cycle jitter. be much more sensitive to component selection. This behavior can be investigated by temporarily shorting out Short-circuit testing can be performed to verify proper the current sensing resistor—don’t worry, the regulator overcurrent latchoff, or 5µA can be provided to the RUN/ will still maintain control of the output voltage. SS pin(s) by resistors from V to prevent the short-circuit IN latchoff from occurring. 3728lxff 32

LTC3728L/LTC3728LX Typical applicaTions 59k 1M 100k VPULL-UP MBRS1100T3 + (<7V) T1, 1:1.8 33µF RUN/SS1 PGOOD PGOOD 10µH 25V 0.1µF 0.015Ω VOUT1 SENSE1+ TG1 5V 180pF 1000pF M1 3A; 4A PEAK 20k 105k, 1% SENSE1– SW1 8 5 1% 0.1µF Q1 Q2 LT1121 ON/OFF VOSENSE1 BOOST1 D1 3 2 1 220k VOUT3 PLLFLTR VIN 12V 120mA PLLIN BG1 150µF, 6.3V + 33pF 10Ω 22µF PANASONIC SP 100k 1µF FCB EXTVCC CMDSH-3TR 50V + 25V LTC3728L/LTC3728LX 0.1µF GND + 15k ITH1 INTVCC 1µF + 1000pF 10V 4.7µF 180µF, 4V SGND PGND PANASONIC SP VIN 33pF CMDSH-3TR M2 7V TO 28V 3.3V 3.3VOUT BG2 Q3 Q4 ITH2 BOOST2 D2 15k 0.1µF 1000pF 20k VOSENSE2 SW2 1% VOUT2 SENSE2– TG2 3.3V 63.4k 1000pF L1 0.01Ω 5A; 6A PEAK 180pF 1% SENSE2+ RUN/SS2 6.3µH 0.1µF 3728 F12 VIN: 7V TO 28V VOUT: 5V, 3A/3.3V, 6A/12V, 150mA SWITCHING FREQUENCY = 250kHz MI, M2: FDS6982S OR VISHAY Si4810DY L1: SUMIDA CEP123-6R3MC T1: 10µH 1:1.8 — DALE LPE6562-A262 GAPPED E-CORE OR BH ELECTRONICS #501-0657 GAPPED TOROID Figure 12. LTC3728L/LTC3728LX High Efficiency Low Noise 5V/3A, 3.3V/5A, 12V/120mA Regulator 3728lxff 33

LTC3728L/LTC3728LX Typical applicaTions VPULL-UP (<7V) RUN/SS1 PGOOD PGOOD L1 4.3µH 0.1µF 0.008Ω SENSE1+ TG1 VOUT1 5V/4A 180pF 1000pF 105k 20k 1% SENSE1– SW1 1% 0.1µF Q1 Q2 VOSENSE1 BOOST1 PIN 4 M1 0.01µF PLLFLTR VIN 1µF 50V 10k 1000pF fSYNC PLLIN BG1 100pF 10Ω 22µF + CMDSH-3TR 50V FLCTBC3728L/LTC37E2X8TLVXCC 0.1µF 150µF, 6.3V GND 8.06k 1500pF ITH1 INTVCC 1µF 4+.7µF, 10V 1µF 50V + 100pF SGND PGND CMDSH-3TR 180µF, 4V VIN 7V TO 3.3V 3.3VOUT BG2 28V PIN 4 ITH2 BOOST2 Q3 Q4 4.75k 0.1µF 1000pF 20k VOSENSE2 SW2 M2 1% SENSE2– TG2 VOUT2 3.3V/5A 63.4k 1000pF L2 0.008Ω 180pF 1% SENSE2+ RUN/SS2 4.3µH 0.1µF 3728 F13 VIN: 7V TO 28V SWITCHING FREQUENCY = 250kHz TO 550kHz L1, L2: SUMIDA CDEP105-4R3MC-88 VOUT: 5V, 4A/3.3V, 5A M1, M2: FDS6982S OR VISHAY Si4810DY OUTPUT CAPACITORS: PANASONIC SP SERIES Figure 13. LTC3728L/LTC3728LX 5V/4A, 3.3V/5A Regulator with External Frequency Synchronization 3728lxff 34

LTC3728L/LTC3728LX package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. GN Package 28-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .386 – .393* .045 ±.005 (9.804 – 9.982) .033 (0.838) 28 27 26 25 24 23 22 21 20 19 18 17 1615 REF .254 MIN .150 – .165 .229 – .244 .150 – .157** (5.817 – 6.198) (3.810 – 3.988) .0165 ±.0015 .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 .015 ± .004 × 45°(cid:28) .0532 – .0688 .004 – .0098 (0.38 ± 0.10) (1.35 – 1.75) (0.102 – 0.249) .0075 – .0098 0° – 8° TYP (0.19 – 0.25) .016 – .050 .008 – .012 .0250 GN28 (SSOP) 0204 (0.406 – 1.270) (0.203 – 0.305) (0.635) NOTE: TYP BSC 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 3728lxff 35

LTC3728L/LTC3728LX package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693 Rev D) 0.70 ±0.05 5.50 ±0.05 4.10 ±0.05 3.45 ± 0.05 3.50 REF (4 SIDES) 3.45 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.30 TYP 5.00 ± 0.10 0.75 ± 0.05 R = 0T.Y0P5 R = 0.T1Y1P5 OR 0.35 × 45° CHAMFER (4 SIDES) 0.00 – 0.05 31 32 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 3.45 ± 0.10 3.50 REF (4-SIDES) 3.45 ± 0.10 (UH32) QFN 0406 REV D 0.200 REF 0.25 ± 0.05 0.50 BSC NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3728lxff 36

LTC3728L/LTC3728LX revision hisTory (Revision history begins at Rev F) REV DATE DESCRIPTION PAGE NUMBER F 12/11 Added labels D1 and D2 to the Typical Application. 1 Corrected pin name for the GN Package Pin 3 to SENSE1–. 2 Changed Note 3 to Note 8 on g on the Electrical Characteristics Table. 4 mGBW1,2 Added new Note 8: Guaranteed by design. 5 Updated threshold on BINH to 4.3V on the Functional Diagram. 11 Updated threshold on EXTV to 4.7V on the Functional Diagram. 11 CC Replaced the Related Parts list. 36 3728lxff 37 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC3728L/LTC3728LX Typical applicaTion IIN 12VIN CIN I1 IIN* 0° BUCK: 2.5V/15A OPEN PHASMD TG1 U1 TG2 180° BUCK: 2.5V/15A 2.5VO/30A I1 LTC3729 90° CLKOUT I2 I2 I3 I3 90° BUCK: 1.5V/15A 1.5VO/15A U2 TTGG12 270° 1.8VO/15A I4 BUCK: 1.8V/15A LTC3728L/ *INPUT RIPPLE CURRENT CANCELLATION 90° LTC3728LX I4 INCREASES THE RIPPLE FREQUENCY AND PLLIN REDUCES THE RMS INPUT RIPPLE CURRENT 3728 F14 THUS, SAVING INPUT CAPACITORS Figure 14. Multioutput PolyPhase® Application relaTeD parTs PART NUMBER DESCRIPTION COMMENTS LTC3880/LTC3880-1 Dual Output PolyPhase Step-Down DC/DC Controller with I2C/PMBus Interface with EEPROM and 16-Bit ADC Digital Power System Management V Up to 24V, 0.5V ≤ V ≤ 5.5V, Analog Control Loop IN OUT LTC3869/LTC3869-2 Dual Output, 2-Phase Synchronous Step-Down DC/DC Controller, PLL Fixed 250kHz to 750kHz Frequency, 4V ≤ V ≤ 38V, IN with Accurate Current Share 0.6V ≤ V ≤ 12.5V OUT LTC3855 Dual Output, 2-Phase, Synchronous Step-Down DC/DC Controller PLL Fixed Frequency 250kHz to 770kHz, 4.5V ≤ V ≤ 38V, IN with Differential Amplifier and DCR Temperature Compensation 0.8V ≤ V ≤ 12V OUT LTC3838 Dual, Multiphase, Controlled On-Time, High Frequency Up to 2MHz Operating Frequency, 4V ≤ V ≤ 38V, IN Synchronous Step-Down Controller with Differential Amplifier 0.8V ≤ V ≤ 5.5V, 3mm × 4mm QFN-20, TSSOP-20E OUT LTC3860 Dual, Multiphase, Synchronous Step-Down DC/DC Controller with Operates with Power Blocks, DRMOS Devices or Differential Amplifier and Three-State Output Drive External Drivers/MOSFETs, 3V ≤ V ≤ 24V, t = 20ns IN ON(MIN) LTC3850/LTC3850-1/ Dual Output, 2-Phase Synchronous Step-Down DC/DC Controller, PLL Fixed 250kHz to 780kHz Frequency, 4V ≤ V ≤ 30V, IN LTC3850-2 R or DCR Current Sensing 0.8V ≤ V ≤ 5.25V SENSE OUT LTC3856 Single Output 2-Channel Synchronous Step-Down DC/DC PLL Fixed 250kHz to 770kHz Frequency, 4.5V ≤ V ≤ 38V, IN Controller with Differential Amplifier and Up to 12-Phase Operation 0.8V ≤ V ≤ 5V OUT LTC3829 Single Output 3-Channel Synchronous Step-Down DC/DC Phase-Lockable Fixed 250kHz to 770kHz Frequency, Controller with Differential Amplifier and Up to 6-Phase Operation 4.5V ≤ V ≤ 38V, 0.8V ≤ V ≤ 5V IN OUT LTC3853 Triple Output, Multiphase Synchronous Step-Down DC/DC PLL Fixed 250kHz to 750kHz Frequency, 4V ≤ V ≤ 24V, IN Controller, R or DCR Current Sensing and Tracking V Up to 13.5V SENSE OUT3 3728lxff 38 Linear Technology Corporation LT 1211 REV F • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2002