LTC3728 Dual, 550kHz, 2-Phase Synchronous Step-Down Switching Regulator FEATURES DESCRIPTION n Dual, 180° Phased Controllers Reduce Required The LTC®3728 is a dual high performance step-down Input Capacitance and Power Supply Induced Noise switching regulator controller that drives all N-channel n OPTI-LOOP® Compensation Minimizes C synchronous power MOSFET stages. A constant-frequency OUT n ±1% Output Voltage Accuracy current mode architecture allows phase-lockable frequency n Power Good Output Voltage Indicator of up to 550kHz. Power loss and noise due to the ESR of n Phase-Lockable Fixed Frequency 250kHz to 550kHz the input capacitors are minimized by operating the two n Dual N-Channel MOSFET Synchronous Drive controller output stages out of phase. n Wide V Range: 3.5V to 36V Operation IN OPTI-LOOP compensation allows the transient response to n Very Low Dropout Operation: 99% Duty Cycle be optimized over a wide range of output capacitance and n Adjustable Soft-Start Current Ramping ESR values. The precision 0.8V reference and power good n Foldback Output Current Limiting output indicator are compatible with future microprocessor n Latched Short-Circuit Shutdown with Defeat Option generations, and a wide 3.5V to 30V (36V maximum) input n Output Overvoltage Protection supply range encompasses all battery chemistries. n Remote Output Voltage Sense n Low Shutdown I : 20μA A RUN/SS pin for each controller provides both soft- Q n 5V and 3.3V Regulators start and optional timed, short-circuit shutdown. Current n 3 Selectable Operating Modes: Constant-Frequency, foldback limits MOSFET dissipation during short-circuit Burst Mode® Operation and PWM conditions when overcurrent latchoff is disabled. Output n Available in 32-Pin 5mm × 5mm QFN and overvoltage protection circuitry latches on the bottom 28-Pin SSOP Packages MOSFET until V returns to normal. The FCB mode OUT pin can select among Burst Mode, constant-frequency APPLICATIONS mode and continuous inductor current mode or regulate n Notebook and Palmtop Computers a secondary winding. The LTC3728 includes a power good n Telecom Systems output pin that indicates when both outputs are within n Portable Instruments 7.5% of their designed set point. n Battery-Operated Digital Devices L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode and OPTI-LOOP are n DC Power Distribution Systems registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5929620, 6177787, 6144194, 6100678, 5408150, 6580258, 5705919. TYPICAL APPLICATION M1 4.7μF+ D3 VIN PGOOD INTVCC D4 1μF M2 C2520INμVF V5.I2NV TO 28V TG1 TG2 L1 L2 BOOST1 BOOST2 3.2μH CB1, 0.1μF CB2, 0.1μF 3.2μH SW1 SW2 LTC3728 BG1 BG2 500kfHINz PLLIN PGND SENSE1+ SENSE2+ RSENSE1 1000pF 1000pF RSENSE2 0.01Ω 0.01Ω SENSE1– SENSE2– VOU55TVA1 + C47OμUFT111R0%52k R1 C22C01pF RVITUOHSN1E/SNSSE11 SGNDVROUSNEN/ISTSHSE222 22C0pCF2 R3 613R%.44k C56OμUFT + V35.AO3UVT2 6SVP 210%k R15Ck1 0C.1SμSF1 C0.S1Sμ2F R15Ck2 210%k S6VP M1, M2: FDS6982S 3728 F01 Figure 1. High Effi ciency Dual 5V/3.3V Step-Down Converter 3728fg 1

LTC3728 ABSOLUTE MAXIMUM RATINGS (Note 1) Input Supply Voltage (V ) .........................36V to –0.3V I I , V , V Voltages ...2.7V to –0.3V IN TH1, TH2 OSENSE1 OSENSE2 Topside Driver Voltages Peak Output Current <10μs (TG1, TG2, BG1, BG2) .....3A (BOOST1, BOOST2) ...............................42V to –0.3V INTV Peak Output Current ................................. 50mA CC Switch Voltage (SW1, SW2) .........................36V to –5V Operating Temperature Range (Note 7)....–40°C to 85°C INTV EXTV , RUN/SS1, RUN/SS2, Junction Temperature (Note 2) .............................125°C CC, CC (BOOST1-SW1), (BOOST2-SW2), PGOOD .....7V to –0.3V Storage Temperature Range ...................–65°C to 125°C SENSE1+, SENSE2+, SENSE1–, Lead Temperature (Soldering, 10 sec) SENSE2– Voltages .........................(1.1)INTV to –0.3V (G Package Only) ..................................................300°C CC PLLIN, PLLFLTR, FCB Voltages ............INTV to –0.3V CC PIN CONFIGURATION TOP VIEW TOP VIEW RSUENNS/SES11+ 12 2287 PTGG1OOD NC–SENSE1+SENSE1 NC RUN/SS1 PGOOD TG1 SW1 SENSE1– 3 26 SW1 32 31 30 29 28 27 26 25 VOSENSE1 4 25 BOOST1 VOSENSE1 1 24 BOOST1 PLLFLTR 5 24 VIN PLLFLTR 2 23 VIN PLLIN 6 23 BG1 PLLIN 3 22 BG1 FCB 7 22 EXTVCC FCB 4 33 21 EXTVCC ITH1 8 21 INTVCC ITH1 5 20 INTVCC SGND 6 19 PGND SGND 9 20 PGND 3.3VOUT 7 18 BG2 3.3VOUT 10 19 BG2 ITH2 8 17 BOOST2 ITH2 11 18 BOOST2 9 10 11 12 13 14 15 16 VSSOEESNNESSNEES22E2–+ 111234 111765 STRGWU2N2/SS2 VOSENSE2 NC–SENSE2+SENSE2 RUN/SS2 TG2 SW2 NC G PACKAGE UH PACKAGE 28-LEAD PLASTIC SSOP 32-LEAD (5mm × 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 90°C/W - SINGLE LAYER BOARD TJMAX = 125°C, θJA = 34°C/W 68º C/W - 4 LAYER EXPOSED PAD IS SGND (MUST BE SOLDERED TO PCB) ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3728EG#PBF LTC3728EG#TRPBF LTC3728EG 28-Lead Plastic SSOP –40°C to 85°C LTC3728IG#PBF LTC3728IG#TRPBF LTC3728IG 28-Lead Plastic SSOP –40°C to 85°C LTC3728EUH#PBF LTC3728EUH#TRPBF 3728 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C LTC3728IUH#PBF LTC3728IUH#TRPBF 3728 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3728EG LTC3728EG#TR LTC3728EG 28-Lead Plastic SSOP –40°C to 85°C LTC3728IG LTC3728IG#TR LTC3728IG 28-Lead Plastic SSOP –40°C to 85°C LTC3728EUH LTC3728EUH#TR 3728 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C LTC3728IUH LTC3728IUH#TR 3728 32-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/ 3728fg 2

LTC3728 ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = 15V, V = 5V unless otherwise noted. A IN RUN/SS1, 2 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loops V Regulated Feedback Voltage (Note 3); I Voltage = 1.2V l 0.792 0.800 0.808 V OSENSE1, 2 TH1, 2 I Feedback Current (Note 3) –5 –50 nA OSENSE1, 2 V Reference Voltage Line Regulation V = 3.6V to 30V (Note 3) 0.002 0.02 %/V REFLNREG IN V Output Voltage Load Regulation (Note 3) LOADREG Measured in Servo Loop; ΔI Voltage = 1.2V to 0.7V l 0.1 0.5 % TH Measured in Servo Loop; ΔI Voltage = 1.2V to 2.0V l –0.1 –0.5 % TH g Transconductance Amplifi er g I = 1.2V; Sink/Source 5μA (Note 3) 1.3 mmho m1, 2 m TH1, 2 g Transconductance Amplifi er GBW I = 1.2V (Note 3) 3 MHzI mGBW1, 2 TH1, 2 Q Input DC Supply Current (Note 4) Normal Mode V = 15V; EXTV Tied to V ; V = 5V 450 μA IN CC OUT1 OUT1 Shutdown V = 0V 20 35 μA RUN/SS1, 2 V Forced Continuous Threshold l 0.76 0.800 0.84 V FCB I Forced Continuous Pin Current V = 0.85V –0.50 –0.18 –0.1 μA FCB FCB V Burst Inhibit (Constant-Frequency) Measured at FCB Pin 4.3 4.8 V BINHIBIT Threshold UVLO Undervoltage Lockout V Ramping Down l 3.5 4 V IN V Feedback Overvoltage Lockout Measured at V l 0.84 0.86 0.88 V OVL OSENSE1, 2 I Sense Pins Total Source Current (Each Channel); V – – = V + + = 0V –85 –60 μA SENSE SENSE1 , 2 SENSE1 , 2 DF Maximum Duty Factor In Dropout 98 99.4 % MAX I Soft-Start Charge Current V = 1.9V 0.5 1.2 μA RUN/SS1, 2 RUN/SS1, 2 V ON RUN/SS Pin ON Threshold V V Rising 1.0 1.5 1.9 V RUN/SS1, 2 RUN/SS1, RUN/SS2 V LT RUN/SS Pin Latchoff Arming V V Rising from 3V 3.8 4.5 V RUN/SS1, 2 RUN/SS1, RUN/SS2 Threshold I RUN/SS Discharge Current Soft-Short Condition V = 0.5V; 0.5 2 4 μA SCL1, 2 OSENSE1, 2 V = 4.5V RUN/SS1, 2 I Shutdown Latch Disable Current V = 0.5V 1.6 5 μA SDLHO OSENSE1, 2 V Maximum Current Sense Threshold V = 0.7V, V – – = 5V 65 75 85 mV SENSE(MAX) OSENSE1, 2 OSENSE1 , 2 V = 0.7V, V – – = 5V l 62 75 88 mV OSENSE1, 2 OSENSE1 , 2 TG Transition Time: (Note 5) TG1, 2 t Rise Time C = 3300pF 50 90 ns r LOAD TG1, 2 t Fall Time C = 3300pF 50 90 ns f LOAD BG Transition Time: (Note 5) BG1, 2 t Rise Time C = 3300pF 40 90 ns r LOAD BG1, 2 t Fall Time C = 3300pF 40 80 ns f LOAD TG/BG t Top Gate Off to Bottom Gate On Delay 1D Synchronous Switch-On Delay Time C = 3300pF Each Driver 90 ns LOAD BG/TG t Bottom Gate Off to Top Gate On Delay 2D Top Switch-On Delay Time C = 3300pF Each Driver 90 ns LOAD t Minimum On-Time Tested with a Square Wave (Note 6) 100 ns ON(MIN) INTV Linear Regulator CC V Internal V Voltage 6V < V < 30V, V = 4V 48 5.0 5.2 V INTVCC CC IN EXTVCC V INT INTV Load Regulation I = 0 to 20mA, V = 4V 0.2 1.0 % LDO CC CC EXTVCC V EXT EXTV Voltage Drop I = 20mA, V = 5V 80 160 mV LDO CC CC EXTVCC 3728fg 3

LTC3728 ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = 15V, V = 5V unless otherwise noted. A IN RUN/SS1, 2 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V EXTV Switchover Voltage I = 20mA, EXTV Ramping Positive l 4.5 4.7 V EXTVCC CC CC CC V EXTV Hysteresis 0.2 V LDOHYS CC Oscillator and Phase-Locked Loop f Nominal Frequency V = 1.2V 360 400 440 kHz NOM PLLFLTR f Lowest Frequency V = 0V 230 260 290 kHz LOW PLLFLTR f Highest Frequency V ≥ 2.4V 480 550 590 kHz HIGH PLLFLTR R PLLIN Input Resistance 50 kΩ PLLIN I Phase Detector Output Current PLLFLTR Sinking Capability f < f –15 μA PLLIN OSC Sourcing Capability f > f 15 μA PLLIN OSC 3.3V Linear Regulator V 3.3V Regulator Output Voltage No Load l 3.25 3.35 3.45 V 3.3OUT V 3.3V Regulator Load Regulation I = 0 to 10mA 0.5 2 % 3.3IL 3.3 V 3.3V Regulator Line Regulation 6V < V < 30V 0.05 0.2 % 3.3VL IN I Leakage Current of 3.3V Regulator in V = 0V, V = 25V 10 50 μA 3.3LEAK RUN/SS1, 2 IN Shutdown PGOOD Output V PGOOD Voltage Low I = 2mA 0.1 0.3 V PGL PGOOD I PGOOD Leakage Current V = 5V ±1 μA PGOOD PGOOD V PGOOD Trip Level, Either Controller V with Respect to Set Output Voltage PG OSENSE V Ramping Negative –6 –7.5 –9.5 % OSENSE V Ramping Positive 6 7.5 9.5 % OSENSE Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: Rise and fall times are measured using 10% and 90% levels. Delay may cause permanent damage to the device. Exposure to any Absolute times are measured using 50% levels. Maximum Rating condition for extended periods may affect device Note 6: The IC minimum on-time is tested under an ideal condition reliability and lifetime. without external power FETs. It can be different when the IC is working in Note 2: T is calculated from the ambient temperature T and power an actual circuit. See Minimum On-Time Considerations in the Application J A dissipation P according to the following formulas: Information section. D LTC3728: T = T + (P • 95 °C/W) Note 7: The LTC3728E is guaranteed to meet performance specifi cations J A D Note 3: The LTC3728 is tested in a feedback loop that servos V to a from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating ITH1, 2 specifi ed voltage and measures the resultant V temperature range are assured by design, characterization and correlation OSENSE1, 2. with statistical process controls. The LTC3728I is guaranteed to meet Note 4: Dynamic supply current is higher due to the gate charge being performance specifi cations over the full –40°C to 85°C operating delivered at the switching frequency. See Applications Information. temperature range. 3728fg 4

LTC3728 TYPICAL PERFORMANCE CHARACTERISTICS Effi ciency vs Output Current and Effi ciency vs Output Current Effi ciency vs Input Voltage Mode (Figure 13) (Figure 13) (Figure 13) 100 100 100 90 OBPuErsRtA MTIoOdNe VIN = 7V 80 90 90 70 VIN = 10V %) FORCED %) VIN = 15V %) CY ( 60 CMOONDTEI N(PUWOUMS) CY ( 80 CY ( 80 EN 50 EN VIN = 20V EN EFFICI 3400 CFROENQSUTEANNCTY EFFICI 70 EFFICI 70 (BURST DISABLE) 20 60 60 10 VVf =ION U2 =T5 0=1k 55HVVz Vf =O U2T5 0=k 5HVz VIfO =OU U2TT 5= 0= 3k 5HAVz 0 50 50 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 5 15 25 35 OUTPUT CURRENT (A) OUTPUT CURRENT (A) INPUT VOLTAGE (V) 3728 G01 3728 G02 3728 G03 Supply Current vs Input Voltage INTV and EXTV Switch CC CC and Mode (Figure 13) EXTV Voltage Drop Voltage vs Temperature CC 1000 250 5.05 GE (V)5.00 INTVCC VOLTAGE SUPPLY CURRENT (A)μ648000000 BCOOTNHTROLLERS ON TV VOLTAGE DROP (mV)CC211005000 ND EXTV SWITCH VOLTACC4444....89895005 200 EX 50 AC EXTVCC SWITCHOVER THRESHOLD C4.75 V T SHUTDOWN N I 0 0 4.70 0 5 10 15 20 25 30 35 0 10 20 30 40 50 –50 –25 0 25 50 75 100 125 INPUT VOLTAGE (V) CURRENT (mA) TEMPERATURE (°C) 3728 G04 3728 G05 3728 G06 Maximum Current Sense Maximum Current Sense Threshold vs Percent of Nominal Internal 5V LDO Line Regulation Threshold vs Duty Factor Output Voltage (Foldback) 5.1 75 80 ILOAD = 1mA 5.0 70 60 GE (V) 4.9 V) 50 V) 50 A 4.8 m m V VOLTCC 4.7 V (SENSE V (SENSE 4300 T 25 IN 4.6 20 4.5 10 4.4 0 0 0 5 10 15 20 25 30 35 0 20 40 60 80 100 0 25 50 75 100 INPUT VOLTAGE (V) DUTY FACTOR (%) PERCENT ON NOMINAL OUTPUT VOLTAGE (%) 3728 G07 3728 G08 3728 G09 3728fg 5

LTC3728 TYPICAL PERFORMANCE CHARACTERISTICS Maximum Current Sense Threshold Maximum Current Sense Threshold Current Sense Threshold vs VRUN/SS (Soft-Start) vs Sense Common Mode Voltage vs ITH Voltage 80 80 90 VSENSE(CM) = 1.6V 80 70 76 60 60 50 mV) mV) 72 mV) 40 (NSE 40 (NSE (NSE 30 VSE VSE 68 VSE 20 10 20 0 64 –10 –20 0 60 –30 0 1 2 3 4 5 6 0 1 2 3 4 5 0 0.5 1 1.5 2 2.5 VRUN/SS (V) COMMON MODE VOLTAGE (V) VITH (V) 3728 G10 3728 G11 3728 G12 Load Regulation V vs V SENSE Pins Total Source Current ITH RUN/SS 0.0 2.5 100 FCB = 0V VOSENSE = 0.7V VIN = 15V 2.0 %)–0.1 50 ALIZED V (OUT–0.2 V (V)ITH 11..05 (A)μSENSE 0 M I R O N–0.3 –50 0.5 –0.4 0 –100 0 1 2 3 4 5 0 1 2 3 4 5 6 0 2 4 6 LOAD CURRENT (A) VRUN/SS (V) VSENSE COMMON MODE VOLTAGE (V) 3728 G13 3728 G14 3728 G15 Maximum Current Sense Dropout Voltage vs Output Current Threshold vs Temperature (Figure 14) RUN/SS Current vs Temperature 80 4 1.8 VOUT = 5V 1.6 78 V (mV)SENSE 7764 OPOUT VOLTAGE (V) 32 RSENSE = 0.015Ω N/SS CURRENT (A)μ 01110.....80246 DR 1 RU 72 0.4 RSENSE = 0.010Ω 0.2 70 0 0 –50 –25 0 25 50 75 100 125 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) OUTPUT CURRENT (A) TEMPERATURE (°C) 3728 G17 3728 G18 3728 G25 3728fg 6

LTC3728 TYPICAL PERFORMANCE CHARACTERISTICS Soft-Start Up (Figure 13) Load Step (Figure 13) Load Step (Figure 13) VOUT VOUT VOUT 5V/DIV 200mV/DIV 200mV/DIV VRUN/SS 5V/DIV IL IL IL 2A/DIV 2A/DIV 2A/DIV VIN = 15V 5ms/DIV 3728 G19 VIN = 15V 20μs/DIV 3728 G20 VIN = 15V 20μs/DIV 3728 G21 VOUT = 5V VOUT = 5V VOUT = 5V VPLLFLTR = 0V VPLLFLTR = 0V LOAD STEP = 0A to 3A LOAD STEP = 0A to 3A Burst Mode OPERATION CONTINUOUS OPERATION Input Source/Capacitor Constant-Frequency (Burst Instantaneous Current (Figure 13) Burst Mode Operation (Figure 13) Inhibit) Operation (Figure 13) IIN 2A/DIV 20mVV/ODUIVT VOUT VIN 20mV/DIV 200mV/DIV VSW1 10V/DIV VSW2 10V/DIV IL IL 0.5A/DIV 0.5A/DIV VIN = 15V 1μs/DIV 3728 G22 VIN = 15V 10μs/DIV 3728 G23 VIN = 15V 2μs/DIV 3728 G24 VOUT = 5V VOUT = 5V VOUT = 5V VPLLFLTR = 0V VPLLFLTR = 0V VPLLFLTR = 0V IOUT = IOUT3.3A= 2A VFCB = OPEN VFCB = 5V IOUT = 20mA IOUT = 20mA Current Sense Pin Input Current EXTV Switch Resistance Oscillator Frequency CC vs Temperature vs Temperature vs Temperature 35 10 700 VOUT = 5V A) URRENT SENSE INPUT CURRENT (μ 32231973 EXTV SWITCH RESISTANCE ()ΩCC 6428 FREQUENCY (kHz) 432651000000000000 VVVPPPLLLLLLFFFLLLTTTRRR = == 1 50.2VVV C 25 0 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3728 G26 3728 G27 3728 G28 3728fg 7

LTC3728 TYPICAL PERFORMANCE CHARACTERISTICS Undervoltage Lockout Shutdown Latch Thresholds vs Temperature vs Temperature 3.50 4.5 V)3.45 S (V) 4.0 LATCH ARMING T ( LD 3.5 U O KO3.40 SH 3.0 LATCHOFF OC RE THRESHOLD L H 2.5 GE 3.35 H T OLTA LATC 2.0 ERV3.30 WN 1.5 D O N D 1.0 U3.25 UT SH 0.5 3.20 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) 3728 G29 3728 G30 PIN FUNCTIONS G Package/UH Package RUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, 13): Combination with 50kΩ. The phase-locked loop will force the rising of soft-start, run control inputs and short-circuit detection top gate signal of controller 1 to be synchronized with timers. A capacitor to ground at each of these pins sets the the rising edge of the PLLIN signal. ramp time to full output current. Forcing either of these pins FCB (Pin 7/Pin 4): Forced Continuous Control Input. back below 1.0V causes the IC to shut down the circuitry This input acts on both controllers and is normally used required for that particular controller. Latchoff overcurrent to regulate a secondary winding. Pulling this pin below protection is also invoked via this pin as described in the 0.8V will force continuous synchronous operation. Applications Information section. I I (Pins 8, 11/Pins 5, 8): Error Amplifi er Output SENSE1+, SENSE2+ (Pins 2, 14/Pins 30, 12): The (+) TH1, TH2 and Switching Regulator Compensation Point. Each as- Input to the Differential Current Comparators. The I pin TH sociated channels’ current comparator trip point increases voltage and controlled offsets between the SENSE– and SENSE+ pins in conjunction with R set the current with this control voltage. SENSE trip threshold. SGND (Pin 9/Pin 6): Small Signal Ground common to SENSE1–, SENSE2– (Pins 3, 13/Pins 31, 11): The (–) both controllers, must be routed separately from high current grounds to the common (–) terminals of the Input to the Differential Current Comparators. C capacitors. OUT V , V (Pins 4, 12/Pins 1, 9): Receives the OSENSE1 OSENSE2 3.3V (Pin 10/Pin 7): Output of a linear regulator ca- remotely-sensed feedback voltage for each controller from OUT pable of supplying 10mA DC with peak currents as high an external resistive divider across the output. as 50mA. PLLFLTR (Pin 5/Pin 2): The Phase-Locked Loop’s Lowpass Filter is Tied to This Pin. Alternatively, this pin can be driven NC (Pins 10, 16, 29, 32 UH Package Only): No Connect. with an AC or DC voltage source to vary the frequency of PGND (Pin 20/Pin 19): Driver Power Ground. Connects to the internal oscillator. the sources of bottom (synchronous) N-channel MOSFETs, PLLIN (Pin 6/Pin 3): External Synchronization Input to anodes of the Schottky rectifi ers and the (–) terminal(s) Phase Detector. This pin is internally terminated to SGND of C . IN 3728fg 8

LTC3728 PIN FUNCTIONS INTV (Pin 21/Pin 20): Output of the Internal 5V Linear are connected between the boost and switch pins and CC Low Dropout Regulator and the EXTV Switch. The driver Schottky diodes are tied between the boost and INTV CC CC and control circuits are powered from this voltage source. pins. Voltage swing at the boost pins is from INTV to CC Must be decoupled to power ground with a minimum of (V + INTV ). IN CC 4.7μF tantalum or other low ESR capacitor. SW1, SW2 (Pins 26, 17/Pins 25, 15): Switch Node EXTV (Pin 22/Pin 21): External Power Input to an Connections to Inductors. Voltage swing at these pins CC Internal Switch Connected to INTV . This switch closes is from a Schottky diode (external) voltage drop below CC and supplies V power, bypassing the internallow drop- ground to V . CC IN out regulator, whenever EXTV is higher than 4.7V. See CC TG1, TG2 (Pins 27, 16/Pins 26, 14): High Current Gate EXTV connection in Applications section. Do not exceed CC Drives for Top N-Channel MOSFETs. These are the out- 7V on this pin. puts of fl oating drivers with a voltage swing equal to BG1, BG2 (Pins 23, 19/Pins 22, 18): High Current Gate INTV – 0.5V superimposed on the switch node voltage CC Drives for Bottom (Synchronous) N-Channel MOSFETs. SW. Voltage swing at these pins is from ground to INTV . CC PGOOD (Pin 28/Pin 27): Open-Drain Logic Output. PGOOD V (Pin 24/Pin 23): Main Supply Pin. A bypass capaci- is pulled to ground when the voltage on either V IN OSENSE tor should be tied between this pin and the signal ground pin is not within ±7.5% of its set point. pin. Exposed Pad (Pin 33) SGND: The Exposed Pad must be BOOST1, BOOST2 (Pins 25, 18/Pins 24, 17): Bootstrapped soldered to PCB ground for electrical contact and rated Supplies to the Topside Floating Drivers. Capacitors thermal performance. 3728fg 9

LTC3728 FUNCTIONAL DIAGRAM PLLIN INTVCC VIN FIN PHASE DET 50k DUPLICATE FOR SECOND BOOST DB CONTROLLER CHANNEL PLLFLTR CLK1 DROP TOP TG CB + RCLLPP OSCILLATOR CL–K2 0.86V ODUETT BTOOTP ONFCB SW D1 CIN S Q PGOOD –+ VOSENSE1 R Q SLWOIGTICCH BOT INTVCC BG + 0.74V B PGND COUT+ – 0.86V 0.55V + VOUT + – VOSENSE2 SHDN RSENSE – VSEC 1.5V + 0.74V I1 + – I2 INTVCC 4.5V – – ++ – + 0.18μA + BINH – + 30k SENSE+ DSEC CSEC R6 FCB 0.86V 3mV + FCB 4(VFB) 30k SENSE– R5 – SLOPE COMP 45k 45k 3.3VOUT + 0.8V VREF 2.4V– VFB VOSENSE R2 – EA + 0.80V R1 VIN OV + VIN – 0.86V 4.7V + 5V 1.2μA ITH CC EXTVCC – LDO REG SHRDSNT SROUFNT CC2 RC INTVCC 6V 4(VFB) START 5V + RUN/SS SGND INTERNAL SUPPLY CSS 3728 FD/F02 Figure 2 3728fg 10

LTC3728 OPERATION (Refer to Functional Diagram) Main Control Loop low current operation. When the FCB pin voltage is below 0.8V, the controller forces continuous PWM current mode The LTC3728 uses a constant-frequency, current mode operation. In this mode, the top and bottom MOSFETs step-down architecture with the two controller channels are alternately turned on to maintain the output voltage operating 180 degrees out of phase. During normal opera- independent of direction of inductor current. When the tion, each top MOSFET is turned on when the clock for FCB pin is below V – 1V but greater than 0.8V, that channel sets the RS latch, and turned off when the INTVCC the controller enters Burst Mode operation. Burst Mode main current comparator, I1, resets the RS latch. The peak operation sets a minimum output current level before inductor current at which I1 resets the RS latch is controlled inhibiting the top switch and turns off the synchronous by the voltage on the I pin, which is the output of each TH MOSFET(s) when the inductor current goes negative. This error amplifi er EA. The V pin receives the voltage OSENSE combination of requirements will, at low currents, force feedback signal, which is compared to the internal refer- the I pin below a voltage threshold that will temporarily ence voltage by the EA. When the load current increases, TH inhibit turn-on of both output MOSFETs until the output it causes a slight decrease in V relative to the 0.8V OSENSE voltage drops. There is 60mV of hysteresis in the burst reference, which in turn causes the I voltage to increase TH comparator B tied to the I pin. This hysteresis produces until the average inductor current matches the new load TH output signals to the MOSFETs that turn them on for several current. After the top MOSFET has turned off, the bottom cycles, followed by a variable “sleep” interval depending MOSFET is turned on until either the inductor current upon the load current. The resultant output voltage ripple starts to reverse, as indicated by current comparator I2, is held to a very small value by having the hysteretic or the beginning of the next cycle. comparator after the error amplifi er gain block. The top MOSFET drivers are biased from fl oating bootstrap capacitor C , which normally is recharged during each off Frequency Synchronization B cycle through an external diode when the top MOSFET The phase-locked loop allows the internal oscillator to turns off. As V decreases to a voltage close to V , the IN OUT be synchronized to an external source via the PLLIN pin. loop may enter dropout and attempt to turn on the top The output of the phase detector at the PLLFLTR pin is MOSFET continuously. The dropout detector detects this also the DC frequency control input of the oscillator that and forces the top MOSFET off for about 400ns every tenth operates over a 250kHz to 550kHz range corresponding cycle to allow C to recharge. B to a DC voltage input from 0V to 2.4V. When locked, the The main control loop is shut down by pulling the RUN/ PLL aligns the turn on of the top MOSFET to the rising SS pin low. Releasing RUN/SS allows an internal 1.2μA edge of the synchronizing signal. When PLLIN is left current source to charge soft-start capacitor C . When open, the PLLFLTR pin goes low, forcing the oscillator to SS C reaches 1.5V, the main control loop is enabled with minimum frequency. SS the I voltage clamped at approximately 30% of its TH maximum value. As C continues to charge, the I Constant-Frequency Operation SS TH pin voltage is gradually released allowing normal, full- When the FCB pin is tied to INTV , Burst Mode opera- CC current operation. When both RUN/SS1 and RUN/SS2 tion is disabled and the forced minimum output current are low, all LTC3728 controller functions are shut down, requirement is removed. This provides constant-frequency, including the 5V and 3.3V regulators. discontinuous (preventing reverse inductor current) current operation over the widest possible output current Low Current Operation range. This constant-frequency operation is not as effi cient The FCB pin is a multifunction pin providing two func- as Burst Mode operation, but does provide a lower noise, tions: 1) to provide regulation for a secondary winding constant-frequency operating mode down to approximately by temporarily forcing continuous PWM operation on 1% of designed maximum output current. both controllers; and 2) select between two modes of 3728fg 11

LTC3728 OPERATION (Refer to Functional Diagram) Continuous Current (PWM) Operation Foldback Current, Short-Circuit Detection and Short-Circuit Latchoff Tying the FCB pin to ground will force continuous current operation. This is the least effi cient operating mode, but The RUN/SS capacitors are used initially to limit the inrush may be desirable in certain applications. The output can current of each switching regulator. After the controller source or sink current in this mode. When sinking current has been started and been given adequate time to charge while in forced continuous operation, current will be forced up the output capacitors and provide full load current, the back into the main power supply. RUN/SS capacitor is used in a short-circuit time-out circuit. If the output voltage falls to less than 70% of its nominal INTVCC/EXTVCC Power output voltage, the RUN/SS capacitor begins discharging on the assumption that the output is in an overcurrent Power for the top and bottom MOSFET drivers and most and/or short-circuit condition. If the condition lasts for other internal circuitry is derived from the INTV pin. When CC a long enough period as determined by the size of the the EXTV pin is left open, an internal 5V low dropout CC RUN/SS capacitor, the controller will be shut down until linear regulator supplies INTV power. If EXTV is taken CC CC the RUN/SS pin(s) voltage(s) are recycled. This built-in above 4.7V, the 5V regulator is turned off and an internal latchoff can be overridden by providing a >5μA pull-up switch is turned on connecting EXTV to INTV . This al- CC CC at a compliance of 5V to the RUN/SS pin(s). This current lows the INTV power to be derived from a high effi ciency CC shortens the soft start period but also prevents net dis- external source such as the output of the regulator itself charge of the RUN/SS capacitor(s) during an overcurrent or a secondary winding, as described in the Applications and/or short-circuit condition. Foldback current limiting Information section. is also activated when the output voltage falls below Output Overvoltage Protection 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. Even if a short is present and An overvoltage comparator, OV, guards against transient the short-circuit latchoff is not enabled, a safe, low output overshoots (>7.5%) as well as other more serious condi- current is provided due to internal current foldback and tions that may overvoltage the output. In this case, the top actual power wasted is low due to the effi cient nature of MOSFET is turned off and the bottom MOSFET is turned the current mode switching regulator. on until the overvoltage condition is cleared. Power Good (PGOOD) Pin THEORY AND BENEFITS OF 2-PHASE OPERATION The PGOOD pin is connected to an open drain of an internal The LTC1628 and the LTC3728 dual high effi ciency DC/DC MOSFET. The MOSFET turns on and pulls the pin low when controllers bring the considerable benefi ts of 2-phase op- either output is not within ±7.5% of the nominal output eration to portable applications for the fi rst time. Notebook level as determined by the resistive feedback divider. When computers, PDAs, handheld terminals and automotive both outputs meet the ±7.5% requirement, the MOSFET is electronics will all benefi t from the lower input fi lter- turned off within 10μs and the pin is allowed to be pulled ing requirement, reduced electromagnetic interference up by an external resistor to a source of up to 7V. (EMI) and increased effi ciency associated with 2-phase operation. 3728fg 12

LTC3728 OPERATION (Refer to Functional Diagram) 5V SWITCH 20V/DIV 3.3V SWITCH 20V/DIV INPUT CURRENT 5A/DIV INPUT VOLTAGE 500mV/DIV IIN(MEAS) = 2.53ARMS 3728 F03a IIN(MEAS) = 1.55ARMS 3728 F03b (a) (b) Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the LTC1628 2-Phase Regulator Allows Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Effi ciency Why the need for 2-phase operation? Up until the 2- that 2-phase operation dropped the input current from phase family, constant-frequency dual switching regula- 2.53A to 1.55A . While this is an impressive RMS RMS tors operated both channels in phase (i.e., single-phase reduction in itself, remember that the power losses are operation). This means that both switches turned on at proportional to I 2, meaning that the actual power wasted RMS the same time, causing current pulses of up to twice the is reduced by a factor of 2.66. The reduced input ripple amplitude of those for one regulator to be drawn from the voltage also means less power is lost in the input power input capacitor and battery. These large amplitude current path, which could include batteries, switches, trace/con- pulses increased the total RMS current fl owing from the nector resistances and protection circuitry. Improvements input capacitor, requiring the use of more expensive input in both conducted and radiated EMI also directly accrue as capacitors and increasing both EMI and losses in the input a result of the reduced RMS input current and voltage. capacitor and battery. Of course, the improvement afforded by 2-phase opera- With 2-phase operation, the two channels of the dual- tion is a function of the dual switching regulator’s relative switching regulator are operated 180 degrees out of phase. duty cycles which, in turn, are dependent upon the input This effectively interleaves the current pulses drawn by the voltage V (Duty Cycle = V /V ). Figure 4 shows how IN OUT IN switches, greatly reducing the overlap time where they add the RMS input current varies for single-phase and 2-phase together. The result is a signifi cant reduction in total RMS operation for 3.3V and 5V regulators over a wide input input current, which in turn allows less expensive input voltage range. capacitors to be used, reduces shielding requirements for It can readily be seen that the advantages of 2-phase opera- EMI and improves real world operating effi ciency. tion are not just limited to a narrow operating range, but Figure 3 compares the input waveforms for a representa- in fact extend over a wide region. A good rule of thumb tive single-phase dual switching regulator to the LTC1628 for most applications is that 2-phase operation will reduce 2-phase dual switching regulator. An actual measurement the input capacitor requirement to that for just one channel of the RMS input current under these conditions shows operating at maximum current and 50% duty cycle. 3728fg 13

LTC3728 OPERATION (Refer to Functional Diagram) A fi nal question: If 2-phase operation offers such an ad- 3.0 vantage over single-phase operation for dual switching SINGLE PHASE regulators, why hasn’t it been done before? The answer 2.5 DUAL CONTROLLER A) is that, while simple in concept, it is hard to implement. NT ( 2.0 Constant-frequency current mode switching regulators RE R U require an oscillator derived slope compensation signal C 1.5 MS 2-PHASE to allow stable operation of each regulator at over 50% R DUAL CONTROLLER T 1.0 U duty cycle. This signal is relatively easy to derive in P N I single-phase dual switching regulators, but required the 0.5 VO1 = 5V/3A development of a new and proprietary technique to allow VO2 = 3.3V/3A 0 2-phase operation. In addition, isolation between the two 0 10 20 30 40 channels becomes more critical with 2-phase operation INPUT VOLTAGE (V) 3728 F04 because switch transitions in one channel could potentially disrupt the operation of the other channel. Figure 4. RMS Input Current Comparison These 2-phase parts are proof that these hurdles have been surmounted. They offer unique advantages for the ever-expanding number of high effi ciency power supplies required in portable electronics. 3728fg 14

LTC3728 APPLICATIONS INFORMATION Figure 1 on the fi rst page is a basic LTC3728 application 2.5 circuit. External component selection is driven by the load requirement, and begins with the selection of R 2.0 SENSE V) and the inductor value. Next, the power MOSFETs and E ( G D1 are selected. Finally, CIN and COUT are selected. The OLTA 1.5 V circuit shown in Figure 1 can be confi gured for operation N up to an input voltage of 28V (limited by the external R PI 1.0 T L MOSFETs). LF L P 0.5 R Selection for Output Current SENSE 0 200 250 300 350 400 450 500 550 R is chosen based on the required output current. The SENSE OPERATING FREQUENCY (kHz) LTC3728 current comparator has a maximum threshold 3728 F05 of 75mV/R and an input common mode range of SENSE Figure 5. PPLFLTR Pin Voltage vs Frequency SGND to 1.1(INTV ). The current comparator threshold CC sets the peak of the inductor current, yielding a maximum and Frequency Synchronization in the Applications Infor- average output current IMAX equal to the peak value less mation section for additional information. half the peak-to-peak ripple current, ΔI . L A graph for the voltage applied to the PLLFLTR pin vs Allowing a margin for variations in the LTC3728 and external frequency is given in Figure 5. As the operating frequency component values yields: is increased the gate charge losses will be higher, reducing effi ciency (see Effi ciency Considerations). The maximum 50mV R = switching frequency is approximately 550kHz. SENSE I MAX Inductor Value Calculation Because of possible PCB noise in the current sensing loop, the AC current sensing ripple of ΔV = ΔI • R The operating frequency and inductor selection are inter- SENSE SENSE also needs to be checked in the design to get good sig- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would nal-to-noise ratio. In general, for a reasonable good PCB anyone ever choose to operate at lower frequencies with layout, a 15mV ΔV voltage is recommended as a SENSE larger components? The answer is effi ciency. A higher conservative number to start with. frequency generally results in lower effi ciency because When using the controller in very low dropout conditions, of MOSFET gate charge losses. In addition to this basic the maximum output current level will be reduced due to the trade-off, the effect of inductor value on ripple current and internal compensation required to meet stability criterion low current operation must also be considered. for buck regulators operating at greater than 50% duty The inductor value has a direct effect on ripple current. factor. A curve is provided to estimate this reduction in The inductor ripple current ΔI decreases with higher peak output current level depending upon the operating L inductance or frequency and increases with higher V : duty factor. IN 1 (cid:2) V (cid:5) Operating Frequency (cid:1)IL = VOUT(cid:3)1– OUT(cid:6) (f)(L) (cid:4) V (cid:7) IN The LTC3728 uses a constant-frequency, phase-lockable architecture with the frequency determined by an internal Accepting larger values of ΔI allows the use of low L capacitor. This capacitor is charged by a fi xed current plus inductances, but results in higher output voltage ripple an additional current which is proportional to the voltage and greater core losses. A reasonable starting point for applied to the PLLFLTR pin. Refer to Phase-Locked Loop setting ripple current is ΔI =0.3(I ) or higher for good L MAX 3728fg 15

LTC3728 APPLICATIONS INFORMATION load transient response and suffi cient ripple current sig- Power MOSFET and D1 Selection nal in the current loop. The maximum ΔI occurs at the L Two external power MOSFETs must be selected for each maximum input voltage. controller in the LTC3728: One N-channel MOSFET for The inductor value also has secondary effects. The tran- the top (main) switch, and one N-channel MOSFET for sition to Burst Mode operation begins when the average the bottom (synchronous) switch. inductor current required results in a peak current below The peak-to-peak drive levels are set by the INTV CC 25% of the current limit determined by R . Lower SENSE voltage. This voltage is typically 5V during start-up inductor values (higher ΔI ) will cause this to occur at L (see EXTV Pin Connection). Consequently, logic-level CC lower load currents, which can cause a dip in effi ciency in threshold MOSFETs must be used in most applications. the upper range of low current operation. In Burst Mode The only exception is if low input voltage is expected operation, lower inductance values will cause the burst (V < 5V); then, sublogic level threshold MOSFETs (V IN GS(TH) frequency to decrease. < 3V) should be used. Pay close attention to the BV DSS specifi cation for the MOSFETs as well; most of the logic Inductor Core Selection level MOSFETs are limited to 30V or less. Once the value for L is known, the type of inductor must Selection criteria for the power MOSFETs include the be selected. High effi ciency converters generally cannot on-resistance R , reverse-transfer capacitance C , afford the core loss found in low cost powdered iron cores, DS(ON) RSS input voltage and maximum output current. When the forcing the use of more expensive ferrite, molypermalloy, LTC3728 is operating in continuous mode the duty cycles or Kool Mμ® cores. Actual core loss is independent of core for the top and bottom MOSFETs are given by: size for a fi xed inductor value, but it is very dependent on inductance selected. As inductance increases, core V MainSwitchDutyCycle= OUT losses go down. Unfortunately, increased inductance V IN requires more turns of wire and therefore copper losses will increase. V –V SynchronousSwitchDutyCycle= IN OUT Ferrite designs have very low core loss and are preferred V IN at high switching frequencies, so design goals can con- The MOSFET power dissipations at maximum output centrate on copper loss and preventing saturation. Ferrite current are given by: core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is V exceeded. This results in an abrupt increase in inductor PMAIN= OUT (IMAX)2(1+(cid:1))RDS(ON)+ V ripple current and consequent output voltage ripple. Do IN not allow the core to saturate! k(V )2(I )(C )(f) IN MAX RSS Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive P = VIN–VOUT (I )2(1+(cid:1))R than ferrite. A reasonable compromise from the same SYNC V MAX DS(ON) IN manufacturer is Kool Mμ. Toroids are very space effi cient, especially when you can use several layers of wire. Because where δ is the temperature dependency of RDS(ON) and k they generally lack a bobbin, mounting is more diffi cult. is a constant inversely related to the gate drive current. However, designs for surface mount are available that do Both MOSFETs have I2R losses while the topside N-channel not increase the height signifi cantly. equation includes an additional term for transition losses, 3728fg 16

LTC3728 APPLICATIONS INFORMATION which are highest at high input voltages. For V < 20V requirement. Increasing the output current, drawn from IN the high current effi ciency generally improves with larger the other out-of-phase controller, will actually decrease the MOSFETs, while for V > 20V the transition losses rapidly input RMS ripple current from this maximum value (see IN increase to the point that the use of a higher R device Figure 4). The out-of-phase technique typically reduces DS(ON) with lower C actually provides higher effi ciency. The the input capacitor’s RMS ripple current by a factor of RSS synchronous MOSFET losses are greatest at high input 30% to 70% when compared to a single phase power voltage when the top switch duty factor is low or during supply solution. a short-circuit when the synchronous switch is on close The type of input capacitor, value and ESR rating have to 100% of the period. effi ciency effects that need to be considered in the selec- The term (1 + δ) is generally given for a MOSFET in the tion process. The capacitance value chosen should be form of a normalized R vs Temperature curve, but suffi cient to store adequate charge to keep high peak DS(ON) δ = 0.005/°C can be used as an approximation for low battery currents down. 20μF to 40μF is usually suffi cient voltage MOSFETs. C is usually specifi ed in the MOSFET for a 25W output supply operating at 200kHz. The ESR of RSS characteristics. The constant k = 1.7 can be used to esti- the capacitor is important for capacitor power dissipation mate the contributions of the two terms in the main switch as well as overall battery effi ciency. All of the power (RMS dissipation equation. ripple current • ESR) not only heats up the capacitor but wastes power from the battery. The Schottky diode D1 shown in Figure 1 conducts dur- ing the dead time between the conduction of the two Medium voltage (20V to 35V) ceramic, tantalum, OS-CON power MOSFETs. This prevents the body diode of the and switcher-rated electrolytic capacitors can be used bottom MOSFET from turning on, storing charge during as input capacitors, but each has drawbacks: ceramic the dead time and requiring a reverse recovery period voltage coeffi cients are very high and may have audible that could cost as much as 3% in effi ciency at high V . piezoelectric effects; tantalums need to be surge-rated; IN A 1A to 3A Schottky is generally a good compromise for OS-CONs suffer from higher inductance, larger case size both regions of operation due to the relatively small aver- and limited surface-mount applicability; electrolytics’ age current. Larger diodes result in additional transition higher ESR and dryout possibility require several to be losses due to their larger junction capacitance. Schottky used. Multiphase systems allow the lowest amount of diodes should be placed in parallel with the synchronous capacitance overall. As little as one 22μF or two to three MOSFETs when operating in pulse-skip mode or in Burst 10μF ceramic capacitors are an ideal choice in a 20W to Mode operation. 35W power supply due to their extremely low ESR. Even though the capacitance at 20V is substantially below their CIN and COUT Selection rating at zero-bias, very low ESR loss makes ceramics an ideal candidate for highest effi ciency battery operated The selection of C is simplifi ed by the multiphase ar- IN systems. Also consider parallel ceramic and high quality chitecture and its impact on the worst-case RMS current electrolytic capacitors as an effective means of achieving drawn through the input network (battery/fuse/capacitor). ESR and bulk capacitance goals. It can be shown that the worst case RMS current occurs when only one controller is operating. The controller with In continuous mode, the source current of the top N-channel the highest (VOUT)(IOUT) product needs to be used in the MOSFET is a square wave of duty cycle VOUT/VIN. To prevent formula below to determine the maximum RMS current large voltage transients, a low ESR input capacitor sized for 3728fg 17

LTC3728 APPLICATIONS INFORMATION the maximum RMS current of one channel must be used. The output ripple (ΔV ) is determined by: OUT The maximum RMS capacitor current is given by: (cid:3) 1 (cid:6) (cid:1)V (cid:2)(cid:1)I ESR+ OUT L(cid:4) (cid:7) 1/2 (cid:5) 8fC (cid:8) (cid:3)V (V (cid:1)V )(cid:5) OUT (cid:4) OUT IN OUT (cid:6) C RequiredI (cid:2)I IN RMS MAX V Where f = operating frequency, C = output capacitance, IN OUT and ΔI = ripple current in the inductor. The output ripple is L This formula has a maximum at VIN = 2VOUT, where highest at maximum input voltage since ΔIL increases with IRMS = IOUT/2. This simple worst case condition is com- input voltage. With ΔIL = 0.3IOUT(MAX) the output ripple monly used for design because even signifi cant deviations will typically be less than 50mV at max V assuming: IN do not offer much relief. Note that capacitor manufacturer’s C Recommended ESR < 2 R ripple current ratings are often based on only 2000 hours OUT SENSE of life. This makes it advisable to further derate the capaci- and C > 1/(8fR ) OUT SENSE tor, or to choose a capacitor rated at a higher temperature The fi rst condition relates to the ripple current into the ESR than required. Several capacitors may also be paralleled of the output capacitance while the second term guarantees to meet size or height requirements in the design. Always that the output capacitance does not signifi cantly discharge consult the manufacturer if there is any question. during the operating frequency period due to ripple current. The benefi t of the LTC3728 multiphase can be calculated by The choice of using smaller output capacitance increases using the equation above for the higher power controller the ripple voltage due to the discharging term but can be and then calculating the loss that would have resulted if compensated for by using capacitors of very low ESR to both controller channels switch on at the same time. The maintain the ripple voltage at or below 50mV. The I pin TH total RMS power lost is lower when both controllers are OPTI-LOOP compensation components can be optimized operating due to the interleaving of current pulses through to provide stable, high performance transient response the input capacitor’s ESR. This is why the input capacitor’s regardless of the output capacitors selected. requirement calculated above for the worst-case controller Manufacturers such as Nichicon, United Chemicon and is adequate for the dual controller design. Remember that Sanyo can be considered for high performance through- input protection fuse resistance, battery resistance and PC hole capacitors. The OS-CON semiconductor dielectric board trace resistance losses are also reduced due to the capacitor available from Sanyo has the lowest (ESR)(size) reduced peak currents in a multiphase system. The overall product of any aluminum electrolytic at a somewhat benefi t of a multiphase design will only be fully realized when the source impedance of the power supply/battery higher price. An additional ceramic capacitor in parallel is included in the effi ciency testing. The drains of the with OS-CON capacitors is recommended to reduce the two top MOSFETs should be placed within 1cm of each inductance effects. other and share a common C (s). Separating the drains IN In surface mount applications multiple capacitors may and C may produce undesirable voltage and current IN need to be used in parallel to meet the ESR, RMS current resonances at V . IN handling and load step requirements of the application. The selection of C is driven by the required effective Aluminum electrolytic, dry tantalum and special polymer OUT series resistance (ESR). Typically, once the ESR require- capacitors are available in surface mount packages. Special ment is satisfi ed the capacitance is adequate for fi ltering. polymer surface mount capacitors offer very low ESR but 3728fg 18

LTC3728 APPLICATIONS INFORMATION have lower storage capacity per unit volume than other input pin. When the voltage applied to the EXTV pin is CC capacitor types. These capacitors offer a very cost-effec- less than 4.7V, all of the INTV current is supplied by CC tive output capacitor solution and are an ideal choice when the internal 5V linear regulator. Power dissipation for the combined with a controller having high loop bandwidth. IC in this case is highest: (V )(I ), and overall ef- IN INTVCC Tantalum capacitors offer the highest capacitance density fi ciency is lowered. The gate charge current is dependent and are often used as output capacitors for switching on operating frequency, as discussed in the Effi ciency regulators having controlled soft-start. Several excellent Considerations section. The junction temperature can be surge-tested choices are the AVX TPS, AVX TPSV or the estimated by using the equations given in Note 2 of the KEMET T510 series of surface mount tantalums, available Electrical Characteristics. For example, the LTC3728 V IN in case heights ranging from 2mm to 4mm. Aluminum current is limited to less than 24mA from a 24V supply electrolytic capacitors can be used in cost-driven ap- when not using the EXTV pin, as follows: CC plications providing that consideration is given to ripple T = 70°C + (24mA)(24V)(95°C/W) = 125°C J current ratings, temperature and long term reliability. A typical application will require several to many aluminum Use of the EXTVCC input pin reduces the junction tem- electrolytic capacitors in parallel. A combination of the perature to: aforementioned capacitors will often result in maximizing T = 70°C + (24mA)(5V)(95°C/W) = 81°C J performance and minimizing overall cost. Other capacitor Dissipation should be calculated to also include any added types include Nichicon PL series, NEC Neocap, Cornell Dubilier ESRE and Sprague 595D series. Consult manu- current drawn from the internal 3.3V linear regulator. facturers for other specifi c recommendations. To prevent maximum junction temperature from being exceeded, the input supply current must be checked op- INTV Regulator erating in continuous mode at maximum V . CC IN An internal P-channel low dropout regulator produces 5V EXTV Connection at the INTV pin from the V supply pin. INTV pow- CC CC IN CC ers the drivers and internal circuitry within the LTC3728. The LTC3728 contains an internal P-channel MOSFET The INTVCC pin regulator can supply a peak current of switch connected between the EXTVCC and INTVCC pins. 50mA and must be bypassed to ground with a minimum When the voltage applied to EXTVCC rises above 4.7V, of 4.7μF tantalum, 10μF special polymer, or low ESR type the internal regulator is turned off and the switch closes, electrolytic capacitor. A 1μF ceramic capacitor placed di- connecting the EXTVCC pin to the INTVCC pin thereby rectly adjacent to the INTV and PGND IC pins is highly supplying internal power. The switch remains closed as CC recommended. Good bypassing is necessary to supply long as the voltage applied to EXTVCC remains above 4.5V. the high transient currents required by the MOSFET gate This allows the MOSFET driver and control power to be drivers and to prevent interaction between channels. derived from the output during normal operation (4.7V < V < 7V) and from the internal regulator when the OUT Higher input voltage applications in which large MOS- output is out of regulation (start-up, short-circuit). If more FETs are being driven at high frequencies may cause the current is required through the EXTV switch than is CC maximum junction temperature rating for the LTC3728 specifi ed, an external Schottky diode can be added between to be exceeded. The system supply current is normally the EXTV and INTV pins. Do not apply greater than 7V CC CC dominated by the gate charge current. Additional external to the EXTV pin and ensure that EXTV < V . CC CC IN loading of the INTV and 3.3V linear regulators also CC needs to be taken into account for the power dissipation Signifi cant effi ciency gains can be realized by powering calculations. The total INTVCC current can be supplied by INTVCC from the output, since the VIN current resulting either the 5V internal linear regulator or by the EXTV from the driver and control currents will be scaled by a CC 3728fg 19

LTC3728 APPLICATIONS INFORMATION factor of (Duty Cycle)/(Effi ciency). For 5V regulators this Topside MOSFET Driver Supply (C , D ) B B supply means connecting the EXTV pin directly to V . CC OUT External bootstrap capacitors C connected to the BOOST B However, for 3.3V and other lower voltage regulators, pins supply the gate drive voltages for the topside MOS- additional circuitry is required to derive INTV power CC FETs. Capacitor C in the Functional Diagram is charged B from the output. though external diode D from INTV when the SW pin B CC The following list summarizes the four possible connec- is low. When one of the topside MOSFETs is to be turned tions for EXTV on, the driver places the C voltage across the gate-source CC: B of the desired MOSFET. This enhances the MOSFET and 1. EXTV Left Open (or Grounded). This will cause INTV CC CC turns on the topside switch. The switch node voltage, SW, to be powered from the internal 5V regulator resulting in rises to V and the BOOST pin follows. With the topside an effi ciency penalty of up to 10% at high input voltages. IN MOSFET on, the boost voltage is above the input supply: 2. EXTV Connected Directly to V . This is the normal CC OUT V = V + V . The value of the boost capacitor BOOST IN INTVCC connection for a 5V regulator and provides the highest C needs to be 100 times that of the total input capacitance B effi ciency. of the topside MOSFET(s). The reverse breakdown of the 3. EXTVCC Connected to an External Supply. If an external external Schottky diode must be greater than VIN(MAX). supply is available in the 5V to 7V range, it may be used When adjusting the gate drive level, the fi nal arbiter is the to power EXTV providing it is compatible with the total input current for the regulator. If a change is made CC MOSFET gate drive requirements. and the input current decreases, then the effi ciency has improved. If there is no change in input current, then there 4. EXTV Connected to an Output-Derived Boost Network. CC is no change in effi ciency. For 3.3V and other low voltage regulators, effi ciency gains can still be realized by connecting EXTV to an CC Output Voltage output-derived voltage that has been boosted to greater than 4.7V. This can be done with either the inductive The LTC3728 output voltages are each set by an exter- boost winding as shown in Figure 6a or the capacitive nal feedback resistive divider carefully placed across charge pump shown in Figure 6b. The charge pump the output capacitor. The resultant feedback signal is has the advantage of simple magnetics. compared with the internal precision 0.800V voltage + VIN VIN 1(cid:77)F OPTIONAL EXTVCC CONNECTION + + 5V < VSEC < 7V CIN CIN BAT85 0.22(cid:77)F BAT85 VIN VSEC VIN + LTC3728 LTC3728 1(cid:77)F VN2222LL BAT85 TG1 TG1 RSENSE RSENSE N-CH VOUT N-CH VOUT EXTVCC SW T1 EXTVCC SW L1 1:N R6 + + FCB BG1 COUT BG1 COUT R5 N-CH N-CH SGND PGND PGND 3728 F06a 3728 F06b Figure 6a. Secondary Output Loop and EXTV Connection Figure 6b. Capacitive Charge Pump for EXTV CC CC 3728fg 20

LTC3728 APPLICATIONS INFORMATION reference by the error amplifi er. The output voltage is given Soft-Start/Run Function by the equation: The RUN/SS1 and RUN/SS2 pins are multipurpose pins (cid:1) R2(cid:4) that provide a soft-start function and a means to shut down V =0.8V 1+ OUT (cid:2) (cid:5) the LTC3728. Soft-start reduces the input power source’s (cid:3) R1(cid:6) surge currents by gradually increasing the controller’s current limit (proportional to V ). This pin can also be where R1 and R2 are defi ned in Figure 2. ITH used for power supply sequencing. SENSE+/SENSE– PINS An internal 1.2μA current source charges up the CSS capacitor. When the voltage on RUN/SS1 (RUN/SS2) The common mode input range of the current comparator reaches 1.5V, the particular controller is permitted to start sense pins is from 0V to (1.1)INTV . Continuous linear CC operating. As the voltage on RUN/SS increases from 1.5V operation is guaranteed throughout this range allowing to 3.0V, the internal current limit is increased from 25mV/ output voltage setting from 0.8V to 7.7V, depending upon R to 75mV/R . The output current limit ramps SENSE SENSE the voltage applied to EXTV . A differential NPN input CC up slowly, taking an additional 1.25s/μF to reach full cur- stage is biased with internal resistors from an internal 2.4V rent. The output current thus ramps up slowly, reducing source, as shown in the Functional Diagram. This requires the starting surge current required from the input power that current either be sourced or sunk from the SENSE supply. If RUN/SS has been pulled all the way to ground pins depending on the output voltage. If the output voltage there is a delay before starting of approximately: is below 2.4V, current will fl ow out of both SENSE pins to the main output. The output can be easily preloaded by 1.5V t = C =(1.25s/μF)C the VOUT resistive divider to compensate for the current DELAY 1.2μA SS SS comparator’s negative input bias current. The maximum current fl owing out of each pair of SENSE pins is: 3V(cid:1)1.5V t = C =(1.25s/μF)C IRAMP SS SS ISENSE+ + ISENSE– = (2.4V – VOUT)/24k 1.2μA Since VOSENSE is servoed to the 0.8V reference voltage, By pulling both RUN/SS pins below 1V, the LTC3728 is put we can choose R1 in Figure 2 to have a maximum value into low current shutdown (I = 20μA). The RUN/SS pins Q to absorb this current. can be driven directly from logic, as shown in Figure 7. Diode D1 in Figure 7 reduces the start delay but allows (cid:1) 0.8V (cid:4) R1(MAX)=24k(cid:2) (cid:5) CSS to ramp up slowly providing the soft-start function. (cid:3)2.4V–VOUT(cid:6) Each RUN/SS pin has an internal 6V Zener clamp (see the Functional Diagram). for V < 2.4V OUT Regulating an output voltage of 1.8V, the maximum value of R1 should be 32k. Note that for an output voltage above 2.4V, R1 has no maximum value necessary to absorb the sense currents; however, R1 is still bounded by the V OSENSE feedback current. 3728fg 21

LTC3728 APPLICATIONS INFORMATION Fault Conditions: Overcurrent Latchoff troubleshooting of the circuit and PC layout. The internal short-circuit and foldback current limiting still remains The RUN/SS pins also provide the ability to latch off the active, thereby protecting the power supply system from controller(s) when an overcurrent condition is detected. The failure. After the design is complete, a decision can be RUN/SS capacitor, C , is used initially to turn on and limit SS made whether to enable the latchoff feature. the inrush current. After the controller has been started and given adequate time to charge up the output capacitor and The value of the soft-start capacitor C may need to be SS provide full load current, the RUN/SS capacitor is used for scaled with output voltage, output capacitance and load a short-circuit timer. If the regulator’s output voltage falls current characteristics. The minimum soft-start capaci- to less than 70% of its nominal value after C reaches tance is given by: SS 4.1V, C begins discharging on the assumption that the SS C > (C )(V ) (10–4) (R ) SS OUT OUT SENSE output is in an overcurrent condition. If the condition lasts for a long enough period, as determined by the size of the The minimum recommended soft-start capacitor of CSS and the specifi ed discharge current, the controller will CSS = 0.1μF will be suffi cient for most applications. be shut down until the RUN/SS pin voltage is recycled. Fault Conditions: Current Limit and Current Foldback If the overload occurs during start-up, the time can be approximated by: The LTC3728 current comparator has a maximum sense voltage of 75mV, resulting in a maximum MOSFET cur- t ≈ [C (4.1 – 1.5 + 4.1 – 3.5)]/(1.2μA) LO1 SS = 2.7 • 106 (C ) rent of 75mV/RSENSE. The maximum value of current SS limit generally occurs with the largest V at the highest IN If the overload occurs after start-up, the voltage on C SS ambient temperature—conditions that cause the highest will begin discharging from the Zener clamp voltage: power dissipation in the top MOSFET. t ≈ [C (6 – 3.5)]/(1.2μA) = 2.1 • 106 (C ) LO2 SS SS The LTC3728 includes current foldback to help further This built-in overcurrent latchoff can be overridden by limit load current when the output is shorted to ground. providing a pull-up resistor to the RUN/SS pin, as shown The foldback circuit is active even when the overload in Figure 7. This resistance shortens the soft-start period shutdown latch previously described is overridden. If the and prevents the discharge of the RUN/SS capacitor during output falls below 70% of its nominal output level, then an over current condition. Tying this pull-up resistor to the maximum sense voltage is progressively lowered from V (as in Figure 7) defeats overcurrent latchoff. 75mV to 25mV. Under short-circuit conditions with very IN low duty cycles, the LTC3728 will begin cycle skipping in Why should you defeat overcurrent latchoff? During the order to limit the short-circuit current. In this situation, prototyping stage of a design there may be a problem the bottom MOSFET will be dissipating most of the power with noise pickup or poor layout, causing the protection but less than in normal operation. The short-circuit ripple circuit to latch off. Defeating this feature will easily allow current is determined by the minimum on-time t ON(MIN) of the LTC3728 (less than 200ns), the input voltage and VIN inductor value: 3.3V OR 5V RUN/SS D1 RSS* ΔIL(SC) = tON(MIN) (VIN/L) The resulting short-circuit current is: CSS 25mV 1 I = + (cid:1)I SC L(SC) R 2 *OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF SENSE 3728 F07 Figure 7. RUN/SS Pin Interfacing 3728fg 22

LTC3728 APPLICATIONS INFORMATION Fault Conditions: Overvoltage Protection (Crowbar) the external and internal oscillators. This type of phase detector will not lock up on input frequencies close to the The overvoltage crowbar is designed to blow a system harmonics of the VCO center frequency. The PLL hold-in input fuse when the output voltage of the regulator rises range, Δf , is equal to the capture range, Δf much higher than nominal levels. The crowbar causes H C: huge currents to fl ow that blow the fuse to protect against Δf = Δf = ±0.5 f (250kHz-550kHz) H C O a shorted top MOSFET, if the short occurs while the con- The output of the phase detector is a complementary pair troller is operating. of current sources charging or discharging the external A comparator monitors the output for overvoltage con- fi lter network on the PLLFLTR pin. ditions. The comparator (OV) detects overvoltage faults If the external frequency (f ) is greater than the oscil- PLLIN greater than 7.5% above the nominal output voltage. When lator frequency, f , current is sourced continuously, OSC this condition is sensed, the top MOSFET is turned off pulling up the PLLFLTR pin. When the external frequency is and the bottom MOSFET is turned on until the overvolt- less than f , current is sunk continuously, pulling down OSC age condition is cleared. The output of this comparator the PLLFLTR pin. If the external and internal frequencies is only latched by the overvoltage condition itself and are the same but exhibit a phase difference, the current will, therefore, allow a switching regulator system hav- sources turn on for an amount of time corresponding to the ing a poor PC layout to function while the design is being phase difference. Thus, the voltage on the PLLFLTR pin is debugged. The bottom MOSFET remains on continuously adjusted until the phase and frequency of the external and for as long as the OV condition persists. If V returns OUT internal oscillators are identical. At this stable operating to a safe level, normal operation automatically resumes. A point, the phase comparator output is open and the fi lter shorted top MOSFET will result in a high current condition capacitor C holds the voltage. The LTC3728 PLLIN pin LP which will open the system fuse. The switching regulator must be driven from a low impedance source such as a will regulate properly with a leaky top MOSFET by altering logic gate located close to the pin. When using multiple the duty cycle to accommodate the leakage. LTC3728’s (or LTC3729’s, as shown in Figure 14) for a phase-locked system, the PLLFLTR pin of the master Phase-Locked Loop and Frequency Synchronization oscillator should be biased at a voltage that will guarantee The LTC3728 has a phase-locked loop comprised of an the slave oscillator(s) ability to lock onto the master’s internal voltage controlled oscillator and phase detector. frequency. A DC voltage of 0.7V to 1.7V applied to the This allows the top MOSFET turn-on to be locked to the master oscillator’s PLLFLTR pin is recommended in order rising edge of an external source. The frequency range to meet this requirement. The resultant operating frequency of the voltage controlled oscillator is ±50% around the can range from 300kHz to 470kHz. center frequency, f . A voltage applied to the PLLFLTR O The loop fi lter components (C , R ) smooth out the pin of 1.2V corresponds to a frequency of approximately LP LP current pulses from the phase detector and provide a 400kHz. The nominal operating frequency range of the stable input to the voltage controlled oscillator. The fi lter LTC3728 is 250kHz to 550kHz. components, C and R , determine how fast the loop LP LP The phase detector used is an edge-sensitive digital acquires lock. Typically, R =10kΩ, and C is 0.01μF LP LP type which provides zero degrees phase shift between to 0.1μF. 3728fg 23

LTC3728 APPLICATIONS INFORMATION Minimum On-Time Considerations from the auxiliary windings. With the loop in continuous mode, the auxiliary outputs may nominally be loaded Minimum on-time, t , is the smallest time duration ON(MIN) without regard to the primary output load. that the LTC3728 is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate The secondary output voltage, V , is normally set (as SEC charge required to turn on the top MOSFET. Low duty shown in Figure 6a) by the turns ratio N of the trans- cycle applications may approach this minimum on-time former: limit and care should be taken to ensure that: VSEC ≅ (N + 1) VOUT V t < OUT However, if the controller goes into Burst Mode operation ON(MIN) V (f) IN and halts switching due to a light primary load current, then V will droop. An external resistive divider from V to SEC SEC If the duty cycle falls below what can be accommodated the FCB pin sets a minimum voltage V : SEC(MIN) by the minimum on-time, the LTC3728 will begin to skip cycles. The output voltage will continue to be regulated, (cid:2) R6(cid:5) V (cid:1)0.8V 1+ but the ripple voltage and current will increase. SEC(MIN) (cid:4)(cid:3) R5(cid:7)(cid:6) The typical tested minimum on-time of the LTC3728 is where R5 and R6 are shown in Figure 2. 100ns under an ideal condition without switching noise. However, the minimum on-time can be affected by PCB If V drops below this level, the FCB voltage forces SEC switching noise in the voltage and current loops. With temporary continuous switching operation until V is SEC reasonably good PCB layout, minimum 30% inductor again above its minimum. current ripple and about 15mV sensing ripple voltage, In order to prevent erratic operation if no external connec- 200ns minimum on-time is a conservative number to tions are made to the FCB pin, the FCB pin has a 0.18μA start with. internal current source pulling the pin high. Include this current when choosing resistor values R5 and R6. FCB Pin Operation Table 1 summarizes the possible states available on the The FCB pin can be used to regulate a secondary winding FCB pin: or as a logic-level input. Continuous operation is forced on both controllers when the FCB pin drops below 0.8V. Table 1 During continuous mode, current fl ows continuously in FCB Pin Condition the transformer primary. The secondary winding(s) draw 0V to 0.75V Forced Continuous Both Controllers current only when the bottom, synchronous switch is on. (Current Reversal Allowed—Burst When primary load currents are low and/or the V /V Inhibited) IN OUT ratio is low, the synchronous switch may not be on for a 0.85V < V < 4.0V Minimum Peak Current Induces FCB Burst Mode Operation suffi cient amount of time to transfer power from the output No Current Reversal Allowed capacitor to the secondary load. Forced continuous opera- Feedback Resistors Regulating a Secondary Winding tion will support secondary windings providing there is >4.8V Burst Mode Operation Disabled suffi cient synchronous switch duty factor. Thus, the FCB Constant-Frequency Mode Enabled input pin removes the requirement that power must be No Current Reversal Allowed No Minimum Peak Current drawn from the inductor primary in order to extract power 3728fg 24

LTC3728 APPLICATIONS INFORMATION Voltage Positioning Although all dissipative elements in the circuit produce losses, four main sources usually account for most Voltage positioning can be used to minimize peak-to-peak of the losses in LTC3728 circuits: 1) LTC3728 V cur- output voltage excursions under worst-case transient IN rent (including loading on the 3.3V internal regulator), loading conditions. The open-loop DC gain of the control 2) INTV regulator current, 3) I2R losses, 4) Topside loop is reduced depending upon the maximum load step CC MOSFET transition losses. specifi cations. Voltage positioning can easily be added to the LTC3728 by loading the I pin with a resistive divider 1. The V current has two components: the fi rst is the TH IN having a Thevenin equivalent voltage source equal to the DC supply current given in the Electrical Characteristics midpoint operating voltage range of the error amplifi er, or table, which excludes MOSFET driver and control cur- 1.2V (see Figure 8). rents; the second is the current drawn from the 3.3V linear regulator output. V current typically results in The resistive load reduces the DC loop gain while main- IN a small (<0.1%) loss. taining the linear control range of the error amplifi er. The maximum output voltage deviation can theoretically be 2. INTV current is the sum of the MOSFET driver and CC reduced to half, or alternatively, the amount of output control currents. The MOSFET driver current results capacitance can be reduced for a particular application. from switching the gate capacitance of the power A complete explanation is included in Design Solutions MOSFETs. Each time a MOSFET gate is switched from 10 (see www.linear.com). low to high to low again, a packet of charge dQ moves from INTV to ground. The resulting dQ/dt is CC a current out of INTV that is typically much larger INTVCC CC than the control circuit current. In continuous mode, RT2 I = f(Q Q ), where Q and Q are the gate ITH GATECHG T B T B charges of the topside and bottom side MOSFETs. RT1 RC LTC3728 CC Supplying INTVCC power through the EXTVCC switch input from an output-derived source will scale the V 3728 F08 IN current required for the driver and control circuits by Figure 8. Active Voltage Positioning a factor of (Duty Cycle)/(Effi ciency). For example, in a Applied to the LTC3728 20V to 5V application, 10mA of INTV current results CC in approximately 2.5mA of V current. This reduces IN the mid-current loss from 10% or more (if the driver Effi ciency Considerations was powered directly from V ) to only a few percent. IN The percent effi ciency of a switching regulator is equal to 3. I2R losses are predicted from the DC resistances of the the output power divided by the input power times 100%. fuse (if used), MOSFET, inductor, current sense resis- It is often useful to analyze individual losses to determine tor, and input and output capacitor ESR. In continuous what is limiting the effi ciency and which change would mode, the average output current fl ows through L and produce the most improvement. Percent effi ciency can R , but is “chopped” between the topside MOSFET SENSE be expressed as: and the synchronous MOSFET. If the two MOSFETs have approximately the same R , then the resis- %Effi ciency = 100% – (L1 + L2 + L3 + ...) DS(ON) tance of one MOSFET can simply be summed with the where L1, L2, etc. are the individual losses as a percent- resistances of L, R and ESR to obtain I2R losses. SENSE age of input power. For example, if each R = 30mΩ, R = 50mΩ, DS(ON) L 3728fg 25

LTC3728 APPLICATIONS INFORMATION R = 10mΩ and R = 40mΩ (sum of both input this recovery time, V can be monitored for excessive SENSE ESR OUT and output capacitance losses), then the total resistance overshoot or ringing, which would indicate a stability is 130mΩ. This results in losses ranging from 3% to problem. OPTI-LOOP compensation allows the transient 13% as the output current increases from 1A to 5A for response to be optimized over a wide range of output a 5V output, or a 4% to 20% loss for a 3.3V output. capacitance and ESR values. The availability of the I pin TH Effi ciency varies as the inverse square of V for the not only allows optimization of control loop behavior but OUT same external components and output power level. The also provides a DC-coupled and AC-fi ltered closed loop combined effects of increasingly lower output voltages response test point. The DC step, rise time and settling and higher currents required by high performance digital at this test point truly refl ects the closed loop response. systems is not doubling but quadrupling the importance Assuming a predominantly second order system, phase of loss terms in the switching regulator system! margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth 4. Transition losses apply only to the topside MOSFET(s), can also be estimated by examining the rise time at the and become signifi cant only when operating at high pin. The I external components shown in the Figure 1 input voltages (typically 15V or greater). Transition TH circuit will provide an adequate starting point for most losses can be estimated from: applications. Transition Loss = (1.7) V 2 I C f IN O(MAX) RSS The I series R -C fi lter sets the dominant pole-zero TH C C Other “hidden” losses such as copper trace and internal loop compensation. The values can be modifi ed slightly battery resistances can account for an additional 5% to (from 0.5 to 2 times their suggested values) to optimize 10% effi ciency degradation in portable systems. It is very transient response once the fi nal PC layout is done and important to include these system level losses during the the particular output capacitor type and value have been design phase. The internal battery and fuse resistance determined. The output capacitors need to be selected losses can be minimized by ensuring C has adequate IN because the various types and values determine the loop charge storage and very low ESR at the switching frequency. gain and phase. An output current pulse of 20% to 80% A 25W supply will typically require a minimum of 20μF of full-load current having a rise time of 1μs to 10μs will to 40μF of capacitance having a maximum of 20mΩ to produce output voltage and I pin waveforms that will TH 50mΩ of ESR. The LTC3728 2-phase architecture typically give a sense of the overall loop stability without break- halves this input capacitance requirement over competing ing the feedback loop. Placing a power MOSFET directly solutions. Other losses, including Schottky conduction across the output capacitor and driving the gate with an losses during dead time and inductor core losses, generally appropriate signal generator is a practical way to produce account for less than 2% total additional loss. a realistic load step condition. The initial output voltage step resulting from the step change in output current may Checking Transient Response not be within the bandwidth of the feedback loop, so this The regulator loop response can be checked by looking at signal cannot be used to determine phase margin. This the load current transient response. Switching regulators is why it is better to look at the I pin signal, which is TH take several cycles to respond to a step in DC (resistive) in the feedback loop and is the fi ltered and compensated load current. When a load step occurs, V shifts by control loop response. The gain of the loop will be in- OUT an amount equal to ΔI (ESR), where ESR is the ef- creased by increasing R and the bandwidth of the loop LOAD C fective series resistance of C . ΔI also begins to will be increased by decreasing C . If R is increased by OUT LOAD C C charge or discharge C , generating the feedback error the same factor that C is decreased, the zero frequency OUT C signal that forces the regulator to adapt to the current will be kept the same, thereby keeping the phase shift the change and return V to its steady-state value. During same in the most critical frequency range of the feedback OUT 3728fg 26

LTC3728 APPLICATIONS INFORMATION loop. The output voltage settling behavior is related to the ging into the supply from hell. The main power line in an stability of the closed-loop system and will demonstrate automobile is the source of a number of nasty potential the actual overall supply performance. transients, including load-dump, reverse-battery and double-battery. A second, more severe transient is caused by switching in loads with large (>1μF) supply bypass capacitors. The Load-dump is the result of a loose battery cable. When the discharged bypass capacitors are effectively put in parallel cable breaks connection, the fi eld collapse in the alterna- with C , causing a rapid drop in V . No regulator can tor can cause a positive spike as high as 60V which takes OUT OUT alter its delivery of current quickly enough to prevent this several hundred milliseconds to decay. Reverse-battery is sudden step change in output voltage if the load switch just what it says, while double-battery is a consequence of resistance is low and it is driven quickly. If the ratio of tow truck operators fi nding that a 24V jump start cranks C to C is greater than 1:50, the switch rise time cold engines faster than 12V. LOAD OUT should be controlled so that the load rise time is limited to The network shown in Figure 9 is the most straight for- approximately 25 • C . Thus, a 10μF capacitor would LOAD ward approach to protect a DC/DC converter from the require a 250μs rise time, limiting the charging current ravages of an automotive power line. The series diode to about 200mA. prevents current from fl owing during reverse-battery, while the transient suppressor clamps the input voltage Automotive Considerations: Plugging into the during load-dump. Note that the transient suppressor Cigarette Lighter should not conduct during double-battery operation, but As battery-powered devices go mobile, there is a natural must still clamp the input voltage below breakdown of the interest in plugging into the cigarette lighter in order to converter. Although the LTC3728 has a maximum input conserve or even recharge battery packs during opera- voltage of 36V, most applications will be limited to 30V tion. But before you connect, be advised: you are plug- by the MOSFET BVDSS. 50A IPK RATING VIN 12V LTC3728 TRANSIENT VOLTAGE SUPPRESSOR GENERAL INSTRUMENT 1.5KA24A 3728 F09 Figure 9. Automotive Application Protection 3728fg 27

LTC3728 APPLICATIONS INFORMATION Design Example Choosing 1% resistors; R1 = 25.5k and R2 = 32.4k yields an output voltage of 1.816V. As a design example for one channel, assume V = 12V IN (nominal), V = 22V(max), V = 1.8V, I = 5A, and The power dissipation on the topside MOSFET can be IN OUT MAX f = 300kHz. easily estimated. Choosing a Siliconix Si4412DY results in R = 0.042Ω, C = 100pF. At maximum input The inductance value is chosen fi rst based on a 30% ripple DS(ON) RSS voltage with T(estimated) = 50°C: current assumption. The highest value of ripple current occurs at the maximum input voltage. Tie the PLLFLTR 1.8V 2 P = (5) [1+(0.005)(50°C–25°C)] pin to a resistive divider using the INTV pin generating MAIN CC 22V 1V for 300kHz operation. The minimum inductance for 2 (0.042(cid:1))+1.7(22V) (5A)(100pF)(300kHz 30% ripple current is: =220mW V (cid:2) V (cid:5) (cid:1)I = OUT 1– OUT L (cid:3) (cid:6) A short-circuit to ground will result in a folded back cur- (f)(L)(cid:4) V (cid:7) IN rent of: A 4.7μH inductor will produce 23% ripple current and a 25mV 1(cid:2)200ns(22V)(cid:5) 3.3μH will result in 33%. The peak inductor current will I = + =3.2A SC (cid:3) (cid:6) 0.01(cid:1) 2(cid:4) 3.3μH (cid:7) be the maximum DC value plus one-half the ripple cur- rent, or 5.84A, for the 3.3μH value. Increasing the ripple current will also help ensure that the minimum on-time with a typical value of RDS(ON) and δ = (0.005/°C)(20) = 0.1. The resulting power dissipated in the bottom MOSFET of 100ns is not violated. The minimum on-time occurs at is: maximum V : IN 22V–1.8V 2 tON(MIN)= VOUT = 1.8V =273ns PSYNC= 22V (3.2A) (1.1)(0.042(cid:1)) V f 22V(300kHz) IN(MAX) =434mW The R resistor value can be calculated by using the SENSE which is less than under full-load conditions. maximum current sense voltage specifi cation with some C is chosen for an RMS current rating of at least 3A at accommodation for tolerances: IN temperature assuming only this channel is on. C is OUT 60mV chosen with an ESR of 0.02Ω for low output ripple. The R (cid:2) (cid:3)0.01(cid:1) SENSE 5.84A output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to Since the output voltage is below 2.4V the output resis- ESR is approximately: tive divider will need to be sized to not only set the output V = R (ΔI ) = 0.02Ω(1.67A) = 33mV voltage but also to absorb the SENSE pins specifi ed input ORIPPLE ESR L P–P current. (cid:1) 0.8V (cid:4) R1 =24k (MAX) (cid:2) (cid:5) (cid:3)2.4V–V (cid:6) OUT (cid:1) 0.8V (cid:4) =24K =32k (cid:2) (cid:5) (cid:3)2.4V–1.8V(cid:6) 3728fg 28

LTC3728 APPLICATIONS INFORMATION PC Board Layout Checklist 2. Are the signal and power grounds kept separate? The combined LTC3728 signal ground pin and the ground When laying out the printed circuit board, the following return of C must return to the combined C checklist should be used to ensure proper operation of INTVCC OUT (–) terminals. The path formed by the top N-channel the LTC3728. These items are also illustrated graphically MOSFET, Schottky diode and the C capacitor should in the layout diagram of Figure 10. Figure 11 illustrates IN have short leads and PC trace lengths. The output the current waveforms present in the various branches capacitor (–) terminals should be connected as close of the 2-phase synchronous regulators operating in the as possible to the (–) terminals of the input capacitor continuous mode. Check the following in your layout: by placing the capacitors next to each other and away 1. Are the top N-channel MOSFETs M1 and M3 located from the Schottky loop described above. within 1cm of each other with a common drain connec- 3. Do the LTC3728 V pins resistive dividers connect tion at C ? Do not attempt to split the input decoupling OSENSE IN to the (+) terminals of C ? The resistive divider must for the two channels as it can cause a large resonant OUT be connected between the (+) terminal of C and loop. OUT RPU VPULL-UP 1 28 (<7V) RUN/SS1 PGOOD PGOOD 2 27 L1 RSENSE SENSE1+ TG1 VOUT1 3 26 R2 SENSE1– SW1 R1 4 25 CB1 M1 M2 VOSENSE1 BOOST1 D1 5 24 PLLFLTR VIN fIN 6 PLLIN BG1 23 COUT1 RIN + INTVCC 7 FCB EXTVCC 22 CIN LTC3728 CVIN GND 8 21 + ITH1 INTVCC + VIN + 9 20 CINTVCC SGND PGND COUT2 10 19 3.3V 3.3VOUT BG2 11 18 ITH2 BOOST2 D2 12 17 CB2 M3 M4 VOSENSE2 SW2 R3 R4 13 16 RSENSE SENSE2– TG2 VOUT2 L2 14 15 SENSE2+ RUN/SS2 3728 F10 Figure 10. LTC3728 Recommended Printed Circuit Layout Diagram 3728fg 29

LTC3728 APPLICATIONS INFORMATION SW1 L1 RSENSE1 VOUT1 + D1 COUT1 RL1 VIN RIN + CIN SW2 L2 RSENSE2 VOUT2 + BOLD LINES INDICATE D2 COUT2 RL2 HIGH, SWITCHING CURRENT LINES. KEEP LINES TO A MINIMUM LENGTH. 3728 F11 Figure 11. Branch Current Waveforms signal ground. The R2 and R4 connections should not 6. Keep the switching nodes (SW1, SW2), top gate nodes be along the high current input feeds from the input (TG1, TG2), and boost nodes (BOOST1, BOOST2) away capacitor(s). from sensitive small-signal nodes, especially from the opposites channel’s voltage and current sensing 4. Are the SENSE– and SENSE+ leads routed together feedback pins. All of these nodes have very large and with minimum PC trace spacing? The fi lter capacitor fast moving signals and therefore should be kept on between SENSE+ and SENSE– should be as close as the output side of the LTC3728 and occupy minimum possible to the IC. Ensure accurate current sensing PC trace area. with Kelvin connections at the SENSE resistor. 7. Use a modifi ed “star ground” technique: a low imped- 5. Is the INTV decoupling capacitor connected close CC ance, large copper area central grounding point on to the IC, betweenthe INTV and the power ground CC the same side of the PC board as the input and output pins? This capacitor carries the MOSFET drivers current capacitors with tie-ins for the bottom of the INTV peaks. An additional 1μF ceramic capacitor placed im- CC decoupling capacitor, the bottom of the voltage feedback mediately next to the INTV and PGND pins can help CC resistive divider and the SGND pin of the IC. improve noise performance substantially. 3728fg 30

LTC3728 APPLICATIONS INFORMATION PC Board Layout Debugging Reduce V from its nominal level to verify operation IN of the regulator in dropout. Check the operation of the Start with one controller on at a time. It is helpful to use undervoltage lockout circuit by further lowering V while a DC-50MHz current probe to monitor the current in the IN monitoring the outputs to verify operation. inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope Investigate whether any problems exist only at higher out- to the internal oscillator and probe the actual output volt- put currents or only at higher input voltages. If problems age. Check for proper performance over the operating coincide with high input voltages and low output currents, voltage and current range expected in the application. The look for capacitive coupling between the BOOST, SW, TG, frequency of operation should be maintained over the input and possibly BG connections and the sensitive voltage voltage range down to dropout and until the output load and current pins. The capacitor placed across the current drops below the low current operation threshold—typically sensing pins needs to be placed immediately adjacent to 10% to 20% of the maximum designed current level in the pins of the IC. This capacitor helps to minimize the Burst Mode operation. effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with The duty cycle percentage should be maintained from cycle high current output loading at lower input voltages, look to cycle in a well designed, low noise PCB implementation. for inductive coupling between C , Schottky and the top Variation in the duty cycle at a subharmonic rate can sug- IN MOSFET components to the sensitive current and voltage gest noise pickup at the current or voltage sensing inputs sensing traces. In addition, investigate common ground or inadequate loop compensation. Overcompensation of path voltage pickup between these components and the the loop can be used to tame a poor PC layout if regulator SGND pin of the IC. bandwidth optimization is not required. Only after each controller is checked for their individual performance An embarrassing problem, which can be missed in an should both controllers be turned on at the same time. otherwise properly working switching regulator, results A particularly diffi cult region of operation is when one when the current sensing leads are hooked up backwards. controller channel is nearing its current comparator trip The output voltage under this improper hookup will still point when the other channel is turning on its top MOSFET. be maintained but the advantages of current mode control This occurs around 50% duty cycle on either channel due will not be realized. Compensation of the voltage loop will to the phasing of the internal clocks and may cause minor be much more sensitive to component selection. This duty cycle jitter. behavior can be investigated by temporarily shorting out the current sensing resistor—don’t worry, the regulator Short-circuit testing can be performed to verify proper will still maintain control of the output voltage. overcurrent latchoff, or 5μA can be provided to the RUN/SS pin(s) by resistors from V to prevent the short-circuit IN latchoff from occurring. 3728fg 31

LTC3728 TYPICAL APPLICATIONS 59k 1M 100k VPULL-UP MBRS1100T3 + (<7V) T1, 1:1.8 33(cid:77)F 1 RUN/SS1 PGOOD 28 PGOOD 10(cid:77)H 25V 0.1(cid:77)F 2 27 0.015(cid:55) VOUT1 SENSE1+ TG1 5V 180pF 1000pF 3A; 4A PEAK 20k 105k, 1% 3 SENSE1– SW1 26 8 5 1% 4 25 0.1(cid:77)F M1 M2 D1 LT1121 ON/OFF VOSENSE1 BOOST1 M14B0RTM3 3 2 1 5 24 220k VOUT3 PLLFLTR VIN 12V 120mA 6 PLLIN BG1 23 150(cid:77)F, 6.3V + 33pF 7 FCB EXTVCC 22 CMDSH-3TR 10(cid:55) 2520(cid:77)VF PANASON+IC SP 100k 12(cid:77)5VF LTC3728 0.1(cid:77)F GND 8 21 15k ITH1 INTVCC 1(cid:77)F + + 33pF 1000pF 9 SGND PGND 20 10V CMDS4.H7-(cid:77)3FTR PA1N8A0S(cid:77)OFN, I4CV SP VIN 10 19 7V TO 3.3V 3.3VOUT BG2 28V 11 18 D2 ITH2 BOOST2 MBRM 15k 1000pF 12 17 0.1(cid:77)F M3 M4 140T3 20k VOSENSE2 SW2 1% 13 16 VOUT2 SENSE2– TG2 3.3V 180pF 613%.4k 1000pF 14 SENSE2+ RUN/SS2 15 6.L31(cid:77)H 0.01(cid:55) 5A; 6A PEAK 0.1(cid:77)F 3728 F12 VIN: 7V TO 28V VOUT: 5V, 3A/3.3V, 5A/12V, 120mA SWITCHING FREQUENCY = 250kHz MI, M2, M3, M4: NDS8410A L1: SUMIDA CEP123-6R3MC T1: 10(cid:77)H 1:1.8 — DALE LPE6562-A262 GAPPED E-CORE OR BH ELECTRONICS #501-0657 GAPPED TOROID Figure 12. LTC3728 High Effi ciency Low Noise 5V/3A, 3.3V/5A, 12V/120mA Regulator 3728fg 32

LTC3728 TYPICAL APPLICATIONS VPULL-UP (<7V) 1 28 RUN/SS1 PGOOD PGOOD L1 8(cid:77)H 0.1(cid:77)F 2 27 0.015(cid:55) VOUT1 SENSE1+ TG1 5V 27pF 1000pF 3A; 4A PEAK 105k 3 26 20k 1% SENSE1– SW1 1% 4 25 0.1(cid:77)F VOSENSE1 BOOST1 5 24 0.01(cid:77)F PLLFLTR VIN M1 10k 1000pF 47(cid:77)F 6 23 fSYNC PLLIN BG1 6.3V 33pF 10(cid:55) 22(cid:77)F + 7 22 CMDSH-3TR 50V FCB EXTVCC LTC3728 0.1(cid:77)F GND 8 21 15k ITH1 INTVCC 1(cid:77)F + + 220pF 9 20 10V 4.7(cid:77)F 33pF SGND PGND CMDSH-3TR 56(cid:77)F, 4V VIN 10 19 5.2V TO 3.3V 3.3VOUT BG2 28V 11 18 ITH2 BOOST2 15k 220pF 12 17 0.1(cid:77)F 20k VOSENSE2 SW2 M2 1% 13 16 VOUT2 SENSE2– TG2 3.3V 63.4k 1000pF L2 0.015(cid:55) 3A; 4A PEAK 27pF 1% 14 SENSE2+ RUN/SS2 15 8(cid:77)H 0.1(cid:77)F 3728 F13 VIN: 5.2V TO 28V SWITCHING FREQUENCY = 250kHz TO 550kHz L1, L2: 8(cid:77)H SUMIDA CEP1238R0MC VOUT: 5V, 4A/3.3V, 4A MI, M2: FDS6982S OUTPUT CAPACITORS: PANASONIC SP SERIES Figure 13. LTC3728 5V/4A, 3.3V/4A Regulator with External Frequency Synchronization 3728fg 33

LTC3728 PACKAGE DESCRIPTION G Package 28-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 9.90 – 10.50* (.390 – .413) 1.25±0.12 28 272625 24 232221201918171615 7.8 – 8.2 5.3 – 5.7 7.40 – 8.20 (.291 – .323) 0.42±0.03 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10 1112 13 14 2.0 5.00 – 5.60** (.079) (.197 – .221) MAX 0° – 8° 0.65 0.09 – 0.25 0.55 – 0.95 (.0256) (.0035 – .010) (.022 – .037) BSC 0.05 NOTE: 0.22 – 0.38 (.002) 1. CONTROLLING DIMENSION: MILLIMETERS (.009 – .015) MIN MILLIMETERS TYP G28 SSOP 0204 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 3728fg 34

LTC3728 PACKAGE DESCRIPTION UH32 Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693 Rev D) 0.70±0.05 5.50±0.05 4.10±0.05 3.45± 0.05 3.50 REF (4 SIDES) 3.45± 0.05 PACKAGE OUTLINE 0.25± 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.30 TYP 5.00± 0.10 0.75± 0.05 R = 0T.Y0P5 R = 0.T1Y1P5 OR 0.35 × 45° CHAMFER (4 SIDES) 0.00 – 0.05 31 32 PIN 1 0.40± 0.10 TOP MARK (NOTE 6) 1 2 3.45± 0.10 3.50 REF (4-SIDES) 3.45± 0.10 (UH32) QFN 0406 REV D 0.200 REF 0.25± 0.05 0.50 BSC NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3728fg Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 35 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC3728 TYPICAL APPLICATION IIN 12VIN CIN I1 IIN* 0° BUCK: 2.5V/15A OPEN PHASMD TG1 U1 TG2 180° BUCK: 2.5V/15A 2.5VO/30A I1 LTC3729 90° CLKOUT I2 I2 I3 I3 90° BUCK: 1.5V/15A 1.5VO/15A U2 TTGG12 270° BUCK: 1.8V/15A 1.8VO/15A I4 LTC3728 *INPUT RIPPLE CURRENT CANCELLATION 90° I4 INCREASES THE RIPPLE FREQUENCY AND PLLIN REDUCES THE RMS INPUT RIPPLE CURRENT 3728 F14 THUS, SAVING INPUT CAPACITORS Figure 14. Multioutput PolyPhase Application RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1350 High Power Step-Down Synchronous DC/DC High Effi ciency 5V to 3.3V Conversion at Up to 15A Controller in SO-8 LTC1628/LTC1628-PG/ 2-Phase, Dual Output Synchronous Step-Down Reduces C and C , Power Good Output Signal, Synchronizable, IN OUT LTC1628-SYNC DC/DC Controller 3.5V ≤ V ≤ 36V, I Up to 20A, 0.8V ≤ V ≤ 5V IN OUT OUT LTC1629/ 20A to 200A PolyPhase® Synchronous Controllers Expandable from 2-Phase to 12-Phase, Uses All Surface Mount LTC1629-PG Components, No Heat Sink, V Up to 36V IN LTC1702 No R ™ 2-Phase Dual Synchronous 550kHz, No Sense Resistor SENSE Step-Down Controller LTC1703 No R 2-Phase Dual Synchronous Step-Down Mobile Pentium III Processors, 550kHz, V ≤ 7V SENSE IN Controller with 5-Bit Mobile VID Control LTC1708-PG 2-Phase, Dual Synchronous Controller with 3.5V ≤ V ≤ 36V, VID Sets V , PGOOD IN OUT1 Mobile VID LT1709/LT1709-8 High Effi ciency, 2-Phase Synchronous Step-Down 1.3V ≤ V ≤ 3.5V, Current Mode Ensures Accurate Current Sharing, OUT Switching Regulators with 5-Bit VID 3.5V ≤ V ≤ 36V IN LTC1735 High Effi ciency Synchronous Step-Down Output Fault Protection, 16-Pin SSOP Switching Regulator LTC1736 High Effi ciency Synchronous Controller with Output Fault Protection, 24-Pin SSOP, 3.5V ≤ V ≤ 36V IN 5-Bit Mobile VID Control LTC1778 No R Current Mode Synchronous Up to 97% Effi ciency, 4V ≤ V ≤ 36V, 0.8V ≤ V ≤ (0.9)(V ), SENSE IN OUT IN Step-Down Controller I Up to 20A OUT LTC1929/LTC1929-PG 2-Phase Synchronous Controllers Up to 42A, Uses All Surface Mount Components, No Heat Sinks, 3.5V ≤ V ≤ 36V IN LTC3711 No R Current Mode Synchronous Step-Down Up to 97% Effi ciency, Ideal for Pentium III Processors, 0.925V ≤ V ≤ 2V, SENSE OUT Controller with Digital 5-Bit Interface 4V ≤ V ≤ 36V, I Up to 20A IN OUT LTC3729 20A to 200A, 550kHz PolyPhase Synchronous Expandable from 2-Phase to 12-Phase, Uses All Surface Mount Controller Components, V Up to 36V IN PolyPhase is a registered trademark of Linear Technology Corporation. No R is a trademark of Linear Technology Corporation. SENSE 3728fg 36 Linear Technology Corporation LT 0909 REV G • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006