LTC3642 High Efficiency, High Voltage 50mA Synchronous Step-Down Converter FEATURES DESCRIPTION n Wide Input Voltage Range: 4.5V to 45V The LTC®3642 is a high efficiency, high voltage step-down n Tolerant of 60V Input Transients DC/DC converter with internal high side and synchronous n Internal High Side and Low Side Power Switches power switches that draws only 12μA typical DC sup- n No Compensation Required ply current at no load while maintaining output voltage n 50mA Output Current regulation. n Low Dropout Operation: 100% Duty Cycle The LTC3642 can supply up to 50mA load current and n Low Quiescent Current: 12µA features a programmable peak current limit that provides n 0.8V Feedback Voltage Reference a simple method for optimizing efficiency in lower current n Adjustable Peak Current Limit applications. The LTC3642’s combination of Burst Mode® n Internal and External Soft-Start operation, integrated power switches, low quiescent cur- n Precise RUN Pin Threshold with Adjustable rent, and programmable peak current limit provides high Hysteresis efficiency over a broad range of load currents. n 3.3V, 5V and Adjustable Output Versions n Only Three External Components Required for Fixed With its wide 4.5V to 45V input range and internal Output Versions overvoltage monitor capable of protecting the part through n Low Profile (0.75mm) 3mm × 3mm DFN and 60V surges, the LTC3642 is a robust converter suited for Thermally-Enhanced MS8E Packages regulating a wide variety of power sources. Additionally, the LTC3642 includes a precise run threshold and soft-start APPLICATIONS feature to guarantee that the power system start-up is well-controlled in any environment. n 4mA to 20mA Current Loops The LTC3642 is available in the thermally enhanced n Industrial Control Supplies 3mm × 3mm DFN and MS8E packages. n Distributed Power Systems n Portable Instruments L, LT, LTC, LTM, Burst Mode, Linear Technology, and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the n Battery-Operated Devices property of their respective owners. n Automotive Power Systems TYPICAL APPLICATION Efficiency and Power Loss vs Load Current 100 VIN = 10V 95 100 5V, 50mA Step-Down Converter EFFICIENCY 90 P 5V TO 4V5IVN VIN SW 150µH 5VVOUT Y (%) 85 10 OWER 1µF RHUYLSNTTC3642V-O5SUST 10µF 50mA FFICIENC 80 POWER LOSS LOSS (m E W ISET 75 1 ) GND 70 3642 TA01a 65 0.1 0.1 1 10 100 LOAD CURRENT (mA) 3642 TA01b 3642fc 1

LTC3642 ABSOLUTE MAXIMUM RATINGS (Note 1) V Supply Voltage .....................................–0.3V to 60V Operating Junction Temperature Range IN SW Voltage (DC) ...........................–0.3V to (V + 0.3V) (Note 2) ..................................................–40°C to 125°C IN RUN Voltage ..............................................–0.3V to 60V Storage Temperature Range ...................–65°C to 150°C HYST, I , SS Voltages ...............................–0.3V to 6V Lead Temperature (Soldering, 10 sec) SET V ...............................................................–0.3V to 6V MS8E ................................................................300°C FB V (Fixed Output Versions) .......................–0.3V to 6V OUT PIN CONFIGURATION TOP VIEW TOP VIEW SW 1 8 GND SW 1 8GND VIN 2 9 7HYST VIN 2 9 7 HYST ISET 3 GND 6VOUT/VFB ISET 3 GND 6 VOUT/VFB SS 4 5RUN SS 4 5 RUN MS8E PACKAGE 8-LEAD PLASTIC MSOP EXPOSETDJM PAAXD = (1P2I5N° 9C), θISJ AG =N D40, °MCU/WS,T θ BJCE =S O5°L-D1E0R°CE/DW T O PCB 8-LEAD (3mDmD × P 3AmCKmA)G PELASTIC DFN TJMAX = 125°C, θJA = 43°C/W, θJC = 3°C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3642EMS8E#PBF LTC3642EMS8E#TRPBF LTDTH 8-Lead Plastic MSOP –40°C to 125°C LTC3642EMS8E-3.3#PBF LTC3642EMS8E-3.3#TRPBF LTDYN 8-Lead Plastic MSOP –40°C to 125°C LTC3642EMS8E-5#PBF LTC3642EMS8E-5#TRPBF LTDYQ 8-Lead Plastic MSOP –40°C to 125°C LTC3642IMS8E#PBF LTC3642IMS8E#TRPBF LTDTH 8-Lead Plastic MSOP –40°C to 125°C LTC3642IMS8E-3.3#PBF LTC3642IMS8E-3.3#TRPBF LTDYN 8-Lead Plastic MSOP –40°C to 125°C LTC3642IMS8E-5#PBF LTC3642IMS8E-5#TRPBF LTDYQ 8-Lead Plastic MSOP –40°C to 125°C LTC3642EDD#PBF LTC3642EDD#TRPBF LDTJ 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTC3642EDD-3.3#PBF LTC3642EDD-3.3#TRPBF LDYM 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTC3642EDD-5#PBF LTC3642EDD-5#TRPBF LDYP 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTC3642IDD#PBF LTC3642IDD#TRPBF LDTJ 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTC3642IDD-3.3#PBF LTC3642IDD-3.3#TRPBF LDYM 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTC3642IDD-5#PBF LTC3642IDD-5#TRPBF LDYP 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3642fc 2

LTC3642 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are for T = 25°C (Note 2). V = 10V, unless otherwise noted. A IN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Supply (V ) IN V Input Voltage Operating Range 4.5 45 V IN UVLO V Undervoltage Lockout V Rising l 3.80 4.15 4.50 V IN IN V Falling l 3.75 4.00 4.35 V IN Hysteresis 150 mV OVLO V Overvoltage Lockout V Rising 47 50 52 V IN IN V Falling 45 48 50 V IN Hysteresis 2 V I DC Supply Current (Note 3) Q Active Mode 125 220 µA Sleep Mode 12 22 µA Shutdown Mode V = 0V 3 6 µA RUN Output Supply (V /V ) OUT FB V Output Voltage Trip Thresholds LTC3642-3.3V, V Rising l 3.260 3.310 3.360 V OUT OUT LTC3642-3.3V, V Falling l 3.240 3.290 3.340 V OUT LTC3642-5V, V Rising l 4.940 5.015 5.090 V OUT LTC3642-5V, V Falling l 4.910 4.985 5.060 V OUT V Feedback Comparator Trip Voltage V Rising l 0.792 0.800 0.808 V FB FB V Feedback Comparator Hysteresis Voltage l 3 5 7 mV HYST I Feedback Pin Current Adjustable Output Version, V = 1V –10 0 10 nA FB FB ∆V Feedback Voltage Line Regulation V = 4.5V to 45V 0.001 %/V LINEREG IN LTC3642-5, V = 6V to 45V IN Operation V Run Pin Threshold Voltage RUN Rising 1.17 1.21 1.25 V RUN RUN Falling 1.06 1.10 1.14 V Hysteresis 110 mV I Run Pin Leakage Current RUN = 1.3V –10 0 10 nA RUN V Hysteresis Pin Voltage Low RUN < 1V, I = 1mA 0.07 0.1 V HYSTL HYST I Hysteresis Pin Leakage Current V = 1.3V –10 0 10 nA HYST HYST I Soft-Start Pin Pull-Up Current V < 1.5V 4.5 5.5 6.5 µA SS SS t Internal Soft-Start Time SS Pin Floating 0.75 ms INTSS I Peak Current Trip Threshold I Floating l 100 115 130 mA PEAK SET 500k Resistor from I to GND 55 mA SET I Shorted to GND 20 25 32 mA SET R Power Switch On-Resistance ON Top Switch I = –25mA 3.0 Ω SW Bottom Switch I = 25mA 1.5 Ω SW Note 1: Stresses beyond those listed under Absolute Maximum Ratings maximum ambient temperature consistent with these specifications is may cause permanent damage to the device. Exposure to any Absolute determined by specific operating conditions in conjunction with board Maximum Rating condition for extended periods may affect device layout, the rated package thermal impedance and other environmental reliability and lifetime. factors. The junction temperature (T , in °C) is calculated from the ambient J Note 2: The LTC3642 is tested under pulsed load conditions such that TJ ≈ TA. temperature (TA, in °C) and power dissipation (PD, in Watts) according to LTC3642E is guaranteed to meet specifications from 0°C to 85°C junction the formula: temperature. Specifications over the –40°C to 125°C operating junction TJ = TA + (PD • θJA), where θJA (in °C/W) is the package thermal temperature range are assured by design, characterization and correlation impedance. with statistical process controls. The LTC3642I is guaranteed over the Note 3: Dynamic supply current is higher due to the gate charge being full –40°C to 125°C operating junction temperature range. Note that the delivered at the switching frequency. See Applications Information. 3642fc 3

LTC3642 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A Efficiency vs Load Current Line Regulation Load Regulation 100 0.30 5.05 FIGURE 11 CIRCUIT ILOAD = 25mA VIN = 10V 95 VISOEUTT O =P E5NV VIN = 10V 0.20 FIGURE 11 CIRCUIT 55..0034 FISIGETU ORPEE 1N1 CIRCUIT 90 VIN = 15V V)5.02 EFFICIENCY (%) 788550 VINV =IN 3 =6 VV2I4NV = 45V V/V (%)∆OUTOUT–00..11000 OUTPUT VOLTAGE (5454....09091908 70 4.97 –0.20 65 4.96 60 –0.30 4.95 0.1 1 10 100 5 10 15 20 25 30 35 40 45 0 10 20 30 40 50 LOAD CURRENT (mA) INPUT VOLTAGE (V) LOAD CURRENT (mA) 3642 G01 3642 G02 3642 G03 Feedback Comparator Voltage Feedback Comparator Hysteresis Peak Current Trip Threshold vs Temperature Voltage vs Temperature vs Temperature and I SET 0.801 5.6 130 FEEDBACK COMPARATOR TRIP VOLTAGE (V)000...778990980 VIN = 10V FEEDBACK COMPARATOR HYSTERESIS (mV) 444555......846402 VIN = 10V PEAK CURRENT TRIP THRESHOLD (mA)1112102135476890000000000000 VIN = 10V RIIISSSEEETTT =O= GP5EN0ND0k –40 –10 20 50 80 110 –40 –10 20 50 80 110 –40 –10 20 50 80 110 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3642 G04 3642 G05 3642 G06 Peak Current Trip Threshold Quiescent Supply Current Quiescent Supply Current vs R vs Input Voltage vs Temperature ISET 120 14 14 VIN = 10V VIN = 10V A)110 m 12 12 ESHOLD (1809000 NT (µA) 10 SLEEP NT (µA) 10 SLEEP THR 70 RRE 8 RRE 8 CURRENT TRIP 465000 V SUPPLY CUIN 64 SHUTDOWN V SUPPLY CUIN 64 SHUTDOWN AK 30 2 2 PE 20 10 0 0 0 200 400 600 800 1000 1200 5 15 25 35 45 –40 –10 20 50 80 110 RSET (kΩ) INPUT VOLTAGE (V) TEMPERATURE (°C) 3642 G07 3642 G08 3642 G09 3642fc 4

LTC3642 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A Switch On-Resistance Switch On-Resistance Switch Leakage Current vs Input Voltage vs Temperature vs Temperature 4.5 5 0.6 VIN = 10V VIN = 45V 4.0 A) 0.5 SWITCH ON-RESISTANCE (Ω) 122331......005055 BOTTOTPOM SWITCH ON-RESISTANCE (Ω) 1423 BOTTOTPOM SWITCH LEAKAGE CURRENT (µ 0000....2413 SW = 45VSW = 0V 0.5 0 0 0 –40 –10 20 50 80 110 –40 –10 20 50 80 110 0 10 20 30 40 50 TEMPERATURE (°C) TEMPERATURE (°C) INPUT VOLTAGE (V) 3642 G11 3642 G12 3642 G10 Run Comparator Threshold Internal Soft-Start Time Efficiency vs Input Voltage Voltage vs Temperature vs Temperature 95 1.30 1.20 FIGURE 11 CIRCUIT 90 ISET OPEN D (V)1.25 RISING ms)1.15 ILOAD = 50mA OL E ( H M EFFICIENCY (%) 788505 ILOAD = 1mAILOAD = 10mA MPARATOR THRES111...112050 FALLING AL SOFT-START TI111...001050 O N C R 70 UN 1.05 NTE0.95 R I 65 1.00 0.90 10 15 20 25 30 35 40 45 –40 –10 20 50 80 110 –40 –10 20 50 80 110 INPUT VOLTAGE (V) TEMPERATURE (°C) TEMPERATURE (°C) 3642 G13 3642 G14 3642 G1 5 Soft-Start Waveforms Operating Waveforms Load Step Transient Response OUTPUT VOLTAGE OUTPUT 50mV/DIV VOLTAGE SWITCH 25mV/DIV OUTPUT VOLTAGE VOLTAGE 5V/DIV 1V/DIV LOAD INDUCTOR CURRENT CURRENT 25mA/DIV 50mA/DIV CSS = 0.047µF 5ms/DIV 3642 G16 VIN = 10V 10µs/DIV 3642 G17 VIN = 10V 1ms/DIV 3642 G18 ISET OPEN ISET OPEN ILOAD = 25mA FIGURE 11 CIRCUIT FIGURE 11 CIRCUIT 3642fc 5

LTC3642 PIN FUNCTIONS SW (Pin 1): Switch Node Connection to Inductor. This V /V (Pin 6): Output Voltage Feedback. For the fixed OUT FB pin connects to the drains of the internal power MOSFET output versions, connect this pin to the output supply. For switches. the adjustable version, an external resistive divider should be used to divide the output voltage down for comparison V (Pin 2): Main Supply Pin. A ceramic bypass capacitor IN to the 0.8V reference. should be tied between this pin and GND (Pin 8). HYST (Pin 7): Run Hysteresis Open-Drain Logic Output. I (Pin 3): Peak Current Set Input. A resistor from this SET This pin is pulled to ground when RUN (Pin 5) is below pin to ground sets the peak current trip threshold. Leave 1.2V. This pin can be used to adjust the RUN pin hysteresis. floating for the maximum peak current (115mA). Short See Applications Information. this pin to ground for the minimum peak current (25mA). A 1µA current is sourced out of this pin. GND (Pin 8, Exposed Pad Pin 9): Ground. The exposed pad must be soldered to the printed circuit board ground SS (Pin 4): Soft-Start Control Input. A capacitor to ground plane for optimal electrical and thermal performance. at this pin sets the ramp time to full current output dur- ing start-up. A 5µA current is sourced out of this pin. If left floating, the ramp time defaults to an internal 0.75ms soft-start. RUN (Pin 5): Run Control Input. A voltage on this pin above 1.2V enables normal operation. Forcing this pin below 0.7V shuts down the LTC3642, reducing quiescent current to approximately 3µA. 3642fc 6

LTC3642 BLOCK DIAGRAM VIN ISET 1µA 2 3 C2 PEAK CURRENT – COMPARATOR + RUN 5 + LOGIC AND SW L1 SHOOT- 1 VOUT THROUGH 1.2V – PREVENTION C1 HYST 7 + REVERSE CURRENT – COMPARATOR VOLTAGE REFERENCE FEEDBACK COMPARATOR + 0.800V 5µA SS + 4 – GND GND R1 VOUT/VFB 8 9 6 3642 BD R2 IMPLEMENT DIVIDER PART EXTERNALLY FOR NUMBER R1 R2 ADJUSTABLE VERSION LTC3642 0 ∞ LTC3642-3.3 2.5M 800k LTC3642-5 4.2M 800k 3642fc 7

LTC3642 OPERATION (Refer to Block Diagram) The LTC3642 is a step-down DC/DC converter with internal The hysteretic nature of this control architecture results power switches that uses Burst Mode control, combining in a switching frequency that is a function of the input low quiescent current with high switching frequency, voltage, output voltage and inductor value. This behavior which results in high efficiency across a wide range of provides inherent short-circuit protection. If the output load currents. Burst Mode operation functions by using is shorted to ground, the inductor current will decay very short “burst” cycles to ramp the inductor current through slowly during a single switching cycle. Since the high side the internal power switches, followed by a sleep cycle switch turns on only when the inductor current is near where the power switches are off and the load current is zero, the LTC3642 inherently switches at a lower frequency supplied by the output capacitor. During the sleep cycle, during start-up or short-circuit conditions. the LTC3642 draws only 12µA of supply current. At light loads, the burst cycles are a small percentage of the total Start-Up and Shutdown cycle time which minimizes the average supply current, If the voltage on the RUN pin is less than 0.7V, the LTC3642 greatly improving efficiency. enters a shutdown mode in which all internal circuitry is disabled, reducing the DC supply current to 3µA. When the Main Control Loop voltage on the RUN pin exceeds 1.21V, normal operation of The feedback comparator monitors the voltage on the V the main control loop is enabled. The RUN pin comparator FB pin and compares it to an internal 800mV reference. If has 110mV of internal hysteresis, and therefore must fall this voltage is greater than the reference, the comparator below 1.1V to disable the main control loop. activates a sleep mode in which the power switches and The HYST pin provides an added degree of flexibility for current comparators are disabled, reducing the V pin IN the RUN pin operation. This open-drain output is pulled supply current to only 12µA. As the load current discharges to ground whenever the RUN comparator is not tripped, the output capacitor, the voltage on the V pin decreases. FB signaling that the LTC3642 is not in normal operation. In When this voltage falls 5mV below the 800mV reference, applications where the RUN pin is used to monitor the V IN the feedback comparator trips and enables burst cycles. voltage through an external resistive divider, the HYST pin At the beginning of the burst cycle, the internal high side can be used to increase the effective RUN comparator power switch (P-channel MOSFET) is turned on and the hysteresis. inductor current begins to ramp up. The inductor current An internal 1ms soft-start function limits the ramp rate of increases until either the current exceeds the peak cur- the output voltage on start-up to prevent excessive input rent comparator threshold or the voltage on the V pin FB supply droop. If a longer ramp time and consequently less exceeds 800mV, at which time the high side power switch supply droop is desired, a capacitor can be placed from the is turned off and the low side power switch (N-channel SS pin to ground. The 5µA current that is sourced out of MOSFET) turns on. The inductor current ramps down until this pin will create a smooth voltage ramp on the capacitor. the reverse current comparator trips, signaling that the If this ramp rate is slower than the internal 1ms soft-start, current is close to zero. If the voltage on the V pin is FB then the output voltage will be limited by the ramp rate still less than the 800mV reference, the high side power on the SS pin instead. The internal and external soft-start switch is turned on again and another cycle commences. functions are reset on start-up and after an undervoltage The average current during a burst cycle will normally be or overvoltage event on the input supply. greater than the average load current. For this architecture, the maximum average output current is equal to half of In order to ensure a smooth start-up transition in any the peak current. application, the internal soft-start also ramps the peak 3642fc 8

LTC3642 OPERATION (Refer to Block Diagram) inductor current from 25mA during its 1ms ramp time to Input Undervoltage and Overvoltage Lockout the set peak current threshold. The external ramp on the The LTC3642 implements a protection feature which dis- SS pin does not limit the peak inductor current during ables switching when the input voltage is not within the start-up; however, placing a capacitor from the I pin SET 4.5V to 45V operating range. If V falls below 4V typical IN to ground does provide this capability. (4.35V maximum), an undervoltage detector disables switching. Similarly, if V rises above 50V typical (47V Peak Inductor Current Programming IN minimum), an overvoltage detector disables switching. The offset of the peak current comparator nominally When switching is disabled, the LTC3642 can safely sustain provides a peak inductor current of 115mA. This peak input voltages up to the absolute maximum rating of 60V. inductor current can be adjusted by placing a resistor Switching is enabled when the input voltage returns to the from the ISET pin to ground. The 1µA current sourced out 4.5V to 45V operating range. of this pin through the resistor generates a voltage that is translated into an offset in the peak current comparator, which limits the peak inductor current. 3642fc 9

LTC3642 APPLICATIONS INFORMATION The basic LTC3642 application circuit is shown on the front maximum average output current for this architecture page of this data sheet. External component selection is is limited to half of the peak current. Therefore, be sure determined by the maximum load current requirement and to select a value that sets the peak current with enough begins with the selection of the peak current programming margin to provide adequate load current under all foresee- resistor, R . The inductor value L can then be determined, able operating conditions. ISET followed by capacitors C and C . IN OUT Inductor Selection Peak Current Resistor Selection The inductor, input voltage, output voltage and peak current The peak current comparator has a maximum current determine the switching frequency of the LTC3642. For limit of 115mA nominally, which results in a maximum a given input voltage, output voltage and peak current, average current of 55mA. For applications that demand the inductor value sets the switching frequency when the less current, the peak current threshold can be reduced output is in regulation. A good first choice for the inductor to as little as 25mA. This lower peak current allows the value can be determined by the following equation: use of lower value, smaller components (input capacitor,  V   V  output capacitor and inductor), resulting in lower input L= OUT •1– OUT supply ripple and a smaller overall DC/DC converter. f•I   V  PEAK IN The threshold can be easily programmed with an ap- The variation in switching frequency with input voltage propriately chosen resistor (R ) between the I pin ISET SET and inductance is shown in the following two figures for and ground. The value of resistor for a particular peak typical values of V . For lower values of I , multiply OUT PEAK current can be computed by using Figure 1 or the follow- the frequency in Figure 2 and Figure 3 by 115mA/I . PEAK ing equation: An additional constraint on the inductor value is the R = I • 9.09 • 106 ISET PEAK LTC3642’s 100ns minimum on-time of the high side switch. where 25mA < I < 115mA. Therefore, in order to keep the current in the inductor well PEAK controlled, the inductor value must be chosen so that it is The peak current is internally limited to be within the larger than L , which can be computed as follows: range of 25mA to 115mA. Shorting the I pin to ground MIN SET programs the current limit to 25mA, and leaving it floating V •t IN(MAX) ON(MIN) L = sets the current limit to the maximum value of 115mA. MIN I PEAK(MAX) When selecting this resistor value, be aware that the where V is the maximum input supply voltage for IN(MAX) 1100 the application, t is 100ns, and I is the ON(MIN) PEAK(MAX) 1000 maximum allowed peak inductor current. Although the 900 above equation provides the minimum inductor value, 800 700 higher efficiency is generally achieved with a larger inductor R (k)ISET560000 vgaivlueen, iwndhuicchto prr toydpuec, ehso aw leovweer,r assw iintcdhuicntga nfrceeq iuse innccyr.e Faosre da 400 DC resistance (DCR) also increases. Higher DCR translates 300 into higher copper losses and lower current rating, both 200 of which place an upper limit on the inductance. The 100 0 recommended range of inductor values for small surface 10 15 20 25 30 35 40 45 50 mount inductors as a function of peak current is shown in MAXIMUM LOAD CURRENT (mA) Figure 4. The values in this range are a good compromise 3642 F01 between the tradeoffs discussed above. For applications Figure 1. R Selection ISET 3642fc 10

LTC3642 APPLICATIONS INFORMATION where board area is not a limiting factor, inductors with 700 VOUT = 5V 600 ISET OPEN L = 47µH larger cores can be used, which extends the recommended Hz) range of Figure 4 to larger values. k CY ( 500 L = 68µH N Inductor Core Selection E QU 400 L = 100µH E R Once the value for L is known, the type of inductor must G F 300 L = 150µH N be selected. High efficiency converters generally cannot HI TC 200 L = 220µH afford the core loss found in low cost powdered iron cores, WI S 100 L = 470µH forcing the use of the more expensive ferrite cores. Actual core loss is independent of core size for a fixed inductor 0 5 10 15 20 25 30 35 40 45 value but is very dependent of the inductance selected. INPUT VOLTAGE (V) As the inductance increases, core losses decrease. Un- 3642 F02 fortunately, increased inductance requires more turns of Figure 2. Switching Frequency for V = 5V OUT wire and therefore copper losses will increase. Ferrite designs have very low core losses and are pre- 500 VOUT = 3.3V ferred at high switching frequencies, so design goals can 450 ISET OPEN L = 47µH concentrate on copper loss and preventing saturation. kHz) 400 Ferrite core material saturates “hard,” which means that Y ( 350 L = 68µH NC inductance collapses abruptly when the peak design current E 300 QU L = 100µH is exceeded. This results in an abrupt increase in inductor E 250 R G F 200 L = 150µH ripple current and consequently output voltage ripple. Do N HI not allow the core to saturate! TC 150 L = 220µH WI 100 S Different core materials and shapes will change the size/ L = 470µH 50 current and price/current relationship of an inductor. Toroid 0 5 10 15 20 25 30 35 40 45 or shielded pot cores in ferrite or permalloy materials INPUT VOLTAGE (V) are small and do not radiate energy but generally cost 3642 F03 more than powdered iron core inductors with similar Figure 3. Switching Frequency for V = 3.3V OUT characteristics. The choice of which style inductor to use mainly depends on the price vs size requirements and any 10000 radiated field/EMI requirements. New designs for surface mount inductors are available from Coiltronics, Coilcraft, Toko, Sumida and Vishay. H) µ LUE ( CIN and COUT Selection A V1000 R The input capacitor, C , is needed to filter the trapezoidal O IN T UC current at the source of the top high side MOSFET. To D N I prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. Approximate RMS current is given by: 100 10 100 PEAK INDUCTOR CURRENT (mA) V V 3642 F04 IRMS =IOUT(MAX)• OUT • IN −1 V V IN OUT Figure 4. Recommended Inductor Values for Maximum Efficiency 3642fc 11

LTC3642 APPLICATIONS INFORMATION This formula has a maximum at V = 2V , where Dry tantalum, special polymer, aluminum electrolytic, IN OUT I = I /2. This simple worst-case condition is and ceramic capacitors are all available in surface mount RMS OUT commonly used for design because even significant packages. Special polymer capacitors offer very low ESR deviations do not offer much relief. Note that ripple current but have lower capacitance density than other types. ratings from capacitor manufacturers are often based Tantalum capacitors have the highest capacitance density only on 2000 hours of life which makes it advisable to but it is important only to use types that have been surge further derate the capacitor, or choose a capacitor rated tested for use in switching power supplies. Aluminum at a higher temperature than required. Several capacitors electrolytic capacitors have significantly higher ESR but may also be paralleled to meet size or height requirements can be used in cost-sensitive applications provided that in the design. consideration is given to ripple current ratings and long- term reliability. Ceramic capacitors have excellent low ESR The output capacitor, C , filters the inductor’s ripple OUT characteristics but can have high voltage coefficient and current and stores energy to satisfy the load current when audible piezoelectric effects. The high quality factor (Q) the LTC3642 is in sleep. The output ripple has a lower limit of ceramic capacitors in series with trace inductance can of V /160 due to the 5mV typical hysteresis of the feed- OUT also lead to significant ringing. back comparator. The time delay of the comparator adds an additional ripple voltage that is a function of the load Using Ceramic Input and Output Capacitors current. During this delay time, the LTC3642 continues to switch and supply current to the output. The output ripple Higher value, lower cost ceramic capacitors are now be- can be approximated by: coming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal ΔV ≈IPEAK –I 4•10–6 + VOUT for switching regulator applications. However, care must OUT LOAD  2  C 160 be taken when these capacitors are used at the input and OUT output. When a ceramic capacitor is used at the input and The output ripple is a maximum at no load and approaches the power is supplied by a wall adapter through long wires, lower limit of VOUT/160 at full load. Choose the output a load step at the output can induce ringing at the input, capacitor COUT to limit the output voltage ripple at mini- VIN. At best, this ringing can couple to the output and be mum load current. mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a The value of the output capacitor must be large enough voltage spike at V large enough to damage the LTC3642. to accept the energy stored in the inductor without a large IN change in output voltage. Setting this voltage step equal to For applications with inductive source impedance, such 1% of the output voltage, the output capacitor must be: as a long wire, a series RC network may be required in parallel with C to dampen the ringing of the input supply. 2 IN   I Figure 5 shows this circuit and the typical values required C >50•L• PEAK OUT V  to dampen the ringing. OUT Typically, a capacitor that satisfies the voltage ripple LIN LTC3642 requirement is adequate to filter the inductor ripple. To VIN avoid overheating, the output capacitor must also be sized R = LIN to handle the ripple current generated by the inductor. The CIN 3642 F05 worst-case ripple current in the output capacitor is given 4 • CIN CIN by I = I /2. Multiple capacitors placed in parallel RMS PEAK may be needed to meet the ESR and RMS current handling requirements. Figure 5. Series RC to Reduce VIN Ringing 3642fc 12

LTC3642 APPLICATIONS INFORMATION Output Voltage Programming controller is enabled. Figure 7 shows examples of con- figurations for driving the RUN pin from logic. For the adjustable version, the output voltage is set by an external resistive divider according to the following equation: VSUPPLY VIN V =0.8V•1+ R1 LTC3642 4.7M LTC3642 OUT  R2 RUN RUN The resistive divider allows the V pin to sense a fraction 3642 F07 FB of the output voltage as shown in Figure 6. Output voltage adjustment range is from 0.8V to V . Figure 7. RUN Pin Interface to Logic IN VOUT The RUN pin can alternatively be configured as a precise R1 undervoltage lockout (UVLO) on the VIN supply with a VFB resistive divider from VIN to ground. The RUN pin com- LTC3642 R2 parator nominally provides 10% hysteresis when used in GND this method; however, additional hysteresis may be added with the use of the HYST pin. The HYST pin is an open- Figure 6. Setting the Output Voltage drain output that is pulled to ground whenever the RUN comparator is not tripped. A simple resistive divider can be used as shown in Figure 8 to meet specific V voltage To minimize the no-load supply current, resistor values in IN requirements. the megohm range should be used; however, large resistor values should be used with caution. The feedback divider VIN is the only load current when in shutdown. If PCB leak- R1 age current to the output node or switch node exceeds RUN the load current, the output voltage will be pulled up. In R2 LTC3642 normal operation, this is generally a minor concern since HYST the load current is much greater than the leakage. The R3 3642 F08 increase in supply current due to the feedback resistors can be calculated from:  V  V  Figure 8. Adjustable Undervoltage Lockout ∆I = OUT • OUT VIN R1+R2  V  IN Specific values for these UVLO thresholds can be computed from the following equations: Run Pin with Programmable Hysteresis  R1 The LTC3642 has a low power shutdown mode controlled Rising VIN UVLO Threshold=1.21V•1+   R2 by the RUN pin. Pulling the RUN pin below 0.7V puts the LTC3642 into a low quiescent current shutdown mode  R1  (IQ ~ 3µA). When the RUN pin is greater than 1.2V, the Falling VIN UVLO Threshold=1.10V•1+R2+R3 3642fc 13

LTC3642 APPLICATIONS INFORMATION The minimum value of these thresholds is limited to the I pin. With only a capacitor connected between I SET SET internal V UVLO thresholds that are shown in the Electri- and ground, the peak current ramps linearly from 25mA IN cal Characteristics table. The current that flows through to 115mA, and the peak current soft-start time can be this divider will directly add to the shutdown, sleep and expressed as: active current of the LTC3642, and care should be taken to 0.8V minimize the impact of this current on the overall efficiency t =C • SS(ISET) ISET 1µA of the application circuit. Resistor values in the megohm range may be required to keep the impact on quiescent A linear ramp of peak current appears as a quadratic shutdown and sleep currents low. Be aware that the HYST waveform on the output voltage. For the case where the pin cannot be allowed to exceed its absolute maximum peak current is reduced by placing a resistor from I rating of 6V. To keep the voltage on the HYST pin from SET to ground, the peak current offset ramps as a decaying exceeding 6V, the following relation should be satisfied: exponential with a time constant of R • C . For this ISET ISET  R3  case, the peak current soft-start time is approximately V • <6V IN(MAX) 3 • R • C . R1+R2+R3 ISET ISET Unlike the SS pin, the I pin does not get pulled to The RUN pin may also be directly tied to the V supply SET IN ground during an abnormal event; however, if the I for applications that do not require the programmable SET pin is floating (programmed to 115mA peak current), undervoltage lockout feature. In this configuration, switch- the SS and I pins may be tied together and connected ing is enabled when V surpasses the internal undervoltage SET IN to a capacitor to ground. For this special case, both the lockout threshold. peak current and the reference voltage will soft-start on power-up and after fault conditions. The ramp time for Soft-Start this combination is C • (0.8V/6µA). SS(ISET) The internal 0.75ms soft-start is implemented by ramping both the effective reference voltage from 0V to 0.8V and the Efficiency Considerations peak current limit set by the I pin (25mA to 115mA). SET The efficiency of a switching regulator is equal to the output To increase the duration of the reference voltage soft-start, power divided by the input power times 100%. It is often place a capacitor from the SS pin to ground. An internal useful to analyze individual losses to determine what is 5µA pull-up current will charge this capacitor, resulting limiting the efficiency and which change would produce in a soft-start ramp time given by: the most improvement. Efficiency can be expressed as: 0.8V Efficiency = 100% – (L1 + L2 + L3 + ...) t =C • SS SS 5µA where L1, L2, etc. are the individual losses as a percent- age of input power. When the LTC3642 detects a fault condition (input supply undervoltage or overvoltage) or when the RUN pin falls Although all dissipative elements in the circuit produce below 1.1V, the SS pin is quickly pulled to ground and the losses, two main sources usually account for most of internal soft-start timer is reset. This ensures an orderly the losses: V operating current and I2R losses. The V IN IN restart when using an external soft-start capacitor. operating current dominates the efficiency loss at very low load currents whereas the I2R loss dominates the The duration of the 1ms internal peak current soft-start efficiency loss at medium to high load currents. may be increased by placing a capacitor from the I pin SET to ground. The peak current soft-start will ramp from 25mA 1. The V operating current comprises two components: IN to the final peak current value determined by a resistor The DC supply current as given in the electrical charac- from I to ground. A 1µA current is sourced out of the teristics and the internal MOSFET gate charge currents. SET 3642fc 14

LTC3642 APPLICATIONS INFORMATION The gate charge current results from switching the gate First, calculate the inductor value that gives the required capacitance of the internal power MOSFET switches. switching frequency: Each time the gate is switched from high to low to Ê 3.3V ˆ Ê 3.3Vˆ high again, a packet of charge, dQ, moves from VIN to L=Á ˜ •Á1– ˜ @100µH Ë250kHz•115mA¯ Ë 24V¯ ground. The resulting dQ/dt is the current out of V IN that is typically larger than the DC bias current. Next, verify that this value meets the L requirement. MIN 2. I2R losses are calculated from the resistances of the For this input voltage and peak current, the minimum internal switches, R , and external inductor R . When SW L inductor value is: switching, the average output current flowing through 24V•100ns the inductor is “chopped” between the high side PMOS L = ≅22µH MIN switch and the low side NMOS switch. Thus, the series 115mA resistance looking back into the switch pin is a function Therefore, the minimum inductor requirement is satisfied, of the top and bottom switch R values and the DS(ON) and the 100μH inductor value may be used. duty cycle (DC = V /V ) as follows: OUT IN Next, C and C are selected. For this design, C should R = (R )DC + (R )(1 – DC) IN OUT IN SW DS(ON)TOP DS(ON)BOT be size for a current rating of at least: The R for both the top and bottom MOSFETs can DS(ON) be obtained from the Typical Performance Characteris- 3.3V 24V I =50mA• • –1≅18mA tics curves. Thus, to obtain the I2R losses, simply add RMS 24V 3.3V RMS R to R and multiply the result by the square of the SW L average output current: Due to the low peak current of the LTC3642, decoupling the V supply with a 1µF capacitor is adequate for most I2R Loss = I 2(R + R ) IN O SW L applications. Other losses, including C and C ESR dissipative IN OUT C will be selected based on the output voltage ripple OUT losses and inductor core losses, generally account for requirement. For a 1.5% (50mV) output voltage ripple at less than 2% of the total power loss. no load, C can be calculated from: OUT Thermal Considerations 115mA•4•10–6 C = OUT  3.3V The LTC3642 does not dissipate much heat due to its high 250mV–  efficiency and low peak current level. Even in worst-case  160  conditions (high ambient temperature, maximum peak current and high duty cycle), the junction temperature will A 7.8µF capacitor gives this typical output voltage ripple at exceed ambient temperature by only a few degrees. no load. Choose a 10µF capacitor as a standard value. The output voltage can now be programmed by choosing Design Example the values of R1 and R2. Choose R2 = 240k and calculate As a design example, consider using the LTC3642 in an R1 as: application with the following specifications: V = 24V, IN V  VOUT = 3.3V, IOUT = 50mA, f = 250kHz. Furthermore, as- R1= OUT –1•R2=750k sume for this example that switching should start when 0.8V  V is greater than 12V and should stop when V is less IN IN than 8V. 3642fc 15

LTC3642 APPLICATIONS INFORMATION The undervoltage lockout requirement on V can be 3. Keep the switching node, SW, away from all sensitive IN satisfied with a resistive divider from V to the RUN and small signal nodes. The rapid transitions on the switching IN HYST pins. Choose R1 = 2M and calculate R2 and R3 as node can couple to high impedance nodes, in particular follows: V , and create increased output ripple. FB   4. Flood all unused area on all layers with copper. Flooding 1.21V R2= •R1=224k with copper will reduce the temperature rise of power   V –1.21V  IN(RISING)  components. You can connect the copper areas to any DC net (V , V , GND or any other DC rail in your   IN OUT 1.1V system). R3= •R1–R2=90.8k   V –1.1V  IN(FALLING)  Choose standard values for R2 = 226k and R3 = 91k. The 2 1 L1 VIN VIN SW VOUT I pin should be left open in this example to select maxi- SET LTC3642 R1 mum peak current (115mA). Figure 9 shows a complete 5 RUN VFB 6 COUT 7 schematic for this design example. CIN HYST 4 3 SS ISET R2 2V4IVN 2M VINLTC3642SW 100µH V35.0O3mUVTA CSS GN8D, 9 RSET 3642 F10a 1µF 10µF RUN ISET 226k SS 750k HYST VFB L1 91k GND 240k 3642 F09 VIN VOUT CIN COUT Figure 9. 24V to 3.3V, 50mA Regulator at 250kHz PC Board Layout Checklist R1 When laying out the printed circuit board, the following checklist should be used to ensure proper operation of R2 the LTC3642. Check the following in your layout: RSET CSS GND 1. Large switched currents flow in the power switches 3642 F10b VIAS TO GROUND PLANE and input capacitor. The loop formed by these compo- VIAS TO INPUT SUPPLY (VIN) nents should be as small as possible. A ground plane OUTLINE OF LOCAL GROUND PLANE is recommended to minimize ground impedance. Figure 10. Layout Example 2. Connect the (+) terminal of the input capacitor, C , as IN close as possible to the V pin. This capacitor provides IN the AC current into the internal power MOSFETs. 3642fc 16

LTC3642 TYPICAL APPLICATIONS Efficiency vs Load Current L1 94 5V TO 4V5IVN VIN SW 220µH 5VVOUT VIN = 10V CIN LTC3642 R1 COUT 93 RSET = 750k 4.7µF RUN VFB 4.2M 100µF RSET = 500k HYST R2 %) 92 RSET ISET GND SS C47SnSF 800k FICIENCY ( 91 ISET OPEN F 3642 F11a E 90 CIN: TDK C5750X7R2A475MT COUT: AVX 1812D107MAT 89 L1: TDK SLF7045T-221MR33-PF Figure 11. High Efficiency 5V Regulator 88 1 10 100 LOAD CURRENT (mA) 3642 F11b 3.3V, 50mA Regulator with Peak Current Soft-Start, Small Size Soft-Start Waveforms L1 4.5V TO 2V4IVN VIN SW 47µH V3.O3UVT CIN LTC3642 R1 COUT 50mA OUTPUT VOLTAGE 1µF 294k 10µF 1V/DIV RUN VFB ISET R2 93.1k SS HYST 3642 TA02a CSS GND INDUCTOR CURRENT 0.1µF 20mA/DIV CIN: TDK C3216X7R1E105KT COUT: AVX 08056D106KAT2A 2ms/DIV 3642 TA03b L1: TAIYO YUDEN CBC2518T470K Positive-to-Negative Converter Maximum Load Current vs Input Voltage L1 50 4.5V TO 3V3IVN C1µINF RVIUNNLTC3642SW 100µH R1M1 NT (mA) 4405 VOUT = –3VVOUT = –5V E ISET VFB COUT RR 35 10µF CU VOUT = –12V HYST SS R2 D 30 GND 71.5k OA L VOUT UM 25 –12V M CCIONU: TT:D MKU CR3A2T2A5 XG7RRM13H21D0R57K1TC106KA01 3642 TA04a MAXI 20 L1: TYCO/COEV DQ6530-101M 15 10 5 10 15 20 25 30 35 40 45 INPUT VOLTAGE (V) 3642 TA04b 3642fc 17

LTC3642 TYPICAL APPLICATIONS Small Size, Limited Peak Current, 10mA Regulator L1 7V TO 4V5IVN VIN SW 470µH V5VOUT CIN R3 LTC3642 R1 COUT 10mA 1µF 470k 470k 10µF RUN VFB R4 R2 100k 88.7k HYST SS 3642 TA05a R5 ISET GND 33k CIN: TDK C3225X7R1H105KT COUT: AVX 08056D106KAT2A L1: MURATA LQH32CN471K23 High Efficiency 15V, 10mA Regulator Efficiency vs Load Current 100 L1 15V TO 4V5IVN VIN SW 4700µH 1V5OVUT 95 VIN = 24V CIN LTC3642 R1 COUT 10mA 90 1µF 3M 4.7µF RUN VFB %) 85 VIN = 36V ISET R2 Y ( 169k C N 80 SS HYST 3642 TA07a CIE VIN = 45V GND FFI 75 E 70 CIN: AVX 18125C105KAT2A COUT: TDK C3216X7R1E475KT 65 L1: COILCRAFT DS1608C-475 60 0.1 1 10 LOAD CURRENT (mA) 3642 TA07b 3642fc 18

LTC3642 PACKAGE DESCRIPTION DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698 Rev C) 0.70 ±0.05 3.5 ±0.05 1.65 ±0.05 2.10 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.38 ±0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED R = 0.125 0.40 ± 0.10 TYP 5 8 3.00 ±0.10 1.65 ± 0.10 (4 SIDES) (2 SIDES) PIN 1 TOP MARK (NOTE 6) (DD8) DFN 0509 REV C 4 1 0.200 REF 0.75 ±0.05 0.25 ± 0.05 0.50 BSC 2.38 ±0.10 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 3642fc 19

LTC3642 PACKAGE DESCRIPTION MS8E Package 8-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1662 Rev I) BOTTOM VIEW OF EXPOSED PAD OPTION 1.88 1 (.074) 0.29 (1..08784 ± ± 0 ..010042) 0.889 ± 0.127 1.68 REF (.035 ± .005) (.066) 0.05 REF 5.23 DETAIL “B” (.206) 1.68 ± 0.102 3.20 – 3.45 CORNER TAIL IS PART OF (.066 ± .004) (.126 – .136) MIN DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY 8 NO MEASUREMENT PURPOSE 3.00 ± 0.102 0.65 0.42 ± 0.038 (.0256) (.118 ± .004) 0.52 (.0165 ± .0015) BSC (NOTE 3) 8 7 6 5 (.0205) TYP REF RECOMMENDED SOLDER PAD LAYOUT 3.00 ± 0.102 4.90 ± 0.152 DETAIL “A” (.118 ± .004) 0.254 (.193 ± .006) (NOTE 4) (.010) 0° – 6° TYP GAUGE PLANE 1 2 3 4 0.53 ± 0.152 (.021 ± .006) 1.10 0.86 (.043) (.034) DETAIL “A” MAX REF 0.18 (.007) SEATING PLANE 0.22 – 0.38 0.1016 ± 0.0508 (.009 – .015) (.004 ± .002) 0.65 TYP MSOP (MS8E) 0910 REV I (.0256) NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 3642fc 20

LTC3642 REVISION HISTORY (Revision history begins at Rev B) REV DATE DESCRIPTION PAGE NUMBER B 6/10 Text updates in Description 1 Updates to Absolute Maximum Ratings 2 LTC3642IMS8E-3.3E#PBF changed to LTC3642IMS8E-3.3#PBF in Order Information 2 Updates to Electrical Characteristics 3 Updates to graphs G05, G06, G14, G16, G17 4, 5 Updated description for Pins 8 and 9 in Pin Functions 6 Text updates in Operation section 8,9 Text updates in Applications Information section 13 Figure 10 graphic added 16 Updated Y-axis text on TA04b graphic 17 Asterisk and related text added to Typical Application 22 Related Parts updated 22 C 10/10 Updated text in C and C Selection section 12 IN OUT Updated text in Design Example section 15 3642fc Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 21 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC3642 TYPICAL APPLICATION 5V, 50mA Regulator for Automotive Applications L1 VB1A2TVT VIN SW 220µH V5VOUT* CIN LTC3642 R1 COUT 50mA 1µF 470k 10µF RUN VFB ISET R2 88.7k SS HYST 3642 TA06a GND CIN: TDK C3225X7R2A105M *VOUT = VBATT FOR VBATT < 5V COUT: KEMET C1210C106K4RAC L1: COILTRONICS DRA73-221-R RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3631/LTC3631-3.3/ 45V, 100mA Synchronous Micropower Step-Down DC/DC V : 4.5V to 45V (60V ), V = 0.8V, I = 12µA, IN MAX OUT(MIN) Q LTC3631-5 Converter ISD = 3µA, 3mm × 3mm DFN8, MS8E LTC3632 50V, 20mA Synchronous Micropower Step-Down DC/DC V : 4.5V to 50V (60V ), V = 0.8V, I = 12µA, IN MAX OUT(MIN) Q Converter ISD = 3µA, 3mm × 3mm DFN8, MS8E LTC1474 18V, 250mA (I ), High Efficiency Step-Down DC/DC Converter V : 3V to 18V, V = 1.2V, I = 10µA, I = 6µA, MSOP8 OUT IN OUT(MIN) Q SD LT1934/LT1934-1 36V, 250mA (I ), Micropower Step-Down DC/DC Converter V : 3.2V to 34V, V = 1.25V, I = 12µA, I < 1µA, OUT IN OUT(MIN) Q SD with Burst Mode Operation ThinSOT™ Package LT1939 25V, 2A, 2.5MHz High Efficiency DC/DC Converter and LDO V : 3.6V to 25V, V = 0.8V, I = 2.5mA, I < 10µA, IN OUT(MIN) Q SD Controller 3mm × 3mm DFN10 LT3437 60V, 400mA (I ), Micropower Step-Down DC/DC Converter V : 3.3V to 60V, V = 1.25V, I = 100µA, I < 1µA, OUT IN OUT(MIN) Q SD with Burst Mode Operation 3mm × 3mm DFN10, TSSOP16E LT3470 40V, 250mA (I ), High Efficiency Step-Down DC/DC V : 4V to 40V, V = 1.2V, I = 26µA, I < 1µA, OUT IN OUT(MIN) Q SD Converter with Burst Mode Operation 2mm × 3mm DFN8, ThinSOT LT3685 36V with Transient Protection to 60V, 2A (I ), 2.4MHz, High V : 3.6V to 38V, V = 0.78V, I = 70µA, I < 1µA, OUT IN OUT(MIN) Q SD Efficiency Step-Down DC/DC Converter 3mm × 3mm DFN10, MSOP10E 3642fc 22 Linear Technology Corporation LT 1010 REV C • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2008