LTC3615/LTC3615-1 Dual 4MHz, 3A Synchronous Step-Down DC/DC Converter FeaTures DescripTion n High Efficiency: Up to 94% The LTC®3615/LTC3615-1 are dual 3A synchronous step- n Dual Outputs with 2 × 3A Output Current Capability down regulators using a current mode, constant-frequency n Low Output Ripple Burst Mode® Operation: I = 130µA architecture. The DC supply current is only 130µA (Burst Q n 2.25V to 5.5V Input Voltage Range Mode operation at no-load) while maintaining the output n ±1% Output Voltage Accuracy voltages, dropping to zero current in shutdown. The 2.25V n Output Voltages Down to 0.6V to 5.5V input supply range makes the parts ideally suited n Programmable Slew Rate at Switch Pins for single Li-Ion applications. 100% duty cycle capability n Low Dropout Operation: 100% Duty Cycle provides low dropout operation, which extends operating n Shutdown Current ≤1µA time in battery-operated systems. n Adjustable Switching Frequency Up to 4MHz The operating frequency is externally programmable up to n Internal or External Compensation 4MHz, allowing the use of small surface mount inductors. n Selectable Pulse-Skipping/Forced Continuous/ 0°, 90°, or 180° (LTC3615) or 140°/180° (LTC3615-1) of Burst Mode Operation with Adjustable Burst Clamp phase shift between the two channels can be selected to n Optional Active Voltage Positioning (AVP) with minimize input current ripple and output voltage ripple in a Internal Compensation dual 3A or single 6A output configuration. Programmable n Selectable 0°/90°/180° (LTC3615) or selectable slew rate limiting reduces EMI, and external synchroniza- 140°/180° (LTC3615-1) Phase Shift Between Channels tion can be applied up to 4MHz. n Fixed Internal and Programmable External Soft-Start n Accurate Start-Up Tracking Capability The internal synchronous switches increase efficiency n DDR Memory Mode I = ±1.5A and eliminate the need for external catch diodes, saving OUT n Available in 4mm × 4mm QFN-24 and TSSOP-24 Packages external components and board space. applicaTions The LTC3615/LTC3615-1 are offered in leadless 24-pin 4mm × 4mm QFN and thermally enhanced 24-pin TSSOP n Point-of-Load Supplies packages. n Distributed Power Supplies L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks n Portable Computer Systems of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5994885, 6304066, 6498466, 6580258, n DDR Memory Termination 6611131. n Handheld Devices Typical applicaTion Efficiency and Power Loss vs Load Current 100 10 VIN 90 100µF SVIN PVIN1 PVIN2 0.47µH VOUT1 80 1 RUN1 SW1 1.8V/3A TIPSTRGRHAOL1CIOMKD/1SS1LTC3615 FB1 422k 47µF NCY (%) 576000 0.1 POWER L MPRHTO/ASDSYEENC SW2 0.47µH 210k V2.O5UVT/23A EFFICIE 3400 0.01 OSS (W) RUN2 665k 47µF 20 VIN = 3.3V 0.001 TRACK/SS2 FB2 10 2.25MHz VIN = 4V PGOOD2 VOUT = 2.5V VIN = 5V ITH2 SGND PGND 210k 0 0.0001 0.001 0.01 0.1 1 3615 TA01a OUTPUT CURRENT (A) 3615 TA01b 3615fb 1 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 absoluTe MaxiMuM raTings (Notes 1, 11) PV , PV Voltages ....................–0.3V to SV + 0.3V Operating Junction Temperature IN1 IN2 IN SV Voltage ................................................–0.3V to 6V Range (Notes 2, 11) ...............................–55°C to 150°C IN SW1 Voltage .............................–0.3V to (PV + 0.3V) Storage Temperature..............................–65°C to 150°C IN1 SW2 Voltage ..............................–0.3V to (PV + 0.3V) Lead Soldering Temperature (eTSSOP) .................300°C IN2 PGOOD1, PGOOD2 Voltages ........................–0.3V to 6V Reflow Peak Body Temperature (QFN) ..................260°C All Other Pins ..............................–0.3V to (SV + 0.3V) IN pin conFiguraTion TOP VIEW S1 TOP VIEW S PHAFSBE2 12 2243 MFBO1DE TRACK/ SVIN PVIN1 PVIN1 SW1 SW1 ITH2 3 22 ITH1 24 23 22 21 20 19 TRACK/SS2 4 21 TRACK/SS1 ITH1 1 18 PGOOD1 SGND 5 20 SVIN FB1 2 17 SRLIM PPVVIINN22 67 PG2N5D 1198 PPVVIINN11 PMHOADSEE 43 PG2N5D 1156 PRGT/OSOYDN2C SW2 8 17 SW1 FB2 5 14 RUN1 ITH2 6 13 RUN2 SW2 9 16 SW1 RUN2 10 15 PGOOD1 7 8 9 10 11 12 RT/RSYUNNC1 1112 1143 SPRGLOIOMD2 ACK/SS2 SGND PVIN2 PVIN2 SW2 SW2 R T FE PACKAGE UF PACKAGE 24-LEAD PLASTIC eTSSOP 24-LEAD (4mm × 4mm) PLASTIC QFN TJMAX = 150°C, θJA = 33°C/W TJMAX = 150°C, θJA = 37°C/W EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3615EFE#PBF LTC3615EFE#TRPBF LTC3615FE 24-Lead Plastic TSSOP –40°C to 125°C LTC3615IFE#PBF LTC3615IFE#TRPBF LTC3615FE 24-Lead Plastic TSSOP –40°C to 125°C LTC3615HFE#PBF LTC3615HFE#TRPBF LTC3615FE 24-Lead Plastic TSSOP –40°C to 150°C LTC3615MPFE#PBF LTC3615MPFE#TRPBF LTC3615FE 24-Lead Plastic TSSOP –55°C to 150°C LTC3615EUF#PBF LTC3615EUF#TRPBF 3615 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C LTC3615IUF#PBF LTC3615IUF#TRPBF 3615 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C LTC3615HUF#PBF LTC3615HUF#TRPBF 3615 24-Lead (4mm × 4mm) Plastic QFN –40°C to 150°C LTC3615MPUF#PBF LTC3615MPUF#TRPBF 3615 24-Lead (4mm × 4mm) Plastic QFN –55°C to 150°C LTC3615EFE-1#PBF LTC3615EFE-1#TRPBF LTC3615FE-1 24-Lead Plastic TSSOP –40°C to 125°C LTC3615IFE-1#PBF LTC3615IFE-1#TRPBF LTC3615FE-1 24-Lead Plastic TSSOP –40°C to 125°C LTC3615HFE-1#PBF LTC3615HFE-1#TRPBF LTC3615FE-1 24-Lead Plastic TSSOP –40°C to 150°C LTC3615MPFE-1#PBF LTC3615MPFE-1#TRPBF LTC3615FE-1 24-Lead Plastic TSSOP –55°C to 150°C LTC3615EUF-1#PBF LTC3615EUF-1#TRPBF 36151 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C LTC3615IUF-1#PBF LTC3615IUF-1#TRPBF 36151 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C LTC3615HUF-1#PBF LTC3615HUF-1#TRPBF 36151 24-Lead (4mm × 4mm) Plastic QFN –40°C to 150°C LTC3615MPUF-1#PBF LTC3615MPUF-1#TRPBF 36151 24-Lead (4mm × 4mm) Plastic QFN –55°C to 150°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3615fb 2 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 elecTrical characTerisTics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at T = 25°C (Note 2), SV = PV = 3.3V, R = 178k, R = 40.2k, unless A IN INx T SRLIM otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Operating Voltage Range l 2.25 5.5 V IN V Undervoltage Lockout Threshold SV Ramping Down l 1.7 V UVLO IN SV Ramping Up 2.25 V IN V Feedback Voltage Internal Reference (Note 3) V = SV , V = 0V FB TRACK IN SRLIM 0°C < T < 85°C 0.592 0.6 0.608 V J –40°C < T < 125°C l 0.590 0.610 V J –55°C < T < 150°C l 0.588 0.612 V J Feedback Voltage External Reference (Note 3) V = 0.3V, V = SV 0.289 0.3 0.311 V TRACK SRLIM IN (Note 7) (Note 3) V = 0.5V, V = SV 0.489 0.5 0.511 V TRACK SRLIM IN I Feedback Input Current V = 0.6V l 0 ±30 nA FB FBx ∆V Line Regulation SV = PV = 2.25V to 5.5V (Note 4) l 0.2 %/V LINEREG IN INx ∆V Load Regulation V from 0.5V to 0.9V (Note 4) 0.2 % LOADREG ITHx V = SV , V = 0.6V (Note 5) 2 % ITHx IN FBx I Active Mode V = 0.5V, V = SV , V = 0V (Note 6) 1100 µA S FB1 MODE IN RUN2 V = 0.5V, V = SV , V = SV (Note 1900 µA FBx MODE IN RUNx IN 6) Sleep Mode V = 0.7V, V = SV , V = 0V, 95 130 µA FB1 RUN1 IN RUN2 V = 0V, V = SV (Note 5) MODE ITH1 IN V = 0.7V, V = SV , V = 0V, 145 220 µA FBx RUN1 IN RUN2 V = 0V (Note 4) MODE V = 0.7V, V = SV , V =0V, 130 200 µA FBx RUNx IN MODE V = SV (Note 5) ITHx IN V = 0.7V, V = SV , V =0V, 240 360 µA FBx RUNx IN MODE I = (Note 4) TH Shutdown SV = PV = 5.5V, V = 0V 0.1 1 µA IN IN RUNx R Top Switch On-Resistance PV = 3.3V (Note 10) 75 mΩ DS(ON) INx Bottom Switch On-Resistance PV = 3.3V (Note 10) 55 mΩ INx I Top Switch Current Limit Sourcing (Note 8), V = 0.5V LIM FB Duty Cycle <35% 4.5 6 7.5 A Duty Cycle = 100% 3.6 A Bottom Switch Current Limit Sinking (Note 8), V = 0.7V, –2.5 –3.5 –5 A FB Forced Continuous Mode I Switch Leakage Current SV = PV = 5.5V, V = 0V 0.01 1 µA SW(LKG) IN IN RUNx g Error Amplifier Transconductance –5µA < I < 5µA 240 µmho m(EA) TH I Error Amplifier Output Current (Note 4) ±30 µA EA t Internal Soft-Start Time V from 0.06V to 0.54V, TRACK/SSx = SV 0.65 1.1 1.7 ms SOFT-START FBx IN R TRACK/SS Pull-Down Resistance at 200 Ω DIS Start-Up t Soft-Start Discharge Time at Start-Up 70 µs DIS f Internal Oscillator Frequency R = 178k l 1.85 2.25 2.65 MHz OSC RT/SYNC V = SV l 1.8 2.25 2.7 MHz RT/SYNC IN f Synchronization Frequency t , t > 30ns 0.4 4 MHz SYNC LOW HIGH V SYNC Level High 1.2 V RT/SYNC SYNC Level Low 0.3 V 3615fb 3 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 elecTrical characTerisTics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at T = 25°C (Note 2), SV = PV = 3.3V, R = 178k, R = 40.2k, unless A IN INx T SRLIM otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS jSW1–SW2 Output Phase Shift Between SW1 VPHASE < 0.15 • SVIN 0 Deg and SW2 (LTC3615) 0.35 • SV < V < 0.65 • SV 90 Deg IN PHASE IN V > 0.85 •SV 180 Deg PHASE IN Output Phase Shift Between SW1 V < 0.65 •SV 140 Deg PHASE IN and SW2 (LTC3615-1) V > 0.85 •SV 180 Deg PHASE IN V Voltage at SRLIM to Enable DDR (Note 9) SV – 0.3 V SRLIM IN Mode V Internal Burst Mode Operation 0.3 V MODE (Note 9) Pulse-Skipping Mode SV – 0.3 V IN Forced Continuous Mode 1.1 SV • 0.58 V IN External Burst Mode Operation 0.5 0.85 V PGOOD Power Good Voltage Windows TRACK/SSx = SV , Entering Window IN V Ramping Up –3.5 –6 % FBx V Ramping Down 3.5 6 % FBx TRACK/SSx = SV , Leaving Window IN V Ramping Up 9 11 % FBx V Ramping Down –9 –11 % FBx t Power Good Blanking Time Entering/Leaving Window 70 105 140 µs PGOOD R Power Good Pull-Down On-Resistance I = 10mA 8 12 30 Ω PGOOD V Enable Pin Input High l 1 V RUN Input Low l 0.4 V Pull-Down Resistance 4 MΩ Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: This parameter is tested in a feedback loop which servos V to FB1,2 may cause permanent damage to the device. Exposure to any Absolute the midpoint for the error amplifier (V = 0.75V). ITH1,2 Maximum Rating condition for extended periods may affect device Note 4: External compensation on ITH pin. reliability and lifetime. Note 5: Tying the ITH pin to SV enables internal compensation and AVP IN Note 2: The LTC3615/LTC3615-1 are tested under pulsed load conditions mode for the selected channel. such that TJ ≈ TA. The LTC3615E/LTC3615E-1 are guaranteed to meet Note 6: Dynamic supply current is higher due to the internal gate charge performance specifications over the 0°C to 85°C operating junction being delivered at the switching frequency. temperature range. Specifications over the –40°C to 125°C operating Note 7: See description of the TRACK/SS pin in the Pin Functions section. junction temperature range are assured by design, characterization and Note 8: When sourcing current, the average output current is defined correlation with statistical process controls. The LTC3615I/LTC3615I-1 as flowing out of the SW pin. When sinking current, the average output are guaranteed to meet specifications over the –40°C to 125°C operating current is defined as flowing into the SW pin. Sinking mode requires the junction temperature range. The LTC3615H/LTC3615H-1 are guaranteed use of forced continuous mode. to meet specifications over the –40°C to 150°C operating temperature range. The LTC3615MP/LTC3615MP-1 are tested and guaranteed to meet Note 9: See description of the MODE pin in the Pin Functions section. specifications over the full –55°C to 150°C operating junction temperature Note 10: Guaranteed by design and correlation to wafer level range. High junction temperatures degrade operating lifetime; operating measurements for QFN packages. lifetime is derated for junction temperatures greater than 125°C. Note that Note 11: This IC includes overtemperature protection that is intended the maximum ambient temperature consistent with these specifications to protect the device during momentary overload conditions. Junction is determined by specific operating conditions in conjunction with board temperature will exceed 150°C when overtemperature protection is active. layout, the rated package thermal impedance and other environmental Continuous operation above the specified maximum operating junction factors. The junction temperature (TJ, in °C) is calculated from the ambient temperature may impair device reliability or permanently damage the temperature device. (T , in °C) and power dissipation (P , in watts) according to the formula: A D TJ = TA + (PD • θJA) where θJA (in °C/W) is the package thermal impedance. 3615fb 4 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 Typical perForMance characTerisTics V = 3.3V, R /SYNC = SV , unless otherwise noted. IN T IN Efficiency vs Load Current Efficiency vs Load Current Efficiency vs Load Current (V = 0V) (V = 0V) (V = 0V) MODE MODE MODE 100 100 100 VOUT = 1.8V VOUT = 1.2V VOUT = 2.5V 90 90 90 80 80 80 70 70 70 %) %) %) Y ( 60 Y ( 60 Y ( 60 C C C N 50 N 50 N 50 E E E FICI 40 FICI 40 FICI 40 F F F E E E 30 30 30 20 20 20 VIN = 2.5V VIN = 2.5V VIN = 3.3V 10 VIN = 3.3V 10 VIN = 3.3V 10 VIN = 4V VIN = 5V VIN = 5V VIN = 5V 0 0 0 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 OUTPUT CURRENT (A) OUTPUT CURRENT (A) OUTPUT CURRENT (A) 3615 G01 3615 G02 3615 G03 Efficiency vs Load Current Efficiency vs Load Current Efficiency vs Input Voltage (V = 0.55 • SV ) (V = 0.55 • SV ) (V = 0V) MODE IN MODE IN MODE 100 100 95 VOUT = 1.8V VOUT = 1.2V VOUT = 1.8V 90 90 90 80 80 85 70 70 %) %) %) 80 Y ( 60 Y ( 60 Y ( 75 NC 50 NC 50 NC EFFICIE 40 EFFICIE 40 EFFICIE 7605 30 30 IOUT = 3A 20 20 60 IOUT = 2A VIN = 2.25V VIN = 2.25V IOUT = 1A 10 VIN = 3.3V 10 VIN = 3.3V 55 IOUT = 0.3A VIN = 5V VIN = 5V IOUT = 0.2A 0 0 50 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 2.25 2.75 3.25 3.75 4.25 4.75 5.25 OUTPUT CURRENT (A) OUTPUT CURRENT (A) INPUT VOLTAGE (V) 3615 G04 3615 G05 3615 G06 Load Regulation Line Regulation 0.5 0.20 VMODE = 1.5V 0.4 0.15 INTERNAL 0.3 COMPENSATION 0.10 (ITH = SVIN ) %) 0.2 %) 0.05 OR ( 0.1 OR ( R R 0 R R V EOUT–0.01 ECXOTMEPRENNASLATION V EOUT–0.05 –0.10 –0.2 –0.3 –0.15 –0.4 –0.20 0 0.5 1 1.5 2 2.5 3 2.25 2.75 3.25 3.75 4.25 4.75 5.25 OUTPUT CURRENT (A) INPUT VOLTAGE (V) 3615 G07 3615 G08 3615fb 5 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 Typical perForMance characTerisTics V = 3.3V, R /SYNC = SV , unless otherwise noted. IN T IN Forced Continuous Mode Operation (FCM) Pulse-Skipping Mode Operation Burst Mode Operation VOUT 20mV/DIV VOUT VOUT 20mV/DIV 20mV/DIV IL 200mA/DIV IL 500mA/DIIVL 500mA/DIV VOUT = 1.8V 1µs/DIV 3615 G09 VOUT = 1.8V 20µs/DIV 3615 G10 VOUT = 1.8V 20µs/DIV 3615 G11 IOUT = 100mA IOUT = 75mA IOUT = 75mA VMODE = 1.5V VMODE = 3.3V VMODE = 0V Load Step Transient in Load Step Transient Load Step Transient in FCM External Compensation in Pulse-Skipping Mode Burst Mode Operation VOUT VOUT VOUT 200mV/DIV 200mV/DIV 200mV/DIV IL 1A/DIIVL 1A/DIIVL 1A/DIV VOUT = 1.8V 50µs/DIV 3615 G12 VOUT = 1.8V 50µs/DIV 3615 G13 VOUT = 1.8V 50µs/DIV 3615 G14 ILOAD = 100mA TO 3A ILOAD = 100mA TO 3A ILOAD = 100mA TO 3A VMODE = 1.5V VMODE = 3.3V VMODE = 0V COMPENSATION FIGURE 1 COMPENSATION FIGURE 1 COMPENSATION FIGURE 1 Load Step Transient in Forced Load Step Transient in FCM Continuous Mode Sourcing and Internal Start-Up in Forced with AVP Mode Sinking Current Continuous Mode VOUT RUN 100mV/DIV VOUT 1V/DIV 200mV/DIV IL 500mVV/ODUIVT 1A/DIV IL IL 1A/DIV 2A/DIV0A PGOOD 2V/DIV VOUT = 1.8V 50µs/DIV 3615 G15 VOUT = 1.8V 500µs/DIV 3615 G17 ILOAD = 100mA TO 3A VOUT = 1.8V 50µs/DIV 3615 G16 IOUT = 3A VMODE = 1.5V ILOAD = –1.5A TO 3A VMODE = 1.5V VITH = 3.3V VMODE = 1.5V OUTPUT CAPACITOR VALUE FIGURE 1 COMPENSATION FIGURE 1 3615fb 6 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 Typical perForMance characTerisTics V = 3.3V, R /SYNC = SV , unless otherwise noted. IN T IN Reference Voltage Switch On-Resistance vs Temperature vs Input Voltage 0.606 0.10 0.09 0.604 0.08 MAIN SWITCH V) E (0.602 0.07 G CE VOLTA0.600 (Ω)S(ON) 00..0065 SYNCHRONOUS SWITCH EN RD 0.04 FER0.598 0.03 E R 0.02 0.596 0.01 0.594 0 –60 –25 10 45 80 115 150 2.25 3.25 4.25 5.25 TEMPERATURE (°C) VIN (V) 3615 G18 3615 G19 Switch On-Resistance vs Temperature Frequency vs RT/SYNC 100 4.0 90 3.6 MAIN SWITCH 80 3.2 µA) 70 2.8 AGE ( 60 Hz) 2.4 K M CH LEA 5400 SYNCHRONOUS SWITCH f (OSC 12..60 T WI 30 1.2 S 20 0.8 10 0.4 0 0 –60 –25 10 45 80 115 150 100 200 300 400 500 600 700 800 9001000 TEMPERATURE (°C) RT/SYNC (kΩ) 3615 G20 3615 G22 Frequency vs Temperature Frequency vs Input Voltage 2.7 2.60 2.6 2.50 2.40 2.5 2.30 RT/SYNC = SVIN 2.4 f (MHz)OSC 22..23 RTR/STY=N 1C7 8=k SVIN f (MHz)OSC 222...201000 RT/SYNC = 200k 2.1 1.90 2.0 1.80 1.9 1.70 1.8 1.60 –60 –25 10 45 80 115 150 2.25 3.00 3.75 4.50 5.25 TEMPERATURE (°C) VIN (V) 3615 G23 3615 G24 3615fb 7 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 Typical perForMance characTerisTics V = 3.3V, R /SYNC = SV , unless otherwise noted. IN T IN No Load Supply Current No Load Supply Current Switch Leakage vs Temperature vs Input Voltage vs Temperature 4.0 180 180 MODE = 0V 3.5 160 RUNx = ITHx = SVIN 160 140 140 GE (µA) 23..50 NT (µA) 120 NT (µA) 120 SWITCH LEAKA 211...005 SYNCHRONOUS SWITCH SUPPLY CURRE 108460000 SUPPLY CURRE 108460000 0.5 20 20 MODE = 0V MAIN SWITCH RUNx = ITHx = SVIN 0 0 0 –60 –25 10 45 80 115 150 2.25 2.75 3.25 3.75 4.25 4.75 5.25 –60 –25 10 45 80 115 150 TEMPERATURE (°C) VIN (V) TEMPERATURE (°C) 3615 G25 3615 G26 3615 G27 Slew Rate of Falling Edge at Slew Rate of Rising Edge at SW1/2 vs SRLIM Resistor SW1/2 vs SRLIM Resistor Sinking Current VIN = 3.3V VIN = 3.3V VOUT VOUT = 1.8V VOUT = 1.8V 20mV/DIV IOUT = 1A SRLIM = IOUT = 1A SRLIM = SGND OR SVIN SGND OR SVIN SW 40.2k 2V/DIV 100k 40.2k 1V/DIV OPEN 1V/DIV 100k IL OPEN 500mA/DIV VOUT = 1.2V 1µs/DIV 3615 G30 IOUT = –1A VMODE = 1.5V 2ns/DIV 3615 G28 2ns/DIV 3615 G29 Tracking Up/Down in Tracking Up/Down in Forced Continuous Mode, Forced Continuous Mode, SRLIM Pin Tied to 0V SRLIM Pin Tied to SV IN VOUT1 500mVVO/DUTIV1 1V/DIV VTRACK/SS VTRACK/SS 500mV/DIV 200mV/DIV PGOOD PGOOD 2V/DIV 2V/DIV 2ms/DIV 3615 G31 2ms/DIV 3615 G32 VOUT = 0V TO 1.8V VOUT = 0V TO 1.2V IOUT = 3A IOUT = 3A VTRACK/SS = 0V TO 0.7V VTRACK/SS = 0V TO 0.4V VMODE = 1.5V VMODE = 1.5V VSRLIM = 0V VSRLIM = 3.3V 3615fb 8 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 pin FuncTions (FE/UF) PHASE (Pin 1/Pin 4): Phase Shift Selection. If pin is tied PGOOD2 (Pin 13/Pin 16): Power Good Output for to SGND, the phase between SW1 and SW2 will be 0° Channel 2. See PGOOD1. (LTC3615) or 140° (LTC3615-1). With the PHASE pin SRLIM (Pin 14 /Pin 17): Slew Rate Limit. Slew rate on the tied to half of the SV voltage, 90° (LTC3615) or 140° IN switch pins is programmed with the SRLIM pin: (LTC3615-1) of phase shift will be selected. Tying PHASE to SV will select 180° (LTC3615 and LTC3615-1). 1. Tying this pin to SGND selects maximum slew rate. IN V (Pin 2/Pin 5): Voltage Feedback Input Pin for Chan- 2. Minimum slew rate is selected when the pin is open. FB2 nel 2. See V . FB1 3. Connecting a resistor from SRLIM to SGND allows the ITH2 (Pin 3/Pin 6): Error Amplifier Compensation of slew rate to be continuously adjusted. Channel 2. See ITH1. 4. If SRLIM is tied to SV the slew rate is set to maxi- IN TRACK/SS2 (Pin 4 /Pin 7): Internal, External Soft-Start, mum and DDR mode is enabled (see the Applications External Reference Input for Channel 2. See TRACK/SS1. Information section). SGND (Pin 5/Pin 8): Signal Ground. All small-signal and PGOOD1 (Pin 15/Pin 18): Power Good Output Pin for compensation components should connect to this ground Channel 1. The open-drain output will be pulled down to pin which, in turn, should be connected to PGND at one ground when the FB1 voltage of the channel is not within point. the power good voltage window. The PGOOD1 will also be pulled down if the channel is not enabled with the RUN1 PV (Pins 6, 7/Pins 9, 10) Channel 2 Power Supply IN2 pin or an undervoltage at SV is detected. In DDR mode IN Input. See PV . IN1 (SRLIM = SV ), the power good window moves in relation IN SW2 (Pins 8, 9/Pins 11, 12): Channel 2 Switching Node. to the actual TRACK/SS pin voltage. See SW1. SW1 (Pins 17, 16/Pins 19, 20): Channel 1 Switching RUN2 (Pin 10/Pin 13): Enable Pin for Channel 2. See RUN1. Node. Connection to the external inductor. This pin con- nects to the drains of the internal synchronous power RUN1 (Pin 11/Pin 14): Enable Pin for Channel 1. Forcing MOSFET switches. RUN1 above the input threshold enables the output SW1 of channel 1. Forcing both RUNx pins to ground shuts down PV (Pins 18, 19/Pins 21, 22): Channel 1 Power Supply IN1 the LTC3615. In shutdown, all functions are disabled and Inputs. These pins connect to the source of the internal the LTC3615 draws <1µA of supply current. power P-channel MOSFET of channel 1. P and P VIN1 VIN2 are independent of each other. They may connect to equal R /SYNC (Pin 12/Pin 15): Oscillator Frequency. This pin T or lower supplies than S . provides three modes of setting the switching frequency. VIN SV (Pin 20/Pin 23) Signal Input Supply. This pin pow- 1. Connecting a resistor from R /SYNC to ground will set IN T ers the internal control circuitry and is monitored by the the switching frequency based on the resistor value. undervoltage lockout comparator. 2. Driving R /SYNC with an external clock signal will T TRACK/SS1 (Pin 21/Pin 24): Internal, External Soft-Start, synchronize the switcher to the applied frequency. The External Reference Input for Channel 1. The type of start-up slope compensation is automatically adapted to the external clock frequency. 3. Tying this pin to SV enables the internal 2.25MHz IN oscillator frequency. 3615fb 9 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 pin FuncTions (FE/UF) behavior for channel 1 is programmable with the TRACK/ 1. Tying the MODE pin to SV or SGND enables pulse- IN SS1 pin: skipping mode or Burst Mode operation (with an internal Burst Mode clamp), respectively. 1. Internal soft-start with a fixed timing can be programmed by tying TRACK/SS1 to SV . 2. If this pin is held at slightly higher than half of SV , IN IN forced continuous mode will be selected. 2. External soft-start can be programmed with the timing set by a capacitor to ground and a resistor to SV . 3. Connecting this pin to an external voltage will select IN Burst Mode operation with the burst clamp set to the 3. Tracking the start-up behavior of another supply is pin voltage. programmable (see the Applications Information section). PGND (Exposed Pad Pin 25/ Exposed Pad Pin 25): Power Ground. The exposed pad connects to the sources of the 4. The pin can be used as external reference input. power N-channel MOSFETs. The PGND pin is common ITH1 (Pin 22/Pin 1): Error Amplifier Compensation. Con- for both channels. The exposed pad must be soldered nection for external compensation from ITH to SGND. to the PCB. The current comparator’s threshold increases with this For electrical connection and rated thermal performance, control voltage. Tying this pin to SV enables AVP mode IN refer to the Operation and Applications Information sec- with internal compensation. tions for more information. V (Pin 23/Pin 2): Voltage Feedback Input Pin for FB1 Channel 1. Receives the feedback voltage for channel 1 from the external resistive divider across the output. MODE (Pin 24/Pin 3): Mode Selection. 3615fb 10 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 FuncTional block DiagraM ITH1 CHANNEL 1 PGOOD1 PGOOD WINDOW- DELAY COMPARATOR INTERNAL/ EXTERNAL COMPENSATION ERROR ITH-VOLTAGE FB1 + AMPLIFIER BURST LIMIT COMPARATOR VREF – +MODE – + IDEAL DIODE PMOS SLOPE PMOS – CURRENT SENSE + – COMPENSATION COCMUPRARREANTTOR PVIN1 MODE CONTROLLER LOGIC SW1 TRACK/SS1 SOFT-START GATE DRIVER RUN1 CLK1 RUN2 OR PLL RT/SYNC OSCILLATOR + NMOS AND PHASE CURRENT SENSE PHASE SELECTOR – 0A SVIN CLK2 UNDERVOLTAGE REVERSE SGND LOCKOUT SHUTDOWN CURRENT COMPARATOR SRLIM PGND DUPLICATE FOR CHANNEL 2 PGOOD2 PVIN2 FB2 SW2 TRACK/SS2 ITH2 3615 FD 3615fb 11 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 operaTion Main Control Loop MODE SELECTION The LTC3615 is a dual monolithic step-down DC/DC The MODE pin is used to select one of four different converter featuring current-mode, constant-frequency operating modes for both channels together (see Figures operation. Both channels are identical and share common 1 and 3): clock and reference circuits to improve channel-to-channel matching. SVIN PS PULSE-SKIPPING MODE ENABLE During normal operation, the internal top power switch SVIN – 0.3V (P-channel MOSFET) of each channel is turned on at SVIN • 0.58 the beginning of its clock cycle. Current in the inductor FC FORCED CONTINUOUS MODE ENABLE increases until the current comparator trips and turns off the top power MOSFET. The peak inductor current at 1.1V which the current comparator shuts off is controlled by 0.8V Burst Mode ENABLE—EXTERNAL CLAMP, BM CONTROLLED BY VOLTAGE APPLIED AT the voltage on the ITH pin. The error amplifier adjusts the EXT 0.5V MODE PIN voltage on the ITH pin by comparing the feedback signals 0.3V BM Burst Mode ENABLE—INTERNAL CLAMP derived from an external resistor divider on the V pin FBx SGND 3615 F01 with an internal 0.6V reference. When the load current increases, it causes a reduction in the feedback voltage Figure 1. Mode Selection Voltage relative to the reference. The error amplifier raises the ITH voltage until the average inductor current matches the new Burst Mode Operation—Internal Clamp load current. Typical voltage range for the ITH pin is from 0.45V to 1.05V with 0.45V corresponding to zero current. Connecting the MODE pin to the SGND pin enables Burst Mode operation with its peak current set internally. In When the top power MOSFET shuts off, the synchronous Burst Mode operation the internal power MOSFETs operate power switch (N-channel MOSFET) turns on until either intermittently at light loads. This increases efficiency by the current limit is reached or the next clock cycle begins. minimizing switching losses. During the intervals when the The bottom current limit is typically set at –4A for forced MOSFETs are not switching, the LTC3615 enters a sleep continuous mode and 0A for Burst Mode operation and state where many of the internal circuits are disabled to pulse-skipping mode. save power. During Burst Mode operation, the ITH volt- The operating frequency defaults to 2.25MHz when age is monitored by the burst comparator to determine RT/SYNC is connected to SVIN, or can be set by an ex- when the sleep state is entered or exited again. When the ternal resistor connected between the RT/SYNC pin and average inductor current is greater than the load current, ground, or by a clock signal applied to the RT/SYNC pin. the voltage on the ITH pin drops. As the ITH voltage falls The switching frequency can be set from 400kHz to 4MHz below the internal threshold, the LTC3615 enters the sleep (see the Applications Information section). state. In the sleep state, the power MOSFETs are held off and the load current is solely supplied by the output Overvoltage and undervoltage comparators pull the PGOOD capacitor. When the output voltage drops, the top power output low if the output voltage varies more than ±7.5% MOSFET is switched back on and the internal circuits are from the set point. reenabled. This process repeats at a rate that is dependent on the load current. 3615fb 12 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 operaTion Burst Mode Operation—External Clamp Forced Continuous Mode Operation Connecting the MODE pin to a voltage in the range of 0.5V In forced continuous mode the inductor current is con- to 0.8V enables Burst Mode operation with external clamp. stantly cycled which creates a minimum output voltage During this mode of operation, the minimum voltage on ripple at all output current levels. the ITH pin is externally set by the voltage on the MODE Connecting the MODE pin, to a voltage in the range of pin. It is recommended to use Burst Mode operation with 1.1V to SV • 0.58 will select the forced continuous mode IN the internal clamp for ambient temperatures above 85°C. operation. Pulse-Skipping Mode Operation The forced continuous mode must be used if the output is required to sink current. Pulse-skipping mode is similar to Burst Mode operation, but the LTC3615 does not disable power to the internal Dropout Operation circuitry during sleep mode. This improves output voltage ripple but uses more quiescent current compromising As the input supply voltage approaches the output voltage, light load efficiency. the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main Connecting the MODE pin to SV enables pulse-skipping IN switch to remain on for more than one cycle, eventually mode. As the load current decreases, the peak inductor reaching 100% duty cycle. The output voltage will then be current will be determined by the voltage on the ITH pin determined by the input voltage minus the voltage drop until the ITH voltage drops below 450mV, corresponding across the internal P-channel MOSFET and the inductor. to 0A. At this point switching cycles will be skipped to keep the output voltage in regulation. LTC3615 LTC3615 VIN SVIN VIN SVIN SW1 VOUT1 RM1 MODE MODE FB1 0V SGND RM2 0V SGND 2a. Burst Mode Operation 2b. Burst Mode Operation Internally Controlled Externally Controlled LTC3615 LTC3615 VIN SVIN VIN SVIN RM1 MODE MODE RM2 0V SGND 0V SGND 3615 F02 2c. Pulse-Skipping Mode 2d. Forced Continuous Mode Figure 2. Modes of Operation 3615fb 13 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 operaTion Low Supply Operation proximately 1.05V which corresponds to about 5A peak inductor current. The LTC3615 is designed to operate down to an input supply voltage of 2.25V. An important consideration at low input When the output is shorted to ground, the inductor current supply voltages is that the R of the P-channel and decays very slowly during a single switching cycle. The DS(ON) N-channel power switches increases by 50% compared to LTC3615 uses two techniques to prevent current runaway 5V. The user should calculate the power dissipation when from occurring: the LTC3615 is used at 100% duty cycle with low input 1. If the output voltage drops below 50% of its nominal voltages to ensure that thermal limits are not exceeded. value, the clamp voltage at pin ITH is lowered, causing the maximum peak inductor current to lower gradu- Slope Compensation and Inductor Peak Current ally with the output voltage. When the output voltage Slope compensation provides stability in current mode reaches 0V, the clamp voltage at the ITH pin drops to constant-frequency architectures by preventing subhar- 40% of the clamp voltage during normal operation. The monic oscillations at duty cycles greater than 50%. The short-circuit peak inductor current is determined by the LTC3615 implements slope compensation by adding a minimum on-time of the LTC3615, the input voltage compensation ramp to the inductor current signal. and the inductor value. This foldback behavior helps in limiting the peak inductor current when the output Short-Circuit Protection is shorted to ground. It is disabled during internal or The peak inductor current at which the current comparator external soft-start and tracking up/down operation (see shuts off the top power switch is controlled by the voltage the Applications Information section). on the ITH pin. 2. If the inductor current of the bottom MOSFET increases If the output current increases, the error amplifier raises beyond 6A typical, the top power MOSFET will be held the ITH pin voltage until the average inductor current off and switching cycles will be skipped until the induc- matches the new load current. In normal operation, the tor current reduces. LTC3615 clamps the maximum ITH pin voltage at ap- 3615fb 14 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 applicaTions inForMaTion Operating Frequency is typically 60ns, therefore, the minimum duty cycle is equal to 60ns • 100% • f (Hz) Selection of the operating frequency is a trade-off between OSC efficiency and component size. High frequency operation Tying the R /SYNC pin to SV sets the default internal T IN allows the use of smaller inductor and capacitor values. operating frequency to 2.25MHz ±20%. Operation at lower frequencies improves efficiency by Frequency Synchronization reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low The LTC3615’s internal oscillator can be synchronized to output ripple voltage. an external frequency by applying a square wave clock signal to the R /SYNC pin. During synchronization, the T The operating frequency of the LTC3615 is determined top MOSFET turn-on of channel 1 is locked to the rising by an external resistor that is connected between pin R / T edge of the external frequency source. The synchronization SYNC and ground. The value of the resistor sets the ramp frequency range is 400kHz to 4MHz. The internal slope current that is used to charge and discharge an internal compensation is automatically adapted to the external timing capacitor within the oscillator and can be calculated clock frequency. by using the following equation: In the signal path from the R /SYNC clock input to the T 4•1011ΩHz SW output, the LTC3615 is processing the external clock R = T f frequency through an internal PLL. OSC After detecting an external clock on the first rising edge Although frequencies as high as 4MHz are possible, the of R /SYNC the PLL starts up with the internal default of minimum on-time of the LTC3615 imposes a minimum T 2.25MHz. The internal PLL then requires a certain number limit on the operating duty cycle. The minimum on-time VIN 3.3V 47µF 47µF 1µF SVIN (2×) PVIN1 (2×) PVIN2 0.47µH VOUT1 RUN1 (2×) SW1 1.8V/3A RSS R1 47µF 4.7M 422k TRACK/SS1 FB1 CSS PGOOD1 R2 10nF ITH1 29.4k LTC3615 MODE RC 10pF R3 15k RT, 200k 178k 1C0C00pF RSRLIM RT/SYNC (2×) SW2 0.47µH 2V.O5UVT/23A 40.2k SRLIM R5 47µF 665k PHASE FB2 R4 RUN2 210k TRACK/SS2 PGOOD2 ITH2 SGND PGND 3615 F03 Figure 3. Soft-Start and Compensation for Channel 1 Externally Programmed, Soft-Start and Compensation for Channel 2 Internally Programmed 3615fb 15 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 applicaTions inForMaTion VIN VIN VIN VIN LTC3615 LTC3615 LTC3615 LTC3615 SRVT/ISNYNC f2S.2W5MHz 0.4V SRVT/ISNYNC fSW ∝1/ROSC SRVT/ISNYNC f1S/WTP 15pF SRVT/ISNYNC f1S/WTP ROSC SGND 1.2V SGND 1.2V RT SGND 0.3V 0.3V TP TP 3615 F04 Figure 4. Setting the Switching Frequency of periods to settle until the frequency at SW matches the on the duty cycle of the two channels, choose the phase frequency and phase of R /SYNC. difference between the channels to keep edges as far away T from each other as possible. When the external clock signal is removed, the LTC3615 needs approximately 5µs to detect the absence of the For example, for duty cycles of less than 40% for one external clock. During this time, the PLL will continue to channel and more than 60% for the other channel, the provide clock cycles before it is switched back to the de- SW node edges will not coincide for 0° or 180° phase fault frequency or selected frequency (set via the external shifts. If both channels have a duty cycle of around 50%, RT resistor). a 90° phase difference would be a better choice. In cases where the duty cycles are ~25% and ~50%, a 140° phase A safe way of driving the R /SYNC input is with an AC T shift (LTC3615-1 only) is preferable to the other phase coupling to the clock generator via a 15pF capacitor. The AC coupling avoids complications if the external clock selections. generator cannot provide a continuous clock signal at the Inductor Selection time of start-up, operation and shut down of the LTC3615. For a given input and output voltage, the inductor value In general, any abrupt clock frequency change of the and operating frequency determine the ripple current. The regulator will have an effect on the SW pin timing and ripple current ∆I increases with higher V and decreases L IN may cause equally sudden output voltage changes. This with higher inductance. must be taken into account in particular if the external clock frequency is significantly different from the internal ⎛ V ⎞ ⎛ V ⎞ default of 2.25MHz. ΔIL =⎜ OUT ⎟•⎜⎜1– OUT ⎟⎟ ⎝fSW •L⎠ ⎝ VIN(MAX)⎠ Phase Selection Having a lower ripple current reduces the core losses Channel 2 of the LTC3615 will operate in-phase, 180° in the inductor, the ESR losses in the output capacitors out-of-phase (anti-phase) or shifted by 90° from chan- and the output voltage ripple. A reasonable starting point nel 1 depending on the state of the PHASE pin—low, for selecting the ripple current is ∆I = 0.3(I ). L OUT(MAX) midrail and high, respectively. Channel 2 of LTC3615-1 The largest ripple current occurs at the highest V . To IN will operate 180° out-of-phase (anti-phase) with PHASE guarantee that the ripple current stays below a specified pin high or shifted by 140° with PHASE midrail or low. maximum, the inductor value should be chosen according Antiphase generally reduces input voltage and current to the following equation: ripple. Crosstalk between switch nodes SW1, SW2 and components or sensitive lines connected to FBx, ITHx, R / ⎛ ⎞ ⎛ ⎞ T V V SYNC or SRLIM can cause unstable switching waveforms L=⎜ OUT ⎟•⎜1– OUT ⎟ ⎜ ⎟ ⎜ ⎟ f •ΔI V and unexpectedly large input and output voltage ripple. ⎝ SW L(MAX)⎠ ⎝ IN(MAX)⎠ The situation improves if rising and falling edges of the The inductor value will also have an effect on Burst Mode switch nodes are timed carefully not to coincide. Depending operation. The transition to low current operation begins 3615fb 16 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 applicaTions inForMaTion when the peak inductor current falls below a level set by The maximum RMS capacitor current is given by: the burst clamp. Lower inductor values result in higher ripple current which causes this to occur at lower DC I =I • VOUT • ⎛⎜ VIN –1⎞⎟ RMS OUT(MAX) load currents. This causes a dip in efficiency in the upper VIN ⎝VOUT ⎠ range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency This formula has a maximum at V = 2V , where I = IN OUT RMS to increase. I /2. This simple worst-case condition is commonly used OUT for design because even significant deviations do not offer Inductor Core Selection much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life Once the value for L is known, the type of inductor must which makes it advisable to further derate the capacitor, be selected. Actual core loss is independent of core size or choose a capacitor rated at a higher temperature than for fixed inductor value, but it is very dependent on the required. Generally select the capacitors respecting the inductance selected. As the inductance increases, core temperature range of the application! Several capacitors losses decrease. Unfortunately, increased inductance may also be paralleled to meet size or height requirements requires more turns of wire, and therefore, copper losses in the design. will increase. Table 1. Representative Surface Mount Inductors Ferrite designs have very low core losses and are pre- INDUCTANCE DCR MAX DIMENSIONS HEIGHT ferred at high switching frequencies, so design goals (µH) (mΩ) CURRENT (A) (mm) (mm) can concentrate on copper loss and preventing satura- Vishay IHLP-2020BZ-01 tion. Ferrite core material saturates hard, which means 0.33 7.6 25 5.18 × 5.49 2 that inductance collapses abruptly when the peak design 0.47 8.9 21 5.18 × 5.49 2 current is exceeded. This results in an abrupt increase in 0.68 11.2 15 5.18 × 5.49 2 inductor ripple current and consequent output voltage 1 18.9 16 5.18 × 5.49 2 ripple. Do not allow a ferrite core to saturate and select Toko DE3518C Series external inductors respecting the temperature range of 0.22 8 24 4.3 × 4.7 2 the application! Sumida CDMC6D28 Series 0.3 3.2 15.4 6.7 × 7.25 3 Different core materials and shapes will change the size/ 0.47 4.2 13.6 6.7 × 7.25 3 current and price/current relationship of an inductor. 0.68 5.4 11.3 6.7 × 7.25 3 Toroid or shielded pot cores in ferrite or permalloy materials 1 8.8 8.8 6.7 × 7.25 3 are small and do not radiate much energy, but generally NEC/Tokin MPLC0730L Series cost more than powdered iron core inductors with similar 0.47 4.5 16.6 6.9 × 7.7 3.0 characteristics. The choice of which style inductor to use 0.75 7.5 12.2 6.9 × 7.7 3.0 mainly depends on the price versus size requirements 1.0 9.0 10.6 6.9 × 7.7 3.0 and any radiated field/EMI requirements. Table 1 shows Coilcraft DO1813H Series some typical surface mount inductors that work well in 0.33 4 10 8.9 × 6.1 5 LTC3615 applications. 0.56 10 7.7 8.9 × 6.1 5 Coilcraft SLC7530 Series Input Capacitor C Selection IN 0.27 0.1 14 7.5 × 6.7 3 In continuous mode, the source current of the top P- 0.35 0.1 11 7.5 × 6.7 3 channel MOSFET is a square wave of duty cycle V /V . 0.4 0.1 8 7.5 × 6.7 3 OUT IN To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current must be used for C . IN 3615fb 17 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 applicaTions inForMaTion Output Capacitor C Selection Capacitors are tempting for switching regulator use OUT because of their very low ESR. Great care must be taken The selection of C is typically driven by the required OUT when using only ceramic input and output capacitors. ESR to minimize voltage ripple and load step transients (low-ESR ceramic capacitors are discussed in the next Ceramic caps are prone to temperature effects which re- section). Typically, once the ESR requirement is satisfied, quire the designer to check loop stability over the operating the capacitance is adequate for filtering. The output ripple temperature range. To minimize their large temperature ∆V is determined by: and voltage coefficients, only X5R or X7R ceramic capaci- OUT tors should be used. ⎛ 1 ⎞ ΔVOUT ≤ΔIL •⎜ESR+ ⎟ When a ceramic capacitor is used at the input, and the ⎝ 8•f •C ⎠ SW OUT power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing where f = operating frequency, C = output capacitance SW OUT at the V pin. At best, this ringing can couple to the output and ∆I = ripple current in the inductor. The output ripple IN L and be mistaken as loop instability. At worst, the ringing is highest at maximum input voltage since ∆I increases L at the input can be large enough to damage the part. with input voltage. Since the ESR of a ceramic capacitor is so low, the input In surface mount applications, multiple capacitors may and output capacitor must instead fulfill a charge storage have to be paralleled to meet the capacitance, ESR or RMS requirement. During a load step, the output capacitor must current handling requirement of the application. Aluminum instantaneously supply the current to support the load electrolytic, special polymer, ceramic and dry tantalum until the feedback loop raises the switch current enough capacitors are all available in surface mount packages. to support the load. The time required for the feedback Tantalum capacitors have the highest capacitance density, loop to respond is dependent on the compensation com- but can have higher ESR and must be surge tested for ponents and the output capacitor size. Typically, three to use in switching power supplies. Aluminum electrolytic four cycles are required to respond to a load step, but capacitors have significantly higher ESR, but can often only in the first cycle does the output drop linearly. The be used in extremely cost-sensitive applications provided output droop, V , is usually about two to three times DROOP that consideration is given to ripple current ratings and the linear drop of the first cycle. Thus, a good place to long term reliability. start is with the output capacitor size of approximately: Ceramic Input and Output Capacitors C ≈ 2.5•ΔIOUT OUT f •V Ceramic capacitors have the lowest ESR and can be cost SW DROOP effective, but also have the lowest capacitance density, More capacitance may be required depending on the duty high voltage and temperature coefficients, and exhibit cycle and load step requirements. In most applications, the audible piezoelectric effects. In addition, the high-Q of input capacitor is merely required to supply high frequency ceramic capacitors along with trace inductance can lead bypassing, since the impedance to the supply is very low. to significant ringing. 3615fb 18 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 applicaTions inForMaTion Output Voltage Programming Pulse-Skipping Mode The output voltages are set by external resistive dividers. Pulse-skipping mode, which is a compromise between low For example, V can be set according to the following output voltage ripple and efficiency, can be implemented OUT2 equation: by connecting the MODE pin to SV . This sets I to IN BURST 0A. In this condition, the peak inductor current is limited ⎛ R5⎞ V =0.6V•⎜1+ ⎟ by the minimum on-time of the current comparator. The OUT2 ⎝ R4⎠ lowest output voltage ripple is achieved while still operating discontinuously. During very light output loads, pulse- The resistive divider allows pin V to sense a fraction of FB skipping allows only a few switching cycles to skip while the output voltage as shown in Figure 3. maintaining the output voltage in regulation. Burst Clamp Programming Internal and External Compensation If the voltage on the MODE pin is less than 0.8V, Burst The regulator loop response can be checked by looking at Mode operation is enabled. If the voltage on the MODE pin the load current transient response. Switching regulators is less than 0.3V, the internal default burst clamp level is take several cycles to respond to a step in DC load current. selected. The minimum voltage on the ITH pin is typically When a load step occurs, like the one shown in Figure 5, 525mV (internal clamp). V shifts by an amount equal to ∆I • ESR, where OUT LOAD If the voltage is between 0.45V and 0.8V, the voltage on ESR is the effective series resistance of C . ∆I OUT LOAD the MODE pin (VBURST) is equal to the minimum voltage also begins to charge or discharge COUT, generating the on the ITH pin (external clamp) and determines the burst feedback error signal that forces the regulator to adapt clamp level IBURST (typically from 1A to 3.5A). to the current change and return VOUT to its steady-state value. During this recovery time, V can be monitored When the ITH voltage falls below the internal (or external) OUT for excessive overshoot or ringing, which would indicate clamp voltage, the sleep state is entered. As the output a stability problem. The availability of the ITH pin allows load current drops, the peak inductor current decreases the transient response to be optimized over a wide range to keep the output voltage in regulation. When the output of output capacitance. load current demands a peak inductor current that is less than IBURST, the burst clamp will force the peak inductor The ITH1 external components (15k and 100pF) shown current to remain equal to IBURST regardless of further in Figure 3 will provide an adequate compensation as reductions in the load current. well as a starting point for most applications. The values can be modified slightly to optimize transient response Since the average inductor current is greater than the once the final PCB layout is complete and the particular output load current, the voltage on the ITH pin will output capacitor type and value have been determined. decrease. When the ITH voltage drops, sleep mode is The output capacitors need to be selected because the enabled in which both power switches are shut off along various types and values determine the loop gain and with most of the circuitry to minimize power consumption. phase. The gain of the loop will be increased by increas- All circuitry is turned back on and the power switches ing R and the bandwidth of the loop will be increased resume operation when the output voltage drops out of C by decreasing C . If R is increased by the same factor regulation. The value for I is determined by the C C BURST that C is decreased, the zero frequency will be kept the desired amount of output voltage ripple. As the value of C same, thereby keeping the phase shift the same in the I increases, the sleep period between pulses and BURST most critical frequency range of the feedback loop. The the output voltage ripple increase. It is recommend to output voltage settling behavior is related to the stabil- use Burst Mode operation with internal clamp for tem- ity of the closed-loop system. The external compensa- peratures above 85°C ambient. tion, forced continuous operation circuit in the Typical 3615fb 19 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 applicaTions inForMaTion Applications section uses faster compensation to improve When the load current suddenly decreases, the output load step response. voltage starts at a level lower than nominal so the output voltage can have more overshoot and stay within the A second, more severe transient is caused by switching specified voltage range. This behavior is demonstrated in loads with large (>1µF) supply bypass capacitors. The in Figure 6. discharged bypass capacitors are effectively put in parallel with C , causing a rapid drop in V . No regulator can The benefit is a lower peak-to-peak output voltage deviation OUT OUT alter its delivery of current quickly enough to prevent this for a given load step without having to increase the output sudden step change in output voltage if the load switch filter capacitance. Alternatively, the output voltage filter resistance is low and it is driven quickly. More output capacitance can be reduced while maintaining the same capacitance may be required depending on the duty cycle peak-to-peak transient response. For this operation mode, and load step requirements. the loop gain is reduced and no external compensation is required. If the ITH pin is tied to SV , the active voltage positioning IN (AVP) mode and the internal compensation is selected. Programmable Switch Pin Slew Rate In AVP mode, the load regulation performance is inten- As switching frequencies rise, it is desirable to minimize the tionally reduced, setting the output voltage at a point that transition time required when switching to minimize power is dependent on the load current. When the load current losses and blanking time for the switch to settle. However, suddenly increases, the output voltage starts from a level fast slewing of the switch node results in relatively high slightly higher than nominal so the output voltage can external radiated EMI and high on-chip supply transients, droop more and stay within the specified voltage range. which can cause problems for some applications. VOUT 100mV/DIV VOUT 200mV/DIV 3A IL 1A/DIV IL 1A/DIV 100mA 50µs/DIV 3615 F05 50µs/DIV 3615 F06 VOUT = 1.8V VOUT = 1.8V ILOAD = 100mA TO 3A ILOAD = 100mA TO 3A VMODE = 1.5V VMODE = 1.5V COMPENSATION AND OUTPUT CAPACITOR VIN = VITH = 3.3V VALUES OF FIGURE 3 OUTPUT CAPACITOR VALUE FIGURE 3 Figure 5. Load Step Transient in FCM with External Compensation Figure 6. Load Step Transient in FCM in AVP Mode 3615fb 20 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 applicaTions inForMaTion The LTC3615 allows the user to control the slew rate of SSx pin to SGND and discharging the external capacitor the switching node SW by using the SRLIM pin. Tying this C (see Figure 3). SS pin to ground selects the fastest slew rate. The slowest The initial discharge is adequate to discharge capacitors slew rate is selected when the pin is open. Connecting a up to 33nF. If a larger capacitor is required, connect the resistor (between 10k to 100k) from SRLIM pin to ground external soft-start resistor R to the RUN pin to fully SS adjusts the slew rate between the maximum and minimum discharge the capacitor. values. The reduced dV/dt of the switch node results in a significant reduction of the supply and ground ringing, as 1. Tying this pin to SVIN selects the internal soft-start well as lower radiated EMI. See Figure 7a and the Typical circuit. This circuit ramps the output voltage to the final Performance Characteristics section for examples. value within 1ms. Reducing the slew rate causes a trade-off between ef- 2. If a longer soft-start period is desired, it can be set ficiency and low EMI (see Figure 7b). externally with a resistor and capacitor on the TRACK/ SSx pins as shown in Figure 3. The voltage applied at Particular attention should be used with very high switching the TRACK/SSx pins sets the value of the internal refer- frequencies. Using the slowest slew rate (SRLIM open) ence at V until TRACK/SSx is pulled above 0.6V. The FB can reduce the minimum duty cycle capability. external soft-start duration can be calculated by using the following equation: Soft-Start ⎛ SV ⎞ The RUNx pins provide a means to shut down each chan- t =R •C •In⎜ IN ⎟ SS SS SS nel of the LTC3615. Pulling both pins below 0.3V places ⎝SV –0.6V⎠ IN the LTC3615 in a low quiescent current shutdown state 3. The TRACK/SSx pin can be used to track the output (I < 1µA). Q voltage of another supply. After enabling the LTC3615 by bringing either one or both Regardless of either the internal or external soft-start RUNx pins above the threshold, the enabled channels state, the MODE pin is ignored during start-up and the enter a soft-start-up state. The type of soft-start behavior regulator defaults to pulse-skipping mode. In addition, is set by the TRACK/SSx pins. The soft-start cycle begins the PGOODx pin is kept low, and the frequency foldback with an initial discharge pulse pulling down the TRACK/ function is disabled. 92 VIN = 3.3V VOUT = 1.8V VOUT = 1.8V 91 IOUT = 1A IOUT = 1A SGNSDR LOIMR S=VIN 90 FCM GND OR SVIN 89 40.2k 100k CY (%) 88 40.2k 20k OPEN 1V/DIV N 87 E OPEN FICI 86 F E 85 84 83 82 2ns/DIV 3615 F07a 2.25 3.06 3.88 4.69 5.50 VIN (V) 3615 07b (7a) Slew Rate of Rising Edge at SW1/2 vs SRLIM Resistor (7b) Efficiency vs SRLIM Resistor Programming Figure 7. Slew Rate and the SRLIM Resistor 3615fb 21 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 applicaTions inForMaTion Output Voltage Tracking Input Through the TRACK/SS pin, the output voltage can be set up to either coincidental or ratiometric tracking, as shown If SRLIM is low, once V reaches or exceeds 0.6V TRACK/SS in Figures 8 and 9. the run state is entered, and the MODE selection, power good and current foldback circuits are enabled. To implement the coincidental tracking waveform in Figure 8, connect an extra resistive divider to the output In the run state, the TRACK/SS pin can be used to track of the master channel and connect its midpoint to the down/up the output voltage of another supply. If the V TRACK/ TRACK/SS pin for the slave channel. The ratio of this again drops below 0.6V, the LTC3615 enters the down- SS divider should be selected the same as that of the slave tracking state and the V is referenced to the TRACK/ OUT channel’s feedback divider (Figure 10). SS voltage. If V reaches 0.1V value the switching TRACK/SS frequency is reduced by 4x to ensure that the minimum In this tracking mode, the master channel’s output must duty cycle limit does not prevent the output from following be set higher than slave channel’s output. To implement the TRACK/SS pin. The run state will resume if the V the ratiometric start-up in Figure 9, no extra divider is TRACK/ again exceeds 0.6V and the V is referenced to the needed; simply connect the TRACK/SS pin to the other SS OUT internal reference. channel’s V pin (Figure 12). FB VOUT1 VOUT1 E E G G A A LT LT O O V V UT VOUT2 UT VOUT2 P P T T U U O O 3615 F08 3615 F09 TIME TIME Figure 8. Coincident Start-Up Tracking Figure 9. Ratiometric Start-Up Tracking VOUT1 VOUT1 R1 VOUT1 R3 R1 LTC3615 R2 LTC3615 R1 LTC3615 FB1 FB1 FB1 R4 R2 R3 R2 TRACK/SS2 TRACK/SS2 TRACK/SS2 VOUT2 VOUT2 VOUT2 R5 R4 R3 FB2 FB2 FB2 R6 R5 R4 3615 F10 3615 F11 3615 F12 Figure 10. Set for Coincidentally Figure 11. Alternative Set-Up for Coincident Figure 12. Set-Up for Tracking (R3 = R5, R4 = R6) Start-Up Tracking (R1 = R3, R2 = R3 = R5) Ratiometric Tracking 3615fb 22 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 applicaTions inForMaTion External Reference Input (DDR Mode) In DDR mode, the maximum slew rate is selected. If V TRACK/ is within 0.3V and 0.5V, the PGOOD function is enabled. If SRLIM is tied to SV , the TRACK/SS pin can be used SS IN If V is less than 0.3V, the output current foldback as an external reference input between 0.3V and 0.5V, if TRACK/SS is disabled and the PGOOD pin is always pulled down. desired (see Figure 13). VFB PIN 0.6V VOLTAGE 0V 0.6V TRACK/SS PIN VOLTAGE 0.1V 0V VIN RUN PIN VOLTAGE 0V VIN SVIN PIN VOLTAGE 0V TIME SHUTDOWN SOFT-START RUN STATE REDUCED RUN STATE STATE STATE SWITCHING 3615 F13 tSS > 1ms FREQUENCY DOWN- UP- TRACKING TRACKING STATE STATE Figure 13. Tracking if V Is Low SRLIM 0.45V VFB PIN 0.3V VOLTAGE 0V EXTERNAL VOLTAGE REFERENCE 0.45V 0.45V TRACK/SS 0.3V PIN VOLTAGE 0.1V 0V VIN RUN PIN VOLTAGE 0V VIN SVIN PIN VOLTAGE 0V TIME SHUTDOWN SOFT-START RUN STATE REDUCED RUN STATE STATE STATE SWITCHING 3615 F14 tSS > 1ms FREQUENCY DOWN- UP- TRACKING TRACKING STATE STATE Figure 14. Tracking if V Is Tied to SV SRLIM IN 3615fb 23 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 applicaTions inForMaTion DDR Application losses, two main sources usually account for most of the losses: V quiescent current and I2R losses. The V IN IN The LTC3615 can be used in DDR memory power supply quiescent current loss dominates the efficiency loss at applications by tying the SRLIM pin to SV . In DDR mode, IN very low load currents whereas the I2R loss dominates the maximum slew rate is selected. The output can both the efficiency loss at medium to high load currents. In a source and sink current. Current sinking is typically limited typical efficiency plot, the efficiency curve at very low load to 1.5A, for 1MHz frequency and 1µH inductance, but can currents can be misleading since the actual power lost is be lower at higher frequencies and low output voltages. of little consequence. If higher ripple current can be tolerated, smaller inductor values can increase the sink current limit. See the Typical 1. The VIN quiescent current is due to two components: the Performance Characteristics curves for more information. DC bias current as given in the Electrical Characteristics In addition, in DDR mode, lower external reference volt- and the internal main switch and synchronous switch ages and tracking output voltages between channels are gate charge currents. The gate charge current results possible. See the Output Voltage Tracking Input section. from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from Single, Low Ripple 6A Output Application high to low to high again, a packet of charge dQ moves from V to ground. The resulting dQ/dt is the current The LT3615 can generate a single, low ripple 6A output if IN out of V due to gate charge, and it is typically larger the outputs of the two switching regulators are tied together IN than the DC bias current. Both the DC bias and gate and share a single output capacitor (see Figure 15 on back charge losses are proportional to V , thus, their effects of data sheet). In order to evenly share the current between IN will be more pronounced at higher supply voltages. the two regulators, it is needed to connect pins FB1 to FB2, ITH1 to ITH2 and to select forced continuous mode 2. I2R losses are calculated from the resistances of the at the MODE pin. To achieve lowest ripple, 90°, or better, internal switches, R , and external inductor R . In SW L 180°, antiphase is selected by connecting the PHASE pin continuous mode the average output current flowing to midrail or SV . There are several advantages to this through inductor L is “chopped” between the main IN 2-phase buck regulator. Ripple currents at the input and switch and the synchronous switch. Thus, the series output are reduced, reducing voltage ripple and allowing resistance looking into the SW pin is a function of both the use of smaller, less expensive capacitors. Although top and bottom MOSFET R and the duty cycle DS(ON) two inductors are required, each will be smaller than the (DC), as follows: inductor required for a single-phase regulator. This may R = (R )(DC) + (R )(1 – DC) SW DS(ON)TOP DS(ON)BOT be important when there are tight height restrictions on the circuit. The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics Efficiency Considerations curves. To obtain I2R losses, simply add R to R and SW L multiply the result by the square of the average output The efficiency of a switching regulator is equal to the output current. power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is Other losses, including C and C ESR dissipative losses IN OUT limiting the efficiency and which change would produce and inductor core losses, generally account for less than the most improvement. Efficiency can be expressed as: 2% of the total loss. Efficiency = 100% – (L1 + L2 + L3 + ...) Thermal Considerations where L1, L2, etc. are the individual losses as a percent- In most applications, the LTC3615 does not dissipate age of input power. much heat due to its high efficiency. However, in ap- plications where the LTC3615 is running at high ambient Although all dissipative elements in the circuit produce 3615fb 24 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 applicaTions inForMaTion temperature with low supply voltage and high duty cycles, Design Example such as in dropout, the heat dissipated may exceed the As a design example, consider using the LTC3615 in an maximum junction temperature of the part. If the junction application with the following specifications: temperature reaches approximately 170°C, all four power switches will be turned off and the SW node will become VIN = 3.3V to 5.5V high impedance. V = 2.5V OUT1 V = 1.2V To prevent the LTC3615 from exceeding the maximum OUT2 I = 1A junction temperature, the user will need to do some ther- OUT1(MAX) I = 3A mal analysis. To determine whether the power dissipated OUT2(MAX) I = 100mA exceeds the maximum junction temperature of the part. OUT(MIN) f = 2.25MHz The temperature rise is given by: Because efficiency is important at both high and low load T = P • θ RISE D JA current, Burst Mode operation will be selected by connect- where PD is the power dissipated by the regulator, and ing the MODE pin to SGND. θ is the thermal resistance from the junction of the die JA First, calculate the timing resistor: to the ambient temperature. The junction temperature, T , is given by: 4E11Ω • Hz J R = =178k RT/SYNC T = T + T 2.25MHz J A RISE where T is the ambient temperature. Next, calculate the inductor values for about 1A ripple A current at maximum V : As an example, consider this case: the LTC3615 is in IN dropout at an input voltage of 3.3V with a load current for ⎛ 2.5V ⎞ ⎛ 2.5V⎞ L1=⎜ ⎟•⎜1– ⎟=0.6µH each channel of 2A at an ambient temperature of 70°C. ⎝2.25MHz•1A⎠ ⎝ 5.5V⎠ Assuming a 20°C rise in junction temperature, to 90°C, results in an R of 0.086mΩ (see the graph in the ⎛ 1.2V ⎞ ⎛ 1.2V⎞ DS(ON) L2=⎜ ⎟•⎜1– ⎟=0.42µH Typical Performance Characteristics section). Therefore, ⎝2.25MHz•1A⎠ ⎝ 5.5V⎠ the power dissipated by the part is: Using a standard value of 0.56µH and 0.47µH inductors P = (I 2 + I 2) • R = 0.69W D 1 2 DS(ON) results in maximum ripple currents of: For the QFN package, the θ is 37°C/W. JA ⎛ 2.5V ⎞ ⎛ 2.5V⎞ Therefore, the junction temperature of the regulator op- ΔIL1= ⎜ ⎟•⎜1– ⎟=1.08A ⎝2.25MHz•0.56µH⎠ ⎝ 5.5V⎠ erating at 70°C ambient temperature is approximately: T = 0.69W • 37°C/W + 70°C = 95°C ⎛ 1.2V ⎞ ⎛ 1.2V⎞ J ΔI = ⎜ ⎟•⎜1– ⎟=0.89A L2 Note that for very low input voltage, the junction tem- ⎝2.25MHz•0.47µH⎠ ⎝ 5.5V⎠ perature will be higher due to increased switch resistance C will be selected based on the ESR that is required to R . It is not recommended to use full load current at OUT DS(ON) satisfy the output voltage ripple requirement and the bulk high ambient temperature and low input voltage. capacitance needed for loop stability. For this design, 47µF To maximize the thermal performance of the LTC3615, ceramic capacitors will be used with X5R or X7R dielectric. the Exposed Pad should be soldered to a ground plane. C should be sized for a maximum current rating of: See the PC Board Layout Checklist. IN I I I = OUT1+ OUT2 =2A RMS(MAX) RMS 2 2 3615fb 25 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 applicaTions inForMaTion Decoupling the PV with two 47µF capacitors is adequate 1. A ground plane is recommended. If a ground plane IN for most applications. layer is not used, the signal and power grounds should be segregated with all small signal components returning Finally, it is possible to define the soft-start up time choos- to the SGND pin at one point which is then connected to ing the proper value for the capacitor and the resistor the PGND node at the exposed pad close to the LTC3615 connected to TRACK/SS pin. If one sets minimum T = SS 5ms and a resistor of 4.7M, the following equation can 2. Connect the (+) terminal of the input capacitors, C , IN be solved with the maximum SV = 5.5V: as close as possible to the PV pins, and the (–) ter- IN INx minal as close as possible to the exposed pad PGND. 5ms C = =9.2nF This capacitor provides the AC current into the internal SS ⎛ 5.5V ⎞ 4.7M•In⎜ ⎟ power MOSFETs. ⎝5.5V–0.6V⎠ 3. Keep the switching nodes, SWx, away from all sensitive The standard value of 10nF and 4.7M guarantees the small signal nodes FBx, ITHx, RTSYNC, SRLIM. minimum soft-start time of 5ms. In Figure 3, channel 1 4. Flood all unused areas on all layers with copper. Flood- shows the schematic for this design example. ing with copper will reduce the temperature rise of power components. Connect the copper areas to PGND PC Board Layout Checklist (exposed pad) for best performance. When laying out the printed circuit board, the following 5. Connect the V pins directly to the feedback resis- FBx checklist should be used to ensure proper operation of tors. The resistor divider must be connected between the LTC3615: V and SGND. OUTx Typical applicaTions DDR Memory Termination VIN 3.3V CIN1 CIN2 CIN3 47µF 47µF 1µF L1 SRVUINN1(2×) PVIN1 (2(2××) )P SVWIN21 0.47µH V1.D8DVQ/3A Ratiometric Start-Up TRACK/SS1 R1 R3 COUT1 PGOOD1 121k 150k 47µF C1 ITH1 FB1 R151k0 10pF RT/SYNC LTC3615 R602.4k R494.9k VDD C2 SRLIM 1000pF MODE L2 500mV/ VTT R9 0.47µH VTT DIV R8 226k (2×) SW2 0.9V 174k PHASE R5 3A/–1.5A 49.9k COUT2 RUN2 47µF FB2 TRACK/SS2 R6 PGOOD2 49.9k 500µs/DIV 3615 TA03b ITH2 SGND PGND C3 R7 10pF 3615 TA03a 15k C4 1000pF 3615fb 26 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 Typical applicaTions External Compensation, Forced Continuous Operation, In-Phase Switching, Slew Rate Limit, Common PGOOD Output VIN 3.3V 47µF 47µF 1µF SVIN (2×) PVIN1 (2×) PVIN2 0.47µH VOUT1 RUN RUN1 (2×) SW1 1.8V/3A TRACK/SS1 R1 47µF 412k PGOOD1 FB1 ITH1 MODE R2 RC1 10pF 1R78Tk LTC3615 205k 43k RT/SYNC CC1 R5 220pF 40.2k SRLIM (2×) SW2 0.47µH VOUT2 2.5V/3A R3 47µF 665k MODE FB2 R6 R7 R4 226k 174k 210k PHASE RUN2 TRACK/SS2 100k PGOOD PGOOD2 ITH2 SGND PGND RC2 10pF 3615 TA02 43k CC2 220pF V Waveform V Waveform OUT1 OUT2 VOUT1 VOUT2 100mV/DIV 100mV/DIV IOUT1 IOUT2 1A/DIV 1A/DIV 3615 TA02b 3615 TA02c 20µs/DIV 20µs/DIV 3615fb 27 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 Typical applicaTions Master and Slave for Coincident Tracking Outputs Using a 2MHz External Clock RF1 24Ω CF1 1µF VIN 3.3V C1 C2 L1 47µF 47µF 4.7M 0.47µH SVIN (2×) PVIN1 (2×) PVIN2 V1.O8UVT/13A RUN1 (2×) SW1 C3 R1 22pF R3 CO11 CO12 TRACK/SS1 715k 453k 47µF 22µF R5 10nF FB1 100k LTC3615-1 R2 R4 C1S5YpNFCPGOOD1 PGOOD1 357k 453k 2MHz RT/SYNC ITH1 CLOCK R20T0k R15Ck1 C10Cp2F SRLIM CC1 MODE L2 1000pF R8 R2296k (2×) SW2 0.47µH V1.O2UVT/23A 174k PHASE R2954k C47Oµ2F1 C22Oµ2F2 C7 RUN2 FB2 22pF R7 TRACK/SS2 R6 100k PGOOD2 294k PGOOD2 ITH2 SGND PGND RC2 C10Cp4F 15k CC3 470pF 3615 TA04a Coincident Start-Up Coincident Tracking Up/Down VOUT1 VOUT2 VOUT1 500mV/ 500mV/ DIV DIV VOUT2 2ms/DIV 3615 TA04b 200ms/DIV 3615 TA04c 3615fb 28 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 package DescripTion FE Package 24-Lead Plastic TSSOP (4.4mm) (Reference LTCF ED WPaGc #k a05g-e08-1771 Rev B) 24-Lead Plastic TSSOP (4.4mm) Exposed Pad Variation AA (Reference LTC DWG # 05-08-1771 Rev B) Exposed Pad Variation AA 7.70 – 7.90* 3.25 (.303 – .311) (.128) 3.25 (.128) 242322 212019181716 151413 6.60 ±0.10 2.74 4.50 ±0.10 (.108) 6.40 SEE NOTE 4 2.74 (.252) (.108) 0.45 ±0.05 BSC 1.05 ±0.10 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 101112 1.20 4.30 – 4.50* (.047) (.169 – .177) 0.25 MAX REF 0° – 8° 0.65 0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15 (.0035 – .0079) (.020 – .030) BSC (.002 – .006) 0.195 – 0.30 (.0077 – .0118) FE24 (AA) TSSOP REV B 0910 TYP NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE MILLIMETERS FOR EXPOSED PAD ATTACHMENT 2. DIMENSIONS ARE IN (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH 3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3615fb 29 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 package DescripTion UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTCU FD WPGa c#k 0a5g-e08-1697 Rev B) 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697 Rev B) 0.70 ±0.05 4.50 ±0.05 2.45 ±0.05 3.10 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.20 TYP OR 4.00 ±0.10 0.75 ±0.05 R = 0.115 0.35 × 45° CHAMFER TYP (4 SIDES) 23 24 PIN 1 0.40 ±0.10 TOP MARK (NOTE 6) 1 2 2.45 ±0.10 (4-SIDES) (UF24) QFN 0105 REV B 0.200 REF 0.25 ±0.05 0.00 – 0.05 0.50 BSC NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3615fb 30 For more information www.linear.com/LTC3615

LTC3615/LTC3615-1 revision hisTory REV DATE DESCRIPTION PAGE NUMBER A 7/10 LTC3615-1 added. Reflected throughout the data sheet. 1 to 32 B 6/13 Clarified temperature maximum ratings. 2 Clarified the Ordering Information section. 2 Clarified the Feedback Voltage specification in the Electrical Characteristics section. 3 Clarified the temperature specifications on Notes 2 and 11. 4 Clarified Typical Performance Characteristics graphs. 7, 8 Clarified paragraphs in the Inductor and Input Capacitor Selection sections. 17 Clarified the maximum junction temperature in the Thermal Considerations section. 25 3615fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 31 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnFecotrio mn oofr iets icnirfcourimts aasti doens cwriwbewd. hlienreeianr .wciollm no/tL iTnCfr3in6g1e 5on existing patent rights.

LTC3615/LTC3615-1 Typical applicaTion VIN 3.3V 47µF 1µF SVIN (2×) (2×) VSW1 RUN1 PVIN1 PVIN2 L1 TRACK/SS1 S(2W×1) 0.47µH 4V17.µO2FUVT/6A 2V/DIV,VSW2 PGOOD1 R1 1A/DIV 102k ITH1 LTC3615 FB1 IL1 20pF RT/SYNC L2 R1022k IL2 0.47µH RC SRLIM (2×) SW2 IL1 + IL2 7.5k 200ns/DIV 3615 F16 CC MODE FB2 MODE = FCM 2000pF R8 R9 226k PHASE Figure 16. Reduced Ripple Current 174k (Waveform I + I ) and Ripple Voltage RUN2 L1 L2 (Not Shown) Through 180° Phase Shift TRACK/SS2 PGOOD2 Between SW1 and SW2 ITH2 SGND PGND 3615 F15 100 VOUT = 1.2V 90 MODE = FCM Figure 15. Single, Low Ripple 6A Output 80 70 %) Y ( 60 C N 50 E CI FI 40 F E 30 20 VIN = 2.5V 10 VIN = 3.3V VIN = 5V 0 0.01 0.1 1 10 OUTPUT CURRENT (A) 3615 F17 Figure 17. Efficiency vs Load Current for V = 1.2V and I Up to 6A OUT OUT relaTeD parTs PART NUMBER DESCRIPTION COMMENTS LTC3633 15V, Dual 3A, 4MHz, Synchronous Step-Down DC/DC 95% Efficiency, V : 3.60V to 15V, V = 0.6V, I = 500µA, I < 13µA, IN OUT(MIN) Q SD Converter 4mm × 5mm QFN-28 and TSSOP-28E Packages LTC3546 5.5V, Dual 3A/1A, 4MHz, Synchronous Step-Down DC/ 95% Efficiency, V : 2.25V to 5.5V, V = 0.6V, I = 160µA, I < 1µA, IN OUT(MIN) Q SD DC Converter 4mm × 5mm QFN-28 Package LTC3417A-2 5.5V, Dual 1.5A/1A, 4MHz, Synchronous Step-Down 95% Efficiency, V : 2.25V to 5.5V, V = 0.8V, I = 125µA, I < 1µA, IN OUT(MIN) Q SD DC/DC Converter TSSOP-16E and 3mm × 5mm DFN-16 Packages LTC3612 5.5V, 3A, 4MHz, Synchronous Step-Down DC/DC 95% Efficiency, V : 2.25V to 5.5V, V = 0.6V, I = 75µA, I < 1µA, IN OUT(MIN) Q SD Converter 3mm × 4mm QFN-20 and TSSOP-20E Packages LTC3614 5.5V, 4A, 4MHz, Synchronous Step-Down DC/DC 95% Efficiency, V : 2.25V to 5.5V, V = 0.6V, I = 75µA, I < 1µA, IN OUT(MIN) Q SD Converter 3mm × 4mm QFN-20 and TSSOP-20E Packages LTC3616 5.5V, 6A, 4MHz, Synchronous Step-Down DC/DC 95% Efficiency, V : 2.25V to 5.5V, V = 0.6V, I = 75µA, I < 1µA, IN OUT(MIN) Q SD Converter 3mm × 5mm QFN-24 Package 3615fb 32 Linear Technology Corporation LT 0613 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC3615 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3615  LINEAR TECHNOLOGY CORPORATION 2010