LTC3026 1.5A Low Input Voltage VLDO Linear Regulator FeaTures DescripTion n Input Voltage Range: The LTC®3026 is a very low dropout (VLDO™) linear regula- 1.14V to 3.5V (with Boost Enabled) tor that can operate at input voltages down to 1.14V. The 1.14V to 5.5V (with External 5V Boost) device is capable of supplying 1.5A of output current with n Low Dropout Voltage: 100mV at I = 1.5A a typical dropout voltage of only 100mV. To allow opera- OUT n Adjustable Output Range: 0.4V to 2.6V tion at low input voltages the LTC3026 includes a boost n Output Current: Up to 1.5A converter that provides the necessary headroom for the n Excellent Supply Rejection Even Near Dropout internal LDO circuitry. n Shutdown Disconnects Load from V and V IN BST Output current comes directly from the input supply to n Low Operating Current: I = 950µA at V = 1.5V IN IN maximize efficiency. The boost converter requires only a n Low Shutdown Current: small chip inductor and ceramic capacitor for operation. I < 1µA (Typ), I = 0.1µA (Typ) IN BST Additionally, the boosted output voltage of one LTC3026 n Stable with 10µF or Greater Ceramic Capacitors can supply the boost voltage for other LTC3026s, thus n Short-Circuit, Reverse Current Protected requiring a single inductor for multiple LDOs. A user sup- n Overtemperature Protected plied boost voltage can be used eliminating the need for n Available in 10-Lead MSOP and 10-Lead an inductor altogether. (3mm × 3mm) DFN Packages The LTC3026 regulator is stable with 10µF or greater applicaTions ceramic output capacitors. The device has a low 0.4V reference voltage which is used to program the output n High Efficiency Linear Regulator voltage via two external resistors. The device also has n Post Regulator for Switching Supplies internal current limit, overtemperature shutdown, and n Microprocessor Supply reverse output current protection. The LTC3026 is avail- L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks able in a small 10-lead MSOP or low profile (0.75mm) and ThinSOT, VLDO are trademarks of Linear Technology Corporation. All other trademarks are 10-lead 3mm × 3mm DFN package. the property of their respective owners. Typical applicaTion 1.2V Output Voltage from 1.5V Input Supply Dropout Voltage vs Output Current 150 L1 SW 10µH 5V BOOST BST CONVERTER 4.7µF VIN = 1.5V IN T (mV) 100 11..25VV 4.7µF 0.4V + OU 2.0V – OUT VOUT = 1.2V, DROP 50 2.6V 1.5A 8.06k OFF ON SHDN ADJ 1C0OµUFT LTC3026 100k 4.02k 00 0.5 1.0 1.5 GND PG IOUT (A) 3026 TA01a 3026 TA01b L1: MURATA LQH2MCN100K02 3026ff 1

LTC3026 absoluTe MaxiMuM raTings (Note 1) V to GND .................................................–0.3V to 6V Output Short-Circuit Duration ..........................Indefinite BST V to GND ...................................................–0.3V to 6V Operating Junction Temperature Range IN PG to GND ...................................................–0.3V to 6V (Note 8) .............................................–40°C to 125°C SHDN to GND ............................................–0.3V to 6.3V Storage Temperature Range ..................–65°C to 125°C ADJ to GND .................................. –0.3V to (V + 0.3V) Lead Temperature (MSE, Soldering, 10 sec) .........300°C IN pin conFiguraTion TOP VIEW TOP VIEW IN 1 10 OUT IN 1 10 OUT IN 2 9 OUT IN 2 9 OUT GND 3 G1N1D 8 ADJ GSNWD 34 G1N1D 87 APDGJ SW 4 7 PG BST 5 6 SHDN BST 5 6 SHDN MSE PACKAGE 10-LEAD PLASTIC MSOP DD PACKAGE 10-LEAD (3mm × 3mm) PLASTIC DFN EXPOSED PAD (PTIJNM A1X1 )= I 1S2 G5N°CD,, θMJAU =S T4 0B°EC S/WOLDERED TO PCB TJMAX = 125°C, θJA = 40°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3026EDD#PBF LTC3026EDD#TRPBF LBHW 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTC3026IDD#PBF LTC3026IDD#TRPBF LBHW 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTC3026EMSE#PBF LTC3026EMSE#TRPBF LTBJB 10-Lead Plastic MSOP –40°C to 125°C LTC3026IMSE#PBF LTC3026IMSE#TRPBF LTBJB 10-Lead Plastic MSOP –40°C to 125°C LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3026EDD LTC3026EDD#TR LBHW 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTC3026IDD LTC3026IDD#TR LBHW 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTC3026EMSE LTC3026EMSE#TR LTBJB 10-Lead Plastic MSOP –40°C to 125°C LTC3026IMSE LTC3026IMSE#TR LTBJB 10-Lead Plastic MSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3026ff 2

LTC3026 elecTrical characTerisTics (BOOST ENABLED, L = 10µH) SW The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at T = 25°C. V = 1.5V, V = 1.2V, C = C = 4.7µF, C = 10µF (all capacitors ceramic) unless otherwise noted. J IN OUT IN BST OUT SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Operating Voltage (Note 2) l 1.14 3.5 V IN I Operating Current I = 0mA, V = 0.8V, V = V , V = 1.2V 1160 µA IN OUT OUT SHDN IN IN I = 0mA, V = 1.2V, V = V , V = 1.5V 950 µA OUT OUT SHDN IN IN I = 0mA, V = 1.2V, V = V , V = 2.5V 640 µA OUT OUT SHDN IN IN I = 0mA, V = 1.2V, V = V , V = 3.5V 400 µA OUT OUT SHDN IN IN I Shutdown Current V = 0V, V = 3.5V l 0.6 20 µA INSHDN SHDN IN Inductor Size Requirement 4.7 10 40 µH Inductor Peak Current Requirement 150 mA V Boost Output Voltage Range V = V 4.8 5 5.2 V BST SHDN IN V Boost Undervoltage Lockout l 4.0 4.2 4.4 V BSTUVLO Boost Output Drive (Note 3) V < 1.4V 7 mA IN V ≥ 1.4V 10 mA IN (BOOST DISABLED, V = 0V or Floating) SW The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at T = 25°C. V = 1.5V, V = 1.2V, V = 5V, C = C = 1µF, C = 10µF (all capacitors ceramic) unless otherwise noted. J IN OUT BST IN BST OUT SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Operating Voltage (Note 2) l 1.14 5.5 V IN I Operating Current I = 100µA, V = V , 1.2V ≤ V ≤ 5V l 95 200 µA IN OUT SHDN IN IN I Shutdown Current V = 0V, V = 3.5V l 0.6 20 µA INSHDN SHDN IN V Boost Operating Voltage (Note 7) V = V l 4.5 5 5.5 V BST SHDN IN V Undervoltage Lockout l 4.0 4.25 4.4 V BSTUVLO I Boost Operating Current I = 100µA, V = V l 175 275 µA BST OUT SHDN IN I Boost Shutdown Current V = 0V 1 5 µA BSTSHDN SHDN (BOOST ENABLED or DISABLED) The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at T = 25°C. V = 1.5V, V = 1.2V, C = C = 1µF, C = 10µF (all capacitors ceramic) unless otherwise noted. J IN OUT IN BST OUT SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Regulation Voltage (Note 5) 1mA ≤ I ≤ 1.5A, 1.14V ≤ V ≤ 3.5V, V = 5V, V = 0.8V 0.397 0.4 0.403 V ADJ OUT IN BST OUT 1mA ≤ I ≤ 1.5A, 1.14V ≤ V ≤ 3.5V, V = 5V, V = 0.8V l 0.395 0.4 0.405 V OUT IN BST OUT OUT Programming Range l 0.4 2.6 V Dropout Voltage (Note 6) V = 1.5V, V = 0.38, I = 1.5A l 100 250 mV IN ADJ OUT I ADJ Input Current V = 0.4V l –100 100 nA ADJ ADJ I Continuous Output Current V = V l 1.5 A OUT SHDN IN I Output Current Current Limit 3 A LIM e Output Voltage Noise f = 10Hz to 100kHz, I = 800mA n L Boost Disabled 110 µV RMS Boost Enabled 210 µV RMS 3026ff 3

LTC3026 elecTrical characTerisTics (BOOST ENABLED or DISABLED) The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at T = 25°C. V = 1.5V, V = 1.2V, C = C = 1µF, C = 10µF (all capacitors ceramic) unless otherwise noted. J IN OUT IN BST OUT SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V SHDN Input High Voltage 1.14V ≤ V ≤ 3.5V l 1.0 V IHSHDN IN 3.5V ≤ V ≤ 5.5V l 1.2 V IN V SHDN Input Low Voltage 1.14V ≤ V ≤ 5.5V l 0.4 V ILSHDN IN I SHDN Input High Current SHDN = V –1 1 µA IHSHDN IN I SHDN Input Low Current SHDN = 0V –1 1 µA ILSHDN V PG Output Low Voltage I = 2mA l 0.1 0.4 V OLPG PG I PG Output High Leakage Current V = 5.5V 0.01 1 µA OHPG PG PG Output Threshold (Note 4) PG High to Low –12 –9 –6 % PG Low to High –10 –7 –4 % Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 6: Dropout voltage is minimum input to output voltage differential may cause permanent damage to the device. Exposure to any Absolute needed to maintain regulation at a specified output current. In dropout, the Maximum Rating condition for extended periods may affect device output voltage will be equal to V – V . IN DROPOUT reliability and lifetime. This IC has overtemperature protection that is Note 7: To maintain correct regulation intended to protect the device during momentary overload conditions. V ≤ V – 2.4V OUT BST Junction temperatures will exceed 125°C when overtemperature is active. Note 8: The LTC3026 is tested under pulsed load conditions such Continuous operation above the specified maximum operating junction that T ≈ T . The LTC3026E is guaranteed to meet specifications from temperature may impair device reliability. J A 0°C to 125°C junction temperature. Specifications over the –40°C to Note 2: Minimum Operating Voltage required for regulation is: 125°C operating junction temperature range are assured by design, V ≥ V + V IN OUT(MIN) DROPOUT characterization and correlation with statistical process controls. The Note 3: When using BST to drive loads other than LTC3026s, the load LTC3026I is guaranteed over the –40°C to 125°C operating junction must be high impedance during start-up (i.e. prior to PG going high). temperature range. Note that the maximum ambient temperature Note 4: PG threshold expressed as a percentage difference from the consistent with these specifications is determined by specific operating “V Regulation Voltage” as given in the table. conditions in conjunction with board layout, the rated package thermal ADJ Note 5: Operating conditions are limited by maximum junction temperature. impedance and other environmental factors. The junction temperature The regulated output voltage specification will not apply for all possible (TJ, in °C) is calculated from the ambient temperature (TA, in °C) and combinations of input voltage and output current. When operating at power dissipation (PD, in watts) according to the formula: maximum input voltage, the output current range must be limited. When TJ = TA + (PD • θJA), where θJA (in °C/W) is the package thermal operating at maximum output current, the input voltage range must be limited. impedance. Typical perForMance characTerisTics IN Supply Current with Boost BST Supply Current with Boost IN Supply Current with Boost Converter Enabled Converter Disabled Converter Disabled 1.50 200 200 1.25 A) 150 150 m1.00 T CURRENT (0.75 I(µA)BST 100 I(µA)IN 100 NPU0.50 VBST = 5V VBST = 5V I 50 –40°C 50 –40°C 0.25 –40°C 25°C 25°C 25°C 85°C 85°C 85°C 125°C 125°C 0 0 0 1.0 1.5 2.0 2.5 3.0 3.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) VIN (V) VIN (V) 3026 G01 3026 G02 3026 G03 3026ff 4

LTC3026 Typical perForMance characTerisTics ADJ Voltage vs Temperature IN Shutdown Current BST Voltage vs Temperature 404 5.0 5.050 VIN = 1.5V 4.5 403 4.0 DJUST VOLTAGE (mV) 444300092109 11.m5AA NPUT CURRENT (µA) 33221.....50505 3.5V BST VOLTAGE (V)55..002050 A 398 I 4.975 1.0 VBST = 5V 397 VIN = 1.5V 0.5 2.5V VOUT =1.2V 1.2V 396 0 4.950 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3026 G04 3026 G05 3026 G06 Dropout Voltage vs Input Voltage Ripple Rejection Ripple Rejection 200 60 70 VFB = 0.38V 180 IOUT =1.5A 10kHz 60 50 160 1MHz 140 dB) dB) 50 V) N ( 40 N ( m 120 O 100kHz O OUT ( 100 JECTI 30 JECTI 40 ROP 80 E RE E RE 30 D 642000 –428055°°°CCC RIPPL 2100 VVIOBOUSUTTT = == 8150.V20VmA RIPPL 2100 VVVIOBIONUSU TT=T = ==1 81.550.V2V0VmA 125°C COUT = 10µF COUT = 10µF 0 0 0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 100 1000 10000 100000 1000000 1E+07 VIN (V) VIN (V) FREQUENCY (Hz) 3026 G07 3026 G08 3026 G09 Shutdown Threshold Output Current Limit BST to OUT Headroom Voltage 1200 5.0 2.22 VOUT = 0V 4.5 TA = 25°C 2.20 RISE 2.18 mV) RFAISLEL 4.0 2.16 THRESHOLD (HDN960000 RFFAAISLLELL I (A)OUT 332...505 CURRENT LIMIT V – V (V)BSTOUT2222....11104208 VS 2.0 2.06 –40°C THERMAL LIMIT 25°C 1.5 2.04 125°C 300 1.0 2.02 1 2 3 4 5 6 1.0 1.5 2.0 2.5 3.0 3.5 –50 –25 0 25 50 75 100 125 VIN (V) VIN (V) TEMPERATURE (°C) 3026 G10 3026 G11 3026 G12 3026ff 5

LTC3026 Typical perForMance characTerisTics Delay from Enable to PG with Delay from Enable to PG with Boost Disabled Boost Enabled Output Load Transient Response 400 5.0 1.5A 4.5 VROUOTU T= =0 .88ΩV IOUT 2mA 375 4.0 –40°C 25°C 3.5 85°C 350 DELAY (µs)325 DELAY (ms) 322...050 AC 20mV/ODUIVT 300 VOUT = 0.8V 1.5 ROUT = 8Ω 1.0 275 –40°C 25°C 0.5 85°C 250 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.0 1.5 2.0 2.5 3.0 3.5 50µs/DIV 3026 G15 VIN (V) 3026 G13 VIN (V) 3026 G14 CVVOOINUU =TT ==1 .117.0V5µVF VBST = 5V BST Ripple and Feedthrough IN Supply Transient Response BST/OUT Start-Up to OUT HI SHDN 2V LO VIN 1.5V 5V VBST AC 20mV/DIV BST 1V 1.5V VOAUCT VOUT AC 5mV/DIV 10mV/DIV OUT 0V ICVOOOUUUTTT = == 8 110.002µmVFA 10µs/DIV 3026 G16 TRVAION U= =T 2 1=5. °71CVΩ 200µs/DIV 3026 G17 VVIOOINUU T=T = =1 1 .15A.V2V 20µs/DIV 3026 G18 VBST = 5V COUT = 10µF TA = 25°C LSW = 10µH TA = 25°C 3026ff 6

LTC3026 pin FuncTions IN (Pins 1, 2): Input Supply Voltage. Output load current has been achieved. When providing an external BST volt- is supplied directly from IN. The IN pin should be locally age (i.e. boost converter disabled) a 1µF low ESR ceramic bypassed to ground if the LTC3026 is more than a few capacitor can be used. inches away from another source of bulk capacitance. SHDN (Pin 6): Shutdown Input Pin, Active Low. This pin In general, the output impedance of a battery rises with is used to put the LTC3026 into shutdown. The SHDN pin frequency, so it is usually advisable to include an input current is typically less than 10nA. The SHDN pin cannot bypass capacitor when supplying IN from a battery. A be left floating and must be tied to a valid logic level (such capacitor in the range of 0.1µF to 4.7µF is usually sufficient. as IN) if not used. GND (Pin 3, Exposed Pad Pin 11): Ground and Heat Sink. PG (Pin 7): Power Good Pin. When PG is high impedance Connect the exposed pad to the PCB ground plane or large OUT is in regulation, and low impedance when OUT is in pad for optimum thermal performance. shutdown or out of regulation. SW (Pin 4): Boost Switching Pin. This is the boost converter ADJ (Pin 8): Output Adjust Pin. This is the input to the error switching pin. A 4.7µH to 40µH inductor able to handle a amplifier. It has a typical bias current of 0.1nA flowing into peak current of 150mA is connected from this pin to V . IN the pin. The ADJ pin reference voltage is 0.4V referenced The boost converter can be disabled by floating this pin. to ground. The output voltage range is 0.4V to 2.6V and is This allows the use of an external boosted supply from typically set by connecting ADJ to a resistor divider from a second LTC3026 or other source. See Operating with OUT to GND. See Figure 2. Boost Converter Disabled section for more information. OUT (Pins 9, 10): Regulated Output Voltage. The OUT pins BST (Pin 5): Boost Output Voltage Pin. With boost con- supply power to the load. A minimum output capacitance verter enabled bypass the BST pin with a ≥4.7µF low ESR of 5µF is required to ensure stability. Larger output capaci- ceramic capacitor to GND (C ). BST does not load V BST IN tors may be required for applications with large transient when in shutdown, but is diode connected to IN through loads to limit peak voltage transients. See the Applica- the external inductor, thus, will not go to ground with V IN tions Information section for more information on output present. Users should not present any loads to the BST capacitance. pin (with boost enabled) until PG signals that regulation 3026ff 7

LTC3026 block DiagraM BOOST CONVERTER SW 4 5 BST – SHDN 6 SWITCHING EN LOGIC + IN SHDN 0.4V + 1,2 REFERENCE UVLO – OUT PG 7 – –VOFF+ – 9,10 + 0.372V + 8 ADJ OVERSHOOT DETECT GND 3,11 3026 BD 3026ff 8

LTC3026 operaTion The LTC3026 is a VLDO (very low dropout) linear regulator Care must be taken not to short the BST pin to GND, since which operates from input voltages as low as 1.14V. The the body diode of the internal PMOS transistor connects LDO uses an internal NMOS transistor as the pass device the BST and SW pins. Shorting BST to GND with an induc- in a source-follower configuration. The BST pin provides tor connected between IN and SW can ramp the inductor the higher supply necessary for the LDO circuitry while the current to destructive levels, potentially destroying the output current comes directly from the IN input for high inductor and/or the part. efficiency regulation. The BST pin can either be supplied off-chip by an external 5V source or it can be generated Operating with Boost Converter Disabled through the internal boost converter of the LTC3026. The LTC3026 has an option to disable the internal boost converter. With the boost converter disabled, the LTC3026 Boost Converter Operation becomes a bootstrapped device and the BST pin must be For applications where an external 5V supply is not avail- driven by an external 5V supply, or driven by the BST pin able, the LTC3026 contains an internal boost converter to of a second LTC3026 with the boost converter enabled. The produce the necessary 5V supply for the LDO. The boost recommended method for disabling the boost converter converter utilizes Burst Mode® operation to achieve high is to simply float the SW pin. With the SW pin floating no efficiency for the relatively low current levels needed for energy can be transferred to BST which effectively disables the LDO circuitry. The boost converter requires only a the boost converter. small chip inductor between the IN and SW pins and a A single LTC3026 boost converter can be used to drive small 4.7µF capacitor at BST. multiple bootstrapped LTC3026s with the internal boost The operation of the boost converter is described as fol- converters disabled. Thus a single inductor can be used lows. During the first half of the switching cycle, an internal to power two (or possibly more) functioning LTC3026s. NMOS switch between SW and GND turns on, ramping In cases where all LTC3026s have the same input supply the inductor current. A peak comparator senses when the (IN) the internal boost converters of the bootstrapped inductor current reaches 100mA, at which point the NMOS LTC3026s can be disabled by floating the SW pin. If the is turned off and an internal PMOS between SW and BST LTC3026s are not all connected to the same input supply turns on, transferring the inductor current to the BST pin. then the internal boost converters of the bootstrapped The PMOS switch continues to deliver power to BST until LTC3026s are disabled by floating the SW pin. the inductor current approaches zero, at which point the PMOS turns off and the NMOS turns back on, repeating LDO Operation the switching cycle. An undervoltage lockout comparator (UVLO) senses the A burst comparator with hysteresis monitors the voltage BST pin voltage to ensure that the bias supply for the LDO on the BST pin. When BST is above the upper threshold is greater than 4.2V before enabling the LDO. If BST is of the comparator, no switching occurs. When BST falls below 4.2V, the UVLO shuts down the LDO, and OUT is below the comparator’s lower threshold, switching com- pulled to GND through the external divider. mences and the BST pin gets charged. The upper and lower thresholds of the burst comparator are set to maintain a 5V supply at BST with approximately 40mV to 50mV of ripple. 3026ff 9

LTC3026 operaTion The LDO provides a high accuracy output capable of HI SHDN supplying 1.5A of output current with a typical dropout LO voltage of only 100mV. A single ceramic capacitor as 1.5V small as 10µF is all that is required for output bypassing. A low reference voltage allows the LTC3026 output to be OUT programmed to much lower voltages than available in common LDOs (range of 0.4V to 2.6V). 0V The devices also include current limit and thermal overload 1.5V protection, and will survive an output short-circuit indefi- PG nitely. The fast transient response of the follower output 0V TA = 25°C 100µs/DIV 3026 F02 stage overcomes the traditional trade-off between dropout ROUT = 1Ω voltage, quiescent current and load transient response VIN = 1.7V VB = 5V inherent in most LDO regulator architectures, see Figure 1. Figure 2. Soft-Start with Boost Disable 1.5A IOUT Adjustable Output Voltage 0mA The output voltage is set by the ratio of two external resis- tors as shown in Figure 3. The device servos the output OUT to maintain the ADJ pin voltage at 0.4V (referenced to AC 20mV/DIV ground). Thus, the current in R1 is equal to 0.4V/R1. For good transient response, stability and accuracy the current in R1 should be at least 80µA, thus, the value of R1 should be no greater than 5k. The current in R2 is the current in R1 plus the ADJ pin bias current. Since the ADJ pin bias VOUT = 1.5V 100µs/DIV 3026 F01 current is typically <10nA it can be ignored in the output COUT = 10µF VIN = 1.7V voltage calculation. The output voltage can be calculated VB = 5V using the formula in Figure 3. Note that in shutdown the Figure 1. Output Load Step Response output is turned off and the divider current will be zero once C is discharged. OUT The LTC3026 also includes a soft-start feature to prevent excessive current flow at V during start-up. When the IN  R2 LDO is enabled, the soft-start circuitry gradually increases VOUT VOUT=0.4V1+R1 the LDO reference voltage from 0V to 0.4V over a period LTC3026 R2 of approximately 200µs, see Figure 2. ADJ COUT R1 GND 3026 F03 Figure 3. Programming the LTC3026 3026ff 10

LTC3026 operaTion The LTC3026 operates at a relatively high gain of The LTC3026 is a micropower device and output transient 270µV/A referred to the ADJ input. Thus, a load current response will be a function of output capacitance. Larger change of 1mA to 1.5A produces a 400µV drop at the ADJ values of output capacitance decrease the peak deviations input. To calculate the change in the output, simply mul- and provide improved transient response for larger load tiply by the gain of the feedback network (i.e. 1 + R2/R1). current changes. Note that bypass capacitors used to For example, to program the output for 1.2V choose decouple individual components powered by the LTC3026 R2/R1 = 2. In this example an output current change of will increase the effective output capacitor value. High 1mA to 1.5A produces –400µV • (1 + 2) = 1.2mV drop at ESR tantalum and electrolytic capacitors may be used, the output. but a low ESR ceramic capacitor must be in parallel at the output. There is no minimum ESR or maximum capacitor Power Good Operation size requirements. The LTC3026 includes an open-drain power good (PG) Extra consideration must be given to the use of ceramic output pin with hysteresis. If the chip is in shutdown or capacitors. Ceramic capacitors are manufactured with a under UVLO conditions (V < 4.25V), PG is low im- variety of dielectrics, each with different behavior across BST pedance to ground. PG becomes high impedance when temperature and applied voltage. The most common di- V rises to 93% of its regulation voltage. PG stays high electrics used are Z5U, Y5V, X5R and X7R. The Z5U and OUT impedance until V falls back down to 91% of its regula- Y5V dielectrics are good for providing high capacitances OUT tion value. A pull-up resistor can be inserted between PG in a small package, but exhibit strong voltage and tem- and a positive logic supply (such as IN, OUT, BST, etc.) perature coefficients as shown in Figures 4 and 5. When to signal a valid power good condition. V should be the used with a 2V regulator, a 10µF Y5V capacitor can exhibit IN minimum operating voltage (1.14V) or greater for PG to an effective value as low as 1µF to 2µF over the operating function correctly. temperature range. The X5R and X7R dielectrics result in more stable characteristics and are more suitable for use Output Capacitance and Transient Response as the output capacitor. The X7R type has better stability across temperature, while the X5R is less expensive and The LTC3026 is designed to be stable with a wide range is available in higher values. of ceramic output capacitors. The ESR of the output capacitor affects stability, most notably with small ca- A minimum capacitance of 5µF must be maintained at all pacitors. An output capacitor of 10µF or greater with an times on the LTC3026 LDO output. ESR of 0.05Ω or less is recommended to ensure stability. 20 20 BOTH CAPACITORS ARE 10µF, 6.3V, 0805 CASE SIZE X5R 0 0 %) X5R %) E (–20 E ( –20 U U L L Y5V A A N V–40 N V –40 E I E I G G N N A–60 A –60 H H C Y5V C –80 –80 BOTH CAPACITORS ARE 10µF, 6.3V, 0805 CASE SIZE –100 –100 0 1 2 3 4 5 6 –50 –25 0 25 50 75 DC BIAS VOLTAGE (V) TEMPERATURE (°C) 3026 F04 3026 F05 Figure 4. Ceramic Capacitor DC Bias Characteristics Figure 5. Ceramic Capacitor Temperature Characteristics 3026ff 11

LTC3026 operaTion Boost Converter Component Selection For surface mount devices, heat sinking is accomplished by using the heat-spreading capabilities of the PC board A 10µH chip inductor with a peak saturation current (I ) SAT and its copper traces. Copper board stiffeners and plated of at least 150mA is recommended for use with the internal through holes can also be used to spread the heat gener- boost converter. The inductor value can range between ated by power devices. 4.7µH to 40µH, but values less than 10µH result in higher switching frequency, increased switching losses, and lower A junction-to-ambient thermal coefficient of 40°C/W is max output current available at the BST pin. See Table 1 achieved by connecting the exposed pad of the MSOP or for a list of component suppliers. DFN package directly to a ground plane of about 2500mm2. Table 1. Inductor Vendor Information Calculating Junction Temperature SUPPLIER PART NUMBER WEBSITE Example: Given an output voltage of 1.2V, an input voltage Coilcraft 0603PS-103KB www.coilcraft.com of 1.8V ±4%, an output current range of 0mA to 1A and Murata LQH2MCN100K02 www.murata.com a maximum ambient temperature of 50°C, what will the Taiyo Yuden LB2016T100M www.t-yuden.com maximum junction temperature be? TDK NLC252018T-100K www.TDK.com The power dissipated by the device will be approximately: It is also recommended that the BST pin be bypassed to I (V – V ) ground with a 4.7µF or greater ceramic capacitor. Larger OUT(MAX) IN(MAX) OUT values of capacitance will not reduce the size of the BST where: ripple much, but will decrease the ripple frequency propor- I = 1A tionally. The BST pin should maintain 1µF of capacitance OUT(MAX) V = 1.87V at all times to ensure correct operation (See the “Output IN(MAX) Capacitance and Transient Response” section about so: capacitor selection). High ESR tantalum and electrolytic P = 1A(1.87V – 1.2V) = 0.67W capacitors may be used, but a low ESR ceramic must be used in parallel for correct operation. Even under worst-case conditions LTC3026’s BST pin power dissipation is only about 1mW, thus can be ignored. Thermal Considerations The junction to ambient thermal resistance will be on the order of 40°C/W. The junction temperature rise above The power handling capability of the device will be limited ambient will be approximately equal to: by the maximum rated junction temperature (125°C). The majority of the power dissipated in the device will be 0.67W(40°C/W) = 26.8°C the output current multiplied by the input/output voltage The maximum junction temperature will then be equal to differential: (I )(V – V ). Note that the BST current OUT IN OUT the maximum junction temperature rise above ambient is less than 200µA even under heavy loads, so its power plus the maximum ambient temperature or: consumption can be ignored for thermal calculations. T = 26.8°C + 50°C = 76.8°C A The LTC3026 has internal thermal limiting designed to protect the device during momentary overload conditions. Short-Circuit/Thermal Protection For continuous normal conditions, the maximum junction The LTC3026 has built-in output short-circuit current temperature rating of 125°C must not be exceeded. It is limiting as well as overtemperature protection. During important to give careful consideration to all sources of short-circuit conditions, internal circuitry automatically thermal resistance from junction to ambient. Additional limits the output current to approximately 3A. At higher heat sources mounted nearby must also be considered. 3026ff 12

LTC3026 operaTion temperatures, or in cases where internal power dissipa- Layout Considerations tion cause excessive self heating on-chip, the thermal Connection from BST and OUT pins to their respec- shutdown circuitry will shut down the boost converter and tive ceramic bypass capacitor should be kept as short LDO when the junction temperature exceeds approximately as possible. The ground side of the bypass capacitors 150°C. It will reenable the converter and LDO once the should be connected directly to the ground plane for best junction temperature drops back to approximately 140°C. results or through short traces back to the GND pin of the The LTC3026 will cycle in and out of thermal shutdown part. Long traces will increase the effective series ESR without latchup or damage until the overstress condition and inductance of the capacitor which can degrade is removed. Long term overstress (T > 125°C) should J performance. be avoided as it can degrade the performance or shorten the life of the part. With the boost converter enabled, the SW pin will be switching between ground and 5V whenever the BST pin Reverse Input Current Protection needs to be recharged. The transition edge rates of the SW pin can be quite fast (~10ns). Thus care must be taken to The LTC3026 features reverse input current protection to make sure the SW node does not couple capacitively to limit current draw from any supplementary power source other nodes (especially the ADJ pin). Additionally, stray at the output. Figure 6 shows the reverse output current capacitance to this node reduces the efficiency and amount limit for constant input and output voltages cases. Note: of current available from the boost converter. For these Positive input current represents current flowing into the reasons it is recommended that the SW pin be connected V pin of LTC3026. IN to the switching inductor with as short a trace as possible. With V held at or below the output regulation voltage If the user has any sensitive nodes near the SW node, a OUT and V varied, IN current flow will follow Figure 6’s curves. ground shield may be placed between the two nodes to IN I reverse current ramps up to about 16µA as the V reduce coupling. IN IN approaches V . Reverse input current will spike up as OUT Because the ADJ pin is relatively high impedance (depend- V approaches within about 30mV of V as the reverse IN OUT ing on the resistor divider used), stray capacitance at this current protection circuitry is disabled and normal opera- pin should be minimized (<10pF) to prevent phase shift tion resumes. As VIN transitions above VOUT the reverse in the error amplifier loop. Additionally special attention current transitions into short-circuit current as long as should be given to any stray capacitances that can couple VOUT is held below the regulation voltage. external signals onto the ADJ pin producing undesirable output ripple. For optimum performance connect the ADJ pin to R1 and R2 with a short PCB trace and minimize all 30 other stray capacitance to the ADJ pin. IN CURRENT 20 LIMIT ABOVE 1.45V A) 10 CIN COUT µ T ( N 1 IN OUT 10 RE 0 UR 2 IN OUT 9 R2 I CIN–10 LSW 3 GND ADJ 8 4 SW PG 7 R1 –20 5 BST SHDN 6 –30 CBST 0 0.3 0.6 0.9 1.2 1.5 1.8 3026 F07 INPUT VOLTAGE (V) VIA CONNECTION TO GND PLANE 3026 F06 Figure 6. Input Current vs Input Voltage Figure 7. Suggested Layout 3026ff 13

LTC3026 Typical applicaTions Using 1 Boost with Multiple Regulators VIN = 2.5V TO ADDITIONAL REGULATORS 10µH SW BST NC SW BST LTC3026 4.7µF LTC3026 1µF IN OUT VOUT1 IN OUT VOUT2 1.8V, 1.5A 1.5V, 1.5A 14k 11k SHDN ADJ 1C0OµUFT1 SHDN ADJ C10OµUFT2 4.7µF 100k 4.02k 1µF 100k 4.02k GND PG PG1 GND PG PG2 LTC3026 WITH BOOST ENABLED FANOUT: BOOT STRAPPED LTC3026 3-LTC3026 FOR VIN <1.4V (BOOST DISABLED) 5-LTC3026 FOR VIN >1.4V 3026 TA02 2.5V Output from 3.3V Supply with External 5V Bias VBIAS = 5V N/C SW* BST LTC3026 1µF VIN = 3.3V IN OUT VOUT 2.5V, 1.5A 21k SHDN ADJ 1C0OµUFT 1µF 100k 4.02k GND PG PG 3026 TA03 *SEE OPERATING WITH BOOST CONVERTER DISABLED SECTION FOR INFORMATION ON DISABLING BOOST CONVERTER. 3026ff 14

LTC3026 package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MSE Package 10-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1664 Rev H) BOTTOM VIEW OF EXPOSED PAD OPTION 1.88 1.88 ±0.102 (.074 ±.004) 0.889 ±0.127 1 (.074) 0.29 (.035 ±.005) 1.68 REF (.066) 5.23 0.05 REF 1.68 ±0.102 3.20 – 3.45 (.206) DETAIL “B” (.066 ±.004) (.126 – .136) MIN CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY 10 NO MEASUREMENT PURPOSE 0.50 0.305 ± 0.038 (.0197) 3.00 ±0.102 (.0120 ±.0015) BSC (.118 ±.004) 0.497 ±0.076 TYP (NOTE 3) (.0196 ±.003) RECOMMENDED SOLDER PAD LAYOUT 10 9 8 76 REF 3.00 ±0.102 4.90 ±0.152 (.118 ±.004) (.193 ±.006) (NOTE 4) DETAIL “A” 0.254 (.010) 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.53 ±0.152 1.10 0.86 (.021 ±.006) (.043) (.034) MAX REF DETAIL “A” 0.18 (.007) SEATING PLANE 0.17 – 0.27 0.1016 ±0.0508 (.007 – .011) (.004 ±.002) 0.50 TYP (.0197) MSOP (MSE) 0911 REV H NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 3026ff 15

LTC3026 package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DD Package 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699 Rev C) 0.70 ±0.05 3.55 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.125 0.40 ±0.10 TYP 6 10 3.00 ±0.10 1.65 ±0.10 (4 SIDES) (2 SIDES) PIN 1 NOTCH PIN 1 R = 0.20 OR TOP MARK 0.35 × 45° (SEE NOTE 6) CHAMFER (DD) DFN REV C 0310 5 1 0.200 REF 0.75 ±0.05 0.25 ±0.05 0.50 BSC 2.38 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3026ff 16

LTC3026 revision hisTory (Revision history begins at Rev D) REV DATE DESCRIPTION PAGE NUMBER D 3/10 Addition to Absolute Maximum Ratings 1 Changes to Electrical Characteristics 3, 4 Changes to Pin Functions 7, Changes to Operation Section 9 Changes to Typical Applications 14, 18 Additions to Related Parts 18 E 5/11 Remove I-grade in Note 8. 4 F 8/12 Added I-grade ordering information 2 Updated I-grade testing assurances, Note 8 4 Modified boost converter disablement methodology 7, 9 Modified Boost with Multiple Regulators schematic and deleted note 14 3026ff Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 17 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC3026 Typical applicaTion Efficient, Low Noise 1.5V Output from 1.8V DC/DC Buck Converter (LTC3026 Boost Converter Disabled) 4.5V ≤ VIN ≤ 5.5V 33pF 200pF 30k 1 10 ITH SW RSENSE 0.1µF LTC1773 0.04Ω 2 RUN/SS SENSE– 9 3 SYNC/FCB VIN 8 VBUCK 1µF 1.8V N/C SW BST L1 2A 4 VFB TG 7 2.5µH LTC3026 VOUT IN OUT 1.5V CIN 5 6 11k 1.5A 4170µVF GND BG SHDN ADJ 1C0OµUFT Si9942DY 1µF 100k 4.02k 80.6k 100k 4C7BµUFCK GND PG PG 1% 1% 10V 3026 TA04 CIN, CBUCK: TAIYO YUDEN LMK550BJ476MM L1: CDRH5D28 RSENSE: IRC LR1206-01-R040-F relaTeD parTs PART NUMBER DESCRIPTION COMMENTS LT1761 100mA, Low Noise LDO in ThinSOT™ 300mV Dropout Voltage, Low Noise: 20µV , V = 1.8V to 20V, ThinSOT Package RMS IN LT1762 150mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20µV , V = 1.8V to 20V, MS8 Package RMS IN LT1763 500mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20µV , V = 1.8V to 20V, SO-8 Package RMS IN LT1764A 3A, Fast Transient Response, Low Noise LDO 340mV Dropout Voltage, Low Noise: 40µV , V = 2.7V to 20V, RMS IN TO-220 and DD Packages LT1844 150mA, Very Low Dropout LDO 80mV Dropout Voltage, Low Noise <30µV , V = 1.6V to 6.5V, RMS IN Stable with 1µF Output Capacitors, ThinSOT Package LT1962 300mA, Low Noise LDO 270mV Dropout Voltage, Low Noise 20µV , V = 1.8V to 20V, MS8 Package RMS IN LT1963A 1.5A Low Noise, Fast Transient Response LDO 340mV Dropout Voltage, Low Noise: 40µV , V = 2.5V to 20V, RMS IN TO-220, DD, SOT-223 and SO-8 Packages LT1964 200mA, Low Noise, Negative LDO 340mV Dropout Voltage, Low Noise 30µV , V = –1.8V to –20V, RMS IN ThinSOT Package LT1965 1.1A, Low Noise, Low Dropout Linear 290mV Dropout Voltage, Low Noise 40µV , V = 1.8V to 20V, TO-220, DDPak, RMS IN Regulator MSOP and 3mm × 3mm DFN Packages LTC3025 300mA Micropower VLDO Linear Regulator 45mV Dropout Voltage, Low Noise 80µV , V = 0.9V to 5.5V, RMS IN Low IQ: 54µA, 2mm × 2mm 6-Lead DFN Package LT3080/LT3080-1 1.1A, Parallelable, Low Noise, Low Dropout 300mV Dropout Voltage (2 Supply), Low Noise 40µV , V = 1.2V to 36V, RMS IN Linear Regulator V = 0V to 35.7V, Directly Parallelable, TO-220, SOT-223, MSOP-8 and OUT 3mm × 3mm DFN Packages LT3150 Fast Transient Response, VLDO Regulator 0.035mV Dropout Voltage via External FET, V = 1.3V to 10V IN Controller 3026ff 18 Linear Technology Corporation LT 0812 REV F • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2005

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: LTC3026EMSE#PBF LTC3026EMSE#TRPBF LTC3026IMSE#TRPBF LTC3026EMSE#TR LTC3026IDD#PBF LTC3026EMSE LTC3026EDD LTC3026IDD#TRPBF LTC3026IMSE#PBF LTC3026EDD#TR LTC3026EDD#PBF LTC3026IDD#TR LTC3026IDD LTC3026EDD#TRPBF