LTC2919 Precision Triple/Dual Input UV, OV and Negative Voltage Monitor FEATURES DESCRIPTIOU ■ Two Low Voltage Adjustable Inputs (0.5V) The LTC®2919 is a triple/dual input monitor intended for a ■ Accurate UVLO Provides a Third Monitor Input variety of system monitoring applications. Polarity selec- ■ Open-Drain RST, OUT1 and OUT2 Outputs tion and a buffered reference output allow the LTC2919 to ■ Pin Selectable Input Polarity Allows Negative, UV monitor positive and negative supplies for undervoltage and OV Monitoring (UV) and overvoltage (OV) conditions. ■ Guaranteed Threshold Accuracy: ±1.5% The two adjustable inputs have a nominal 0.5V threshold, ■ 6.5V Shunt Regulator for High Voltage Operation featuring tight 1.5% threshold accuracy over the entire ■ Low 50μA Quiescent Current operating temperature range. Glitch fi ltering ensures out- ■ Buffered 1V Reference for Negative Supply Offset puts operate reliably without false triggering. An accurate ■ Input Glitch Rejection threshold at the V pin provides a third input supply CC ■ Adjustable Reset Timeout Period monitor for a 2.5V, 3.3V or 5V supply. ■ Selectable Internal Timeout Saves Components ■ Outputs Guaranteed Low With V = 0.5V Two independent output pins indicate the status of each CC ■ Space Saving 10-Lead 3mm × 2mm DFN and MSOP adjustable input. A third common output provides a Packages confi gurable reset timeout that may be set by an accu- rate internal 200ms timer, programmed with an external APPLICATIOUS capacitor, or disabled for a fast response. A three-state input pin sets the input polarity of each adjustable input ■ Desktop and Notebook Computers without requiring any external components. ■ Network Servers The LTC2919 provides a highly versatile, precise, space- ■ Core, I/O Monitor conscious, micropower solution for supply monitoring. ■ Automotive , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6949965, 7292076. TYPICAL APPLICATIOU 3.3V UV/OV (Window) Monitor Application with 200ms Internal Timeout (3.3V Logic Out) SEL Pin Connection for Input Polarity Combinations 3.3V POLARITY 0.1μF 453k VCC LTC2919–2.5 10k ADJ1 ADJ2 SEL PIN ADJ1 OUT1 10k 10.7k REF OUT2 UV 10k + + VCC OV FAULT ADJ2 RST + – OPEN SEL TMR 76.8k – – GND GND 2919 TA01a 2919f 1

LTC2919 ABSOLUTE WAXIWUW RATIUGS (Notes 1, 2) Terminal Voltages Operating Temperature Range V (Note 3) .............................................–0.3V to 6V LTC2919C ................................................0°C to 70°C CC OUT1, OUT2, RST .................................–0.3V to 7.5V LTC2919I..............................................– 40°C to 85°C ADJ1, ADJ2 ..........................................–0.3V to 7.5V LTC2919H ..........................................–40°C to 125°C TMR, SEL ..................................–0.3V to (V + 0.3V) Maximum Junction Temperature...........................150°C CC Terminal Currents Storage Temperature Range ...................– 65°C to 150°C I (Note 3) ......................................................±10mA Lead Temperature (Soldering, 10 sec) CC I ....................................................................±1mA MSOP-10 ..........................................................300°C REF PIN CONFIGURATION TOP VIEW SEL 1 10 ADJ1 TOP VIEW VCC 2 9 ADJ2 SEL 1 10 ADJ1 OUT1 3 11 8 TMR VCC 2 9 ADJ2 OUT1 3 8 TMR OUT2 4 7 REF OUT2 4 7 REF RST 5 6 GND RST 5 6 GND MS PACKAGE DDB PACKAGE 10-LEAD PLASTIC MSOP 10-LEAD (3mm × 2mm) PLASTIC DFN TJMAX = 150°C, θJA = 120°C/W TJMAX = 150°C, θJA = 76°C/W EXPOSED PAD (PIN 11) MAY BE LEFT OPEN OR TIED TO GND ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2919CDDB-2.5#PBF LTC2919CDDB-2.5#TRPBF LDGT 10-Lead (3mm × 2mm) Plastic DFN 0°C to 70°C LTC2919IDDB-2.5#PBF LTC2919IDDB-2.5#TRPBF LDGT 10-Lead (3mm × 2mm) Plastic DFN –40°C to 85°C LTC2919HDDB-2.5#PBF LTC2919HDDB-2.5#TRPBF LDGT 10-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C LTC2919CDDB-3.3#PBF LTC2919CDDB-3.3#TRPBF LDMW 10-Lead (3mm × 2mm) Plastic DFN 0°C to 70°C LTC2919IDDB-3.3#PBF LTC2919IDDB-3.3#TRPBF LDMW 10-Lead (3mm × 2mm) Plastic DFN –40°C to 85°C LTC2919HDDB-3.3#PBF LTC2919HDDB-3.3#TRPBF LDMW 10-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C LTC2919CDDB-5#PBF LTC2919CDDB-5#TRPBF LDMX 10-Lead (3mm × 2mm) Plastic DFN 0°C to 70°C LTC2919IDDB-5#PBF LTC2919IDDB-5#TRPBF LDMX 10-Lead (3mm × 2mm) Plastic DFN –40°C to 85°C LTC2919HDDB-5#PBF LTC2919HDDB-5#TRPBF LDMX 10-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C LTC2919CMS-2.5#PBF LTC2919CMS-2.5#TRPBF LTDGS 10-Lead Plastic MSOP 0°C to 70°C LTC2919IMS-2.5#PBF LTC2919IMS-2.5#TRPBF LTDGS 10-Lead Plastic MSOP –40°C to 85°C LTC2919HMS-2.5#PBF LTC2919HMS-2.5#TRPBF LTDGS 10-Lead Plastic MSOP –40°C to 125°C LTC2919CMS-3.3#PBF LTC2919CMS-3.3#TRPBF LTDMT 10-Lead Plastic MSOP 0°C to 70°C LTC2919IMS-3.3#PBF LTC2919IMS-3.3#TRPBF LTDMT 10-Lead Plastic MSOP –40°C to 85°C LTC2919HMS-3.3#PBF LTC2919HMS-3.3#TRPBF LTDMT 10-Lead Plastic MSOP –40°C to 125°C LTC2919CMS-5#PBF LTC2919CMS-5#TRPBF LTDMV 10-Lead Plastic MSOP 0°C to 70°C LTC2919IMS-5#PBF LTC2919IMS-5#TRPBF LTDMV 10-Lead Plastic MSOP –40°C to 85°C LTC2919HMS-5#PBF LTC2919HMS-5#TRPBF LTDMV 10-Lead Plastic MSOP –40°C to 125°C Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *Temperature grades are identifi ed by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based fi nish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/ 2919f 2

LTC2919 ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = 2.5V (LTC2919-2.5), V = 3.3V (LTC2919-3.3), V = 5V A CC CC CC (LTC2919-5), ADJ1 = ADJ2 = 0.55V, SEL = fl oating, unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Operating Supply Voltage RST, OUT1, OUT2 in Correct State ● 0.5 V CC(MIN) V V Shunt Regulation Voltage I = 1mA, I = 0 ● 6.0 6.5 7.1 V CC(SHUNT) CC CC REF I V Input Current 2.175V < V < 6V (C-Grade, I-Grade) ● 50 220 μA CC CC CC 2.175V < VCC < 6V (H-Grade) ● 50 280 μA V ADJ Input Threshold 495.0 500 505.0 mV RT ● 492.5 500 507.5 mV ΔVRT ADJ Hysteresis (Note 4) TMR = VCC 1.5 3.5 10.0 mV I ADJ Input Current V = 0.55V (C-Grade, I-Grade) ● 0 ±15 nA ADJ ADJ VADJ = 0.55V (H-Grade) ● 0 ±40 nA V V –10% UVLO Threshold LTC2919-2.5 ● 2.175 2.213 2.250 V CC(UVLO) CC LTC2919-3.3 ● 2.871 2.921 2.970 V LTC2919-5 ● 4.350 4.425 4.500 V ΔVCC(UVLO) UVLO Hysteresis (Note 4) TMR = VCC 0.3 0.7 2.0 % V Buffered Reference Voltage V > 2.175V, I = ±1mA 0.990 1.000 1.010 V REF CC REF ● 0.985 1.000 1.015 V I TMR Pull-Up Current V = 1V ● –1.5 –2.2 –2.9 μA TMR(UP) TMR I TMR Pull-Down Current V = 1V ● 1.5 2.2 2.9 μA TMR(DOWN) TMR t Reset Timeout Period, External C = 2.2nF ● 15 20 27 ms RST(EXT) TMR t Reset Timeout Period, Internal V = 0V ● 140 200 280 ms RST(INT) TMR V Timer Disable Voltage V Rising ● V V V V TMR(DIS) TMR CC CC CC – 0.40 – 0.20 – 0.10 ΔVTMR(DIS) Timer Disable Hysteresis VTMR Falling ● 40 100 160 mV V Timer Internal Mode Voltage V Falling ● 0.10 0.20 0.40 V TMR(INT) TMR ΔVTMR(INT) Timer Internal Mode Hysteresis VTMR Rising ● 40 100 160 mV t ADJx Comparator Propagation Delay to ADJx Driven Beyond Threshold (V ) by ● 50 150 800 μs PROP RTX OUT 5mV X t V Undervoltage Detect to RST V Less Than UVLO Threshold ● 50 150 800 μs UV CC CC (V ) by 1% CC(UVLO) V Output Voltage Low V = 0.5V, I = 5μA ● 0 0.01 0.15 V OL CC VCC = 1V, I = 100μA ● 0 0.01 0.15 V VCC = 3V, I = 2500μA ● 0 0.10 0.30 V I Output Voltage High Leakage Output = V (C-Grade, I-Grade) ● 0 ±1 μA OH CC Output = VCC (H-Grade) ● 0 ±5 μA Three-State Input SEL V Low Level Input Voltage ● 0 0.4 V IL V High Level Input Voltage ● 1.4 V V IH CC V Pin Voltage when Left in Open State I = 0μA 0.8 0.9 1.0 V Z SEL 2919f 3

LTC2919 ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = 2.5V (LTC2919-2.5), V = 3.3V (LTC2919-3.3), V = 5V A CC CC CC (LTC2919-5), ADJ1 = ADJ2 = 0.55V, SEL = fl oating, unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I Allowable Leakage When Open ● ±5 μA SEL(Z) I SEL Input Current SEL = V or SEL = GND ● ±17 ±25 μA SEL CC Note 1: Stresses beyond those listed under Absolute Maximum Ratings which exceeds 6V may exceed the rated terminal current. Operation may cause permanent damage to the device. Exposure to any Absolute from higher voltage supplies requires a series dropping resistor. See Maximum Rating condition for extended periods may affect device Applications Information. reliability and lifetime. Note 4: Threshold voltages have no hysteresis unless the part is in Note 2: All currents into pins are positive; all voltages are referenced to comparator mode. Hysteresis is one-sided, affecting only invalid-to-valid GND unless otherwise noted. transitions. See Applications Information. Note 3: V maximum pin voltage is limited by input current. Since the CC V pin has an internal 6.5V shunt regulator, a low impedance supply CC TYPICAL PERFORW AU CE CHARACTERISTICS T = 25°C unless otherwise noted. A ADJ Threshold Voltage V UVLO Threshold Variation REF Output Voltage CC vs Temperature vs Temperature vs Temperature E) 508 LU 1.5 1.015 VA IREF = 0A C V) 506 25° 1.0 1.010 m F ESHOLD VOLTAGE, V (RT455549000960428 OLTAGE VARIATION (% O–00..505 REF VOLTAGE, V (V)REF011...900900505 R V TH 494 OLD –1.0 0.990 H S 492 RE–1.5 0.985 –50 –25 0 25 50 75 100 125 150 TH –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 2919 G01 2919 G02 2919 G03 E) Quiescent Supply Current VALUE) 0.6 REF Output Load Regulation C VALU 0.6 REF Output Line Regulation 90vs Temperature AD AND 25°C 0.4 VCC = 2.5V TA = 150°C PPLY AND 25° 0.4 IREF = 0A TA = 150°C NT, I (μA)CC 8700 AASDDELJJ 12= ==O 00P..E54N55VV O 0.2 U 0.2 E GE, VARIATION (%OF NO L ––000...420 TA = 125°C TAT A= =2 5–°4C0°C E VARIATION (% OF 2.5V S ––000...420 TA = 125°C TTAA = = – 2450°°CC QUIESCENT SUPPLY CURR 43650000 VCC = 5VVCC = 2.5VVCC = 3.3V A G OLT –0.6 LTA –0.6 20 REF V –1 –0.L5OAD CUR0RENT (mA)0.5 1 EF VO 2 3SUPPLY VO4LTAGE (V)5 6 –50 –25 0 TEM25PERA5T0URE7 5(°C)100 125 150 R 2919 G04 2919 G05 2919 G06 2919f 4

LTC2919 TYPICAL PERFORW AU CE CHARACTERISTICS T = 25°C unless otherwise noted. A Reset Timeout Period Reset Timeout Period Propagation Delay vs Overdrive vs Capacitance vs Temperature 700 10000 260 600 ms) ms) 240 PAGATION DELAY (μs) 345000000 MEOUT PERIOD, t (RST1100000 MEOUT PERIOD, t (RST122802000 EXTERNAL,I NCTTEMRRN =A 2L2nF PRO 200 ET TI 10 ET TI 100 RES RES 160 0 1 140 0.1 1 10 100 0.1 1 10 100 1000 –50 –25 0 25 50 75 100 125 150 GLITCH PERCENTAGE PAST THRESHOLD (%) TMR PIN CAPACITANCE, CTMR (nF) TEMPERATURE (°C) 2919 G07 2919 G08 2919 G09 Shunt Regulation Voltage Shunt Regulation Voltage OUT1, OUT2, RST Output Voltage vs Temperature vs Supply Current vs V CC (V)NT)7.0 (V)NT) 7.6 TA = 25°C 5 AADDJJ12 == 00..5455VV SHUNT REGULATOR VOLTAGE, VCC(SHU66666.....04286 ICC = I1C0Cm =A 100ICμCA = 1mA SHUNT REGULATION VOLTAGE, VCC(SHU 6766....4280 OUTPUT VOLTAGE (V) 14203 S10EkL P=U OLLLTPTLCCE-2UN299P11 9R9-- 32T..3O5 VCC LTC2919-5 –50 –25 0 25 50 75 100 125 150 0.01 0.1 1 10 100 0 1 2 3 4 5 TEMPERATURE (°C) SUPPLY CURRENT, ICC (mA) SUPPLY VOLTAGE, VCC (V) 2919 G10 2919 G11 2919 G12 OUT1, OUT2, RST Output Voltage OUT1, OUT2, RST Pull-Down OUT1, OUT2, RST Pull-Down vs V Current vs V Current vs V CC CC CC 0.4 6 1 ADJ1 = 0.45V OLTAGE (V) 00..32 VCC WN CURRENT (mA) 345 ASDELJ 2= =O 0P.E5N5V OUTPUT AT 150mV WN CURRENT (mA) 0.00.11 OUTPUT AT 150mOVUTPUT AT 50mV OUTPUT V 0.1 WITH 100k PUWLILT-HU P10k PULL-UP OUTPUT PULL-DO 12 OUTPUT AT 50mV OUTPUT PULL-DO0.001 0 0 0.0001 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 1 2 3 4 5 0 0.2 0.4 0.6 0.8 1 SUPPLY VOLTAGE, VCC (V) SUPPLY VOLTAGE, VCC (V) SUPPLY VOLTAGE, VCC (V) 2919G13 2919 G14 2919 G15 2919f 5

LTC2919 TYPICAL PERFORW AU CE CHARACTERISTICS T = 25°C unless otherwise noted. A OUT1, OUT2, RST V vs Output OL Sink Current I vs Temperature I vs Temperature SEL SEL 1.0 –10 22 VCC = 3V SEL = GND SEL = VCC NO PULL-UP R –12 20 0.8 TA = 150°C V) –14 18 V (OL 0.6 TA = 125°C TA = 25°C μA) μA) TPUT, 0.4 I (SEL–16 I (SEL 16 U O TA = –40°C –18 14 0.2 –20 12 0 –22 10 0 5 10 15 20 25 30 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 OUTPUT SINK CURRENT (mA) TEMPERATURE (°C) TEMPERATURE (°C) 2919 G16 2919 G17 2919 G18 PIU FUUCTIOUS (MSOP/DFN Package) SEL (Pin 1): Input Polarity Select Three-State Input. Con- Requires an external pull-up resistor and may be pulled nect to V , GND or leave unconnected in open state to above V . CC CC select one of three possible input polarity combinations GND (Pin 6): Device Ground. (refer to Table 1). REF (Pin 7): Buffered Reference Output. 1V nominal V (Pin 2): Power Supply. Bypass this pin to ground with CC reference used for the offset of negative-monitoring ap- a 0.1μF (or greater) capacitor. Operates as a direct supply plications. The buffered reference can source and sink input for voltages up to 6V. Operates as a shunt regulator up to 1mA. The reference can drive a capacitive load of for supply voltages greater than 6V and should have a up to 1000pF. Larger capacitance may degrade transient resistor between this pin and the supply to limit V input CC performance. This pin does not require a bypass capacitor, current to no greater than 10mA. When used without a nor is one recommended. Leave open if unused. current-limiting resistor, pin voltage must not exceed 6V. UVLO options allow V to be used as an accurate third TMR (Pin 8): Reset Timeout Control. Attach an external CC fi xed -10% UV supply monitor. capacitor (CTMR) to GND to set a reset timeout period of 9ms/nF. A low leakage ceramic capacitor is recom- OUT1 (Pin 3): Open-Drain Logic Output 1. Asserts low mended for timer accuracy. Capacitors larger than 1μF when positive polarity ADJ1 voltage is below threshold or (9 second timeout) are not recommended. See Applica- negative polarity ADJ1 voltage is above threshold. Requires tions Information for further details. Leaving this pin open an external pull-up resistor and may be pulled above V . CC generates a minimum timeout of approximately 400μs. A OUT2 (Pin 4): Open-Drain Logic Output 2. Asserts low 2.2nF capacitor will generate a 20ms timeout. Tying this when positive polarity ADJ2 voltage is below threshold pin to ground will enable the internal 200ms timeout. Ty- or negative polarity ADJ2 voltage is above threshold. ing this pin to V will disable the reset timer and put the CC Requires an external pull-up resistor and may be pulled part in comparator mode. Signals from the comparator above V . outputs will then go directly to RST. CC RST (Pin 5): Open-Drain Inverted Reset Logic Output. ADJ2 (Pin 9): Adjustable Voltage Input 2. Input to volt- Asserts low when any positive polarity input voltage is age monitor comparator 2 (0.5V nominal threshold). The below threshold or any negative polarity input voltage is polarity of the input is selected by the state of the SEL above threshold or V is below UVLO threshold. Held pin (refer to Table 1). Tie to GND if unused (with SEL = CC low for a timeout period after all voltage inputs are valid. GND or Open). 2919f 6

LTC2919 PIU FUUCTIOUS (MSOP/DFN Package) ADJ1 (Pin 10): Adjustable Voltage Input 1. Input to volt- Exposed Pad (Pin 11, DFN Only): The Exposed Pad may age monitor comparator 1 (0.5V nominal threshold). The be left unconnected. For better thermal contact, tie to a PCB polarity of the input is selected by the state of the SEL trace. This trace must be grounded or unconnected. pin (refer to Table 1). Tie to REF if unused (with SEL = V or Open). CC BLOCK DIAGRAW SEL VCC VCC THREE-STATE DECODE 6.5V OUT1 CONTROL 2 CONTROL 1 ADJ1 + – TMR VCC THREE-STATE DECODE ADJUSTABLE PULSE RST + GENERATOR EN – 200ms GND PULSE GENERATOR ADJ2 + OUT2 – SEL CONTROL 1 CONTROL 2 +– 500mV GND H H + OPEN L H REF +– 1.000V VCC L L – CONTROL = H = NEGATIVE POLARITY CONTROL = L = POSITIVE POLARITY 2919 BD TIW IU G DIAGRAW S Positive Polarity Input Timing VADJ VRT VRT+ΔVRT tPROP tRST RST 1V tPROP tPROP OUT 1V Negative Polarity Input Timing VADJ VRT VRT–ΔVRT tPROP tRST RST 1V tPROP tPROP OUT 1V UVLO Timing VCC VCC(UVLO) VCC(UVLO)+ΔVCC(UVLO) tUV tRST RST 1V N1.OΔTVERST: AND ΔVCC(UVLO) = 0, except in tPROP tPROP Comparator Mode OUT 1V 2. IN COMPARATOR MODE, tRST = tPROP. 2919 TD 2919f 7

LTC2919 APPLICATIOUS IUFORWATIOU The LTC2919 is a low power, high accuracy triple/dual Shunt Regulator supply monitor with two adjustable inputs and an accurate The LTC2919 contains an internal 6.5V shunt regulator on UVLO that can monitor a third supply. Reset timeout may the V pin to allow operation from a high voltage supply. CC be selected with an external capacitor, set to an internally To operate the part from a supply higher than 6V, the V CC generated 200ms, or disabled entirely. pin must have a current-limiting series resistor, R , to CC The three-state polarity select pin (SEL) chooses one of the supply. This resistor should be sized according to the three possible polarity combinations for the adjustable following equation: input thresholds, as described in Table 1. An individual V –6.2V V –6.8V S(MAX) S(MIN) output is released when its corresponding ADJ input is ≤R ≤ CC valid (above threshold if confi gured for positive polarity, 10mA 200µA+IREF below threshold if confi gured for negative polarity). where V and V are the operating minimum and S(MIN) S(MAX) Both input voltages (VADJ1 and VADJ2) must be valid and maximum of the supply, and IREF is the maximum current VCC above the UVLO threshold for longer than the reset the user expects to draw from the reference output. timeout period before RST is released. The LTC2919 as- As an example, consider operation from an automobile bat- serts the reset output during power-up, power-down and tery which might dip as low as 10V or spike to 60V. Assume brownout conditions on any of the voltage inputs. that the user will be drawing 100μA from the reference. We must then pick a resistance between 5.4k and 10.7k. Power-Up When the V pin is connected to a low impedance supply, The LTC2919 uses proprietary low voltage drive circuitry CC it is important that the supply voltage never exceed 6V, for the RST, OUT1 and OUT2 pins which holds them low or the shunt regulator may begin to draw large currents. with V as low as 200mV. This helps prevent indeter- CC Some supplies may have a nominal value suffi ciently minate voltages from appearing on the outputs during close to the shunt regulation voltage to prevent sizing of power-up. the resistor according to the above equation. For such In applications where the low voltage pull-down capabil- supplies, a 470Ω series resistor may be used. ity is important, the supply to which the external pull-up resistor connects should be the same supply which pow- Adjust Polarity Selection ers the part. Using the same supply for both ensures that The external connection of the SEL pin selects the polarities RST, OUT1 and OUT2 never fl oat above 200mV during of the LTC2919 adjustable inputs. SEL may be connected power-up, as the pull-down ability of the pin will then to GND, connected to V or left unconnected during CC increase as the required pull-down current to maintain a normal operation. When left unconnected, the maximum logic low increases. leakage allowable from the pin is ±5μA. Table 1 shows Once V passes the UVLO threshold, polarity selection and the three possible selections of polarity based on SEL CC timer initialization will occur. If the monitored ADJ input is connection. valid, the corresponding OUT will be released. When both Table 1. Voltage Threshold Selection ADJ1 and ADJ2 are valid, the appropriate timeout delay ADJ1 INPUT ADJ2 INPUT SEL will begin, after which RST will be released. Positive Polarity Positive Polarity V (+) UV or (–) OV (+) UV or (–) OV CC Power-Down Positive Polarity Negative Polarity Open On power-down, once V drops below the UVLO threshold (+) UV or (–) OV (–) UV or (+) OV CC or either V becomes invalid, RST asserts logic low. V Negative Polarity Negative Polarity ADJ CC Ground (–) UV or (+) OV (–) UV or (+) OV of at least 0.5V guarantees a logic low of 0.15V at RST. Note: Open = open circuit or driven by a three-state buffer in high impedance state with leakage current less than 5μA. 2919f 8

LTC2919 APPLICATIOUS IUFORWATIOU If the user’s application requires, the SEL pin may be driven opposite is true for a “positive polarity” input (–OV or using a three-state buffer which satisfi es the VIL, VIH and +UV). These polarity defi nitions are also shown in Table leakage conditions of this three-state input pin. 1. For purposes of this data sheet, a negative voltage is considered “undervoltage” if it is closer to ground than it If the state of the SEL pin confi gures a given input as should be (e.g., –4.3V for a –5V supply). “negative polarity,” the voltage at that ADJ pin must be below the trip point (0.5V nominal), or the corresponding Proper confi guration of the SEL pin and setting of the OUT and RST output will be pulled low. Conversely, if a trip-points via external resistors allows for any two fault given input is confi gured as “positive polarity”, the ADJ pin conditions to be detected. For example, the LTC2919 may voltage must be above the trip point or the corresponding monitor two supplies (positive, negative or one of each) OUT and RST will assert low. for UV or for OV (or one UV and one OV). It may also Thus, a “negative polarity” input may be used to deter- monitor a single supply (positive or negative) for both UV mine whether a monitored negative voltage is smaller in and OV. Tables 2a and 2b show example confi gurations absolute value than it should be (–UV), or a monitored for monitoring possible combinations of fault condition positive voltage is larger than it should be (+OV). The and supply polarity. Table 2a. Possible Combinations of Supply Monitoring. For Example Purposes, All Supplies are Monitored at 5% Tolerance and Connections are Shown Only for ADJ1, ADJ2, REF, SEL, OUT1 and OUT2. Output Pull-up Resistors are Omitted for Clarity. SEL = VCC SEL = GND 15V 5V –15V –5V RP2A RP2B RN2A RN2B 309k 115k 309k 137k ADJ1 OUT1 UV (15V) ADJ1 OUT1 UV (–15V) ADJ2 OUT2 UV (5V) ADJ2 OUT2 UV (–5V) RP1A RP1B RN1A RN1B 11.5k 13.7k 10.7k 13.3k REF SEL REF SEL 2 Positive UV 2 Negative UV –15V –5V 15V 5V RN2A RN2B RP2A RP2B 1.02M 137k 619k 133k ADJ1 OUT1 OV (–15V) ADJ1 OUT1 OV (15V) ADJ2 OUT2 OV (–5V) ADJ2 OUT2 0V (5V) RN1A RN1B RP1A RP1B 30.9k 11.8k 20k 13.7k REF SEL REF SEL 2 Negative OV 2 Positive OV 15V –15V 15V –15V RP2 RN2 RP2 RN2 309k 1.02M 619k 309k ADJ1 OUT1 UV (15V) ADJ1 OUT1 OV (15V) ADJ2 OUT2 OV (–15V) ADJ2 OUT2 UV (–15V) RP1 RN1 RP1 RN1 11.5k 30.9k 20k 10.7k REF SEL REF SEL 1 Positive UV, 1 Negative OV 1 Positive OV, 1 Negative UV 2919f 9

LTC2919 APPLICATIOUS IUFORWATIOU Table 2b. Possible Combinations of Supply Monitoring. For Example Purposes, All Supplies are Monitored at 5% Tolerance and Connections are Shown Only for ADJ1, ADJ2, REF, SEL, OUT1 and OUT2. Output Pull-up Resistors are Omitted for Clarity. SELOPEN 15V –15V RP6 RN6 2.37M 1.02M ADJ1 OUT1 UV ADJ1 OUT1 OV RP5 RN5 10.7k 4.02k ADJ2 OUT2 OV ADJ2 OUT2 UV RP4 RN4 76.8k 30.9k REF SEL REF SEL 1 Positive UV and OV 1 Negative UV and OV 15V –15V –15V 15V RP2 RN2 RN2 RP2 309k 309k 1.02M 619k ADJ1 OUT1 UV(15V) ADJ1 OUT1 OV(–15V) ADJ2 OUT2 UV(–15V) ADJ2 OUT2 OV(15V) RP1 RN1 RN1 RP1 11.5k 10.7k 30.9k 20k REF SEL REF SEL 1 Positive UV, 1 Negative UV 1 Negative OV, 1 Positive OV 15V 5V –15V –5V RP2A RP2B RN2A RN2B 309k 133k 1.02M 137k ADJ1 OUT1 UV(15V) ADJ1 OUT1 OV(–15V) ADJ2 OUT2 OV(5V) ADJ2 OUT2 UV(–5V) RP1A RP1B RN1A RN1B 11.5k 13.7k 30.9k 13.3k REF SEL REF SEL 1 Positive UV, 1 Positive OV 1 Negative UV, 1 Negative OV Adjust Input Trip Point To prevent nuisance resets, the supervisor threshold must be guaranteed to lie outside the power supply tolerance The trip threshold for the supplies monitored by the band. To ensure that the threshold lies outside the power adjustable inputs is set with an external resistor divider, supply tolerance range, the nominal threshold must lie out- allowing the user complete control over the trip point. side that range by the monitor’s accuracy specifi cation. Selection of this trip voltage is crucial to the monitoring of the system. All three of the LTC2919 inputs (ADJ1, ADJ2, V UVLO) CC have the same maximum threshold accuracy of ±1.5% of Any power supply has some tolerance band within which the programmed nominal input voltage (over the full operat- it is expected to operate (e.g., 5V ±10%). It is generally ing temperature range). Therefore, using the LTC2919, the undesirable that a supervisor issue a reset when the power typical 10% UV threshold is at 11.5% below the nominal supply is inside this tolerance band. Such a “nuisance” input voltage level. For a 5V input, the threshold is nominally reset reduces reliability by preventing the system from 4.425V. With ±1.5% accuracy, the trip threshold range is functioning under normal conditions. 2919f 10

LTC2919 APPLICATIOUS IUFORWATIOU 4.425V ±75mV over temperature (i.e., 10% to 13% below it may be added externally. See 48V Telecom UV/OV with 5V). The monitored system must thus operate reliably Hysteresis Applications on page 14 for an example. down to 4.35V or 13% below 5V over temperature. Selecting External Resistors The above discussion is concerned only with the DC value In a typical positive supply monitoring application, the of the monitored supply. Real supplies also have relatively ADJx pin connects to a tap point on an external resistive high frequency variations from sources such as load transients, noise and pickup. divider between a positive voltage being monitored and ground, as shown in Figure 1. The LTC2919 uses two techniques to combat spurious outputs toggling from high frequency variation. First, When monitoring a negative supply, the ADJx pin connects to a tap point on a resistive divider between the negative the timeout period helps prevent high frequency varia- tion whose frequency is above 1/ t from appearing at voltage being monitored and the buffered reference (REF), RST the RST output. Second, the propagation delay versus as shown in Figure 2. overdrive function fi lters short glitches before the OUT1, OUT2 toggling or RST pulling low. VMON When an ADJ becomes invalid, the corresponding OUT and RST pin assert low. When the supply recovers past RP2 ADJx + the valid threshold, the reset timer starts (assuming it is RP1 not disabled) and RST does not go high until it fi nishes. – If the supply becomes invalid any time during the timeout + period, the timer resets and starts fresh when the supply 0.5V – next becomes valid. 2919 F01 To reduce sensitivity of short glitches from toggling the Figure 1. Setting Positive Supply Trip Point output pins, the comparator outputs go through a lowpass fi lter before triggering the output logic. Any transient at the input of a comparator needs to be of suffi cient magnitude and duration to pass the fi lter before it can change the REF monitor state. RN1 ADJx + The combination of the reset timeout and comparator RN2 fi ltering prevents spurious changes in the output state – VMON without sacrifi cing threshold accuracy. If further supply + 0.5V – glitch immunity is needed, the user may place an external capacitor from the ADJ input to ground. The resultant RC 2919 F02 lowpass fi lter with the resistor divider will further reject Figure 2. Setting Negative Supply Trip Point high frequency components of the supply, at the cost of slowing the monitor’s response to fault conditions. Normally the user will select a desired trip voltage based A common solution to the problem of spurious reset is on their supply and acceptable tolerances, and a value of to introduce hysteresis around the nominal threshold. R or R based on current draw. Current used by the N1 P1 However, this hysteresis degrades the effective accuracy resistive divider will be approximately: of the monitor and increases the range over which the 0.5V 0.5V system must operate. The LTC2919 therefore does not I= .OR= have hysteresis, except in comparator mode (by tying R R P1 N1 TMR pin to V ). If hysteresis is desired in other modes, CC 2919f 11

LTC2919 APPLICATIOUS IUFORWATIOU To minimize errors arising from ADJ input bias and to REF minimize loading on REF choose resistor R (for positive P1 ADJ1 supply monitoring) or R (for negative supply monitoring) + LOGIC N1 & OUT1 in the range of 5k to 100k. OPEN OV RN4 – DRAIN MOSFET For a positive-monitoring application, R is then chosen P2 by: RN5 ADJ2 + LOGIC & OUT2 RP2 = RP1(2VTRIP – 1) RN6 OPEN UV DRAIN – For a negative-monitoring application: –VMON + MOSFET 0.5V – R = R (1 – 2V ) N2 N1 TRIP 2919 F04 Note that the value V should be negative for a negative Figure 4. Setting UV and OV Trip Point for a Negative Supply TRIP application. For example, consider monitoring a –5V supply at ±10%. For The LTC2919 can also be used to monitor a single supply this supply application: V = –5.575V and V = –4.425V. OV UV for both UV and OV. This may be accomplished with three Suppose we wish to consume about 5μA in the divider, so resistors, instead of the four required for two independent R = 100k. We then fi nd R = 21.0k, R = 1.18M (nearest N4 N5 N6 supplies. Confi gurations are shown in Figures 3 and 4. R 1% standard values have been chosen). P4 or R may be chosen as is R or R above. N4 P1 N1 V Monitoring/UVLO CC For a given R , monitoring a positive supply: P4 The LTC2919 contains an accurate third -10% undervoltage V –V R =R OV UV monitor on the VCC pin. This monitor is fi xed at a nominal P5 P4 V 11.5% below the V specifi ed in the part number. The UV CC V standard part (LTC2919-2.5) is confi gured to monitor a R =R (2V –1) OV 2.5V supply (UVLO threshold of 2.213V), but versions P6 P4 UV V UV to monitor 3.3V and 5.0V (UVLO of 2.921V and 4.425V, respectively) are available. For monitoring a negative supply with a given R : N4 For applications that do not need V monitoring, the CC V –V R =R UV OV 2.5V version should be used, and the UVLO will simply N5 N4 1–V guarantee that the V is above the minimum required for UV CC 1–V proper threshold and timer accuracy before the timeout RN6 =RN4(1–2VUV) OV begins. 1–V UV Setting the Reset Timeout ADJ1 + LOGIC VMON & OUT1 RST goes high after a reset timeout period set by the TMR OPEN UV RP6 – DRAIN pin when the VCC and ADJ inputs are valid. This reset MOSFET timeout may be confi gured in one of three ways: internal RP5 200ms, programmed by external capacitor and no timeout ADJ2 + LOGIC & OUT2 (comparator mode). RP4 OPEN OV DRAIN – MOSFET In externally-controlled mode, the TMR pin is connected + 0.5V – by a capacitor to ground. The value of that capacitor allows for selection of a timeout ranging from about 400μs to 9 2919 F03 seconds. See the following section for details. Figure 3. Setting UV and OV Trip Point for a Positive Supply 2919f 12

LTC2919 AAPPPPLLIICCAATTIIOOUUSS IIUUFFOORRWWAATTIIOOUU If the user wishes to avoid having an external capacitor, Maximum length of the reset timeout is limited by the the TMR pin should be tied to ground, switching the part ability of the part to charge a large capacitor on start-up. to an internal 200ms timer. Initially, with a large (discharged) capacitor on the TMR pin, the part will assume it is in internal timer mode (since If the user requires a shorter timeout than 400μs, or the pin voltage will be at ground). If the 2.2μA fl owing wishes to perform application-specifi c processing of the out of the TMR pin does not charge the capacitor to the reset output, the part may be put in comparator mode by ground-sense threshold within the fi rst 200ms after sup- tying the TMR pin to V . In comparator mode, the timer CC is bypassed and comparator outputs go straight to the plies become good, the internal timer cycle will complete reset output. and RST will go high too soon. The current required to hold TMR at ground or V is This imposes a practical limit of 1μF (9 second timeout) if CC about 2.2μA. To force the pin from the fl oating state to the length of timeout during power-up needs to be longer ground or V may require as much as 100μA during the than 200ms. If the power-up timeout is not important, CC transition. larger capacitors may be used, subject to the limitation that the capacitor leakage current must not exceed 500nA, When the part is in comparator mode, one of the two or the function of the timer will be impaired. means of preventing false reset has been removed, so a small amount of one-sided hysteresis is added to the Output Pins Characteristics inputs to prevent oscillation as the monitored voltage passes through the threshold. This hysteresis is such The DC characteristics of the OUT1, OUT2 and RST pull- that the valid-to-invalid transition threshold is unchanged, down strength are shown in the Typical Performance but the invalid-to-valid threshold is moved by about Characteristics section. OUT1, OUT2 and RST are open- 0.7%. Thus, when the ADJ input polarity is positive, drain pins and thus require external pull-up resistors to the threshold voltage is 500mV nominal when the in- the logic supply. They may be pulled above VCC, providing put is above 500mV. As soon as the input drops below the absolute maximum rating of the pin are observed. 500mV, the threshold moves up to 503.5mV nominal. As noted in the discussion of power up and power down, Conversely, when confi gured as a negative-polarity input, the circuits that drive OUT1, OUT2 and RST are powered the threshold is 500mV when the input is below 500mV, by V . During a fault condition, V of at least 0.5V CC CC and switches to 496.5mV when the input goes above guarantees a V of 0.15V. OL 500mV. The open-drain nature of the RST pin allows for wired-OR The comparator mode feature is enabled by directly short- connection of several LTC2919s to monitor more than two ing the TMR pin to the V pin. Connecting the pin to any CC supplies (see Typical Applications). Other logic with open- other voltage may have unpredictable results. drain outputs may also connect to the RST line, allowing other logic-determined conditions to issue a reset. Selecting the Reset Timing Capacitor Connecting a capacitor, C , between the TMR pin and TMR ground sets the reset timeout, t . The following formula RST approximates the value of capacitor needed for a particular timeout: C = t • 110 [pF/ms] TMR RST Leaving the TMR pin open with no external capacitor generates a reset timeout of approximately 400μs. 2919f 13

LTC2919 TYPICAL APPLICATIOU S Six Supply Undervoltage Monitor with 2.5V Reset Output and 20ms Timeout 15V 5V –5V –15V SYSTEM 3.3V 2.5V 1C0B0YnPF1 RPU1 RPU5 RPU4 1C0B0YnPF2 10k 10k 10k RPU2 RPU3 10k 10k SYSTEM_OK R13N72kA VCC VCC R11P52kA ADJ1 SEL SEL ADJ1 RN2B RN1A LTC2919-2.5 LTC2919-3.3 RP1A RP2B 309k 13.3k 13.7k 309k REF RST RST REF RN1B RP1B 10.7k –5V_OK 5V_OK 11.5k ADJ2 OUT1 OUT1 ADJ2 2919 TA02 –15V_OK 15V_OK TMR OUT2 OUT2 TMR CTMR1 GND GND CTMR2 2.2nF 2.2nF 48V Telecom UV/OV Monitor with Hysteresis VIN SYSTEM 36V TO 72V R1.P423AM R1.P921BM 0.2R25C7WCk 1C0B0YnPF 5V RP2A2 M2 169k RPU3 VCC 10k VUV(RISING): 43.3V ADJ1 RST RPU1 VUV(FALLING): 38.7V LTC2919-2.5 PWRGD 10k VVOOVV(F(ARLISLIINNGG)):: 7710..62VV RP1A RP1B RP1B2 ADJ2 OUT1 UV R10PkU2 18.7k 13.7k 681k REF OUT2 OV M1 SEL TMR GND M1, M2: FDG6301N OR SIMILAR 2919 TA03 ±12V UV Monitor Powered from 12V, 20ms Timeout (1.8V Logic Out) CBYP RCC 100nF 10k 1.8V 12V R1.P027M VCC R10PkU3 10k* ADJ1 RST RPU1 MARNEUSAETL R49P.19k LTC2919-2.5 10k R10PkU2 PUSHBUTTON REF OUT1 RN2 RN1 12V_OK 249k 10.7k –12V ADJ2 OUT2 –12V_OK SEL TMR GND CTMR 2.2nF 2919 TA01b *OPTIONAL FOR ESD 2919f 14

LTC2919 PACKAGE DESCRIPTIOU DDB Package 10-Lead Plastic DFN (3mm × 2mm) (Reference LTC DWG # 05-08-1722 Rev Ø) 0.64 ±0.05 3.00 ±0.10 R = 0.115 0.40 ± 0.10 (2 SIDES) R = 0.05 TYP (2 SIDES) TYP 6 10 0.70 ±0.05 2.55 ±0.05 2.00 ±0.10 1.15 ±0.05 PIN 1 BAR (2 SIDES) PIN 1 TOP MARK R = 0.20 OR PACKAGE (SEE NOTE 6) 0.64 ± 0.05 0.25 × 45° OUTLINE (2 SIDES) 5 1 CHAMFER 0.25 ± 0.05 0.200 REF 0.75 ±0.05 0.25 ± 0.05 (DDB10) DFN 0905 REV Ø 0.50 BSC 0.50 BSC 2.39 ±0.05 2.39 ±0.05 (2 SIDES) (2 SIDES) 0 – 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229 2.DRAWING NOT TO SCALE 3.ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6.SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661 Rev E) 3.00± 0.102 (.118± .004) 0.497± 0.076 (NOTE 3) 10 9 8 76 (.0196± .003) 0(..808395±± 0.0.10257) REF 4.90± 0.152 3.00± 0.102 5.23 3.20 – 3.45 0.254 DETAIL “A” (.193± .006) (.1(1N8O±TE . 040)4) (.M20IN6) (.126 – .136) (.010) 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.305± 0.038 0.50 (.0120± .0015) (.0197) 0.53± 0.152 TYP BSC (.021± .006) 1.10 0.86 RECOMMENDED SOLDER PAD LAYOUT (.043) (.034) DETAIL “A” MAX REF 0.18 (.007) SEATING PLANE 0.17 – 0.27 0.1016± 0.0508 (.007 – .011) (.004± .002) 0.50 TYP (.0197) MSOP (MS) 0307 REV E NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 2919f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 15 However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC2919 TYPICAL APPLICATIOU Powered from 12V, +5V is Sequenced to Start-up First, OUT Followed by –5V , with ±5V UV Monitor, 200ms Timeout OUT +12V RCC 4.7k CBYP 0.1μF +5V VCC +5V 1R1P52k LTC2919-2.5 RPU2 DC/DC ADJ1 SEL 10k CONVERTER 13R.7Pk1 REF OUT2 PWRGD R10PkU3 DC/DC –5V 1R3N7k2 13R.N3k1 ADJ2 RST SYS_RESET CONVERTER SHDN OUT1 TMR 2919TA06 GND RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1326/LTC1326-2.5 Micropower Precision Triple Supply Monitor for 4.725V, 3.118V, 1V Threshold (±0.75%) 5V/2.5V, 3.3V and ADJ LTC1536 Precision Triple Supply Monitor for PCI Applications Meets PCI t Timing Specifi cations FAIL LTC1540 Nanopower Comparator with Reference Adjustable Hysteresis LTC1726-2.5/LTC1726-5 Micropower Triple Supply Monitor for 2.5V/5V, 3.3V Adjustable Reset and Watchdog Time-Outs and ADJ LTC1727/LTC1728 Micropower Triple Supply Monitor with Open-Drain Individual Monitor Outputs in MSOP/5-Lead SOT-23 Reset LTC1985-1.8 Micropower Triple Supply Monitor with Push-Pull 5-Lead SOT-23 Package Reset Output LTC2900 Programmable Quad Supply Monitor Adjustable Reset, 10-Lead MSOP and 3mm × 3mm 10-Lead DFN Package LTC2901 Programmable Quad Supply Monitor Adjustable Reset and Watchdog Timer, 16-Lead SSOP Package LTC2902 Programmable Quad Supply Monitor Adjustable Reset and Tolerance, 16-Lead SSOP Package, Margining Functions LTC2903 Precision Quad Supply Monitor 6-Lead SOT-23 Package, Ultralow Voltage Reset LTC2904/LTC2905 3-State Programmable Precision Dual Supply Monitor Adjustable Tolerance and Reset Timer, 8-Lead SOT-23 Package LTC2906/LTC2907 Precision Dual Supply Monitor 1-Selectable and Separate V Pin, RST/RST Outputs/Adjustable Reset Timer CC 1 Adjustable LTC2908 Precision Six Supply Monitor (Four Fixed and 8-Lead SOT-23 and DFN Packages 2 Adjustable) LTC2909 Precision, Dual Input UV, OV and Negative Voltage 8-Lead SOT-23 and DFN Packages Monitor LTC2912-LTC2914 Single/Dual/Quad UV and OV Voltage Monitors Separate V Pin, Adjustable Reset Timer, H-Grade Temperature Range CC LTC2915-LTC2918 Single Voltage Monitor with 27 Unique Thresholds Manual Reset, Watchdog, TSOT-8/MSOP-10 and 3mm × 2mm DFN Package, H-Grade Temperature Range LT6700 Micropower, Low Voltage, Dual Comparator with 6-Lead SOT-23 Package 400mV Reference 2919f 16 Linear Technology Corporation LT 0208 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008