LTC2911 Precision Triple Supply Monitor with Power-Fail Comparator FEATURES DESCRIPTION n Ultralow Voltage Reset: VCC = 0.5V Guaranteed The LTC®2911 is a low power, high accuracy triple supply n Monitors Three Inputs Simultaneously: monitor with a power-fail comparator. Reset timeout may 3.3V, 5V, ADJ (LTC2911-1) be selected with an external capacitor or set to an internally 3.3V, 2.5V, ADJ (LTC2911-2) generated 200ms. 3.3V, 1.8V, ADJ (LTC2911-3) The V1 pin monitors a 3.3V supply. The V2 pin monitors a 3.3V, 1.2V, ADJ (LTC2911-4) 5V, 2.5V, 1.8V, 1.2V or adjustable supply. A third adjustable 3.3V, ADJ, ADJ (LTC2911-5) input has a nominal 0.5V threshold allowing a resistive n ±1.5% Threshold Accuracy divider to configure its threshold. All three comparators n Power-Fail Monitor feature a tight 1.5% threshold accuracy over the entire n RST State Can Be Held for Margining operating temperature range while a glitch filter ensures n Low Supply Current: 30µA Typical reliable reset operation. n Input Glitch Immunity n Adjustable Reset Timeout Period A spare comparator can be configured to provide early n Selectable Internal Timeout Saves Components warning of a low voltage condition. It causes the PFO output n Space Saving 8-Lead TSOT-23 and 3mm × 2mm DFN to pull low when the voltage of the PFI input falls below 0.5V, Packages allowing the power-fail threshold to be configured with a resistive divider. A latch feature on the TMR pin allows the RST output to be latched to prevent system resets, APPLICATIONS simplifying margin testing. n Network Servers L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Desktop and Notebook Computers Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6949965, 7292076. n Automotive and Industrial Electronics TYPICAL APPLICATION RST Output Voltage With 10k Pull-Up to V1 3.3V 6 V1 = V2 DC/DC 2.5V SYSTEM CONVERTER 1.0V LOGIC 5 TMR 10k 4 RESET 76.8k VV12LTC2911RP-SF2OT LOBAT (V)RST 3 V ADJ 2 + Li-Ion 576k 100k BATTERY PFI STACK 1 100k GND tRST = 200ms 0 2911 TA01a 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V1 (V) 2911 TA01b 2911f 1

LTC2911 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2, 3) Supply Voltages Operating Temperature Range V1, V2 ...................................................–0.3V to 6.5V LTC2911C ................................................0°C to 70°C Input Voltages LTC2911I..............................................–40°C to 85°C ADJ .......................................................–0.3V to 6.5V LTC2911H ..........................................–40°C to 125°C PFI ...........................................................–0.3V to 2V Storage Temperature Range ...................–65°C to 150°C TMR ............................................–0.3V to (V1 + 0.3V) Lead Temperature (Soldering, 10 sec) Output Voltages TSOT-23 ............................................................300°C RST, PFO ..............................................–0.3V to 6.5V PIN CONFIGURATION TOP VIEW TOP VIEW V2 1 8 PFI PFI 1 8 V2 ADJ 2 7 V1 V1 2 9 7 ADJ TMR 3 6 PFO PFO 3 GND 6 TMR GND 4 5 RST RST 4 5 GND TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 DDB PACKAGE TJMAX = 150°C, θJA = 195°C/W 8-LEAD (3mm × 2mm) PLASTIC DFN TJMAX = 150°C, θJA = 76°C/W EXPOSED PAD (PIN 9) IS GND, PCB CONNECTION OPTIONAL ORDER INFORMATION LTC2911 C DDB –1 #TRM PBF LEAD FREE DESIGNATOR PBF = Lead Free Finish Parts None = Lead Based Finish Parts TAPE AND REEL #TR = Tape and Reel #TRM = 500-Piece Tape and Reel PRODUCT SELECTION –1, –2, –3, –4, –5 See Product Selection Guide for Details PACKAGE TYPE DDB = 8-Lead (3mm × 2mm) Plastic DFN TS8 = 8-Lead Plastic TSOT-23 TEMPERATURE GRADE C = Commercial Temperature Range (0°C to 70°C) I = Industrial Temperature Range (–40°C to 85°C) H = Automotive Temperature Range (–40°C to 125°C) PRODUCT PART NUMBER Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2911f 2

LTC2911 PRODUCT SELECTION GUIDE PART NUMBER PART MARKING PACKAGE DESCRIPTION V1 V2 LTC2911-1 LFHZ 8-Lead (3mm × 2mm) Plastic DFN 3.3V 5V LTC2911-2 LFPG 8-Lead (3mm × 2mm) Plastic DFN 3.3V 2.5V LTC2911-3 LFPJ 8-Lead (3mm × 2mm) Plastic DFN 3.3V 1.8V LTC2911-4 LFPM 8-Lead (3mm × 2mm) Plastic DFN 3.3V 1.2V LTC2911-5 LFPP 8-Lead (3mm × 2mm) Plastic DFN 3.3V ADJ LTC2911-1 LTFJB 8-Lead Plastic TSOT-23 3.3V 5V LTC2911-2 LTFPH 8-Lead Plastic TSOT-23 3.3V 2.5V LTC2911-3 LTFPK 8-Lead Plastic TSOT-23 3.3V 1.8V LTC2911-4 LTFPN 8-Lead Plastic TSOT-23 3.3V 1.2V LTC2911-5 LTFPQ 8-Lead Plastic TSOT-23 3.3V ADJ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 0.55V, V = 0.55V, V1 = 3.3V unless otherwise noted. (Notes 2, 3) A ADJ PFI SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V 3.3V, 5% Reset Threshold V1 Input l 3.036 3.086 3.135 V RT33 V 5V, 5% Reset Threshold V2 Input (LTC2911-1) l 4.600 4.675 4.750 V RT50 V 2.5V, 5% Reset Threshold V2 Input (LTC2911-2) l 2.300 2.338 2.375 V RT25 V 1.8V, 5% Reset Threshold V2 Input (LTC2911-3) l 1.656 1.683 1.710 V RT18 V 1.2V, 5% Reset Threshold V2 Input (LTC2911-4) l 1.104 1.122 1.140 V RT12 V ADJ Pin Threshold ADJ Input and V2 Input of l 492.5 500 507.5 mV RTA LTC2911-5 V PFI Pin Threshold PFI Input Threshold (Falling) l 492.5 500 507.5 mV PFT ∆VPFT PFI Hysteresis l 10 15 19 mV V Minimum Operating Voltage to Guarantee PFO V = 0.55V l 2.3 V CC,OP PFI High (Note 3) I V1 input Current (Note 4) V1 = 3.3V, V1 > V2 l 10 30 80 µA V1 V1 = 3.3V, V1 < V2 l 3 10 30 µA I V2 Input Current (Note 4) V2 = 5V (LTC2911-1) l 10 35 80 µA V2 V2 = 2.5V (LTC2911-2) l 3 10 30 µA V2 = 1.8V (LTC2911-3) l 2 10 30 µA V2 = 1.2V (LTC2911-4) l 2 10 30 µA V2 = 0.55V (LTC2911-5) C-Grade/I-Grade l ±15 nA H-Grade l ±40 nA I ADJ Input Current V = 0.55V (C-Grade) (I-Grade) l ±15 nA ADJ ADJ V = 0.55V (H-Grade) l ±40 nA ADJ I PFI Input Current V = 0.55V (C-Grade) (I-Grade) l ±15 nA PFI PFI V = 0.55V (H-Grade) l ±40 nA PFI I TMR Pull-Up Current V = 1V l –1.5 –2.2 –2.9 µA TMR(UP) TMR I TMR Pull-Down Current V = 1V l 1.5 2.2 2.9 µA TMR(DOWN) TMR I RST, PFO Pull-Up Current V = 0V l –20 –29 –40 µA PU PIN 2911f 3

LTC2911 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 0.55V, V = 0.55V, V1 = 3.3V unless otherwise noted. (Notes 2, 3) A ADJ PFI SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t PFI Comparator Propagation Delay to PFO V Driven Beyond Threshold l 8 30 80 µs P,PF PFI V by More Than 10% PFT t V1, V2, ADJ Undervoltage Detect to RST Low V Less Than Threshold V by l 8 30 80 µs UV X RTX More Than 10% V RST, PFO Output Voltage High (Note 5) I = –1µA l V1 – 1 V1 V OH RST V RST, PFO Output Voltage Low (Note 6) V = 0.5V, I = 5µA l 0.01 0.15 V OL CC V = 1V, I = 100µA l 0.01 0.15 V CC V = 3V, I = 2.5mA l 0.10 0.30 V CC t Reset Timeout Period, External C = 2.2nF l 15 20 27 ms RST(EXT) TMR t Reset Timeout Period, Internal V = V1 l 140 200 280 ms RST(INT) TMR V Timer Internal Mode Threshold V Rising l V1 – 0.40 V1 – 0.020 V1 – 0.10 V TMR(INT) TMR ∆VTMR(INT) Timer Internal Mode Hysteresis VTMR Falling l 40 100 160 mV V Timer Latch Mode Threshold V Falling l 0.10 0.20 0.40 V TMR(LATCH) TMR ∆VTMR(LATCH) Timer Latch Mode Hysteresis VTMR Rising l 40 75 160 mV t Latch Release Propagation Delay to RST Low V Rising, Step 0V to 0.6V l 0.5 3 µs P, LR TMR t Monitor Input Setup Time to Latch Enable (Note 7) V Falling, Step 0.6V to 0V l 2 ms SU,MON TMR Monitor Input Setup Time to Latch Release V Rising, Step 0V to 0.6V TMR t Monitor Input Hold Time to Latch Enable V Falling, Step 0.6V to 0V l 0 µs HD, MON TMR Monitor Input Hold Time to Latch Release V Rising, Step 0V to 0.6V TMR Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: The RST and PFO output pins on the LTC2911 have internal pull- may cause permanent damage to the device. Exposure to any Absolute ups to V1. However, for faster rise times or for V voltages greater than OH Maximum Rating condition for extended periods may affect device V1, use an external pull-up resistor. reliability and lifetime. Note 6: The RST and PFO pull-down currents are derived from V1 and V2 Note 2: All currents into pins are positive; all voltages are referenced to except for the LTC2911-5 where the pull-down strength is derived only GND unless otherwise noted. from V1. Note 3: The internal supply voltage (V ) is generated from the greater of Note 7: t is required to latch a low RST state and t + t is CC SU,MON SU,MON RST the voltages on the V1 and V2 inputs. V = V1 for the LTC2911-5. required to latch a high RST state. CC Note 4: Under typical operating conditions, quiescent current is drawn from the greater of the voltages on the V1 and V2 inputs. For the LTC2911-5 only V1 supplies the quiescent current. 2911f 4

LTC2911 TYPICAL PERFORMANCE CHARACTERISTICS Normalized Reset and Power-Fail Quiescent Supply Current Allowable Glitch Duration Threshold Voltages vs Temperature vs Temperature vs Overdrive 1.015 60 500 V) IV2 FOR LTC2911-1 AGE (V/1.010 T (µA) 50 400 HRESHOLD VOLT11..000005 SUPPLY CURREN 3400 H DURATION (µs)320000 ED T0.995 ENT 20 LITC Z C G MALI0.990 UIES 10 100 R Q O N 0.985 0 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 0.1 1 10 100 TEMPERATURE (°C) TEMPERATURE (°C) OVERDRIVE (%) 2911 G01 2911 G02 2911 G03 Reset Timeout Period vs RST, PFO Voltage Output Low PFI Hysteresis vs Temperature Temperature vs Sink Current 18.0 260 1.0 VCC = 3V 17.5 240 HYSTERESIS (mV)1111167556.....00055 TIMEOUT PERIOD (ms)221028000 CEITNXMTTREE R=R NN2AA2LnLF VOLTAGE OUTPUT LOW (V) 000...468 –2450°C°C 160 0.2 85°C 14.5 125°C 150°C 14.0 140 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 0 5 10 15 20 25 30 TAMB (°C) TEMPERATURE (°C) SINK CURRENT (mA) 2911 G04 2911 G05 2911 G06 RST, PFO Voltage Output High RST, PFO Voltage Output High RST, PFO Pin Source Current vs Source Current vs V vs V1 CC 3.0 6 100 V1 = 3.135V, V2 = 5V FOR RST V1 = V2 = ADJ = PFI 5 10k PULL-UP TO VCC UT HIGH (V) 22..50 UT HIGH (V) 34 LTRCS2T9 1F1O-R1 CURRENT (µA) 6800 GE OUTP 1.5 GE OUTP 2 RLLTTSCCT22 F99O1111R--23 SOURCE 40 VOLTA 1.0 VOLTA 1 PFO LLTTCC22991111--45 UTPUT 20 0.5 0 O PFO RST 0 –1 0 0 5 10 15 20 25 30 35 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 1 2 3 4 5 6 SOURCE CURRENT (µA) VCC (V) V1 (V) 2911 G07 2911 G08 2911 G09 2911f 5

LTC2911 PIN FUNCTIONS ADJ: Adjustable Voltage Monitor Input. Input to a voltage TMR: Reset Timeout Control. Attach an external capacitor, monitor comparator with a 0.5V nominal threshold. Tie C , to GND to set a reset timeout period of 9.4ms/nF. A TMR to V1 if unused. low leakage ceramic capacitor is recommended for timer accuracy. A 2.2nF capacitor generates a 20ms timeout. Exposed Pad (DFN Only): Exposed pad may be left open Leaving the TMR pin open without a capacitor generates or connected to device ground. a minimum timeout of approximately 400µs which will GND: Device Ground. vary depending on the parasitic capacitance on the pin. Tying this pin to V1 enables the internal 200ms timeout. PFI: Power-Fail Voltage Monitor Input. Input to the power- Pulling this pin to GND latches the reset state. fail comparator with a 500mV threshold at the falling edge and a 515mV threshold at the rising edge, giving V1: 3.3V Monitor and Power Supply Input. V1 is an accu- a 3% hysteresis for noise rejection. Tie to V1 or GND if rate 3.3V, –5% undervoltage supply monitor. The internal unused. V is generated from the greater of the voltages at the CC V1 and V2 inputs for the LTC2911-1/LTC2911-2/LTC2911- PFO: Power-Fail Logic Output. This pin asserts low when 3/LTC2911-4 options. The LTC2911-5 option always derives the PFI input voltage is below its threshold and goes high its power supply from the V1 pin. Bypass this pin to GND when the PFI input voltage is above its threshold. This pin with a 0.1µF (or greater) capacitor for the LTC2911-2 provides a weak pull-up current to V1. This current is typi- through LTC2911-5. cally 29µA at V1 = 3.3V. The pin can be pulled to voltages higher than V1 by external pull-up resistors. PFO provides V2: Voltage Monitor and Power Supply Input. V2 is a an early warning signal of a system power failure. –5% undervoltage supply monitor for a 5V, 2.5V, 1.8V or 1.2V supply for the LTC2911-1/LTC2911-2/LTC2911- RST: Reset Logic Output. This pin asserts low when any 3/LTC2911-4 options, respectively. Because the internal of the V1, V2, or ADJ inputs are below their reset thresh- V is generated from the greater of the V1 and V2 inputs olds. Pulls high when all the monitored inputs are above CC for these options, the V2 pin should be bypassed to GND their thresholds for longer than a timeout period. This pin with a 0.1µF (or greater) capacitor for the LTC2911-1. The provides a weak pull-up current to V1. This current is typi- V2 pin of the LTC2911-5 is a high impedance input with a cally 29µA at V1 = 3.3V. The pin can be pulled to voltages 0.5V threshold, allowing the trip threshold of the monitored higher than V1 by external pull-up resistors. The status of supply to be configured with a resistive divider. RST can be latched by holding the TMR pin at GND. 2911f 6

LTC2911 BLOCK DIAGRAM V1 V1 POWER 114k V2* DETECT VCC PFI – PFO PFI COMP + LOW VCC VOLTAGE PULL-DOWN TMR 1.36M V1 – V1 THREE-STATE 263k V1 COMP DECODE + 114k ADJUSTABLE V2 RX** – GENPEURLASTEOR RST 231k** V2 COMP LATCH + 200ms PULSE GENERATOR LOW ADJ – VCC PUVLOLL-TDAOGWEN ADJ COMP + GND MONITORED VOLTAGES + 0.5V – LTC2911 LTC2911-1 LTC2911-2 LTC2911-3 LTC2911-4 LTC2911-5 V2 5V 2.5V 1.8V 1.2V ADJ RX 1.93M 850k 547k 288k ** *FOR OPTIONS LTC2911-1 THROUGH LTC2911-4 ONLY. **OMIT THE RESISTIVE DIVIDER FOR THE LTC2911-5. 2911 BD 2911f 7

LTC2911 TIMING DIAGRAMS Undervoltage and Reset Timing Power-Fail Timing VX VRTX PFI VPFT tUV tRST tP,PF tP,PF PFO 1.0V 2911 TD03 RST 1.0V 2911 TD01 Latch Release to RST Low Timing TMR 0.4V tP,LR RST 1.0V 2911 TD02 NOTE: ADJ FORCED LOW BEFORE TMR RELEASE Latching RST High Input Valid to Latch Enable Input Valid to Latch Release Setup and Hold Timing Setup Timing TMR VTMR(LATCH) ∆VTVMTMR(RL(ALTACTHC)H +) tSU,MON tRST tHD,MON t > tSU,MON 3% OVERDRIVE ADJ, V1, V2 VRTX MARGINING –3% OVERDRIVE POWER UP RST 1V 2911 TD04 LATCH IN INPUT RETURNING TO ABOVE VRTX NOTE: FOR THE LTC2911-5, V1 LOW RESETS RST TO A LOW STATE FOR t > tSU,MON, RST PIN STAYS HIGH Latching RST Low Input Invalid to Latch Enable Input Invalid to Latch Setup and Hold Timing Release Setup Timing TMR VTMR(LATCH) ∆VTVMTMR(RL(ALTACTHC)H +) tSU,MON tHD,MON t > tSU,MON tUV 3% OVERDRIVE MARGINING ADJ, V1, V2 VRTX VRTX –3% OVERDRIVE –3% OVERDRIVE RST 1V LATCH IN 2911 TD05 NOTE: FOR THE LTC2911-5, V1 LOW RESETS RST TO A LOW STATE INPUT RETURNING TO BELOW VRTX FOR t > tSU,MON, RST PIN STAYS LOW 2911f 8

LTC2911 APPLICATIONS INFORMATION The LTC2911 is a low power, high accuracy triple supply The LTC2911 uses proprietary low voltage drive circuitry monitor with power-fail comparator. For the LTC2911-1, for the RST and PFO pins which holds them low with LTC2911-2, LTC2911-3 and LTC2911-4 options, the V1 V (the higher of V1 and V2) as low as 0.5V. This helps CC and V2 pins monitor two supplies. Their thresholds are prevent indeterminate voltages from appearing on the preset internally based on the option chosen. A resistive outputs during power-up. For additional details refer to divider connected to the ADJ pin configures the third the Output Pin Characteristics section. threshold. For the LTC2911-5, the V2 pin is a high imped- When V1 and V2 are ramped simultaneously (for ance adjustable input similar to the ADJ pin. LTC2911-1/LTC2911-2/LTC2911-3/LTC2911-4), the pull- Reset timeout of the device may be selected with an external down current from the RST and PFO pins is about twice capacitor or set to an internally generated 200ms. The ADJ, the current available when V1 or V2 is grounded. V1 and V2 inputs must be valid (above their thresholds) for longer than the reset timeout period before the RST Power Down pin transitions high. On power-down, when the voltage monitored by the power- The power-fail comparator causes the PFO pin to pull fail comparator falls below the threshold configured by its low when the PFI pin falls below 0.5V. A resistive divider resistive divider, the PFO pin pulls low to provide an early connected to the PFI pin configures the threshold of the warning of imminent power failure. In a typically config- monitored voltage. The PFO output typically provides ured system, this occurs before the supplies monitored an early warning of imminent power failure so that the by V1, V2 or ADJ fall below their thresholds and cause system may begin shutdown procedures such as supply the RST pin to pull low. The RST and PFO pins maintain sequencing and/or storage of system state in nonvolatile a logic low output for VCC as low as 0.5V. See the Output memory. PIn Characteristics section for additional details. Power-Up Power-Fail Monitoring and PFO Signaling The LTC2911-1, LTC2911-2, LTC2911-3 and LTC2911-4 The LTC2911’s PFI input monitors a voltage through a supervisors are powered from the V1 and V2 pins, auto- resistive divider and compares it to the internal power-fail matically selecting the pin with the higher potential. The threshold. When PFI drops below 0.50V (the power-fail exception in the device family, the LTC2911-5, derives threshold) the PFO output pulls low to provide an early its internal supply voltage (V ) only from V1. When all warning of a low voltage condition. When the PFI pin rises CC monitor inputs are above their thresholds, the quiescent above 0.515V again, the PFO output signals high indicating supply current drawn from V is typically 30µA (35µA a valid supply condition. CC for the LTC2911-1). When the three monitor inputs (V1, The PFI input typically monitors the primary power supply V2 and ADJ) rise above their thresholds, the appropriate of a system. For example, the PFI pin may monitor the timeout delay begins, after which RST pulls to V1. Once input supply of a DC/DC converter or a Li-Ion battery stack the PFI input rises above 515mV, the PFO output signals voltage. The PFO output typically provides a warning to high indicating that the supply or voltage monitored by the system that the power supply is on the verge of fail- PFI is above threshold. ing so that it can prepare for a controlled shutdown. For 2911f 9

LTC2911 APPLICATIONS INFORMATION example, the PFO pin may connect to a processor non- Figure 1 illustrates a typical 3.3V monitor. The LTC2911 maskable interrupt. When the battery pack voltage drops has ±1.5% reset threshold accuracy. The nearest practical below the shutdown threshold, as sensed at PFI, the PFO supervisor trip point is the sum of power supply toler- pin pulls low to issue an interrupt. Next, the processor ance and the LTC2911 tolerance. So a “5%” threshold begins shutdown procedures which may include supply is typically set to –6.5%, excluding resistor errors. Thus sequencing and/or storage/erasure of system state in for a 3.3V “5%” threshold, the practical supervisor trip nonvolatile memory. point is at 3.086V. The threshold is guaranteed to lie in the band between 3.036V and 3.135V over the operating Threshold Accuracy temperature range. This 3.135V maximum threshold is at the lower limit of supply tolerance (3.3V – 5%) to prevent Specifying the minimum supply voltage for a system false tripping. requires the designer to consider three factors: minimum supply voltage for proper operation, power supply toler- The system must operate reliably a little below 3.036V ance, and supervisor reset threshold accuracy. Highly (or 3.3V, –8%), or risk malfunction before a reset signal accurate supervisors ease the design challenge by de- is properly issued. A less accurate supervisor increases creasing the overall voltage margin required for reliable the supply voltage tolerance requirements and the risk system operation. of system malfunction. The LTC2911’s ±1.5% threshold voltage specification minimizes these requirements. The reset threshold band and the power supply tolerance bands should not overlap. This prevents false or nuisance V1 and V2 Supply Monitors resets when the power supply is actually within its specified tolerance band. The actual reset threshold of supervisors All the LTC2911 options have a V1 threshold equal to varies over a specified band. The LTC2911 supervisor 3.086V (3.3V – 6.5%). The V2 thresholds are 4.675V varies ±1.5% around its nominal threshold voltage over (5V – 6.5%), 2.338V (2.5V – 6.5%), 1.683V (1.8V – 6.5%) temperature. and 1.122V (1.2V – 6.5%) for options LTC2911-1, NOMINAL 3.3V SUPPLY SUPPLY TOLERANCE VOLTAGE MINIMUM RELIABLE IDEAL SYSTEM SUPERVISOR VOLTAGE THRESHOLD 3.135V –5% ±1.5% THRESHOLD 3.086V –6.5% BAND 3.036V –8% REGION OF POTENTIAL MALFUNCTION 2911 F01 Figure 1. 1.5% Threshold Accuracy Improves System Reliability 2911f 10

LTC2911 APPLICATIONS INFORMATION LTC2911-2, LTC2911-3 and LTC2911-4 respectively. V2 To minimize errors arising from the ADJ input bias current, of the LTC2911-5 option is a high impedance input with a value of less than 100k is recommended for R1. a nominal 0.5V threshold. R2 is then chosen by: Input Noise Filtering for RST  V  TRIP_ADJ R2=R1• –1   The V1, V2 and ADJ comparators have a response time that  0.5V  is inversely proportional to overdrive. This characteristic is illustrated in the Typical Performance Characteristics where, VTRIP_ADJ is the supply threshold when the ADJ as the graph Allowable Glitch Duration versus Overdrive. pin falls below its 0.5V threshold. The ADJ and the LTC2911-5’s V2 pin may be bypassed For accurate monitoring, the resistor tolerance should be with a capacitor to increase the filtering in applications that as small as possible. Resistor tolerance of 0.1% or some demand it. The resultant RC lowpass filter at the inputs will trimming of components should be considered for R2/R1 further reject high frequency components, at the cost of in applications that require an accurate trip point. slowing the monitor’s response to fault conditions. Resistor Selection for PFI Resistor Selection for ADJ An external resistive divider (R3 and R4) connected between The threshold of the supply monitored by the ADJ pin is the supply and ground configures the threshold of the configured with an external resistive divider (R2 and R1) supply monitored by the power-fail comparator. The tap connected between the supply and ground. The tap point point for the divider is connected to the PFI input which for the divider is connected to the adjustable input (ADJ) has a 0.5V threshold. (See Figure 3a) which has a 0.5V threshold. (See Figure 2) Resistor selection follows a process similar to that for Normally, the user selects a trip voltage based on the sup- the ADJ pin. ply and acceptable tolerances, and a value of R1 based on R3 is given by: current drawn. For a given current, I, R1 is given by: 0.5V 0.5V R3= R1= I I VTRIP R2 LTC2911 ADJ – R1 + + 0.5V – 2911 F02 Figure 2. Setting the Adjustable (ADJ) Trip Point 2911f 11

LTC2911 APPLICATIONS INFORMATION V1 R5 V1 VTRIP LTC2911 114k R4 VTRIP LTC2911 114k V1 PFI – PFO R4 R6 R3 PFI – PFO + R3 + 0.5V – + + 0.5V – 2911 F03a Figure 3a. Setting the Power-Fail (PFI) Trip Point 2911 F03b Figure 3b. Increasing Power-Fail Hysteresis Again, to minimize errors arising from the PFI input bias current, a value of less than 100k is recommended for edges. The nominal threshold is 500mV at the falling edge R3. and 515mV at the rising edge. The hysteresis prevents oscillation when the monitored voltage passes through R4 can be chosen either using the PFI falling threshold or the thresholds. If the PFI pin is connected to an external the PFI rising threshold. resistive divider, it may be bypassed with a capacitor for For the falling edge threshold, use the equation: additional noise filtering.  V  R4=R3• TRIP_PFI_FALL –1 Increasing the Power-Fail Hysteresis    0.5V  The power-fail comparator hysteresis can be increased by adding two resistors, R5 and R6, as shown in Figure 3b. Alternatively, for the rising edge threshold, use the When PFO is low, R5 sinks current from the center tap equation: of the R3 and R4 resistive divider. The upper threshold is  V  therefore given by: TRIP_PFI_RISE R4=R3• –1    0.515V   R4 R4 V =0.515V 1+ + H    R3 R5 where V is the supply threshold when the PFI TRIP_PFI_FALL pin falls below the 0.5V falling threshold, and V TRIP_PFI_RISE When PFO is high, the series combination of R5 and R6 is the supply threshold when the PFI pin rises above the sources current into the center tap of the R3 and R4 resis- 0.515V rising threshold. tive divider. This leads to a lower threshold of: Note that V is typically 3% above the TRIP_PFI_RISE  R4 (3.3V–0.5V)R4 VTRIP_PFI_FALL due to the fact that the PFI 515mV rising VL =0.5V1+  – threshold is 3% above its 500mV falling threshold.  R3 R5+R6 In applications that require an accurate trip point, the R4 The addition of R5 and R6 increases the hysteresis to: and R3 resistors should have small tolerances. Hysteresis for Power-Fail Comparator VHYST =VH–VL The power-fail comparator uses a positive 3% accurate  R4 R4 (3.3V–0.5V)R4 =0.015 1+ +0.515 +     hysteresis to combat spurious triggering while maintain-  R3 R5 R5+R6 ing accurate thresholds for both the rising and falling 2911f 12

LTC2911 APPLICATIONS INFORMATION Resistor Selection for Combined Reset See Threshold Accuracy section for more details. In the and Power-Fail Divider design, if we wish to consume about 5µA in the divider, R = 100k. We then find R = 12.4k and R = 787k (nearest When the power-fail and reset signals are based on the A B C 1% standard values). same supply, the PFI and ADJ inputs may be connected to a single resistive divider formed from three resistors. Setting the Reset Timeout The configuration is shown in Figure 4. For a given bias current I, R , R and R can be calculated from: RST goes high after the V1, V2 and ADJ inputs are above A B C their thresholds for a reset timeout period. Connecting 0.5V R = the TMR pin to V1 enables the internal 200ms timer. A I To configure a different reset timeout period connect a  V  capacitor between the TMR pin and ground. TRIP_PFI_FALL R =R • –1 B A    V  The following formula approximates the value of capacitor TRIP_ADJ needed for a particular timeout:  V   V  TRIP_ADJ TRIP_PFI_FALL RC =RA • 0.5V –1 • V  CTMR = tRST • 106.5 [pF/ms] TRIP_ADJ Leaving the TMR pin open with no external capacitor For example, consider monitoring a 5V, ±5% supply with generates a reset timeout of approximately 400µs. Larger V = 4.5V and V = 4V. The resulting capacitors may be used to increase the timeout, but the TRIP_PFI_FALL TRIP_ADJ V is equal to 4.63V or 3% above V . capacitor leakage current must not exceed 500nA. Other- TRIP_PFI_RISE TRIP_PFI_FALL The maximum V should not overlap the mini- wise, the timer accuracy will be severely affected. TRIP_PFI_RISE mum power supply voltage level for PFO to deassert when Suitable values of C for a given t may be selected TMR RST the supply recovers. Mathematically, after factoring in the from Figure 5. sum of the power supply tolerance and the LTC2911 toler- ance, the V should be lower than 5V – 6.5%. TRIP_PFI_RISE VTRIP 10000 RC LTC2911 ADJ – ms)1000 (ST R + UT, t 100 RB O E M L TI 10 A PFI – RN E T RA EX 1 + + 0.1 0.5V – 10p 100p 1n 10n 100n 1µ CTMR (F) 2911 F04 2911 F05 Figure 4. Combining PFI/ADJ Monitoring of One Supply Figure 5. External Timeout vs C TMR with Three Resistors 2911f 13

LTC2911 APPLICATIONS INFORMATION Reset Latch Mode before TMR was pulled low, and all inputs are valid when TMR is released, RST will deassert (go high) after a t At any time, the TMR pin can be pulled low to latch the RST delay (see Figures 6b and 6c). The RST pin remains as- RST pin status, overriding the reset operation. This feature serted for a full t timeout after the TMR pin is released, is useful when testing a system at supply voltages that RST regardless of the state of the t timer before the latch might otherwise cause the RST pin to assert. RST was enabled. The reset latch mode is useful for perform- If the RST pin is unasserted (high) before the latch is ing supply margining tests without resetting the system enabled (by pulling the TMR pin low), RST will remain (see Figure 6d). unasserted after the TMR pin is released. This is true At least 2.9µA of pull-up or pull-down current is required provided that all reset monitor inputs are valid when TMR to hold the TMR pin high or low to configure the internal releases, regardless of their state while the TMR pin was timer or reset latch mode. However, during the timer mode low. However, if RST was unasserted before TMR was transition, 100µA will be required to switch the TMR float- pulled low, and now one of the inputs is invalid when TMR ing state to ground or V1. Connecting the TMR pin to any is released, RST will assert after a t propagation delay PL,LR voltage other than ground or V1 may have unpredictable (see Figure 6a). Conversely, if RST was asserted (low) results. LATCH RELEASE LATCH RELEASE TMR VTMR(LATCH) VTMR(LATCH) + ∆VTMR TMR VTRM(LATCH) V∆TVMTMR(RLATCH) + ADJ, V1, V2 VRTX ADJ, V1, V2 VRTX tRST RST 1.0V t < tRST RST 1.0V t > tSU,MON 2911 F06a 2911 F06c tP,LR Figure 6c. Timer Latched Before Timeout. After Latch Release, Figure 6a. Input Toggled Low While Timer Latched. RST Stays Low for a Full Timeout Before Going High RST Goes Low t After Latch Release P,LR LATCH RELEASE LATCH RELEASE TMR VTMR(LATCH) V∆TVMTMR(RLATCH) + TMR VTRM(LATCH) V+ T∆MVRT(MLARTCH) MARGINING ADJ, V1, V2 VRTX ADJ, V1, V2 VTRX t > tHD,MON t > tSU,MON tRST tRST t > tSU,MON 2911 F06d RST 1.0V RST 1.0V 2911 F06b NO RECOUNTING t > tRST Figure 6b. Input Toggled High While Timer Latched. Figure 6d. Timer Latched After Timeout and RST High. RST Goes High t After Latch Release RST Stays High After Margining if Inputs are Restored RST Before Release 2911f 14

LTC2911 APPLICATIONS INFORMATION During power-up, with a capacitor connected to the TMR Output Pin Characteristics pin, the part remains in the reset latch mode described The DC characteristics of the RST and PFO pull-down above until the 2.2µA flowing out of the TMR pin charges strength are shown in the Typical Performance Character- the capacitor beyond the V threshold. For this TMR(LATCH) istics. The circuits that drive the pull-down of the output reason, large capacitors will extend the RST timeout during pins are powered by the internal V (the greater voltage power-up. For example, if C = 1µF, the LTC2911 leaves CC TMR of V1 or V2). During power-up, a V of at least 0.5V en- the reset latch mode 90ms after power-up and the RST CC sures a low output state. The V voltage depends on the pin goes high after a 9 second timeout. OL current sunk by RST and PFO as shown in the Figure 8. Figures 7a and 7b show how the TMR pin can be driven The open-drain nature of the RST and PFO pins allows for low to latch the state of the RST pin or floated or driven wire-ORed connections. For example, multiple LTC2911s high for external and internal reset timing, respectively. may be wire-ORed to monitor additional supplies, or open- drain logic can be connected to allow other conditions to TMR issue the reset and/or power-fail signals. SYSTEM LOGIC Output Pin Rise and Fall Time 2911 F07a The open-drain output pins (RST and PFO) contain weak Figure 7a. Open-Drain (or Three-State Buffer) Output. pull-up circuitry to V1. Use an external pull-up resistor Grounds TMR to Latch the State of RST. Floats TMR for External Reset Timing when the outputs need to pull beyond V1 and/or require a faster rise time. Use external pull-up resistor values of 100k or less. V1 When output pins are externally pulled up to voltages higher SYSTEM TMR than V1, an internal network automatically protects the LOGIC weak pull-up circuitry from reverse currents. For a given 2911 F07b external load capacitance or C , the rise and fall times LOAD Figure 7b. V1 Powered Inverter. Grounds TMR can be estimated using Figure 9. The output pins have very to Latch the State of RST. Drives TMR High for strong pull-down capability. With a 150pF load capacitance Internal Reset Timing the reset line can pull down in about 30ns. 2000 10m VCC = 0.5V 1m mV)1600 tRISE LTC2911-1 W ( 100µ O s) TAGE OUTPUT L1280000 t OR t (FALLRISE101001µnµ tFALL LTC2911-1 L O V 400 10n 0 1n 0 10 20 30 40 50 60 70 80 90 100 10p 100p 1n 10n ISINK (µA) CLOAD (F) 2911 F08 2911 F09 Figure 8. Voltage Output Low vs I at V = 0.5V Figure 9. t and t vs C SINK CC RISE FALL LOAD 2911f 15

LTC2911 TYPICAL APPLICATIONS Triple Supply Monitor and Overtemperature Signal 3.3V 3.3V 5V 5V 12V 12V VTRIP = 10.75V RESET V1 RST LTC2911-1 OVERTEMP V2 PFO R4 0.1µF TRIP TEMPERATURE = 90°C 200k RECOVER TEMPERATURE = 89°C PFI R2 2.05M R3 C1** ADJ TMR 270k R31* 10nF R1 GND CTMR 2.2nF 100k 2911 TA02 tRST = 20ms *THERMISTOR MURATA NTC NCP15WM474J03RC TOLERANCE 5%. NTC RESISTANCE IS 474k AT ROOM, 35.8k AT 85°C **OPTIONAL BYPASS CAPACITOR FOR SUPPLY TRANSIENT NOISE FILTERING Quad Supply Monitor 3.3V V1 RST RESET 0.1µF LTC2911-2 2.5V V2 PFO R4 806k 5V PFI R5 R6 VTRIP = 4.53V R3 1.62M 383k 100k 12V ADJ TMR VTRIP = 10.5V R1 GND CTMR 100k 2.2nF D1 tRST = 20ms BAS119 2911 TA03 2911f 16

LTC2911 TYPICAL APPLICATIONS 48V Telecom UV/OV Monitor with Hysteresis VIN 36V TO 72V RCC 27k 0.25W R2A 0.1µF 1.43M 5.6V 16V 5V M1 TMRV1 V2 R2B RPU1 169k R4 LTC2911-1 10k 1.87M UV ADJ RST R1 OV 18.7k PFI PFO R3 GND 13.7k 2911 TA04 M1: FDG6301N OR SIMILAR VUV(RISING) = 43.3V VUV(FALLING) = 38.7V VOV(RISING) = 70.8V VOV(FALLING) = 68.8V 4-Cell NiMH Stack Voltage Monitor with Input Overvoltage Signaling 1N5817 FROM CHARGER + 0.1µF 1.2V V1 V2 + TMR 1.2V R5726k R1.418M LTC2911-2 LOBAT + ADJ RST 1.2V OV PFI PFO + 1.2V R1 R3 GND 100k 102k tRST = 200ms BATTERY LOW RESET THRESHOLD = 3.38V 2911 TA05 OVERVOLTAGE TRIP THRESHOLD = 6.47V OVERVOLTAGE RECOVER THRESHOLD = 6.28V 4-Cell Alkaline Stack Voltage Monitor with Early Power-Fail Warning + 0.1µF 1.5V V1 V2 + TMR 1.5V RC 665k LTC2911-2 RESET + ADJ RST 1.5V RB 15k LOBAT + PFI PFO 1.5V RA GND 100k tRST = 200ms 2911 TA06 POWER-FAIL FALLING THRESHOLD = 3.90V POWER-FAIL RISING THRESHOLD = 4.02V RESET THRESHOLD = 3.39V 2911f 17

LTC2911 PACKAGE DESCRIPTION TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637) 2.90 BSC 0.52 0.65 (NOTE 4) MAX REF 1.22 REF 1.50 – 1.75 3.85 MAX2.62 REF 1.4 MIN 2.80 BSC (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT 0.22 – 0.36 0.65 BSC PER IPC CALCULATOR 8 PLCS (NOTE 3) 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 1.95 BSC 0.09 – 0.20 (NOTE 3) TS8 TSOT-23 0802 NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 2911f 18

LTC2911 PACKAGE DESCRIPTION DDB Package 8-Lead Plastic DFN (3mm × 2mm) (Reference LTC DWG # 05-08-1702 Rev B) 0.61 ±0.05 (2 SIDES) 0.70 ±0.05 2.55 ±0.05 1.15 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.20 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 ±0.10 R = 0.115 0.40 ± 0.10 R = 0.05 TYP (2 SIDES) TYP 5 8 2.00 ±0.10 PIN 1 BAR (2 SIDES) PIN 1 TOP MARK R = 0.20 OR (SEE NOTE 6) 0.56 ± 0.05 0.25 × 45° (2 SIDES) 4 1 CHAMFER (DDB8) DFN 0905 REV B 0.200 REF 0.75 ±0.05 0.25 ± 0.05 0.50 BSC 2.15 ±0.05 (2 SIDES) 0 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2911f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 19 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC2911 TYPICAL APPLICATION Triple Supply Monitor with Early Power-Fail Warning (With Manual Reset and Latchable Reset for Margining) 3.3V DC/DC 1.8V SYSTEM CONVERTER 1.0V LOGIC VTRIP = 0.88V RESET V1 RST 0.1µF LTC2911-3 LOBAT RESD* R2 V2 PFO 10k 76.8k VTRIP = 3.37V ADJ R4 R1 + 1.43M 100k VN2222 Li-Ion PFI TMR RST_LATCH R3 GND CTMR SIGNAL HIGH 249k 2.2nF TO PERFORM MARGINING *OPTIONAL RESISTOR FOR ADDED ESD PROTECTION 2911 TA07 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1326/LTC1326-2.5 Micropower Precision Triple Supply Monitor for 5V/2.5V, 4.725V, 3.118V, 1V Threshold (±0.75%) 3.3V and ADJ LTC1536 Precision Triple Supply Monitor for PCI Applications Meets PCI t Timing Specifications FAIL LTC1726-2.5/LTC1726-5 Micropower Triple Supply Monitor for 2.5V/5V, 3.3V Adjustable Reset and Watchdog Timeouts and ADJ LTC1727/LTC1728 Micropower Triple Supply Monitor With Open-Drain Reset Individual Monitor Outputs in MSOP/5-Lead SOT-23 LTC1985-1.8 Micropower Triple Supply Monitor with Push-Pull Reset 5-Lead SOT-23 Package Output LTC2909 Precision, Triple/Dual Input UV, OV and Negative Voltage 8-Lead SOT-23 and DFN Packages Monitor LTC2912/LTC2913/ Single/Dual/Quad UV and OV Voltage Monitors Separate V Pin, Adjustable Reset Timer, H-Grade Temperature CC LTC2914 Range LTC2915/LTC2916/ Single Voltage Monitor With 27 Unique Thresholds Manual Reset, Watchdog, TSOT-8/MSOP-10 and 3mm × 2mm DFN LTC2917/LTC2918 Packages, H-Grade Temperature Range LTC2919 Precision, Triple/Dual Input UV, OV and Negative Voltage 10-Lead 3mm × 2mm and MSOP Packages, H-Grade Temperature Monitor Range (Individual Outputs for ADJ Comparators and System RST) 2911f 20 Linear Technology Corporation LT 0910 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2010