LTC2637 2 Octal 12-/10-/8-Bit I C V OUT DACs with 10ppm/°C Reference FEATURES DESCRIPTION n Integrated Precision Reference: The LTC®2637 is a family of octal 12-, 10-, and 8-bit 2.5V Full-Scale 10ppm/°C (LTC2637-L) voltage-output DACs with an integrated, high-accuracy, 4.096V Full-Scale 10ppm/°C (LTC2637-H) low-drift 10ppm/°C reference in 14-lead DFN and 16-lead n Maximum INL Error: 2.5LSB (LTC2637-12) MSOP packages. It has a rail-to-rail output buffer and is n Low Noise: 0.75mV 0.1Hz to 200kHz guaranteed monotonic. The LTC2637-L has a full-scale P-P n Guaranteed Monotonic Over –40°C to 125°C output of 2.5V, and operates from a single 2.7V to 5.5V Temperature Range supply. The LTC2637-H has a full-scale output of 4.096V, n Selectable Internal or External Reference and operates from a 4.5V to 5.5V supply. Each DAC can n 2.7V to 5.5V Supply Range (LTC2637-L) also operate with an external reference, which sets the n Ultralow Crosstalk Between DACs (<3nV•s) DAC full-scale output to the external reference voltage. n Low Power: 100µA per DAC at 3V (LTC2637-L) These DACs communicate via a 2-wire I2C-compatible n Power-On-Reset to Zero-Scale/Mid-Scale serial interface. The LTC2637 operates in both the stan- n Double-Buffered Data Latches dard mode (clock rate of 100kHz) and the fast mode (clock n Tiny 14-Lead 4mm × 3mm DFN and 16-Lead MSOP rate of 400kHz). The LTC2637 incorporates a power-on Packages reset circuit. Options are available for reset to zero-scale APPLICATIONS or reset to mid-scale in internal reference mode, or reset n Mobile Communications to mid-scale in external reference mode after power-up. n Process Control and Industrial Automation All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 5396245, 5859606, 6891433, 6937178, 7414561. n Automatic Test Equipment n Portable Equipment n Automotive n Optical Networking BLOCK DIAGRAM Integral Nonlinearity (LTC2637-LZ12) INTERNAL REFERENCE SWITCH REF GND VREF 2 VCC VINCTCE =R N3VAL REF. R R R R VOUTA DAC A GISTE GISTE GISTE GISTE DAC H VOUTH 1 RE RE RE RE VREF VREF SB) VOUTB DAC B GISTER GISTER GISTER GISTER DAC G VOUTG INL (L 0 RE RE RE RE VREF VREF –1 R R R R VOUTC DAC C GISTE GISTE GISTE GISTE DAC F VOUTF RE RE RE RE –2 VREF VREF 0 1024 2048 3072 4095 R R R R CODE VOUTD DAC D GISTE GISTE GISTE GISTE DAC E VOUTE 2637 TA01 RE RE RE RE POWER-ON RESET CAO (CA1) I2C DECODE SCL ADDRESS DECODE (CA2) SDA I2C INTERFACE 2637 BD ( ) MSOP PACKAGE ONLY Rev D 1 Document Feedback For more information www.analog.com

LTC2637 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (V ) ...................................–0.3V to 6V LTC2637I .............................................–40°C to 85°C CC SCL, SDA .....................................................–0.3V to 6V LTC2637H (Note 3) ............................–40°C to 125°C V - V , Maximum Junction Temperature ..........................150°C OUTA OUTH CA0, CA1, CA2 ...................–0.3V to Min(V + 0.3V, 6V) Storage Temperature Range ..................–65°C to 150°C CC REF ...................................–0.3V to Min(V + 0.3V, 6V) Lead Temperature (Soldering, 10 sec) CC Operating Temperature Range MS Package ......................................................300°C LTC2637C ................................................0°C to 70°C PIN CONFIGURATION TOP VIEW VCC 1 14 GND TOP VIEW VOUTA 2 13 VOUTH VCC 1 16 GND VOUTB 3 12 VOUTG VVOOUUTTAB 23 1154 VVOOUUTTHG VVOOUUTTDC 45 15 1110 VVOOUUTTFE VVOOCUUATTD2C 456 111321 VVROOEUUFTTFE CA0 6 9 REF CA0 7 10 CA1 SCL 8 9 SDA SCL 7 8 SDA MS PACKAGE DE PACKAGE 16-LEAD (4mm × 5mm) PLASTIC MSOP 14-LEAD (4mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 110°C/W TJMAX = 150°C, θJA = 37°C/W EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB Rev D 2 For more information www.analog.com

LTC2637 ORDER INFORMATION http://www.linear.com/product/LTC2637#orderinfo LTC2637 C DE –L Z 12 #TR PBF LEAD FREE DESIGNATOR TAPE AND REEL TR = 2500-Piece Tape and Reel RESOLUTION 12 = 12-Bit 10 = 10-Bit 8 = 8-Bit POWER-ON RESET MI = Reset to Mid-Scale in Internal Reference Mode MX = Reset to Mid-Scale in External Reference Mode Z = Reset to Zero-Scale in Internal Reference Mode FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE L = 2.5V H = 4.096V PACKAGE TYPE DE = 14-Lead DFN MS = 16-Lead MSOP TEMPERATURE GRADE C = Commercial Temperature Range (0°C to 70°C) I = Industrial Temperature Range (–40°C to 85°C) H = Automotive Temperature Range (–40°C to 125°C) PRODUCT PART NUMBER Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Rev D 3 For more information www.analog.com

LTC2637 PRODUCT SELECTION GUIDE PART MARKING* POWER-ON V WITH INTERNAL POWER-ON REFERENCE MAXIMUM FS PART NUMBER DFN MSOP REFERENCE RESET TO CODE MODE RESOLUTION V INL CC LTC2637-LMI12 7LMI2 7LMI12 2.5V • (4095/4096) Mid-Scale Internal 12-Bit 2.7V to 5.5V ±2.5LSB LTC2637-LMI10 7LMI1 7LMI10 2.5V • (1023/1024) Mid-Scale Internal 10-Bit 2.7V to 5.5V ±1LSB LTC2637-LMI8 7LMI8 37LMI8 2.5V • (255/256) Mid-Scale Internal 8-Bit 2.7V to 5.5V ±0.5LSB LTC2637-LMX12 7LMX2 7LMX12 2.5V • (4095/4096) Mid-Scale External 12-Bit 2.7V to 5.5V ±2.5LSB LTC2637-LMX10 7LMX1 7LMX10 2.5V • (1023/1024) Mid-Scale External 10-Bit 2.7V to 5.5V ±1LSB LTC2637-LMX8 7LMX8 37LMX8 2.5V • (255/256) Mid-Scale External 8-Bit 2.7V to 5.5V ±0.5LSB LTC2637-LZ12 7LZ12 37LZ12 2.5V • (4095/4096) Zero-Scale Internal 12-Bit 2.7V to 5.5V ±2.5LSB LTC2637-LZ10 7LZ10 37LZ10 2.5V • (1023/1024) Zero-Scale Internal 10-Bit 2.7V to 5.5V ±1LSB LTC2637-LZ8 37LZ8 637LZ8 2.5V • (255/256) Zero-Scale Internal 8-Bit 2.7V to 5.5V ±0.5LSB LTC2637-HMI12 7HMI2 7HMI12 4.096V • (4095/4096) Mid-Scale Internal 12-Bit 4.5V to 5.5V ±2.5LSB LTC2637-HMI10 7HMI1 7HMI10 4.096V • (1023/1024) Mid-Scale Internal 10-Bit 4.5V to 5.5V ±1LSB LTC2637-HMI8 7HMI8 37HMI8 4.096V • (255/256) Mid-Scale Internal 8-Bit 4.5V to 5.5V ±0.5LSB LTC2637-HMX12 7HMX2 7HMX12 4.096V • (4095/4096) Mid-Scale External 12-Bit 4.5V to 5.5V ±2.5LSB LTC2637-HMX10 7HMX1 7HMX10 4.096V • (1023/1024) Mid-Scale External 10-Bit 4.5V to 5.5V ±1LSB LTC2637-HMX8 7HMX8 37HMX8 4.096V • (255/256) Mid-Scale External 8-Bit 4.5V to 5.5V ±0.5LSB LTC2637-HZ12 7HZ12 37HZ12 4.096V • (4095/4096) Zero-Scale Internal 12-Bit 4.5V to 5.5V ±2.5LSB LTC2637-HZ10 7HZ10 37HZ10 4.096V • (1023/1024) Zero-Scale Internal 10-Bit 4.5V to 5.5V ±1LSB LTC2637-HZ8 37HZ8 637HZ8 4.096V • (255/256) Zero-Scale Internal 8-Bit 4.5V to 5.5V ±0.5LSB *Above options are available in a 14-lead DFN package (LTC2637xDE) or 16-lead MSOP package (LTC2637xMS). Rev D 4 For more information www.analog.com

LTC2637 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 2.7V to 5.5V, V unloaded unless otherwise specified. A CC OUT LTC2637-LMI12/ LTC2637-LMI10/ LTC2637-LMI8/ LTC2637-LMX12/ LTC2637-LMX10/ LTC2637-LMX8/ LTC2637-LZ12/ LTC2637-LZ10/ LTC2637-LZ8 (V = 2.5V) FS LTC2637-8 LTC2637-10 LTC2637-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Resolution l 8 10 12 Bits Monotonicity V = 3V, Internal Reference (Note 4) l 8 10 12 Bits CC DNL Differential Nonlinearity V = 3V, Internal Reference (Note 4) l ±0.5 ±0.5 ±1 LSB CC INL Integral Nonlinearity V = 3V, Internal Reference (Note 4) l ±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 LSB CC ZSE Zero-Scale Error V = 3V, Internal Reference, Code = 0 l 0.5 5 0.5 5 0.5 5 mV CC V Offset Error V = 3V, Internal Reference (Note 5) l ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV OS CC V V Temperature V =3V, Internal Reference ±10 ±10 ±10 µV/°C OSTC OS CC Coefficient GE Gain Error V = 3V, Internal Reference l ±0.2 ±0.8 ±0.2 ±0.8 ±0.2 ±0.8 %FSR CC GE Gain Temperature V = 3V, Internal Reference (Note 10) TC CC Coefficient C-Grade 10 10 10 ppm/°C I-Grade 10 10 10 ppm/°C H-Grade 10 10 10 ppm/°C Load Regulation Internal Reference, Mid-Scale, V = 3V±10%, l 0.009 0.016 0.035 0.064 0.14 0.256 LSB/ CC –5mA ≤ I ≤ 5mA mA OUT V = 5V±10%, (Note 15) l 0.009 0.016 0.035 0.064 0.14 0.256 CC –10mA ≤ I ≤ 10mA LSB/ OUT mA R DC Output Impedance Internal Reference, Mid-Scale, OUT V = 3V±10%, l 0.09 0.156 0.09 0.156 0.09 0.156 Ω CC –5mA ≤ I ≤ 5mA OUT V = 5V±10%, (Note 15) l 0.09 0.156 0.09 0.156 0.09 0.156 Ω CC –10mA ≤ I ≤ 10mA OUT SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V DAC Output Span External Reference 0 to V V OUT REF Internal Reference 0 to 2.5 V PSR Power Supply Rejection V = 3V±10% or 5V±10% –80 dB CC I Short Circuit Output Current (Note 6) V = V = 5.5V SC FS CC Sinking Zero-Scale; V shorted to V l 27 48 mA OUT CC Sourcing Full-Scale; V shorted to GND l –28 –48 mA OUT Power Supply V Positive Supply Voltage For Specified Performance l 2.7 5.5 V CC I Supply Current (Note 7) V = 3V, V =2.5V, External Reference l 0.8 1.1 mA CC CC REF V = 3V, Internal Reference l 0.9 1.3 mA CC V = 5V, V =2.5V, External Reference l 0.9 1.3 mA CC REF V = 5V, Internal Reference l 1 1.5 mA CC I Supply Current in Power-Down Mode V = 5V, C-Grade, I-Grade l 1 20 µA SD CC (Note 7) V = 5V, H-Grade l 1 30 µA CC Rev D 5 For more information www.analog.com

LTC2637 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 2.7V to 5.5V, V unloaded unless otherwise specified. A CC OUT LTC2637-LMI12/ LTC2637-LMI10/ LTC2637-LMI8/ LTC2637-LMX12/ LTC2637-LMX10/ LTC2637-LMX8/ LTC2637-LZ12/ LTC2637-LZ10/ LTC2637-LZ8 (V = 2.5V) FS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Reference Input Input Voltage Range l 1 V V CC Resistance l 120 160 200 kΩ Capacitance 12 pF I Reference Current, Power-Down Mode DAC Powered Down l 0.005 1.5 µA REF Reference Output Output Voltage l 1.24 1.25 1.26 V Reference Temperature Coefficient ±10 ppm/°C Output Impedance 0.5 kΩ Capacitive Load Driving 10 µF Short Circuit Current V = 5.5V; REF Shorted to GND 2.5 mA CC Digital I/O V Low Level Input Voltage (SDA and SCL) (Note 14) l –0.5 0.3V V IL CC V High Level Input Voltage (SDA and SCL) (Note 11) l 0.7V V IH CC VIL(CAn) Low Level Input Voltage on CAn See Test Circuit 1 l 0.15VCC V (n = 0, 1, 2) VIH(CAn) High Level Input Voltage on CAn See Test Circuit 1 l 0.85VCC V (n = 0, 1, 2) RINH Resistance from CAn (n=0, 1,2) See Test Circuit 2 l 10 kΩ to VCC to Set CAn = VCC RINL Resistance from CAn (n=0, 1,2) See Test Circuit 2 l 10 kΩ to GND to Set CAn = GND RINF Resistance from CAn (n=0, 1,2) See Test Circuit 2 l 2 MΩ to VCC or GND to Set CAn = Float V Low Level Output Voltage Sink Current = 3mA l 0 0.4 V OL t Output Fall Time V = V to V = V , l 20 + 0.1C 250 ns OF O IH(MIN) O IL(MAX) B C = 10pF to 400pF (Note 12) B t Pulse Width of Spikes Suppressed l 0 50 ns SP by Input Filter I Input Leakage 0.1V ≤ V ≤ 0.9V l ±1 µA IN CC IN CC C I/O Pin Capacitance (Note 8) l 10 pF IN C Capacitive Load for Each Bus Line l 400 pF B C External Capacitive Load on Address l 10 pF CAn Pin CAn (n=0, 1,2) Rev D 6 For more information www.analog.com

LTC2637 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 2.7V to 5.5V, V unloaded unless otherwise specified. A CC OUT LTC2637-LMI12/ LTC2637-LMI10/ LTC2637-LMI8/ LTC2637-LMX12/ LTC2637-LMX10/ LTC2637-LMX8/ LTC2637-LZ12/ LTC2637-LZ10/ LTC2637-LZ8 (V = 2.5V) FS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS AC Performance t Settling Time V = 3V (Note 9) S CC ±0.39% (±1LSB at 8 Bits) 3.5 µs ±0.098% (±1LSB at 10 Bits) 4.1 µs ±0.024% (±1LSB at 12 Bits) 4.5 µs Voltage Output Slew Rate 1.0 V/µs Capacitive Load Driving 500 pF Glitch Impulse At Mid-Scale Transition 2.1 nV•s DAC-to-DAC Crosstalk 1 DAC held at FS, 1 DAC Switched 0 to FS 2.6 nV•s Multiplying Bandwidth External Reference 320 kHz e Output Voltage Noise Density At f = 1kHz, External Reference 180 nV/√Hz n At f = 10kHz, External Reference 160 nV/√Hz At f = 1kHz, Internal Reference 200 nV/√Hz At f = 10kHz, Internal Reference 180 nV/√Hz Output Voltage Noise 0.1Hz to 10Hz, External Reference 35 µV P-P 0.1Hz to 10Hz, Internal Reference 40 µV P-P 0.1Hz to 200kHz, External Reference 680 µV P-P 0.1Hz to 200kHz, Internal Reference 730 µV P-P TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 2.7V to 5.5V. (See Figure 1) (Note 13) A CC LTC2637-LMI12/ LTC2637-LMI10/ LTC2637-LMI8/ LTC2637-LMX12/ LTC2637-LMX10/ LTC2637-LMX8/ LTC2637-LZ12/ LTC2637-LZ10/ LTC2637-LZ8 (V = 2.5V) FS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f SCL Clock Frequency l 0 400 kHz SCL t Hold Time (Repeated) Start Condition l 0.6 µs HD(STA) t Low Period of the SCL Clock Pin l 1.3 µs LOW t High Period of the SCL Clock Pin l 0.6 µs HIGH t Set-Up Time for a Repeated Start Condition l 0.6 µs SU(STA) t Data Hold Time l 0 0.9 µs HD(DAT) t Data Set-Up Time l 100 ns SU(DAT) t Rise Time of Both SDA and SCL Signals (Note 12) l 20 + 0.1C 300 ns r B t Fall Time of Both SDA and SCL Signals (Note 12) l 20 + 0.1C 300 ns f B t Set-Up Time for Stop Condition l 0.6 µs SU(STO) t Bus Free Time Between a Stop and Start Condition l 1.3 µs BUF Rev D 7 For more information www.analog.com

LTC2637 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 4.5V to 5.5V, V unloaded unless otherwise specified. A CC OUT LTC2637-HMI12/ LTC2637-HMI10/ LTC2637-HMI8/ LTC2637-HMX12/ LTC2637-HMX10/ LTC2637-HMX8/ LTC2637-HZ12/ LTC2637-HZ10/ LTC2637-HZ8 (V =4.096V) FS LTC2637-8 LTC2637-10 LTC2637-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Resolution l 8 10 12 Bits Monotonicity V = 5V, Internal Reference (Note 4) l 8 10 12 Bits CC DNL Differential V = 5V, Internal Reference (Note 4) l ±0.5 ±0.5 ±1 LSB CC Nonlinearity INL Integral Nonlinearity V = 5V, Internal Reference (Note 4) l ±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 LSB CC ZSE Zero-Scale Error V = 5V, Internal Reference, Code = 0 l 0.5 5 0.5 5 0.5 5 mV CC V Offset Error V = 5V, Internal Reference (Note 5) l ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV OS CC V V Temperature V = 5V, Internal Reference ±10 ±10 ±10 µV/°C OSTC OS CC Coefficient GE Gain Error V = 5V, Internal Reference l ±0.2 ±0.8 ±0.2 ±0.8 ±0.2 ±0.8 %FSR CC GE Gain Temperature V = 5V, Internal Reference (Note 10) TC CC Coefficient C-Grade 10 10 10 ppm/°C I-Grade 10 10 10 ppm/°C H-Grade 10 10 10 ppm/°C Load V = 5V±10%, (Note 15) l 0.006 0.01 0.022 0.04 0.09 0.16 LSB/mA CC Regulation Internal Reference, Mid-Scale, –10mA ≤ I ≤ 10mA OUT R DC Output V = 5V±10%, (Note 15) l 0.09 0.156 0.09 0.156 0.09 0.156 Ω OUT CC Impedance Internal Reference, Mid-Scale, –10mA ≤ I ≤ 10mA OUT SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V DAC Output Span External Reference 0 to V V OUT REF Internal Reference 0 to 4.096 V PSR Power Supply Rejection V = 5V±10% –80 dB CC I Short Circuit Output Current (Note 6) V = V = 5.5V SC FS CC Sinking Zero-Scale; V Shorted to V l 27 48 mA OUT CC Sourcing Full-Scale; V Shorted to GND l –28 –48 mA OUT Power Supply V Positive Supply Voltage For Specified Performance l 4.5 5.5 V CC I Supply Current (Note 7) V = 5V, V = 4.096V, External Reference l 1.0 1.3 mA CC CC REF V = 5V, Internal Reference l 1.1 1.5 mA CC I Supply Current in Power-Down Mode V = 5V, C-Grade, I-Grade l 1 20 µA SD CC (Note 7) V = 5V, H-Grade l 1 30 µA CC Reference Input Input Voltage Range l 1 V V CC Resistance l 120 160 200 kΩ Capacitance 12 pF I Reference Current, Power-Down Mode DAC Powered Down l 0.005 1.5 µA REF Reference Output Output Voltage l 2.032 2.048 2.064 V Reference Temperature Coefficient ±10 ppm/°C Rev D 8 For more information www.analog.com

LTC2637 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 4.5V to 5.5V, V unloaded unless otherwise specified. A CC OUT LTC2637-HMI12/ LTC2637-HMI10/ LTC2637-HMI8/ LTC2637-HMX12/ LTC2637-HMX10/ LTC2637-HMX8/ LTC2637-HZ12/ LTC2637-HZ10/ LTC2637-HZ8 (V =4.096V) FS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Output Impedance 0.5 kΩ Capacitive Load Driving 10 µF Short Circuit Current V = 5.5V; REF Shorted to GND 4 mA CC Digital I/O V Low Level Input Voltage (SDA and SCL) (Note 14) l –0.5 0.3V V IL CC V High Level Input Voltage (SDA and SCL) (Note 11) l 0.7V V IH CC VIL(CAn) Low Level Input Voltage on CAn See Test Circuit 1 l 0.15VCC V (n = 0, 1, 2) VIH(CAn) High Level Input Voltage on CAn See Test Circuit 1 l 0.85VCC V (n = 0, 1, 2) RINH Resistance from CAn (n=0, 1,2) See Test Circuit 2 l 10 kΩ to VCC to Set CAn = VCC RINL Resistance from CAn (n=0, 1,2) See Test Circuit 2 l 10 kΩ to GND to Set CAn = GND RINF Resistance from CAn (n=0, 1,2) See Test Circuit 2 l 2 MΩ to VCC or GND to Set CAn = Float V Low Level Output Voltage Sink Current = 3mA l 0 0.4 V OL t Output Fall Time V = V to V = V , l 20 + 0.1C 250 ns OF O IH(MIN) O IL(MAX) B C = 10pF to 400pF (Note 12) B t Pulse Width of Spikes Suppressed l 0 50 ns SP by Input Filter I Input Leakage 0.1V ≤ V ≤ 0.9V l ±1 µA IN CC IN CC C I/O Pin Capacitance (Note 8) l 10 pF IN C Capacitive Load for Each Bus Line l 400 pF B C External Capacitive Load on Address l 10 pF CAn Pin CAn (n=0, 1,2) AC Performance t Settling Time V = 3V (Note 9) S CC ±0.39% (±1LSB at 8 Bits) 3.9 µs ±0.098% (±1LSB at 10 Bits) 4.3 µs ±0.024% (±1LSB at 12 Bits) 5 µs Voltage Output Slew Rate 1 V/µs Capacitive Load Driving 500 pF Glitch Impulse At Mid-Scale Transition 3 nV•s DAC-to-DAC Crosstalk 1 DAC held at FS, 1 DAC Switched 0 to FS 3 nV•s Multiplying Bandwidth External Reference 320 kHz e Output Voltage Noise Density At f = 1kHz, External Reference 180 nV/√Hz n At f = 10kHz, External Reference 160 nV/√Hz At f = 1kHz, Internal Reference 250 nV/√Hz At f = 10kHz, Internal Reference 230 nV/√Hz Output Voltage Noise 0.1Hz to 10Hz, External Reference 35 µV P-P 0.1Hz to 10Hz, Internal Reference 50 µV P-P 0.1Hz to 200kHz, External Reference 680 µV P-P 0.1Hz to 200kHz, Internal Reference 750 µV P-P Rev D 9 For more information www.analog.com

LTC2637 TIMING CHARACTERISTICS The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at T = 25°C. V =4.5V to 5.5V. (See Figure 1) (Note 13). A CC LTC2637-HMI12/ LTC2637-HMI10/ LTC2637-HMI8/ LTC2637-HMX12/ LTC2637-HMX10/ LTC2637-HMX8/ LTC2637-HZ12/ LTC2637-HZ10/ LTC2637-HZ8 (V =4.096V) FS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f SCL Clock Frequency l 0 400 kHz SCL t Hold Time (Repeated) Start Condition l 0.6 µs HD(STA) t Low Period of the SCL Clock Pin l 1.3 µs LOW t High Period of the SCL Clock Pin l 0.6 µs HIGH t Set-Up Time for a Repeated Start Condition l 0.6 µs SU(STA) t Data Hold Time l 0 0.9 µs HD(DAT) t Data Set-Up Time l 100 ns SU(DAT) t Rise Time of Both SDA and SCL Signals (Note 12) l 20 + 0.1C 300 ns r B t Fall Time of Both SDA and SCL Signals (Note 12) l 20 + 0.1C 300 ns f B t Set-Up Time for Stop Condition l 0.6 µs SU(STO) t Bus Free Time Between a Stop and Start Condition l 1.3 µs BUF Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 7: Digital inputs at 0V or V . CC may cause permanent damage to the device. Exposure to any Absolute Note 8: Guaranteed by design and not production tested. Maximum Rating condition for extended periods may affect device Note 9: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale reliability and lifetime. and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND. Note 2: All voltages are with respect to GND. Note 10: Temperature coefficient is calculated by dividing the maximum Note 3: Operating at temperatures above 90°C and with VCC > 4V requires change in output voltage by the specified temperature range. V slew rates to be no greater than 110mV/µs. CC Note 11: Maximum V = V + 0.5V. IH CC(MAX) Note 4: Linearity and monotonicity are defined from code k to code 2N–1, L Note 12: C = Capacitance of one bus line in pF. where N is the resolution and k is given by k = 0.016•(2N/ V ), rounded B L L FS Note 13: All values refer to V = V and V = V levels. to the nearest whole code. For V = 2.5V and N = 12, k = 26 and linearity IH IN(MIN) IL IL(MAX) FS L is defined from code 26 to code 4,095. For VFS = 4.096V and N = 12, kL = Note 14: Minimum VIL exceeds Absolute Maximum rating. This condition 16 and linearity is defined from code 16 to code 4,095. won’t damage the IC, but could degrade performance. Note 5: Inferred from measurement at code 16 (LTC2637-12), code 4 Note 15: Thermal resistance of MSOP package limits IOUT to (LTC2637-10) or code 1 (LTC2637-8), and at full-scale. –5mA ≤ IOUT ≤ 5mA for H-grade MSOP parts and VCC = 5V ±10%. Note 6: This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Rev D 10 For more information www.analog.com

LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. LTC2637-L12 (Internal Reference, V = 2.5V) A FS Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1.0 1.0 VCC = 3V VCC = 3V 0.5 0.5 NL (LSB) 0 NL (LSB) 0 I D –0.5 –0.5 –1.0 –1.0 0 1024 2048 3072 4095 0 1024 2048 3072 4095 CODE CODE 2637 G01 2637 G02 Reference Output Voltage INL vs Temperature DNL vs Temperature vs Temperature 1.0 1.0 1.260 VCC = 3V VCC = 3V VCC = 3V 0.5 INL (POS) 0.5 1.255 INL (LSB) 0 INL (NEG) DNL (LSB) 0 DDNNLL ((PNOEGS)) V (V)REF1.250 –0.5 –0.5 1.245 –1.0 –1.0 1.240 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 2637 G03 2637 G04 2637 G05 Settling to ±1LSB Rising Settling to ±1LSB Falling 3/4 SCALE TO 1/4 SCALE STEP 9TH CLOCK OF SCL 3RD DATA BYTE VCC = 3V, VFS = 2.5V 5V/DIV VOUT RL = 2k, CL = 100pF 1LSB/DIV AVERAGE OF 256 EVENTS 4.5µs 3.6µs VOUT 1/4 SCALE TO 1LSB/DIV 3/4 SCALE STEP SCL 9TH CLOCK OF VCC = 3V, VFS = 2.5V 5V/DIV 3RD DATA BYTE RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2µs/DIV 2637 G06 2µs/DIV 2637 G07 Rev D 11 For more information www.analog.com

LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. LTC2637-H12 (Internal Reference, V = 4.096V) A FS Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1.0 1.0 VCC = 5V VCC = 5V 0.5 0.5 NL (LSB) 0 NL (LSB) 0 I D –0.5 –0.5 –1.0 –1.0 0 1024 2048 3072 4095 0 1024 2048 3072 4095 CODE CODE 2637 G08 2637 G09 Reference Output Voltage INL vs Temperature DNL vs Temperature vs Temperature 1.0 1.0 2.068 VCC = 5V VCC = 5V VCC = 5V 0.5 INL (POS) 0.5 2.058 NL (LSB) 0 NL (LSB) 0 DNL (POS) V (V)REF2.048 I INL (NEG) D DNL (NEG) –0.5 –0.5 2.038 –1.0 –1.0 2.028 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 2637 G10 2637 G11 2637 G12 Settling to ±1LSB Rising Settling to ±1LSB Falling 3/4 SCALE TO 1/4 SCALE STEP 9TH CLOCK OF SCL 3RD DATA BYTE VCC = 5V, VFS = 4.095V 5V/DIV VOUT RL = 2k, CL = 100pF 1LSB/DIV AVERAGE OF 256 EVENTS 5µs 4.1µs 9TH CLOCK OF SCL VOUT 1/4 SCALE TO 5V/DIV 3RD DATA BYTE 1LSB/DIV 3/4 SCALE STEP VCC = 5V, VFS = 4.095V RL = 2k, CL = 100pF AVERAGE OF 256 EVENTS 2µs/DIV 2637 G13 2µs/DIV 2637 G14 Rev D 12 For more information www.analog.com

LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A LTC2637-10 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1.0 1.0 VCC = 3V VCC = 3V VFS = 2.5V VFS = 2.5V INTERNAL REF. INTERNAL REF. 0.5 0.5 NL (LSB) 0 NL (LSB) 0 I D –0.5 –0.5 –1.0 –1.0 0 256 512 768 1023 0 256 512 768 1023 CODE CODE 2637 G15 2637 G16 LTC2637-8 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 0.50 0.50 VCC = 3V VCC = 3V VFS = 2.5V VFS = 2.5V INTERNAL REF. INTERNAL REF. 0.25 0.25 NL (LSB) 0 NL (LSB) 0 I D –0.25 –0.25 –0.50 –0.50 0 64 128 192 255 0 64 128 192 255 CODE CODE 2637 G17 2637 G18 LTC2637 Load Regulation Current Limiting Offset Error vs Temperature 10 0.20 3 VCC = 5V (LTC2637-H) VCC = 5V (LTC2637-H) 8 VCC = 5V (LTC2637-L) 0.15 VCC = 5V (LTC2637-L) 6 VCC = 3V (LTC2637-L) VCC = 3V (LTC2637-L) 2 0.10 4 mV) 1 V (mV)∆OUT–220 V (V)∆OUT–00..00550 SET ERROR ( 0 F–1 –4 OF –0.01 –6 –2 –8 INTERNAL REF. –0.15 INTERNAL REF. CODE = MID-SCALE CODE = MID-SCALE –10 –0.20 –3 –30 –20 –10 0 10 20 30 –30 –20 –10 0 10 20 30 –50 –25 0 25 50 75 100 125 150 IOUT (mA) IOUT (mA) TEMPERATURE (°C) 2637 G19 2637 G20 2637 G21 Rev D 13 For more information www.analog.com

LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A LTC2637 Large-Signal Response Mid-Scale Glitch Impulse Power-On Reset Glitch LTC2637-L 9TH CLOCK OF 3RD DATA BYTE SCL 5V/DIV VCC 2V/DIV VOUT 0.5V/DIV LTC2637-H12 VCC = 5V, 3nV•s TYP VOUT VOUT ZERO-SCALE 5mV/DIV 5mV/DIV LTC2637-L12 VFS = VCC = 5V VCC = 3V, 2.1nV•s TYP 1/4 SCALE to 3/4 SCALE 2µs/DIV 2µs/DIV 2637 G23 200µs/DIV 2637 G22 2637 G24 Headroom at Rails vs Output Current Exiting Power-Down to Mid-Scale Power-On Reset to Mid-Scale 5.0 4.5 5V SOURCING 9TH CLOCK OF 4.0 5V/SDCIVL 3RD DATA BYTE 2V/VDCIVC 3.5 3V (LTC2637-L) SOURCING LTC2637-H 3.0 V) (UT 2.5 O V 2.0 DACs A TO G IN 1.5 POWER-DOWN VOUT 5V SINKING MODE 0.5V/DIV LTC2637-L 1.0 VOUT LTC2637H 0.5 3V (LTC2637-L) SINKING 0.5V/DIV VCC = 5V INTERNAL REF 0 0 1 2 3 4 5 6 7 8 9 10 5µs/DIV 2637 G26 200µs/DIV IOUT (mA) 2637 G27 2637 G25 Supply Current vs Logic Voltage DAC to DAC Crosstalk (Dynamic) Multiplying Bandwidth 1.8 2 SWEEP SDA, SCL, 9TH CLOCK OF BETWEEN 0V AND VCC 3RD DATA BYTE 0 1.6 –2 SCL LTC2637-H12 –4 1.4 5V/DIV VCC = 5V, 3nV•s TYP –6 A) VCC = 5V CREF = 0.1µF (mC 1.2 SWITCH 0 1T OD AFCS dB –8 C I 2V/DIV –10 1.0 VCC = 3V –12 (LTC2637-L) 2mVV/ODUIVT –14 VCC = 5V 0.8 VREF(DC) = 2V –16 VREF(AC) = 0.2VP-P CODE = FULL-SCALE 0.60 1 2 3 4 5 2µs/DIV 2637 G29 –181k 10k 100k 1M LOGIC VOLTAGE (V) FREQUENCY (Hz) 2637 G28 2637 G30 Rev D 14 For more information www.analog.com

LTC2637 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A LTC2637 Gain Error vs. Temperature Noise Voltage vs. Frequency 1.0 500 VCC = 5V CODE = MID-SCALE INTERNAL REF. 400 R (%FSR) 0.5 GE (nV/√Hz) 300 O 0 A LTC2637-H AIN ERR SE VOLT 200 G–0.5 NOI LTC2637-L 100 –1.0 0 –50 –25 0 25 50 75 100 125 150 100 1k 10k 100k 1M TEMPERATURE (°C) FREQUENCY (Hz) 2637 G31 2637 G32 Gain Error vs Reference Input 0.1Hz to 10Hz Voltage Noise 1.0 VCC = 5.5V VCC = 5V, VFS = 2.5V 0.8 GAIN ERROR OF 8 CHANNELS CODE = MID-SCALE INTERNAL REF. 0.6 R) 0.4 S F % 0.2 R ( O 0 10µV/DIV R R N E –0.2 GAI –0.4 –0.6 –0.8 –1.0 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 1s/DIV REFERENCE VOLTAGE (V) 2637 G35 2637 G34 Rev D 15 For more information www.analog.com

LTC2637 PIN FUNCTIONS (DFN/MSOP) V (Pin 1/Pin 1): Supply Voltage Input. 2.7V ≤ V ≤ 5.5V REF (Pin 9/Pin 11): Reference Voltage Input or Output. CC CC (LTC2637-L) or 4.5V ≤ V ≤ 5.5V (LTC2637-H). Bypass When External Reference mode is selected, REF is an input CC to GND with a 0.1µF capacitor. (1V ≤ V ≤ V ) where the voltage supplied sets the REF CC full-scale DAC output voltage. When Internal Reference V to V (Pins 2–5, 10–13/Pins 2–5, 12–15): DAC OUTA OUTH is selected, the 10ppm/°C 1.25V (LTC2637-L) or 2.048V Analog Voltage Outputs. (LTC2637-H) internal reference (half full-scale) is avail- CAO (Pin 6/Pin 7): Chip Address Bit 0. Tie this pin to VCC, able at the pin. This output may be bypassed to GND with GND or leave it floating to select an I2C slave address for up to 10µF, and must be buffered when driving external the part (See Tables 1 and 2). DC load current. SCL (Pin 7/Pin 8): Serial Clock Input Pin. Data is shifted GND (Pin 14/Pin 16): Ground. into the SDA pin at the rising edges of the clock. This CA2 (Pin 6, MSOP only): Chip Address Bit 2. Tie this high impedance pin requires a pull-up resistor or current pin to V , GND or leave it floating to select an I2C slave source to V . CC CC address for the part (See Table 1). SDA (Pin 8/Pin 9): Serial Data Bidirectional Pin. Data is CA1 (Pin 10, MSOP only): Chip Address Bit 1. Tie this shifted into the SDA pin and acknowledged by the SDA pin to V , GND or leave it floating to select an I2C slave pin. This pin is high impedance while data is shifted in. CC address for the part (See Table 1). Open drain N-channel output during acknowledgment. SDA requires a pull-up resistor or current source to V . Exposed Pad (Pin 15, DFN Only): Ground. Must be CC soldered to PCB Ground. Rev D 16 For more information www.analog.com

LTC2637 BLOCK DIAGRAM INTERNAL REFERENCE SWITCH REF GND VREF VCC R R R R E E E E T T T T VOUTA DAC A GIS GIS GIS GIS DAC H VOUTH E E E E R R R R VREF VREF R R R R E E E E T T T T VOUTB DAC B GIS GIS GIS GIS DAC G VOUTG E E E E R R R R VREF VREF R R R R E E E E T T T T VOUTC DAC C GIS GIS GIS GIS DAC F VOUTF E E E E R R R R VREF VREF R R R R E E E E T T T T VOUTD DAC D GIS GIS GIS GIS DAC E VOUTE E E E E R R R R POWER-ON RESET CAO I2C DECODE SCL (CA1) ADDRESS DECODE (CA2) SDA I2C INTERFACE 2637 BD ( ) MSOP PACKAGE ONLY Rev D 17 For more information www.analog.com

LTC2637 TEST CIRCUITS Test Circuit 1 100Ω CAn VIH(CAn)/VIL(CAn) 2637 TC01 Test Circuit 2 VDD RINH/RINL/RINF CAn GND 2637 TC01b Rev D 18 For more information www.analog.com

LTC2637 TIMING DIAGRAM 2637 F02 CK 9 A X 8 X 7 X 6 BYTE X 5 ATA D D 4 R 3 3 S2637 F01 2 1 tBUF CK 9 A P 8 tr tSP tSU(STO) ATA BYTE 567 action tHD(STA) g 2ND D 34 e Trans min 2 Writ Sr C Ti 1 37 ttfSU(DAT)tr tSU(STA)ttHD(DAT)HIGH S REFER TO V AND V LEVELSIH(MIN)IL(MAX) 2Figure 1. I 1ST DATA BYTE C2C1C0A3A2A1A0ACK 23456789 Figure 2. Typical LTC26 tLOW tHD(STA) OLTAGE LEVEL C3ACK 91 V S ALL W 8 SDA tf SCL A0 7 A1 6 RESS A2 5 D AD A3 4 SLAVE A4 3 A5 2 A6 1 RT STA CL S Rev D 19 For more information www.analog.com

LTC2637 OPERATION The LTC2637 is a family of octal voltage output DACs in Transfer Function 14-lead DFN and 16-lead MSOP packages. Each DAC can The digital-to-analog transfer function is: operate rail-to-rail using an external reference, or with its full-scale voltage set by an integrated reference. Eighteen ⎛ k ⎞ V = V combinations of accuracy (12-, 10-, and 8-bit), power-on OUT(IDEAL) ⎝⎜2N⎠⎟ REF reset value (zero-scale, mid-scale in internal reference where k is the decimal equivalent of the binary DAC mode, or mid-scale in external reference mode), and full- input code, N is the resolution, and V is either 2.5V scale voltage (2.5V or 4.096V) are available. The LTC2637 REF is controlled using a 2-wire I2C interface. (LTC2637-LMI/LTC2637-LMX/LTC2637-LZ) or 4.096V (LTC2637-HMI/LTC2637-HMX/LTC2637-HZ) when in Power-On Reset Internal Reference mode, and the voltage at REF when in External Reference mode. The LTC2637-HZ/LTC2637-LZ clear the output to zero- scale when power is first applied, making system initial- I2C Serial Interface ization consistent and repeatable. The LTC2637 communicates with a host using the stan- For some applications, downstream circuits are active dard 2-wire I2C interface. The timing diagrams (Figures during DAC power-up, and may be sensitive to nonzero 1 and 2) show the timing relationship of the signals on outputs from the DAC during this time. The LTC2637 the bus. The two bus lines, SDA and SCL, must be high contains circuitry to reduce the power-on glitch: the when the bus is not in use. External pull-up resistors or analog output typically rises less than 5mV above zero- current sources are required on these lines. The value of scale during power on. In general, the glitch amplitude these pull-up resistors is dependent on the power supply decreases as the power supply ramp time is increased. and can be obtained from the I2C specifications. For an See Power-On Reset Glitch in the Typical Performance I2C bus operating in the fast mode, an active pull-up will Characteristics section. be necessary if the bus capacitance is greater than 200pF. The LTC2637-HMI/LTC2637-HMX/LTC2637-LMI/ The LTC2637 is a receive-only (slave) device. The master LTC2637-LMX provide an alternative reset, setting the can write to the LTC2637. The LTC2637 will not acknowl- output to mid-scale when power is first applied. The edge (NAK) a read request from the master. LTC2637-LMI and LTC2637-HMI power up in internal reference mode, with the output set to a mid-scale volt- START (S) and STOP (P) Conditions age of 1.25V and 2.048V, respectively. The LTC2637- When the bus is not in use, both SCL and SDA must be LMX and LTC2637-HMX power-up in external reference high. A bus master signals the beginning of a communica- mode, with the output set to mid-scale of the external tion to a slave device by transmitting a START condition. A reference. Default reference mode selection is described START condition is generated by transitioning SDA from in the Reference Modes section. high to low while SCL is high. Power Supply Sequencing When the master has finished communicating with the slave, it issues a STOP condition. A STOP condition is The voltage at REF (Pin 9, DFN; Pin 11, MSOP) must be generated by transitioning SDA from low to high while kept within the range –0.3V ≤ V ≤ V + 0.3V (see REF CC SCL is high. The bus is then free for communication with Absolute Maximum Ratings). Particular care should be another I2C device. taken to observe these limits during power supply turn- on and turn-off sequences, when the voltage at V is in CC transition. Rev D 20 For more information www.analog.com

LTC2637 OPERATION Acknowledge Table 1. Slave Address Map (MSOP Package) The Acknowledge (ACK) signal is used for handshaking CA2 CA1 CA0 A6 A5 A4 A3 A2 A1 A0 between the master and the slave. An ACK (active LOW) GND GND GND 0 0 1 0 0 0 0 generated by the slave lets the master know that the lat- GND GND FLOAT 0 0 1 0 0 0 1 est byte of information was properly received. The ACK GND GND V 0 0 1 0 0 1 0 CC related clock pulse is generated by the master. The master GND FLOAT GND 0 0 1 0 0 1 1 releases the SDA line (HIGH) during the ACK clock pulse. GND FLOAT FLOAT 0 1 0 0 0 0 0 The slave-receiver must pull down the SDA bus line dur- GND FLOAT V 0 1 0 0 0 0 1 CC ing the ACK clock pulse so that it remains a stable LOW GND V GND 0 1 0 0 0 1 0 CC during the HIGH period of this clock pulse. The LTC2637 GND V FLOAT 0 1 0 0 0 1 1 CC responds to a write by a master in this manner but does GND V V 0 1 1 0 0 0 0 not acknowledge a read operation; in that case, SDA is CC CC FLOAT GND GND 0 1 1 0 0 0 1 retained HIGH during the period of the ACK clock pulse. FLOAT GND FLOAT 0 1 1 0 0 1 0 Chip Address FLOAT GND VCC 0 1 1 0 0 1 1 FLOAT FLOAT GND 1 0 0 0 0 0 0 The state of pins CA0, CA1 and CA2 (CA1 and CA2 are FLOAT FLOAT FLOAT 1 0 0 0 0 0 1 only available on the MSOP package) determines the FLOAT FLOAT V 1 0 0 0 0 1 0 slave address of the part. These pins can each be set to CC any one of three states: V , GND or float. This results FLOAT VCC GND 1 0 0 0 0 1 1 CC in 27 (MSOP Package) or 3 (DFN Package) selectable FLOAT VCC FLOAT 1 0 1 0 0 0 0 addresses for the part. The slave address assignments FLOAT VCC VCC 1 0 1 0 0 0 1 are shown in Tables 1 and 2. V GND GND 1 0 1 0 0 1 0 CC V GND FLOAT 1 0 1 0 0 1 1 In addition to the address selected by the address pins, CC V GND V 1 1 0 0 0 0 0 the part also responds to a global address. This address CC CC allows a common write to all LTC2637 parts to be accom- VCC FLOAT GND 1 1 0 0 0 0 1 plished using one 3-byte write transaction on the I2C bus. VCC FLOAT FLOAT 1 1 0 0 0 1 0 The global address, listed at the end of Tables 1 and 2, is VCC FLOAT VCC 1 1 0 0 0 1 1 a 7-bit hardwired address not selectable by CA0, CA1 or V V GND 1 1 1 0 0 0 0 CC CC CA2. If another global address is required, please consult V V FLOAT 1 1 1 0 0 0 1 CC CC the factory. V V V 1 1 1 0 0 1 0 CC CC CC The maximum capacitive load allowed on the address pins GLOBAL ADDRESS 1 1 1 0 0 1 1 (CA0, CA1 and CA2) is 10pF, as these pins are driven during address detection to determine if they are floating. Table 2. Slave Address Map (DFN Package) CA0 A6 A5 A4 A3 A2 A1 A0 GND 0 0 1 0 0 0 0 FLOAT 0 0 1 0 0 0 1 V 0 0 1 0 0 1 0 CC GLOBAL ADDRESS 1 1 1 0 0 1 1 Rev D 21 For more information www.analog.com

LTC2637 OPERATION Write Word Protocol Table 3. Command Codes The master initiates communication with the LTC2637 COMMAND* with a START condition and a 7-bit slave address followed C3 C2 C1 C0 by the Write bit (W) = 0. The LTC2637 acknowledges by 0 0 0 0 Write to Input Register n pulling the SDA pin low at the 9th clock if the 7-bit slave 0 0 0 1 Update (Power Up) DAC Register n address matches the address of the part (set by CA0, CA1 0 0 1 0 Write to Input Register n, Update (Power Up) All or CA2) or the global address. The master then transmits 0 0 1 1 Write to and Update (Power Up) DAC Register n three bytes of data. The LTC2637 acknowledges each byte 0 1 0 0 Power Down n of data by pulling the SDA line low at the 9th clock of each 0 1 0 1 Power Down Chip (All DAC’s and Reference) data byte transmission. After receiving three complete 0 1 1 0 Select Internal Reference (Power Up Reference) bytes of data, the LTC2637 executes the command speci- 0 1 1 1 Select External Reference (Power Down Internal fied in the 24-bit input word. Reference) If more than three data bytes are transmitted after a valid 1 1 1 1 No Operation 7-bit slave address, the LTC2637 does not acknowledge *Command codes not shown are reserved and should not be used. the extra bytes of data (SDA is high during the 9th clock). Table 4. Address Codes The format of the three data bytes is shown in Figure 3. The first byte of the input word consists of the 4-bit com- ADDRESS (n)* mand, followed by the 4-bit DAC address. The next two A3 A2 A1 A0 bytes contain the 16-bit data word, which consists of the 0 0 0 0 DAC A 12-, 10- or 8-bit input code, MSB to LSB, followed by 0 0 0 1 DAC B 4, 6 or 8 don’t-care bits (LTC2637-12, LTC2637-10 and 0 0 1 0 DAC C LTC2637-8, respectively). A typical LTC2637 write trans- 0 0 1 1 DAC D action is shown in Figure 4. 0 1 0 0 DAC E The command bit assignments (C3-C0) and address (A3- 0 1 0 1 DAC F A0) assignments are shown in Tables 3 and 4. The first 0 1 1 0 DAC G four commands in the table consist of write and update 0 1 1 1 DAC H operations. A write operation loads a 16-bit data word 1 1 1 1 All DACs from the 32-bit shift register into the input register. In an *Address codes not shown are reserved and should not be used. update operation, the data word is copied from the input register to the DAC register. Once copied into the DAC Reference Modes register, the data word becomes the active 12-, 10-, or For applications where an accurate external reference is 8-bit input code, and is converted to an analog voltage at either not available, or not desirable due to limited space, the DAC output. Write to and Update combines the first the LTC2637 has a user-selectable, integrated reference. two commands. The Update operation also powers up the The integrated reference voltage is internally amplified DAC if it had been in power-down mode. The data path by 2x to provide the full-scale DAC output voltage range. and registers are shown in the Block Diagram. Rev D 22 For more information www.analog.com

LTC2637 OPERATION Write Word Protocol for LTC2637 S SLAVE ADDRESS W ACK 1ST DATA BYTE ACK 2ND DATA BYTE ACK 3RD DATA BYTE ACK P INPUT WORD Input Word (LTC2637-12) C3 C2 C1 C0 A3 A2 A1 A1 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE Input Word (LTC2637-10) C3 C2 C1 C0 A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE Input Word (LTC2637-8) C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X 1ST DATA BYTE 2ND DATA BYTE 3RD DATA BYTE 2637 F03 Figure 3. Command and Data Input Format The LTC2637-LMI/LTC2637-LMX/ LTC2637-LZ provides The reference mode of LTC2637-HZ/LTC2637-LZ/ a full-scale output of 2.5V. The LTC2637-HMI/LTC2637- LTC2637-HMI/LTC2637-LMI (internal reference power- HMX/LTC2637-HZ provides a full-scale output of 4.096V. on default), can be changed by software command after The internal reference can be useful in applications where power up. The same is true for LTC2637-HMX/LTC2637- the supply voltage is poorly regulated. Internal Reference LMX (external reference power-on default). mode can be selected by using command 0110b, and is the power-on default for LTC2637-HZ/ LTC2637-LZ, as Power-Down Mode well as for LTC2637-HMI/LTC2637-LMI. For power-constrained applications, power-down mode The 10ppm/°C, 1.25V (LTC2637-LMI/LTC2637-LMX/ can be used to reduce the supply current whenever less LTC2637-LZ) or 2.048V (LTC2637-HMI/LTC2637-HMX/ than eight DAC outputs are needed. When in power- LTC2637-HZ) internal reference is available at the REF pin. down, the buffer amplifiers, bias circuits, and integrated Adding bypass capacitance to the REF pin will improve reference circuits are disabled, and draw essentially zero noise performance; and up to 10µF can be driven without current. The DAC outputs are put into a high-impedance oscillation. The REF output must be buffered when driving state, and the output pins are passively pulled to ground an external DC load current. through individual 200kΩ resistors. Input and DAC regis- ter contents are not disturbed during power down. Alternatively, the DAC can operate in External Reference mode using command 0111b. In this mode, an input Any DAC channel or combination of channels can be put voltage supplied externally to the REF pin provides the into power-down mode by using command 0100b in com- reference (1V ≤ V ≤ V ) and the supply current is bination with the appropriate DAC address, (n). The sup- REF CC reduced. The external reference voltage supplied sets the ply current is reduced approximately 10% for each DAC full-scale DAC output voltage. External Reference mode is powered down. The integrated reference is automatically the power-on default for LTC2637-HMX/LTC2637-LMX. powered down when external reference is selected using Rev D 23 For more information www.analog.com

LTC2637 OPERATION command 0111b. In addition, all the DAC channels and DC output impedance is equivalent to load regulation, and the integrated reference together can be put into power- may be derived from it by simply calculating a change in down mode using Power Down Chip command 0101b. units from LSB/mA to ohms. The amplifier’s DC output When the integrated reference and all DAC channels are impedance is 0.1Ω when driving a load well away from in power-down mode, the REF pin becomes high imped- the rails. ance (typically > 1GΩ). For all power-down commands When drawing a load current from either rail, the output the 16-bit data word is ignored. voltage headroom with respect to that rail is limited by the Normal operation resumes after executing any command 50Ω typical channel resistance of the output devices (e.g., that includes a DAC update, (as shown in Table 1). The when sinking 1mA, the minimum output voltage is 50Ω selected DAC is powered up as its voltage output is up- • 1mA, or 50mV). See the graph Headroom at Rails vs dated. When a DAC which is in a powered-down state is Output Current in the Typical Performance Characteristics powered up and updated, normal settling is delayed. If section. less than eight DACs are in a powered-down state prior The amplifier is stable driving capacitive loads of up to to the update command, the power-up delay time is 10µs. 500pF. However, if all eight DACs and the integrated reference are powered down, then the main bias generation circuit Rail-to-Rail Output Considerations block has been automatically shut down in addition to In any rail-to-rail voltage output device, the output is lim- the DAC amplifiers and reference buffers. In this case, ited to voltages within the supply range. the power up delay time is 12µs. The power-up of the integrated reference depends on the command that pow- Since the analog output of the DAC cannot go below ered it down. If the reference is powered down using the ground, it may limit for the lowest codes as shown in Select External Reference Command (0111b), then it can Figure 5b. Similarly, limiting can occur near full scale only be powered back up using Select Internal Reference when the REF pin is tied to V . If V = V and the CC REF CC Command (0110b). However, if the reference was pow- DAC full-scale error (FSE) is positive, the output for the ered down using Power Down Chip Command (0101b), highest codes limits at V , as shown in Figure 5c. No CC then in addition to Select Internal Reference Command full-scale limiting can occur if V is less than V –FSE. REF CC (0110b), any command that powers up the DACs will also Offset and linearity are defined and tested over the region power up the integrated reference. of the DAC transfer function where no output limiting can occur. Voltage Output The LTC2637’s DAC output integrated rail-to-rail ampli- Board Layout fiers have guaranteed load regulation when sourcing or The PC board should have separate areas for the analog sinking up to 10mA at 5V, and 5mA at 3V. and digital sections of the circuit. A single, solid ground Load regulation is a measure of the amplifier’s ability to plane should be used, with analog and digital signals care- maintain the rated voltage accuracy over a wide range of fully routed over separate areas of the plane. This keeps load current. The measured change in output voltage per digital signals away from sensitive analog signals and change in forced load current is expressed in LSB/mA. minimizes the interaction between digital ground currents Rev D 24 For more information www.analog.com

LTC2637 OPERATION and the analog section of the ground plane. The resistance supply is connected to the board and the DAC ground pin. from the LTC2637 GND pin to the ground plane should Thus the DAC ground pin becomes the common point for be as low as possible. Resistance here will add directly to analog ground, digital ground, and power ground. When the effective DC output impedance of the device (typically the LTC2637 is sinking large currents, this current flows 0.1Ω). Note that the LTC2637 is no more susceptible to out the ground pin and directly to the power ground trace this effect than any other parts of this type; on the con- without affecting the analog ground plane voltage. trary, it allows layout-based performance improvements It is sometimes necessary to interrupt the ground plane to shine rather than limiting attainable performance with to confine digital ground currents to the digital portion of excessive internal resistance. the plane. When doing this, make the gap in the plane only Another technique for minimizing errors is to use a sepa- as long as it needs to be to serve its purpose and ensure rate power ground return trace on another board layer. that no traces cross over the gap. The trace should run between the point where the power SLAVE ADDRESS COMMAND/ADDRESS MS DATA LS DATA A6 A5 A4 A3 A2 A1 A0 W C3 C2 C1 C0 A3 A2 A1 A0 D11D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X START STOP SDA A6 A5 A4 A3 A2 A1 A0 ACK C3 C2 C1 C0 A3 A2 A1 A0 ACK ACK ACK SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 FULL-SCALE VOLTAGE VOUT ZERO-SCALE X = DON’T CARE VOLTAGE 2637 F04 Figure 4. Typical LTC2637 Input Waveform—Programming DAC Output for Full-Scale POSITIVE VREF = VCC FSE VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE 2637 F04 (c) OUTPUT VOLTAGE 0V 0 2,048 4,095 INPUT CODE (a) 0V NEGATIVE INPUT CODE OFFSET (b) Figure 5. Effects of Rail-to-Rail Operation On a DAC Transfer Curve (Shown for 12 Bits). (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale Rev D 25 For more information www.analog.com

LTC2637 TYPICAL APPLICATION LTC2637 DACs Adjust LTC2755-16 Offsets, Amplified with LT1991 PGA to ±5V 5V 15 15V 0.1µF 61 RVDODFSA LTC2755 RFBA 60 15V L+TC6240 64 RIN1 0.1µF 0.1µF – 7 0.11µ84/F2 LT146+–9 56 6632 RRCEOFAM1 DAC A IIROOVUUOTTS12AAA 52598 32 –+1/2 LT146849 10.1µF OUTA0.1µ1F1 REF LTC2637MS-LMI12 VCC 1 5V 0.1µF 1890 MMM931 V1C5CV7 0.1µF –15V – –15V 2 DAC A DAC H 15 1 P1 LT199R1EFOUT 6 VOUT = ±5V OUTD + DAC D LT1634-1.25 23 PP39 VEE4 5 LT1634-1.25 30k 3 DAC B DAC G 14 0.1µF 30k LT1634-1.25 –15V –15V –15V – 30k 4 13 OUTC + DAC C – DAC C DAC F DAC B + OUTB –15V LT1634-1.25 5 12 DAC D DAC E 30k 19 GND 7 –15V CA0 I2C 9 SDA CA1 10 BUS 8 SCL CA2 6 16 GND 2637 TA02 Rev D 26 For more information www.analog.com

LTC2637 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC2637#packaging for the most recent package drawings. DE Package 14-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1708 Rev B) 0.70 ±0.05 3.60 ±0.05 3.30 ±0.05 2.20 ±0.05 1.70 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 3.00 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ±0.10 R = 0.115 0.40 ±0.10 TYP (2 SIDES) 8 14 R = 0.05 TYP 3.30 ±0.10 3.00 ±0.10 (2 SIDES) 1.70 ±0.10 PIN 1 NOTCH PIN 1 R = 0.20 OR TOP MARK 0.35 × 45° (SEE NOTE 6) CHAMFER (DE14) DFN 0806 REV B 7 1 0.200 REF 0.75 ±0.05 0.25 ±0.05 0.50 BSC 3.00 REF 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Rev D 27 For more information www.analog.com

LTC2637 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC2637#packaging for the most recent package drawings. MS Package 16-Lead Plastic MSOP (Reference LTC DWG # 05-08-1669 Rev A) 0.889 ±0.127 (.035 ±.005) 5.10 3.20 – 3.45 (.201) (.126 – .136) MIN 4.039 ±0.102 0.305 ±0.038 0.50 (.159 ±.004) (.0120 ±.0015) (.0197) (NOTE 3) 0.280 ±0.076 TYP BSC 16151413121110 9 (.011 ±.003) RECOMMENDED SOLDER PAD LAYOUT REF DETAIL “A” 3.00 ±0.102 0.254 4.90 ±0.152 (.118 ±.004) (.010) 0° – 6° TYP (.193 ±.006) (NOTE 4) GAUGE PLANE 0.53 ±0.152 1234567 8 (.021 ±.006) 1.10 0.86 (.043) (.034) DETAIL “A” MAX REF 0.18 (.007) SEATING PLANE 0.17 – 0.27 0.1016 ±0.0508 (.007 – .011) (.004 ±.002) TYP 0.50 NOTE: (.0197) MSOP (MS16) 0213 REV A 1. DIMENSIONS IN MILLIMETER/(INCH) BSC 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX Rev D 28 For more information www.analog.com

LTC2637 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 10/09 Update LTC2637-12 Maximum Limits. 5, 6, 8 B 06/10 Added details to Note 3. 10 Revised Typical Application circuit. 25 Added Typical Application drawing and revised Related Parts. 28 C 06/17 Updated Note 3. 10 D 04/18 Edits to Note 3. 10 Rev D 29 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license Fiso gr rmanoterde biny fiomrpmlicaattiioonn owr wotwhe.arwniasleo ugn.cdeorm any patent or patent rights of Analog Devices.

LTC2637 TYPICAL APPLICATION LTC2637 DACs Adjust LTC2755-16 Offsets, Amplified with LT®1991 PGA to ±5V 5V 15 15V 0.1µF 61 RVDODFSA LTC2755 RFBA 60 15V L+TC6240 64 RIN1 0.1µF 0.1µF – 7 0.11µ84/F2 LT146+–9 56 6632 RRCEOFAM1 DAC A IIROOVUUOTTS12AAA 52598 32 –+1/2 LT146849 10.1µF OUTA0.1µ1F1 REF LTC2637MS-LMI12 VCC 1 5V 0.1µF 1890 MMM931 V1C5CV7 0.1µF –15V – –15V 2 DAC A DAC H 15 1 P1 LT199R1EFOUT 6 VOUT = ±5V OUTD + DAC D LT1634-1.25 23 PP39 VEE4 5 LT1634-1.25 30k 3 DAC B DAC G 14 0.1µF 30k LT1634-1.25 –15V –15V –15V – 30k 4 13 OUTC + DAC C – DAC C DAC F DAC B + OUTB –15V LT1634-1.25 5 12 DAC D DAC E 30k GND 19 CA0 7 –15V I2C 9 SDA CA1 10 BUS 8 SCL CA2 6 16 GND 2637 TA03 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2636 Octal 12-/10-/8-Bit, SPI V DACs with 10ppm/°C Reference 125μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, OUT External REF Mode, Rail-to-Rail Output, 14-Lead 4mm × 3mm DFN and 16-Lead MSOP Packages LTC1660/LTC1665 Octal 10/8-Bit V DACs in 16-Pin Narrow SSOP V = 2.7V to 5.5V, Micropower, Rail-to-Rail Output OUT CC LTC2605/LTC2615/ Octal 16-/14-/12-Bit V DACs with I2C Interface 250μA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, OUT LTC2625 I2C Interface LTC2600/LTC2610/ Octal 16-/14-/12-Bit V DACs in 16-Lead Narrow SSOP 250μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, OUT LTC2620 SPI Serial Interface LTC2656/LTC2657 Octal 16-/12 Bit, SPI/I2C V DACs with 10ppm/°C Max ±4LSB INL max at 16-Bits and ±2mV Offset Error, Rail-to-Rail OUT Reference Output, 20-Lead 4mm × 5mm QFN and 16-Lead TSSOP Packages LTC2654/LTC2655 Quad 16-/12 Bit, SPI/I2C V DACs with 10ppm/°C Max ±4LSB INL max at 16-Bits and ±2mV Offset Error, Rail-to-Rail OUT Reference Output, 20-Lead 4mm × 4mm QFN and 16-Lead Narrow SSOP Packages LTC2634/LTC2635 Quad 12-/10-/8-Bit SPI/I2C V DACs with 10ppm/°C ±2.5 LSB INL, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, OUT Reference External REF Mode, 16-Pin 3mm × 3mm QFN and 10-Lead MSOP Packages LTC2630/LTC2632 Single 12-/10-/8-Bit, SPI/ I2C V DACs with 10ppm/°C 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, OUT Reference Rail-to-Rail Output, in SC70 (LTC2630)/ ThinSOT™ (LTC2631) LTC2640 Single 12-/10-/8-Bit, SPI V DACs with 10ppm/°C Reference 180μA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, OUT External REF Mode, Rail-to-Rail Output, in ThinSOT Amplifiers LT1991 Precision, 100µA Gain Selectable Amplifier Gain Accuracy of 0.04%, Gains from –13 to 14, 100μA Precision Op-Amp LT1469 Dual 90MHz, 22V/µs 16-Bit Accurate Operational Amplifier 90MHz Gain Bandwidth, 125µV offset, 900ns , 22V/µs Slew Rate Precision Op-Amp Rev D 30 D16869-0-5/18(D) www.analog.com For more information www.analog.com  ANALOG DEVICES, INC. 2009-2018