LTC2632 Dual 12-/10-/8-Bit SPI V DACs with OUT 10ppm/°C Reference FEATURES DESCRIPTION n Integrated Precision Reference The LTC®2632 is a family of dual 12-, 10-, and 8-bit 2.5V Full-Scale 10ppm/°C (LTC2632-L) voltage-output DACs with an integrated, high-accuracy, 4.096V Full-Scale 10ppm/°C (LTC2632-H) low-drift reference in an 8-lead TSOT-23 package. It has n Maximum INL Error: ±1.5LSB (LTC2632A-12) rail-to-rail output buffers and is guaranteed monotonic. n Low Noise: 0.75mV 0.1Hz to 200kHz P-P The LTC2632-L has a full-scale output of 2.5V, and oper- n Guaranteed Monotonic –40°C to 125°C Automotive ates from a single 2.7V to 5.5V supply. The LTC2632-H Temperature Range has a full-scale output of 4.096V, and operates from a n Selectable Internal or External Reference 4.5V to 5.5V supply. Each DAC can also operate with an n 2.7V to 5.5V Supply Range (LTC2632-L) external reference, which sets the full-scale output to the n Low Power Operation 0.4mA at 3V external reference voltage. n Power-On-Reset to Zero-Scale/Mid-Scale n Double-Buffered Data Latches These DACs communicate via a simple SPI/MICROWIRE n 8-Lead ThinSOT™ Package compatible 3-wire serial interface which operates at clock rates up to 50MHz. The LTC2632 incorporates a power-on APPLICATIONS reset circuit. Options are available for reset to zero-scale or reset to mid-scale in internal reference mode, or reset n Mobile Communications to mid-scale in external reference mode after power-up. n Process Control and Industrial Automation All registered trademarks and trademarks are the property of their respective owners. Protected n Automatic Test Equipment by U.S. patents, including 5396245, 5859606, 6891433, and 6937178. n Portable Equipment n Automotive BLOCK DIAGRAM REF GND INTERNAL SWITCH Integral Nonlinearity (LTC2632A-LZ12) REFERENCE VCC VREF 2 VINCTCE =R N3VAL REF. R R R R 1 VOUTA TE TE TE TE VOUTB DAC A EGIS EGIS EGIS EGIS DAC B B) R R R R S L (L 0 N I CS/LD SDI CONTROL –1 DECODE LOGIC SCK –2 POWER-ON 0 1024 2048 3072 4095 32-BIT SHIFT REGISTER RESET CODE 2632 TA01 2632 BD Rev. C 1 Document Feedback For more information www.analog.com

LTC2632 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) TOP VIEW Supply Voltage (V ) ...................................–0.3V to 6V CC SCK 1 8 SDI SCK, SDI ......................................................–0.3V to 6V CS/LD 2 7 VCC CS/LD (Note 10) ...............–0.3V to Min (VCC + 0.3V, 6V) REF 3 6 VOUTB V , V ...................–0.3V to Min (V + 0.3V, 6V) GND 4 5 VOUTA OUTA OUTB CC REF ..................................–0.3V to Min (V + 0.3V, 6V) TS8 PACKAGE CC 8-LEAD PLASTIC TSOT-23 Operating Temperature Range TJMAX = 150°C (NOTE 6), θJA = 195°C/W LTC2632C ................................................0°C to 70°C LTC2632H ..........................................–40°C to 125°C Maximum Junction Temperature ..........................150°C Storage Temperature Range ..................–65°C to 150°C Lead Temperature (Soldering, 10 sec) ...................300°C ORDER INFORMATION LTC2632 A C TS8 –L Z 12 #TRM PBF LEAD FREE DESIGNATOR TAPE AND REEL TR = 2,500-Piece Tape and Reel TRM = 500-Piece Tape and Reel RESOLUTION 12 = 12-Bit 10 = 10-Bit 8 = 8-Bit POWER-ON RESET I = Reset to Mid-Scale in Internal Reference Mode X = Reset to Mid-Scale in External Reference Mode (2632-L Only) Z = Reset to Zero-Scale in Internal Reference Mode FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE L = 2.5V H = 4.096V PACKAGE TYPE TS8 = 8-Lead Plastic TSOT-23 TEMPERATURE GRADE C = Commercial Temperature Range (0°C to 70°C) H = Automotive Temperature Range (–40°C to 125°C) ELECTRICAL GRADE (OPTIONAL) A = ±1.5LSB Maximum INL (12-Bit) PRODUCT PART NUMBER Contact the factory for parts specified with wider operating temperature ranges. Contact the factory for information on lead based finish parts. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Rev. C 2 For more information www.analog.com

LTC2632 PRODUCT SELECTION GUIDE V WITH INTERNAL POWER-ON POWER-ON FS PART NUMBER PART MARKING* REFERENCE RESET TO CODE REFERENCE MODE RESOLUTION V MAXIMUM INL CC LTC2632A-LI12 LTFSJ 2.5V • (4095/4096) Mid-Scale Internal 12-Bit 2.7V to 5.5V ±1.5LSB LTC2632A-LX12 LTFSH 2.5V • (4095/4096) Mid-Scale External 12-Bit 2.7V to 5.5V ±1.5LSB LTC2632A-LZ12 LTFSG 2.5V • (4095/4096) Zero Internal 12-Bit 2.7V to 5.5V ±1.5LSB LTC2632A-HI12 LTFSM 4.096V • (4095/4096) Mid-Scale Internal 12-Bit 4.5V to 5.5V ±1.5LSB LTC2632A-HZ12 LTFSK 4.096V • (4095/4096) Zero Internal 12-Bit 4.5V to 5.5V ±1.5LSB LTC2632-LI12 LTFSJ 2.5V • (4095/4096) Mid-Scale Internal 12-Bit 2.7V to 5.5V ±2.5LSB LTC2632-LI10 LTFSQ 2.5V • (1023/1024) Mid-Scale Internal 10-Bit 2.7V to 5.5V ±1LSB LTC2632-LI8 LTFSW 2.5V • (255/256) Mid-Scale Internal 8-Bit 2.7V to 5.5V ±0.5LSB LTC2632-LX12 LTFSH 2.5V • (4095/4096) Mid-Scale External 12-Bit 2.7V to 5.5V ±2.5LSB LTC2632-LX10 LTFSP 2.5V • (1023/1024) Mid-Scale External 10-Bit 2.7V to 5.5V ±1LSB LTC2632-LX8 LTFSV 2.5V • (255/256) Mid-Scale External 8-Bit 2.7V to 5.5V ±0.5LSB LTC2632-LZ12 LTFSG 2.5V • (4095/4096) Zero Internal 12-Bit 2.7V to 5.5V ±2.5LSB LTC2632-LZ10 LTFSN 2.5V • (1023/1024) Zero Internal 10-Bit 2.7V to 5.5V ±1LSB LTC2632-LZ8 LTFST 2.5V • (255/256) Zero Internal 8-Bit 2.7V to 5.5V ±0.5LSB LTC2632-HI12 LTFSM 4.096V • (4095/4096) Mid-Scale Internal 12-Bit 4.5V to 5.5V ±2.5LSB LTC2632-HI10 LTFSS 4.096V • (1023/1024) Mid-Scale Internal 10-Bit 4.5V to 5.5V ±1LSB LTC2632-HI8 LTFSY 4.096V • (255/256) Mid-Scale Internal 8-Bit 4.5V to 5.5V ±0.5LSB LTC2632-HZ12 LTFSK 4.096V • (4095/4096) Zero Internal 12-Bit 4.5V to 5.5V ±2.5LSB LTC2632-HZ10 LTFSR 4.096V • (1023/1024) Zero Internal 10-Bit 4.5V to 5.5V ±1LSB LTC2632-HZ8 LTFSX 4.096V • (255/256) Zero Internal 8-Bit 4.5V to 5.5V ±0.5LSB * The temperature grade is identified by a label on the shipping container. Above options are available in an 8-lead TSOT package (LTC2632xTS8). Rev. C 3 For more information www.analog.com

LTC2632 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 2.7V to 5.5V, V unloaded unless otherwise specified. A CC OUT LTC2632-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8, LTC2632A-LI12/-LX12/-LZ12 (V = 2.5V) FS LTC2632-8 LTC2632-10 LTC2632-12 LTC2632A-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS DC Performance Resolution l 8 10 12 12 Bits Monotonicity V = 3V, Internal Ref. l 8 10 12 12 Bits CC (Note 3) DNL Differential V = 3V, Internal Ref. l ±0.5 ±0.5 ±1 ±1 LSB CC Nonlinearity (Note 3) INL Integral V = 3V, Internal Ref. l ±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 ±0.5 ±1.5 LSB CC Nonlinearity (Note 3) ZSE Zero-Scale V = 3V, Internal Ref., l 0.5 5 0.5 5 0.5 5 0.5 5 mV CC Error Code = 0 V Offset Error V = 3V, Internal Ref. l ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV OS CC (Note 4) V V V = 3V, Internal Ref. ±10 ±10 ±10 ±10 µV/°C OSTC OS CC Temperature Coefficient GE Gain Error V = 3V, Internal Ref. l 0.2 0.8 0.2 0.8 0.2 0.8 0.2 0.8 %FSR CC GE Gain V = 3V, Internal Ref. TC CC Temperature (Note 9) Coefficient C-Grade 10 10 10 10 ppm/°C H-Grade 10 10 10 10 ppm/°C Load Internal Ref., Mid-Scale, Regulation V = 3V±10%, l 0.009 0.016 0.035 0.064 0.14 0.256 0.14 0.256 LSB/mA CC –5mA ≤ I ≤ 5mA OUT V = 5V±10%, l 0.009 0.016 0.035 0.064 0.14 0.256 0.14 0.256 LSB/mA CC –10mA ≤ I ≤ 10mA OUT R DC Output Internal Ref., Mid-Scale, OUT Impedance V = 3V±10%, l 0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 Ω CC –5mA ≤ I ≤ 5mA OUT V = 5V±10%, l 0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 Ω CC –10mA ≤ I ≤ 10mA OUT SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V DAC Output Span External Reference 0 to V V OUT REF Internal Reference 0 to 2.5 V PSR Power Supply Rejection V = 3V±10% or 5V±10% –80 dB CC I Short-Circuit Output Current (Note 5) V = V = 5.5V SC FS CC Sinking Zero-Scale; V Shorted to V l 27 48 mA OUT CC Sourcing Full-Scale; V Shorted to GND l –28 –48 mA OUT Power Supply V Positive Supply Voltage For Specified Performance l 2.7 5.5 V CC I Supply Current (Note 6) V = 3V, V = 2.5V, External Reference l 0.3 0.5 mA CC CC REF V = 3V, Internal Reference l 0.4 0.6 mA CC V = 5V V = 2.5V, External Reference l 0.3 0.5 mA CC REF V = 5V, Internal Reference l 0.4 0.6 mA CC I Supply Current in Power-Down Mode V = 5V l 0.5 2 µA SD CC (Note 6) Rev. C 4 For more information www.analog.com

LTC2632 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 2.7V to 5.5V, V unloaded unless otherwise specified. A CC OUT LTC2632-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8, LTC2632A-LI12/-LX12/-LZ12 (V = 2.5V) FS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Reference Input Input Voltage Range l 1 V V CC Resistance l 120 160 200 kΩ Capacitance 12 pF I Reference Current, Power-Down Mode DAC Powered Down l 0.005 5.0 µA REF Reference Output Output Voltage l 1.24 1.25 1.26 V Reference Temperature Coefficient ±10 ppm/°C Output Impedance 0.5 kΩ Capacitive Load Driving 10 µF Short-Circuit Current V = 5.5V, REF Shorted to GND 2.5 mA CC Digital I/O V Digital Input High Voltage V = 3.6V to 5.5V l 2.4 V IH CC V = 2.7V to 3.6V l 2.0 V CC V Digital Input Low Voltage V = 4.5V to 5.5V l 0.8 V IL CC V = 2.7V to 4.5V l 0.6 V CC I Digital Input Leakage V = GND to V l ±1 µA LK IN CC C Digital Input Capacitance (Note 7) l 8 pF IN AC Performance t Settling Time V = 3V (Note 8) S CC ±0.39% (±1LSB at 8 Bits) 3.5 µs ±0.098% (±1LSB at 10 Bits) 3.9 µs ±0.024% (±1LSB at 12 Bits) 4.4 µs Voltage Output Slew Rate 1.0 V/µs Capacitive Load Driving 500 pF Glitch Impulse At Mid-Scale Transition 2.8 nV•s DAC-to-DAC Crosstalk 1 DAC Held at FS, 1 DAC Switch 0 to FS 4.5 nV•s Multiplying Bandwidth External Reference 320 kHz e Output Voltage Noise Density At f = 1kHz, External Reference 180 nV/√Hz n At f = 10kHz, External Reference 160 nV/√Hz At f = 1kHz, Internal Reference 200 nV/√Hz At f = 10kHz, Internal Reference 180 nV/√Hz Output Voltage Noise 0.1Hz to 10Hz, External Reference 30 µV P-P 0.1Hz to 10Hz, Internal Reference 35 µV P-P 0.1Hz to 200kHz, External Reference 680 µV P-P 0.1Hz to 200kHz, Internal Reference 730 µV P-P C = 0.1µF REF Rev. C 5 For more information www.analog.com

LTC2632 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 2.7V to 5.5V, V unloaded unless otherwise specified. A CC OUT LTC2632-LI12/-LI10/-LI8/-LX12/-LX10/-LX8/-LZ12/-LZ10/-LZ8, LTC2632A-LI12/-LX12/-LZ12 (V = 2.5V) FS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t SDI Valid to SCK Setup (Figure 1) l 4 ns 1 t SDI Valid to SCK Hold (Figure 1) l 4 ns 2 t SCK High Time (Figure 1) l 9 ns 3 t SCK Low Time (Figure 1) l 9 ns 4 t CS/LD Pulse Width (Figure 1) l 10 ns 5 t LSB SCK High to CS/LD High (Figure 1) l 7 ns 6 t CS/LD Low to SCK High (Figure 1) l 7 ns 7 t CS/LD High to SCK Positive Edge (Figure 1) l 7 ns 10 SCK Frequency 50% Duty Cycle l 50 MHz Rev. C 6 For more information www.analog.com

LTC2632 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 4.5V to 5.5V, V unloaded unless otherwise specified. A CC OUT LTC2632-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8, LTC2632A-HI12/-HZ12 (V = 4.096V) FS LTC2632-8 LTC2632-10 LTC2632-12 LTC2632A-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS DC Performance Resolution l 8 10 12 12 Bits Monotonicity V = 5V, Internal Ref. (Note 3) l 8 10 12 12 Bits CC DNL Differential V = 5V, Internal Ref. (Note 3) l ±0.5 ±0.5 ±1 ±1 LSB CC Nonlinearity INL Integral V = 5V, Internal Ref. (Note 3) l ±0.05 ±0.5 ±0.2 ±1 ±1 ±2.5 ±0.5 ±1.5 LSB CC Nonlinearity ZSE Zero-Scale V = 5V, Internal Ref., Code l 0.5 5 0.5 5 0.5 5 0.5 5 mV CC Error = 0 V Offset Error V = 5V, Internal Ref. (Note 4) l ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV OS CC V V V = 5V, Internal Ref. ±10 ±10 ±10 ±10 µV/°C OSTC OS CC Temperature Coefficient GE Gain Error V = 5V, Internal Ref. l 0.2 0.8 0.2 0.8 0.2 0.8 0.2 0.8 %FSR CC GE Gain V = 5V, Internal Ref. (Note 9) TC CC Temperature C-Grade 10 10 10 10 ppm/°C Coefficient H-Grade 10 10 10 10 ppm/°C Load V = 5V±10%, Internal Ref. l 0.006 0.01 0.022 0.04 0.09 0.16 0.09 0.16 LSB/ CC Regulation Mid-Scale, –10mA ≤ I ≤ 10mA mA OUT R DC Output V = 5V±10%, Internal Ref. l 0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 Ω OUT CC Impedance Mid-Scale, –10mA ≤ I ≤ 10mA OUT SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V DAC Output Span External Reference 0 to V V OUT REF Internal Reference 0 to 4.096 V PSR Power Supply Rejection V = 5V±10% –80 dB CC I Short-Circuit Output Current (Note 5) V = V = 5.5V SC FS CC Sinking Zero-Scale; V Shorted to V l 27 48 mA OUT CC Sourcing Full-Scale; V Shorted to GND l –28 –48 mA OUT Power Supply V Positive Supply Voltage For Specified Performance l 4.5 5.5 V CC I Supply Current (Note 6) V = 5V, V = 4.096V, External Reference l 0.4 0.6 mA CC CC REF V = 5V, Internal Reference l 0.5 0.7 mA CC I Supply Current in Power-Down Mode V = 5V l 0.5 2 µA SD CC (Note 6) Rev. C 7 For more information www.analog.com

LTC2632 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 4.5V to 5.5V, V unloaded unless otherwise specified. A CC OUT LTC2632-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8, LTC2632A-HI12/-HZ12 (V = 4.096V) FS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Reference Input Input Voltage Range l 1 V V CC Resistance l 120 160 200 kΩ Capacitance 12 pF I Reference Current, Power-Down Mode DAC Powered Down l 0.005 5.0 µA REF Reference Output Output Voltage l 2.032 2.048 2.064 V Reference Temperature Coefficient ±10 ppm/°C Output Impedance 0.5 kΩ Capacitive Load Driving 10 µF Short-Circuit Current V = 5.5V; REF Shorted to GND 4 mA CC Digital I/O V Digital Input High Voltage l 2.4 V IH V Digital Input Low Voltage l 0.8 V IL I Digital Input Leakage V = GND to V l ±1 µA LK IN CC C Digital Input Capacitance (Note 7) l 8 pF IN AC Performance t Settling Time V = 5V (Note 8) S CC ±0.39% (±1LSB at 8 Bits) 3.9 µs ±0.098% (±1LSB at 10 Bits) 4.1 µs ±0.024% (±1LSB at 12 Bits) 4.9 µs Voltage Output Slew Rate 1.0 V/µs Capacitive Load Driving 500 pF Glitch Impulse At Mid-Scale Transition 3.0 nV•s DAC-to-DAC Crosstalk 1 DAC Held at FS, 1 DAC Switch 0 to FS 6.7 nV•s Multiplying Bandwidth External Reference 320 kHz e Output Voltage Noise Density At f = 1kHz, External Reference 180 nV/√Hz n At f = 10kHz, External Reference 160 nV/√Hz At f = 1kHz, Internal Reference 250 nV/√Hz At f = 10kHz, Internal Reference 230 nV/√Hz Output Voltage Noise 0.1Hz to 10Hz, External Reference 30 µV P-P 0.1Hz to 10Hz, Internal Reference 40 µV P-P 0.1Hz to 200kHz, External Reference 680 µV P-P 0.1Hz to 200kHz, Internal Reference 750 µV P-P C = 0.1µF REF Rev. C 8 For more information www.analog.com

LTC2632 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 4.5V to 5.5V, V unloaded unless otherwise specified. A CC OUT LTC2632-HI12/-HI10/-HI8/-HZ12/-HZ10/-HZ8, LTC2632A-HI12/-HZ12 (V = 4.096V) FS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t SDI Valid to SCK Setup (Figure 1) l 4 ns 1 t SDI Valid to SCK Hold (Figure 1) l 4 ns 2 t SCK High Time (Figure 1) l 9 ns 3 t SCK Low Time (Figure 1) l 9 ns 4 t CS/LD Pulse Width (Figure 1) l 10 ns 5 t LSB SCK High to CS/LD High (Figure 1) l 7 ns 6 t CS/LD Low to SCK High (Figure 1) l 7 ns 7 t CS/LD High to SCK Positive Edge (Figure 1) l 7 ns 10 SCK Frequency 50% Duty Cycle l 50 MHz Note 1: Stresses beyond those listed under Absolute Maximum Ratings above the specified maximum operating junction temperature may impair may cause permanent damage to the device. Exposure to any Absolute device reliability. Maximum Rating condition for extended periods may affect device Note 6: Digital inputs at 0V or V . CC reliability and lifetime. Note 7: Guaranteed by design and not production tested. Note 2: All voltages are with respect to GND Note 8: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale Note 3: Linearity and monotonicity are defined from code kL to code 2N–1, and 3/4 scale to 1/4 scale. Load is 2kΩ in parallel with 100pF to GND. where N is the resolution and k is given by k = 0.016•(2N/V ), rounded to L L FS Note 9: Temperature coefficient is calculated by dividing the maximum the nearest whole code. For V = 2.5V and N = 12, k = 26 and linearity is FS L change in output voltage by the specified temperature range. defined from code 26 to code 4,095. For V = 4.096V and N = 12, k = 16 FS L Note 10: CS/LD can be held at high voltage as V ramps upon power-up. and linearity is defined from code 16 to code 4,095. CC Note 4: Inferred from measurement at code 16 (LTC2632-12), code 4 (LTC2632-10) or code 1 (LTC2632-8), and at full-scale. Note 5: This IC includes current limiting that is intended to protect the device during momentary overload conditions. Junction temperature can exceed the rated maximum during current limiting. Continuous operation Rev. C 9 For more information www.analog.com

LTC2632 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. LTC2632-L12 (Internal Reference, V = 2.5V) A FS Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1.0 1.0 VCC = 3V VCC = 3V 0.5 0.5 INL (LSB) 0 DNL (LSB) 0 –0.5 –0.5 –1.0 –1.0 0 1024 2048 3072 4095 0 1024 2048 3072 4095 CODE CODE 2632 G01 2632 G02 Reference Output Voltage INL vs Temperature DNL vs Temperature vs Temperature 1.0 1.0 1.260 VCC = 3V VCC = 3V VCC = 3V 0.5 INL (POS) 0.5 1.255 DNL (POS) NL (LSB) 0 NL (LSB) 0 V (V)REF1.250 I D DNL (NEG) –0.5 INL (NEG) –0.5 1.245 –1.0 –1.0 1.240 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 2632 G03 2632 G04 2632 G05 Settling to ±1LSB Rising Settling to ±1LSB Falling 3/4 SCALE TO 1/4 SCALE STEP CS/LD 1LSBV/ODUIVT VVCFSC == 23.V5, V 5V/DIV RL = 2k, CL = 100pF 4.4µs AVERAGE OF 256 EVENTS 1/4 SCALE TO 3.3µs 3/4 SCALE STEP VOUT VCC = 3V, 1LSB/DIV VFS = 2.5V RL = 2k, CS/LD CL = 100pF 5V/DIV AVERAGE OF 256 EVENTS 2µs/DIV 2632 G06 2µs/DIV 2632 G07 Rev. C 10 For more information www.analog.com

LTC2632 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. LTC2632-H12 (Internal Reference, V = 4.096V) A FS Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1.0 1.0 VCC = 5V VCC = 5V 0.5 0.5 INL (LSB) 0 DNL (LSB) 0 –0.5 –0.5 –1.0 –1.0 0 1024 2048 3072 4095 0 1024 2048 3072 4095 CODE CODE 2632 G08 2632 G09 Reference Output Voltage INL vs Temperature DNL vs Temperature vs Temperature 1.0 1.0 2.068 VCC = 5V VCC = 5V VCC = 5V INL (POS) 0.5 0.5 2.058 DNL (POS) INL (LSB) 0 INL (NEG) DNL (LSB) 0 DNL (NEG) V (V)REF2.048 –0.5 –0.5 2.038 –1.0 –1.0 2.028 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 2632 G10 2632 G11 2632 G12 Settling to ±1LSB Rising Settling to ±1LSB Falling 3/4 SCALE TO 1/4 SCALE STEP CS/LD 5V/DIV VOUT VCC = 5V, 1LSB/DIV VFS = 4.095V RL = 2k, CL = 100pF 4.9µs AVERAGE OF 256 EVENTS 1/4 SCALE TO VOUT 3/4 SCALE STEP 4.1µs 1LSB/DIV VCC = 3V, VFS = 4.095V CS/LD RL = 2k, 5V/DIV CL = 100pF AVERAGE OF 256 EVENTS 2µs/DIV 2632 G13 2µs/DIV 2632 G14 Rev. C 11 For more information www.analog.com

LTC2632 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A LTC2632-10 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1.0 1.0 VCC = 3V VCC = 3V VFS = 2.5V VFS = 2.5V INTERNAL REF INTERNAL REF 0.5 0.5 NL (LSB) 0 NL (LSB) 0 I D –0.5 –0.5 –1.0 –1.0 0 256 512 768 1023 0 256 512 768 1023 CODE CODE 2632 G15 2632 G16 LTC2632-8 Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 0.50 0.50 VCC = 3V VCC = 3V VFS = 2.5V VFS = 2.5V INTERNAL REF INTERNAL REF 0.25 0.25 INL (LSB) 0 DNL (LSB) 0 –0.25 –0.25 –0.50 –0.50 0 64 128 192 255 0 64 128 192 255 CODE CODE 2632 G17 2632 G18 LTC2632 Load Regulation Current Limiting Offset Error vs Temperature 10 0.20 3 VCC = 5V (LTC2632-H) VCC = 5V (LTC2632-H) 8 VCC = 5V (LTC2632-L) 0.15 VCC = 5V (LTC2632-L) 6 VCC = 3V (LTC2632-L) VCC = 3V (LTC2632-L) 2 0.10 4 mV) 1 ∆V (mV)OUT –202 ∆V (V)OUT–00..00505 SET ERROR ( 0 F–1 –4 OF –0.10 –6 –2 –8 INTERNAL REFERENCE –0.15 INTERNAL REFERENCE CODE = MID-SCALE CODE = MID-SCALE –10 –0.20 –3 –30 –20 –10 0 10 20 30 –30 –20 –10 0 10 20 30 –50 –25 0 25 50 75 100 125 150 IOUT (mA) IOUT (mA) TEMPERATURE (°C) 2632 G19 2632 G20 2632 G21 Rev. C 12 For more information www.analog.com

LTC2632 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A LTC2632 Large-Signal Response Mid-Scale Glitch Impulse Power-On Reset Glitch LTC2632-L CS/LD 5V/DIV VCC 2V/DIV VOUT 0.5V/DIV 2mVV/ODUIVT L3T.0Cn2V6-3s2 T-YHP12, VCC = 5V VOUT ZERO-SCALE 10mV/DIV VFS = VCC = 5V L2T.8Cn2V6-3s2 T-YL1P2, VCC = 3V 1/4 SCALE to 3/4 SCALE 2µs/DIV 2µs/DIV 2632 G23 200µs/DIV 2632 G24 2632 G22 Headroom at Rails vs Output Current Exiting Power-Down to Mid-Scale 5.0 LTC2632-H 5V SOURCING 4.5 4.0 CS/LD VINCTCE =R N5VAL REF 5V/DIV 3.5 3V (LTC2632-L) SOURCING 3.0 V) (UT2.5 O V 2.0 DAC B IN 1.5 5V SINKING POWER-DOWN 1.0 VOUTA MODE 0.5V/DIV 0.5 3V (LTC2632-L) SINKING 0 0 1 2 3 4 5 6 7 8 9 10 5µs/DIV 2632 G26 IOUT (mA) 2632 G25 Power-On Reset to Mid-Scale Supply Current vs Logic Voltage 1.2 SWEEP SCK, SDI, CS/LD BETWEEN VCC 1.0 0V AND VCC 2V/DIV LTC2632-H 0.8 A) m (C VCC = 5V C I 0.6 VOUT 0.5V/DIV LTC2632-L 0.4 VCC = 3V (LTC2632-L) 0.2 200µs/DIV 2632 G27 0 1 2 3 4 5 LOGIC VOLTAGE (V) 2632 G28 Rev. C 13 For more information www.analog.com

LTC2632 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. A LTC2632 Multiplying Bandwidth Noise Voltage vs Frequency 2 500 VCC = 5V 0 CODE = MID-SCALE INTERNAL REFERENCE –2 400 –4 √Hz) V/ –6 E (n 300 dB –8 LTAG LTC2632-H –10 VO 200 E ––1124 VCC = 5V NOIS 100 LTC2632-L VREF(DC) = 2V –16 VREF(AC) = 0.2VP-P CODE = FULL-SCALE –18 0 1k 10k 100k 1M 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) 2632 G29 2632 G30 Gain Error vs Reference Input 0.1Hz to 10Hz Voltage Noise 0.8 VCC = 5.5V VCC = 5V, VFS = 2.5V 0.6 GAIN ERROR OF 2 CHANNELS CODE = MID-SCALE INTERNAL REFERENCE 0.4 R) S %F 0.2 OR ( 0 10µV/DIV R R E N –0.2 AI G –0.4 –0.6 –0.8 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 1s/DIV 2632 G32 REFERENCE VOLTAGE (V) 2632 G31 DAC to DAC Crosstalk (Dynamic) Gain Error vs Temperature 1.0 CS/LD 5V/DIV 0.5 R) S F % SWITCH1 0D-AFCS OR ( 0 2V/DIV RR E N AI VOUT G–0.5 2mV/DIV LTC2632-H12, VCC = 5V 6.7nV-s TYP –1.0 2µs/DIV 2632 G33 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 2634 G34 Rev. C 14 For more information www.analog.com

LTC2632 PIN FUNCTIONS SCK (Pin 1): Serial Interface Clock Input. CMOS and TTL GND (Pin 4): Ground. compatible. V A, V B (Pins 5, 6): DAC Analog Voltage Output. OUT OUT CS/LD (Pin 2): Serial Interface Chip Select/Load Input. V (Pin 7): Supply Voltage Input. 2.7V ≤ V ≤ 5.5V CC CC When CS/LD is low, SCK is enabled for shifting data on (LTC2632-L) or 4.5V ≤ V ≤ 5.5V (LTC2632-H). Bypass CC SDI into the register. When CS/LD is taken high, SCK to GND with a 0.1µF capacitor. is disabled and the specified command (see Table 1) is executed. SDI (Pin 8): Serial Interface Data Input. Data on SDI is clocked into the DAC on the rising edge of SCK. The REF (Pin 3): Reference Voltage Input or Output. When LTC2632 accepts input word lengths of either 24 or 32 external reference mode is selected, REF is an input (1V ≤ bits. V ≤ V ) where the voltage supplied sets the full-scale REF CC DAC output voltage. When internal reference is selected, the 10ppm/°C 1.25V (LTC2632-L) or 2.048V (LTC2632-H) internal reference (half full-scale) is available at the pin. This output may be bypassed to GND with up to 10µF (0.1µF is recommended) and must be buffered when driv- ing external DC load current. Rev. C 15 For more information www.analog.com

LTC2632 BLOCK DIAGRAM REF GND INTERNAL SWITCH REFERENCE VREF VCC R R R R VOUTA TE TE TE TE VOUTB DAC A GIS GIS GIS GIS DAC B E E E E R R R R CS/LD SDI CONTROL DECODE LOGIC SCK POWER-ON 32-BIT SHIFT REGISTER RESET 2632 BD TIMING DIAGRAM t1 t2 t3 t4 t6 SCK 1 2 3 23 24 t10 SDI t5 t7 CS/LD 2632 F01 Figure 1. Serial Interface Timing Rev. C 16 For more information www.analog.com

LTC2632 OPERATION The LTC2632 is a family of dual voltage output DACs in Transfer Function an 8-lead TSOT package. Each DAC can operate rail-to-rail The digital-to-analog transfer function is using an external reference, or with its full-scale voltage set by an integrated reference. Fifteen combinations of ⎛ k ⎞ accuracy (12-, 10-, and 8-bit), power-on reset value (zero- VOUT(IDEAL) =⎝⎜2N⎠⎟• VREF scale, mid-scale in internal reference mode, or mid-scale where k is the decimal equivalent of the binary DAC in external reference mode), and full-scale voltage (2.5V input code, N is the resolution, and V is either 2.5V or 4.096V) are available. The LTC2632 is controlled using REF (LTC2632-LI/LTC2632-LX/LTC2632-LZ) or 4.096V a 3-wire SPI/MICROWIRE compatible interface. (LTC2632-HI/LTC2632-HZ) when in internal reference Power-On Reset mode, and the voltage at REF when in external reference mode. The LTC2632-HZ/LTC2632-LZ clear the output to zero- scale when power is first applied, making system initial- Table 1. Command Codes ization consistent and repeatable. COMMAND* C3 C2 C1 C0 For some applications, downstream circuits are active 0 0 0 0 Write to Input Register n during DAC power-up, and may be sensitive to nonzero 0 0 0 1 Update (Power-Up) DAC Register n outputs from the DAC during this time. The LTC2632 con- tains circuitry to reduce the power-on glitch: the analog 0 0 1 0 Write to Input Register n, Update (Power-Up) All output typically rises less than 10mV above zero-scale 0 0 1 1 Write to and Update (Power-Up) DAC Register n during power-on if the power supply is ramped to 5V in 0 1 0 0 Power-Down n 1ms or more. In general, the glitch amplitude decreases as 0 1 0 1 Power-Down Chip (All DAC’s and Reference) the power supply ramp time is increased. See “Power-On 0 1 1 0 Select Internal Reference (Power-Up Reference) Reset Glitch” in the Typical Performance Characteristics 0 1 1 1 Select External Reference (Power-Down Internal Reference) section. 1 1 1 1 No Operation The LTC2632-HI/LTC2632-LI/LTC2632-LX provides an *Command codes not shown are reserved and should not be used. alternative reset, setting the output to mid-scale when Table 2. Address Codes power is first applied. The LTC2632-LI and LTC2632-HI ADDRESS (n)* power-up in internal reference mode, with the output set A3 A2 A1 A0 to a mid-scale voltage of 1.25V and 2.048V respectively. 0 0 0 0 DAC A The LTC2632-LX powers up in external reference mode, with the output set to mid-scale of the external refer- 0 0 0 1 DAC B ence. Default reference mode selection is described in 1 1 1 1 All DACs the Reference Modes section. * Address codes not shown are reserved and should not be used. Power Supply Sequencing The voltage at REF (Pin 3) must be kept within the range –0.3V ≤ V ≤ V + 0.3V (see the Absolute Maximum REF CC Ratings section). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at V is in transition. CC Rev. C 17 For more information www.analog.com

LTC2632 OPERATION INPUT WORD (LTC2632-12) COMMAND ADDRESS DATA (12 BITS + 4 DON’T-CARE BITS) C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X MSB LSB INPUT WORD (LTC2632-10) COMMAND ADDRESS DATA (10 BITS + 6 DON’T-CARE BITS) C3 C2 C1 C0 A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X MSB LSB INPUT WORD (LTC2632-8) COMMAND ADDRESS DATA (8 BITS + 8 DON’T-CARE BITS) C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X MSB LSB 2632 F02 Figure 2. Command and Data Input Format Serial Interface The CS/LD input is level triggered. When this input is operation loads a 16-bit data word from the 24-bit shift taken low, it acts as a chip-select signal, enabling the register into the input register of the selected DAC, n. An SDI and SCK buffers and the input shift register. Data Update operation copies the data word from the input (SDI input) is transferred at the next 24 rising SCK edges. register to the DAC register. Once copied into the DAC The 4-bit command, C3-C0, is loaded first; then the 4-bit register, the data word becomes the active 12-, 10-, or DAC address, A3-A0; and finally the 16-bit data word. 8-bit input code, and is converted to an analog voltage at The data word comprises the 12-, 10- or 8-bit input code, the DAC output. Write to and Update combines the first ordered MSB-to-LSB, followed by 4, 6 or 8 don’t-care bits two commands. The Update operation also powers up the (LTC2632-12, LTC2632-10 and LTC2632-8 respectively; DAC if it had been in power-down mode. The data path see Figure 2). Data can only be transferred to the device and registers are shown in the Block Diagram. when the CS/LD signal is low, beginning on the first rising While the minimum input sequence is 24 bits, it may edge of SCK. SCK may be high or low at the falling edge optionally be extended to 32 bits to accommodate micro- of CS/LD. The rising edge of CS/LD ends the data transfer processors that have a minimum word width of 16 bits (2 and causes the device to execute the command specified bytes). To use the 32-bit width, 8 don’t-care bits are trans- in the 24-bit input sequence. The complete sequence is ferred to the device first, followed by the 24-bit sequence shown in Figure 3a. described. Figure 3b shows the 32-bit sequence. The command (C3-C0) and address (A3-A0) assignments The 16-bit data word is ignored for all commands that do are shown in Tables 1 and 2. The first four commands in not include a Write operation. Table 1 consist of write and update operation. A Write Rev. C 18 For more information www.analog.com

LTC2632 OPERATION Reference Modes Power-Down Mode For applications where an accurate external reference For power-constrained applications, power-down mode is not available, nor desirable due to limited space, the can be used to reduce the supply current whenever less LTC2632 has a user-selectable, integrated reference. The than two DAC outputs are needed. When in power-down, integrated reference voltage is internally amplified by 2x the buffer amplifiers, bias circuits, and integrated ref- to provide the full-scale DAC output voltage range. The erence circuits are disabled, and draw essentially zero LTC2632-LI/LTC2632-LX/LTC2632-LZ provides a full- current. The DAC outputs are put into a high-impedance scale output of 2.5V. The LTC2632-HI/LTC2632-HZ pro- state, and the output pins are passively pulled to ground vides a full-scale output of 4.096V. The internal reference through individual 200k resistors. Input and DAC-register can be useful in applications where the supply voltage is contents are not disturbed during power-down. poorly regulated. Internal reference mode can be selected Either channel or both channels can be put into power- by using command 0110b, and is the power-on default down mode by using command 0100b in combination for LTC2632-HZ/LTC2632-LZ, as well as for LTC2632-HI/ with the appropriate DAC address (n). The supply cur- LTC2632-LI. rent is reduced approximately 30% for each DAC powered The 10ppm/°C, 1.25V (LTC2632-LI/LTC2632-LX/ down. The integrated reference is automatically powered LTC2632-LZ) or 2.048V (LTC2632-HI/LTC2632-HZ) inter- down when external reference is selected using command nal reference is available at the REF pin. Adding bypass 0111b. In addition, all the DAC channels and the inte- capacitance to the REF pin will improve noise perfor- grated reference together can be put into power-down mance; 0.1µF is recommended, and up to 10µF can be mode using power-down chip command 0101b. When driven without oscillation. This output must be buffered the integrated reference is in power-down mode, the REF when driving an external DC load current. pin becomes high impedance (typically > 1GΩ). For all power-down commands the 16-bit data word is ignored. Alternatively, the DAC can operate in external reference mode using command 0111b. In this mode, an input Normal operation resumes after executing any com- voltage supplied externally to the REF pin provides the mand that includes a DAC update (as shown in Table 1). reference (1V ≤ V ≤ V ) and the supply current is The selected DAC is powered up as its voltage output is REF CC reduced. The external reference voltage supplied sets the updated. When a DAC which is in a powered-down state full-scale DAC output voltage. External reference mode is is powered up and updated, normal settling is delayed. If the power-on default for the LTC2632-LX. less than two DACs are in a powered-down state prior to the update command, the power-up delay time is 10µs. The reference mode of LTC2632-HZ/LTC2632-LZ/ However, if both DACs and the integrated reference are LTC2632-HI/LTC2632-LI (internal reference power-on powered down, then the main bias generation circuit block default), can be changed by software command after has been automatically shut down in addition to the DAC power-up. The same is true for the LTC2632-LX (external amplifiers and reference buffers. In this case, the power reference power-on default). up delay time is 12µs. The power-up of the integrated reference depends on the command that powered it down. If the reference is powered down using the select external reference command (0111b), then it can only be pow- ered back up using select internal reference command (0110b). However, if the reference was powered down using power-down chip command (0101b), then in addi- tion to the select internal reference command (0110b), any command that powers up the DACs will also power-up the integrated reference. Rev. C 19 For more information www.analog.com

LTC2632 OPERATION Voltage Output Board Layout The LTC2632’s integrated rail-to-rail amplifier has guar- The PC board should have separate areas for the analog anteed load regulation when sourcing or sinking up to and digital sections of the circuit. A single, solid ground 10mA at 5V, and 5mA at 3V. plane should be used, with analog and digital signals care- fully routed over separate areas of the plane. This keeps Load regulation is a measure of the amplifier’s ability to digital signals away from sensitive analog signals and maintain the rated voltage accuracy over a wide range of minimizes the interaction between digital ground currents load current. The measured change in output voltage per and the analog section of the ground plane. The resistance change in forced load current is expressed in LSB/mA. from the LTC2632 GND pin to the ground plane should DC output impedance is equivalent to load regulation, and be as low as possible. Resistance here will add directly to may be derived from it by simply calculating a change in the effective DC output impedance of the device (typically units from LSB/mA to ohms. The amplifier’s DC output 0.1Ω). Note that the LTC2632 is no more susceptible to impedance is 0.1Ω when driving a load well away from this effect than any other parts of this type; on the con- the rails. trary, it allows layout-based performance improvements to shine rather than limiting attainable performance with When drawing a load current from either rail, the output excessive internal resistance. voltage headroom with respect to that rail is limited by the 50Ω typical channel resistance of the output devices Another technique for minimizing errors is to use a sepa- (e.g., when sinking 1mA, the minimum output voltage is rate power ground return trace on another board layer. 50Ω • 1mA, or 50mV). See the graph Headroom at Rails The trace should run between the point where the power vs Output Current in the Typical Performance Charac- supply is connected to the board and the DAC ground pin. teristics section. Thus the DAC ground pin becomes the common point for analog ground, digital ground, and power ground. When The amplifier is stable driving capacitive loads of up to the LTC2632 is sinking large currents, this current flows 500pF. out the ground pin and directly to the power ground trace Rail-to-Rail Output Considerations without affecting the analog ground plane voltage. In any rail-to-rail voltage output device, the output is lim- It is sometimes necessary to interrupt the ground plane ited to voltages within the supply range. to confine digital ground currents to the digital portion of the plane. When doing this, make the gap in the plane only Since the analog output of the DAC cannot go below as long as it needs to be to serve its purpose and ensure ground, it may limit for the lowest codes as shown in that no traces cross over the gap. Figure 4b. Similarly, limiting can occur near full-scale when the REF pin is tied to V . If V = V and the Bypass capacitors should be placed as close to the pins CC REF CC DAC full-scale error (FSE) is positive, the output for the as possible with a low impedance path to GND. highest codes limits at V , as shown in Figure 4c. No CC full-scale limiting can occur if V is less than V –FSE. REF CC Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. Rev. C 20 For more information www.analog.com

LTC2632 OPERATION 2632 F03b 32 X 31 X 2632 F03a 2930 X X 24 X 28 D0 23 X 27 1 D 22 X 26 2 D 21 X 25 3 RD 181920 D2D1D0 m Input Word) Care Bits; re Bits 222324 D5D4D6D DATA WO Care Bits; re Bits 151617 D5D4D3 DATA WORD ence (Minimuode + 6 Don’t-e + 8 Don’t-Ca 192021 D9D8D7 nce ode + 6 Don’t-e + 8 Don’t-Ca 567891011121314 A3A2A0D11D10D9D8D7D6A1 ADDRESS 24-BIT INPUT WORD Figure 3a. . LTC2632-12 24-Bit Load SequLTC2632-10 SDI Data Word: 10-Bit Input CLTC2632-8 SDI Data Word: 8-Bit Input Cod 1891011121314151617 C3C2C1C0A3A2A0D11D10A1 ADDRESSCOMMAND WORD 32-BIT INPUT WORD Figure 3b. LTC2632-12 32-Bit Load SequeLTC2632-10 SDI Data Word: 10-Bit Input CLTC2632-8 SDI Data Word: 8-Bit Input Cod 4 C0 D 8 X R 3 C1 D WO 7 X N 2 C2 MMA 6 X S 1 C3 CO 5 X RE BIT A C 4 X N’T O D S/LD SCK SDI 3 X 8 C 2 X 1 X S/LD SCK SDI C Rev. C 21 For more information www.analog.com

LTC2632 OPERATION POSITIVE VREF = VCC FSE VREF = VCC OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE 2632 F04 (c) OUTPUT VOLTAGE 0V 0 2,048 4,095 INPUT CODE (a) 0V NEGATIVE INPUT CODE OFFSET (b) Figure 4. Effects of Rail-to-Rail Operation On a DAC Transfer Curve (Shown for 12 Bits) (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero (c) Effect of Positive Full-Scale Error for Codes Near Full-Scale PACKAGE DESCRIPTION TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637 Rev A) 0.40 0.65 2.90 BSC MAX REF (NOTE 4) 1.22 REF 3.85 MAX2.62 REF 1.4 MIN 2.80 BSC 1(.5N0O T–E 1 4.7)5 PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT 0.22 – 0.36 0.65 BSC PER IPC CALCULATOR 8 PLCS (NOTE 3) 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 1.95 BSC TS8 TSOT-23 0710 REV A (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 Rev. C 22 For more information www.analog.com

LTC2632 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 03/11 Revised part numbering. 2 to 9, 17, 19, 24 B 06/17 Removed Note 3. 9 C 07/19 Changed A-Grade INL from ±1LSB to ±1.5LSB. 1 to 4, 7 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog 23 Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license Fiso gr rmanoterde biny fiomrpmlicaattiioonn owr wotwhe.arwniasleo ugn.cdeorm any patent or patent rights of Analog Devices.

LTC2632 TYPICAL APPLICATION LTC2632 DACs Adjust LTC2755-16 Offset, Amplified with LT1991 PGA to ±5V 5V 15V0.1µF VDD LTC2755 15V ROFSA 30pF 00..11µµFF RIN1 RFBA 0.1µF + – IOUT1A 1/2 LT1469 RCOM1 DAC A IOUT2A 1/2 LT1469 OUTA – + RVOSA 5V 0.1µF 30pF 0.1µF –15V –15V REFA LT1634-1.25 – 0.1µF LT6240 DAC D DAC B + 30k 0.1µF 10V 5V –15V REF VCC 0.1µF DAC C GND LTC2632TS8-LI12 0.1µF M9 M3 VCC M1LT1991 OUT VOUT ±6V DAC A DAC B P1 REF P3 VEE P9 CS/LD SERIAL BUS SCK GND –10V 0.1µF SDI 2632 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1662 Dual 10-Bit Ultralow Power V DAC in 8-Lead MSOP 1.5µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, OUT with External Reference SPI Serial Interface LTC2602/LTC2612/ Dual 16-/14-/12-Bit V DACs in 8-Lead MSOP 300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, OUT LTC2622 with External Reference SPI Serial Interface LTC2607/LTC2617/ Dual 16-/14-/12-Bit V DACs in 12-Lead DFN 260µA per DAC, 2.7V to 5.5V Supply Range, Rail-to-Rail Output, OUT LTC2627 with External Reference I2C Serial Interface LTC2630 Single 12-/10-/8-Bit V DACs with 10ppm/°C Reference 180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, OUT in SC70 Rail-to-Rail Output, SPI Serial Interface LTC2631 Single 12-/10-/8-Bit I2C V DACs with 10ppm/°C 180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, OUT Reference in ThinSOT External REF Mode, Rail-to-Rail Output, I2C Interface LTC2634 Quad 12-/10-/8-Bit V DACs with 10ppm/°C Reference 125µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, OUT External REF Mode, Rail-to-Rail Output, SPI Interface LTC2636 Octal 12-/10-/8-Bit V DACs with 10ppm/°C Reference 125µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, OUT External REF Mode, Rail-to-Rail Output, SPI Interface LTC2640 Single 12-/10-/8-Bit V DACs with 10ppm/°C Reference 180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference, OUT in ThinSOT External REF Mode, Rail-to-Rail Output, SPI Interface LTC2654 Quad 16-/12-Bit V DACs with ±4 LSB INL, ±1 LSB DNL 4mm × 4mm QFN-20, SSOP-16 Packages, SPI Interface, OUT Internal 10ppm/°C (Max) Reference Rev. C 24 07/19 www.analog.com For more information www.analog.com  ANALOG DEVICES, INC. 2011-2019