LTC2493 24-Bit 2-/4-Channel ∆∑ ADC with Easy Drive Input Current Cancellation and I2C Interface FeaTures DescripTion n Up to 2 Differential or 4 Single-Ended Inputs The LTC®2493 is a 4-channel (2-channel differential), 24-bit, n Easy Drive™ Technology Enables Rail-to-Rail No Latency ∆∑™ ADC with Easy Drive technology and a Inputs with Zero Differential Input Current 2-wire, I2C interface. The patented sampling scheme elimi- n Directly Digitizes High Impedance Sensors with nates dynamic input current errors and the shortcomings Full Accuracy of on-chip buffering through automatic cancellation of n 2-Wire I2C Interface with 9 Addresses Plus One differential input current. This allows large external source Global Address for Synchronization impedances and rail-to-rail input signals to be directly digi- n 600nV RMS Noise tized while maintaining exceptional DC accuracy. n Integrated High Accuracy Temperature Sensor The LTC2493 includes a high accuracy temperature n GND to V Input/Reference Common Mode Range CC sensor and an integrated oscillator. This device can be n Programmable 50Hz, 60Hz or Simultaneous configured to measure an external signal (from combi- 50Hz/60Hz Rejection Mode nations of 4 analog input channels operating in single- n 2ppm INL, No Missing Codes ended or differential modes) or its internal temperature n 1ppm Offset and 15ppm Full-Scale Error sensor. The integrated temperature sensor offers 1/30th °C n 2× Speed/Reduced Power Mode (15Hz Using Internal resolution and 2°C absolute accuracy. Oscillator and 80µA at 7.5Hz Output) n No Latency: Digital Filter Settles in a Single Cycle, The LTC2493 allows a wide common mode input range Even After a New Channel Is Selected (0V to VCC), independent of the reference voltage. Any n Single Supply 2.7V to 5.5V Operation (0.8mW) combination of single-ended or differential inputs can n Internal Oscillator be selected and the first conversion, after a new channel n Tiny 4mm × 3mm DFN Package is selected, is valid. Access to the multiplexer output en- ables optional external amplifiers to be shared between all applicaTions analog inputs and auto-calibration continuously removes their associated offset and drift. n Direct Sensor Digitizer n Direct Temperature Measurement L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and No Latency ∆∑ and Easy Drive are trademarks of Linear Technology Corporation. All other n Instrumentation trademarks are the property of their respective owners. n Industrial Process Control Typical applicaTion Data Acquisition System with Temperature Compensation Integrated High Performance Temperature Sensor 2.7V TO 5.5V 5 4 0.1µF 10µF CH0 VCC 3 CH1 IN+ REF+ 1.7k RROR (°C) 21 CCHH32 4-CHMAUNXNEL IN–W2IT4H-RB EEITAF S–∆Y∑- DARDICVE SSCDCAAL1 2I92--CWP IIINNR TSEEERLFEACCTEABLE ABSOLUTE E––210 COM CA0 ADDRESSES –3 TEMPERATURE fO –4 SENSOR OSC –5 –55 –30 –5 20 45 70 95 120 2493 vTA01a TEMPERATURE (°C) 2493 TA02 2493fe 1 For more information www.linear.com/LTC2493

LTC2493 absoluTe MaxiMuM raTings pin conFiguraTion (Notes 1, 2) Supply Voltage (V ) ...................................–0.3V to 6V CC fO 1 14 REF– Analog Input Voltage CA0 2 13 REF+ (CH0 to CH3, COM) ..................–0.3V to (VCC + 0.3V) CA1 3 12 VCC REF+, REF– ..................................–0.3V to (V + 0.3V) SCL 4 15 11 CH3 CC SDA 5 10 CH2 Digital Input Voltage.....................–0.3V to (V + 0.3V) CC GND 6 9 CH1 Digital Output Voltage ..................–0.3V to (V + 0.3V) CC COM 7 8 CH0 Operating Temperature Range DE PACKAGE LTC2493C ................................................0°C to 70°C 14-LEAD (4mm × 3mm) PLASTIC DFN LTC2493I .............................................–40°C to 85°C TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB Storage Temperature Range ..................–65°C to 150°C orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2493CDE#PBF LTC2493CDE#TRPBF 2493 14-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C LTC2493IDE#PBF LTC2493IDE#TRPBF 2493 14-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2493fe 2 For more information www.linear.com/LTC2493

LTC2493 elecTrical characTerisTics (norMal speeD) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Notes 3, 4) A PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) 0.1V ≤ V ≤ V , –FS ≤ V ≤ +FS (Note 5) 24 Bits REF CC IN Integral Nonlinearity 5V ≤ V ≤ 5.5V, V = 5V, V = 2.5V (Note 6) l 2 10 ppm of V CC REF IN(CM) REF 2.7V ≤ V ≤ 5.5V, V = 2.5V, V = 1.25V (Note 6) l 1 ppm of V CC REF IN(CM) REF Offset Error 2.5V ≤ V ≤ V , GND ≤ IN+ = IN– ≤ V (Note 13) l 0.5 2.5 µV REF CC CC Offset Error Drift 2.5V ≤ V ≤ V , GND ≤ IN+ = IN– ≤ V 10 nV/°C REF CC CC Positive Full-Scale Error 2.5V ≤ V ≤ V , IN+ = 0.75V , IN– = 0.25V l 25 ppm of V REF CC REF REF REF Positive Full-Scale Error Drift 2.5V ≤ V ≤ V , IN+ = 0.75V , IN– = 0.25V 0.1 ppm of V /°C REF CC REF REF REF Negative Full-Scale Error 2.5V ≤ V ≤ V , IN+ = 0.25V , IN– = 0.75V l 25 ppm of V REF CC REF REF REF Negative Full-Scale Error Drift 2.5V ≤ V ≤ V , IN+ = 0.25V , IN– = 0.75V 0.1 ppm of V /°C REF CC REF REF REF Total Unadjusted Error 5V ≤ V ≤ 5.5V, V = 2.5V, V = 1.25V 15 ppm of V CC REF IN(CM) REF 5V ≤ V ≤ 5.5V, V = 5V, V = 2.5V 15 ppm of V CC REF IN(CM) REF 2.7V ≤ V ≤ 5.5V, V = 2.5V, V = 1.25V 15 ppm of V CC REF IN(CM) REF Output Noise 2.7V < V < 5.5V, 2.5V ≤ V ≤ V , 0.6 µV CC REF CC RMS GND ≤ IN+ = IN– ≤ V (Note 12) CC Internal PTAT Signal T = 27°C (Note 13) 27.8 28.0 28.2 mV A Internal PTAT Temperature Coefficient 93.5 µV/°C elecTrical characTerisTics (2x speeD) The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Notes 3, 4) A PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) 0.1V ≤ V ≤ V , –FS ≤ V ≤ +FS (Note 5) 24 Bits REF CC IN Integral Nonlinearity 5V ≤ V ≤ 5.5V, V = 5V, V = 2.5V (Note 6) l 2 10 ppm of V CC REF IN(CM) REF 2.7V ≤ V ≤ 5.5V, V = 2.5V, V = 1.25V (Note 6) 1 ppm of V CC REF IN(CM) REF Offset Error 2.5V ≤ V ≤ V , GND ≤ IN+ = IN– ≤ V (Note 13) l 0.2 2 mV REF CC CC Offset Error Drift 2.5V ≤ V ≤ V , GND ≤ IN+ = IN– ≤ V 100 nV/°C REF CC CC Positive Full-Scale Error 2.5V ≤ V ≤ V , IN+ = 0.75V , IN– = 0.25V l 25 ppm of V REF CC REF REF REF Positive Full-Scale Error Drift 2.5V ≤ V ≤ V , IN+ = 0.75V , IN– = 0.25V 0.1 ppm of V /°C REF CC REF REF REF Negative Full-Scale Error 2.5V ≤ V ≤ V , IN+ = 0.25V , IN– = 0.75V l 25 ppm of V REF CC REF REF REF Negative Full-Scale Error Drift 2.5V ≤ V ≤ V , IN+ = 0.25V , IN– = 0.75V 0.1 ppm of V /°C REF CC REF REF REF Output Noise 5V ≤ V ≤ 5.5V, V = 5V, GND ≤ IN+ = IN– ≤ V 0.85 µV CC REF CC RMS converTer characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3) A PARAMETER CONDITIONS MIN TYP MAX UNITS Input Common Mode Rejection DC 2.5V ≤ V ≤ V , GND ≤ IN+ = IN– ≤ V (Note 5) l 140 dB REF CC CC Input Common Mode Rejection 50Hz ±2% 2.5V ≤ V ≤ V , GND ≤ IN+ = IN– ≤ V (Notes 5, 7) l 140 dB REF CC CC Input Common Mode Rejection 60Hz ±2% 2.5V ≤ V ≤ V , GND ≤ IN+ = IN– ≤ V (Notes 5, 8) l 140 dB REF CC CC Input Normal Mode Rejection 50Hz ±2% 2.5V ≤ V ≤ V , GND ≤ IN+ = IN– ≤ V (Notes 5, 7) l 110 120 dB REF CC CC Input Normal Mode Rejection 60Hz ±2% 2.5V ≤ V ≤ V , GND ≤ IN+ = IN– ≤ V (Notes 5, 8) l 110 120 dB REF CC CC Input Normal Mode Rejection 50Hz/60Hz ±2% 2.5V ≤ V ≤ V , GND ≤ IN+ = IN– ≤ V (Notes 5, 9) l 87 dB REF CC CC Reference Common Mode Rejection DC 2.5V ≤ V ≤ V , GND ≤ IN+ = IN– ≤ V (Note 5) l 120 140 dB REF CC CC Power Supply Rejection DC V = 2.5V, IN+ = IN– = GND 120 dB REF Power Supply Rejection, 50Hz ±2%, 60Hz ±2% V = 2.5V, IN+ = IN– = GND (Notes 7, 8, 9) 120 dB REF 2493fe 3 For more information www.linear.com/LTC2493

LTC2493 analog inpuT anD reFerence The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IN+ Absolute/Common Mode IN+ Voltage GND – 0.3V V + 0.3V V CC (IN+ Corresponds to the Selected Positive Input Channel) IN– Absolute/Common Mode IN– Voltage GND – 0.3V V + 0.3V V CC (IN– Corresponds to the Selected Negative Input Channel to COM) V Input Voltage Range (IN+ – IN–) Differential/Single-Ended l –FS +FS V IN FS Full-Scale of the Input (IN+ – IN–) Differential/Single-Ended l 0.5V V REF LSB Least Significant Bit of the Output Code l FS/224 REF+ Absolute/Common Mode REF+ Voltage l 0.1 V V CC REF– Absolute/Common Mode REF– Voltage l GND REF+ – 0.1V V V Reference Voltage Range (REF+ – REF–) l 0.1 V V REF CC CS(IN+) IN+ Sampling Capacitance 11 pF CS(IN–) IN– Sampling Capacitance 11 pF CS(V ) V Sampling Capacitance 11 pF REF REF I + IN+ DC Leakage Current Sleep Mode, IN+ = GND l –10 1 10 nA DC_LEAK(IN ) I – IN– DC Leakage Current Sleep Mode, IN– = GND l –10 1 10 nA DC_LEAK(IN ) I + REF+ DC Leakage Current Sleep Mode, REF+ = V l –100 1 100 nA DC_LEAK(REF ) CC I – REF– DC Leakage Current Sleep Mode, REF– = GND l –100 1 100 nA DC_LEAK(REF ) t MUX Break-Before-Make 50 ns OPEN QIRR MUX Off Isolation V = 2V DC to 1.8MHz 120 dB IN P-P 2 i c inpuTs anD DigiTal ouTpuTs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V High Level Input Voltage l 0.7V V IH CC V Low Level Input Voltage l 0.3V V IL CC V Low Level Input Voltage for Address Pins CA0, CA1 and l 0.05V V IHA CC Pin f O V High Level Input Voltage for Address Pins CA0, CA1 l 0.95V V ILA CC R Resistance from CA0, CA1 to V to Set Chip Address l 10 kΩ INH CC Bit to 1 R Resistance from CA0, CA1 to GND to Set Chip Address l 10 kΩ INL Bit to 0 R Resistance from CA0, CA1 to GND or V to Set Chip l 2 MΩ INF CC Address Bit to Float I Digital Input Current (f ) l –10 10 µA I O V Hysteresis of Schmitt Trigger Inputs (Note 5) l 0.05V V HYS CC V Low Level Output Voltage (SDA) I = 3mA l 0.4 V OL t Output Fall Time V to V Bus Load C 10pF to l 20 + 0.1C 250 ns OF IH(MIN) IL(MAX) B B 400pF (Note 14) I Input Leakage (SDA, SCL) 0.1V ≤ V ≤ 0.9V l 1 µA IN CC IN CC C External Capacitative Load On-Chip Address Pins (CA0, l 10 pF CAX CA1) for Valid Float 2493fe 4 For more information www.linear.com/LTC2493

LTC2493 power requireMenTs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Supply Voltage l 2.7 5.5 V CC I Supply Current Conversion Current (Note 11) l 160 275 µA CC Temperature Measurement (Note 11) l 200 300 µA Sleep Mode (Note 11) l 1 2 µA DigiTal inpuTs anD DigiTal ouTpuTs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f External Oscillator Frequency Range (Note 16) l 10 1000 kHz EOSC t External Oscillator High Period l 0.125 50 µs HEO t External Oscillator Low Period l 0.125 50 µs LEO t Conversion Time for 1× Speed Mode 50Hz Mode l 157.2 160.3 163.5 ms CONV_1 60Hz Mode l 131 133.6 136.3 ms Simultaneous 50Hz/60Hz Mode l 144.1 146.9 149.9 ms External Oscillator (Note 10) 41036/f (in kHz) ms EOSC t Conversion Time for 2× Speed Mode 50Hz Mode l 78.7 80.3 81.9 ms CONV_2 60Hz Mode l 65.6 66.9 68.2 ms Simultaneous 50Hz/60Hz Mode l 72.2 73.6 75.1 ms External Oscillator (Note 10) 20556/f (in kHz) ms EOSC 2 i c TiMing characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3, 15) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f SCL Clock Frequency l 0 400 kHz SCL t Hold Time (Repeated) START Condition l 0.6 µs HD(STA) t LOW Period of the SCL Pin l 1.3 µs LOW t HIGH Period of the SCL Pin l 0.6 µs HIGH t Set-Up Time for a Repeated START Condition l 0.6 µs SU(STA) t Data Hold Time l 0 0.9 µs HD(DAT) t Data Set-Up Time l 100 ns SU(DAT) t Rise Time for SDA Signals (Note 14) l 20 + 0.1C 300 ns r B t Fall Time for SDA Signals (Note 14) l 20 + 0.1C 300 ns f B t Set-Up Time for STOP Condition l 0.6 µs SU(STO) Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 7: 50Hz mode (internal oscillator) or f = 256kHz ±2% (external oscillator). EOSC may cause permanent damage to the device. Exposure to any Absolute Note 8: 60Hz mode (internal oscillator) or f = 307.2kHz ±2% (external oscillator). EOSC Maximum Rating condition for extended periods may affect device Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or f = EOSC reliability and lifetime. 280kHz ±2% (external oscillator). Note 2: All voltage values are with respect to GND. Note 10: The external oscillator is connected to the f pin. The external O Note 3: Unless otherwise specified: VCC = 2.7V to 5.5V oscillator frequency, fEOSC, is expressed in kHz. VREFCM = VREF/2, fS = 0.5VREF Note 11: The converter uses its internal oscillator. VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2, Note 12: The output noise includes the contribution of the internal where IN+ and IN– are the selected input channels. calibration operations. Note 4: Use internal conversion clock or external conversion clock source Note 13: Guaranteed by design and test correlation. with f = 307.2kHz unless otherwise specified. EOSC Note 14: C = capacitance of one bus line in pF (10pF ≤ C ≤ 400pF). B B Note 5: Guaranteed by design, not subject to test. Note 15: All values refer to V and V levels. IH(MIN) IL(MAX) Note 6: Integral nonlinearity is defined as the deviation of a code from a Note 16: Refer to Applications Information section for Performance vs straight line passing through the actual endpoints of the transfer curve. Data Rate graphs. The deviation is measured from the center of the quantization band. 2493fe 5 For more information www.linear.com/LTC2493

LTC2493 Typical perForMance characTerisTics Integral Nonlinearity Integral Nonlinearity Integral Nonlinearity (V = 5V, V = 5V) (V = 5V, V = 2.5V) (V = 2.7V, V = 2.5V) CC REF CC REF CC REF 3 3 3 VCC = 5V VCC = 5V VCC = 2.7V VREF = 5V VREF = 2.5V VREF = 2.5V 2 VIN(CM) = 2.5V 2 VIN(CM) = 1.25V 2 VIN(CM) = 1.25V fO = GND fO = GND fO = GND V)REF 1 –45°C 25°C V)REF 1 –45°C, 25°C, 85°C V)REF 1 –45°C, 25°C, 85°C of of of m 0 m 0 m 0 p p p p 85°C p p L ( L ( L ( N –1 N –1 N –1 I I I –2 –2 –2 –3 –3 –3 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –1.25 –0.75 –0.25 0.25 0.75 1.25 –1.25 –0.75 –0.25 0.25 0.75 1.25 INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V) 2493 G03 2493 G01 2493 G02 Total Unadjusted Error Total Unadjusted Error Total Unadjusted Error (V = 5V, V = 5V) (V = 5V, V = 2.5V) (V = 2.7V, V = 2.5V) CC REF CC REF CC REF 12 12 12 VCC = 5V VCC = 5V VCC = 2.7V VREF = 5V VREF = 2.5V 85°C VREF = 2.5V 8 VIN(CM) = 2.5V 8 VIN(CM) = 1.25V 8 VIN(CM) = 1.25V fO = GND 25°C 85°C fO = GND 25°C fO = GND 25°C 85°C )REF 4 )REF 4 )REF 4 V V V m of 0 –45°C m of 0 –45°C m of 0 –45°C p p p p p p E ( E ( E ( TU –4 TU –4 TU –4 –8 –8 –8 –12 –12 –12 –2.5–2–1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –1.25 –0.75 –0.25 0.25 0.75 1.25 –1.25 –0.75 –0.25 0.25 0.75 1.25 INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V) 2493 G04 2493 G05 2493 G06 Noise Histogram (6.8sps) Noise Histogram (7.5sps) Long-Term ADC Readings 14 14 5 10,000 CONSECUTIVE 10,000 CONSECUTIVE VCC = 5V TA = 25°C %) 12 RVVCRECEAF D= = I5N 5VGVS AVERRMASG E= =0 .–600.µ6V9µV %) 12 RVVCRECEAF D= = I2N 2.G7.5VSV AVERRMASG E= =0 .–509.µ1V9µV 43 VVVRIINNE (F=C M=0 )V5 =V 2.5VRMS NOISE = 0.60µV ADINGS ( 180 VTAIN = = 2 05V°C ADINGS ( 180 VTAIN = = 2 05V°C NG (µV) 12 RE RE DI 0 MBER OF 64 MBER OF 64 ADC REA ––12 U U N N –3 2 2 –4 0 0 –5 –3 –2.4 –1.8 –1.2 –0.6 0 0.6 1.2 1.8 –3 –2.4 –1.8 –1.2 –0.6 0 0.6 1.2 1.8 0 10 20 30 40 50 60 OUTPUT READING (µV) OUTPUT READING (µV) TIME (HOURS) 2493 G07 2493 G08 2493 G09 2493fe 6 For more information www.linear.com/LTC2493

LTC2493 Typical perForMance characTerisTics RMS Noise vs Input Differential Voltage RMS Noise vs V RMS Noise vs Temperature (T ) IN(CM) A 1.0 1.0 1.0 VCC = 5V VCC = 5V VCC = 5V VREF = 5V VREF = 5V VREF = 5V 0.9 VIN(CM) = 2.5V 0.9 VIN = 0V 0.9 VIN = 0V TA = 25°C TA = 25°C VIN(CM) = GND OISE (µV) 00..87 fO = GND OISE (µV) 00..78 fO = GND OISE (µV) 00..78 fO = GND N N N MS MS MS R 0.6 R 0.6 R 0.6 0.5 0.5 0.5 0.4 0.4 0.4 –2.5–2–1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –1 0 1 2 3 4 5 6 –45 –30 –15 0 15 30 45 60 75 90 INPUT DIFFERENTIAL VOLTAGE (V) VIN(CM) (V) TEMPERATURE (°C) 2493 G10 2493 G11 2493 G12 RMS Noise vs V RMS Noise vs V Offset Error vs V CC REF IN(CM) 1.0 1.0 0.3 VREF = 2.5V VCC = 5V VCC = 5V VIN = 0V VIN = 0V VREF = 5V 0.9 VTAIN =(C 2M5)° =C GND 0.9 VTAIN =(C 2M5)° =C GND )REF 0.2 VTAIN = = 2 05V°C µV) 0.8 fO = GND µV) 0.8 fO = GND m of V 0.1 fO = GND E ( E ( pp MS NOIS 0.7 MS NOIS 0.7 ERROR ( 0 R 0.6 R 0.6 T –0.1 E S F F O 0.5 0.5 –0.2 0.4 0.4 –0.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 0 1 2 3 4 5 –1 0 1 2 3 4 5 6 VCC (V) VREF (V) VIN(CM) (V) 2493 G13 2493 G14 2493 G15 Offset Error vs Temperature Offset Error vs V Offset Error vs V CC REF 0.3 0.3 0.3 VVCRCEF = = 5 5VV RREEFF+– == 2G.N5DV VRCECF –= =5 VGND m of V)REF00..12 VVfOIINN = ( =CG M0N)VD = GND m of V)REF 00..21 VfVTOAIINN == ( =C G2 M0N5)V°D =C GND m of V)REF00..12 VfVTOAIINN == ( =C G2 M0N5)V°D =C GND R (pp 0 R (pp 0 R (pp 0 O O O R R R R R R OFFSET E––00..12 OFFSET E––00..12 OFFSET E––00..21 –0.3 –0.3 –0.3 –45–30 –15 0 15 30 45 60 75 90 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 0 1 2 3 4 5 TEMPERATURE (°C) VCC (V) VREF (V) 2493 G16 2493 G17 2493 G18 2493fe 7 For more information www.linear.com/LTC2493

LTC2493 Typical perForMance characTerisTics On-Chip Oscillator Frequency On-Chip Oscillator Frequency vs Temperature vs V PSRR vs Frequency at V CC CC 310 310 0 VREF = 2.5V VCC = 4.1V DC ±0.7V 308 308 VVfOIINN = ( =CG M0N)VD = GND –20 IIVNNR+–E F== =GG 2NN.DD5V Hz) Hz) TA = 25°C B) –40 fTOA == G2N5°DC Y (k306 Y (k306 N (d –60 C C O EQUEN304 EQUEN304 EJECTI –80 R R R F VCC = 4.1V F –100 302 VVRINE F= =0 V2.5V 302 –120 VIN(CM) = GND fO = GND 300 300 –140 –45 –30 –15 0 15 30 45 60 75 90 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1 10 100 1k 10k 100k 1M TEMPERATURE (°C) VCC (V) FREQUENCY AT VCC (Hz) 2493 G19 2493 G20 2493 G21 Conversion Current PSRR vs Frequency at V PSRR vs Frequency at V vs Temperature CC CC 0 0 200 VCC = 4.1V DC ±1.4V VCC = 4.1V DC ±0.7V fO = GND –20 IVNR+E F= =G 2N.D5V –20 IVNR+E F= =G 2N.D5V IN– = GND IN– = GND A)180 µ –40 fO = GND –40 fO = GND T ( VCC = 5V ECTION (dB) ––6800 TA = 25°C ECTION (dB) ––6800 TA = 25°C ON CURREN160 VCC = 2.7V REJ REJ RSI140 E –100 –100 V N O C120 –120 –120 –140 –140 100 0 20 40 60 80 100120140160180200220 30600 30650 30700 30750 30800 –45–30 –15 0 15 30 45 60 75 90 FREQUENCY AT VCC (Hz) FREQUENCY AT VCC (Hz) TEMPERATURE (°C) 2493 G22 2493 G23 2493 G24 Sleep Mode Current Conversion Current Integral Nonlinearity (2x Speed vs Temperature vs Output Data Rate Mode; V = 5V, V = 5V) CC REF 2.0 500 3 LEEP MODE CURRENT (µA) 0011111.......6804682 fO = GND VVCCCC = = 2 5.7VV SUPPLY CURRENT (µA) 443322505050000000 IfTVINNOAR +– =E= F == E 2 =XGG5 TVNN° CCDDOCSC VCC = 5V INL (µV) –1102 25°C, VVVf8O–5CRIN 4°C=E(C5F C=G °M= CN5 )5VD =V 2.5V S 0.4 –2 0.2 150 VCC = 3V 0 100 –3 –45–30 –15 0 15 30 45 60 75 90 0 10 20 30 –2.5–2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 TEMPERATURE (°C) OUTPUT DATA RATE (READINGS/SEC) INPUT VOLTAGE (V) 2493 G25 2493 G26 2493 G27 2493fe 8 For more information www.linear.com/LTC2493

LTC2493 Typical perForMance characTerisTics Integral Nonlinearity (2x Speed Integral Nonlinearity (2x Speed Noise Histogram Mode; V = 5V, V = 2.5V) Mode; V = 2.7V, V = 2.5V) (2x Speed Mode) CC REF CC REF 3 3 16 VCC = 5V VCC = 2.7V 10,000 CONSECUTIVE RMS = 0.85µV VREF = 2.5V VREF = 2.5V 14 READINGS AVERAGE = 0.184mV 2 VIN(CM) = 1.25V 2 VIN(CM) = 1.25V VCC = 5V fO = GND fO = GND %) 12 VREF = 5V INL (ppm OF V)REF –110 –4855°°CC, 25°C INL (ppm OF V)REF –110 –4855°°CC, 25°C MBER OF READINGS ( 1860 VTAIN = = 2 05V°C U 4 N –2 –2 2 –3 –3 0 –1.25 –0.75 –0.25 0.25 0.75 1.25 –1.25 –0.75 –0.25 0.25 0.75 1.25 179 181.4 183.8 186.2 188.6 INPUT VOLTAGE (V) INPUT VOLTAGE (V) OUTPUT READING (µV) 2493 G28 2493 G29 2493 G30 RMS Noise vs V Offset Error vs V Offset Error vs Temperature REF IN(CM) (2x Speed Mode) (2x Speed Mode) (2x Speed Mode) 1.0 200 240 198 VVCRCEF = = 5 5VV 230 VVCRCEF = = 5 5VV 0.8 196 VIN = 0V VIN = 0V fO = GND 220 VIN(CM) = GND E (µV) 0.6 OR (µV)119942 TA = 25°C OR (µV) 210 fO = GND S R R MS NOI 0.4 SET ER118980 SET ER 129000 R VCC = 5V OFF186 OFF 0.2 VIN = 0V 184 180 VIN(CM) = GND fO = GND 182 170 TA = 25°C 0 180 160 0 1 2 3 4 5 –1 0 1 2 3 4 5 6 –45 –30 –15 0 15 30 45 60 75 90 VREF (V) VIN(CM) (V) TEMPERATURE (°C) 2493 G31 2493 G32 2493 G33 2493fe 9 For more information www.linear.com/LTC2493

LTC2493 Typical perForMance characTerisTics Offset Error vs V Offset Error vs V PSRR vs Frequency at V CC REF CC (2x Speed Mode) (2x Speed Mode) (2x Speed Mode) 250 240 0 OR (µV)125000 TVVVfOARIINN =E= (F =C G 2 M=0N5 )V2°D =C.5 GVND OR (µV) 222231000 TVVVfOACIINN C== ( =C =G2 M 0N55)V°VD =C GND N (dB) –––246000 RIIfTVRNNOACEE +– C=FF= ==+– =G2 =GG=N54 NN°.D2G1CDD.NV5DV DC ±0.7V R R O SET ER100 SET ER 210900 EJECTI –80 F F R F F O O –100 180 50 170 –120 0 160 –140 2 2.5 3 3.5 4 4.5 5 5.5 0 1 2 3 4 5 1 10 100 1k 10k 100k 1M VCC (V) VREF (V) FREQUENCY AT VCC (Hz) 2493 G34 2493 G35 2493 G36 PSRR vs Frequency at V PSRR vs Frequency at V CC CC (2x Speed Mode) (2x Speed Mode) 0 0 VCC = 4.1V DC ±1.4V VCC = 4.1V DC ±0.7V REF+ = 2.5V REF+ = 2.5V –20 REF– = GND –20 REF– = GND IN+ = GND IN+ = GND –40 IN– = GND –40 IN– = GND RREJECTION (dB) ––6800 fTOA == G2N5°DC REJECTION (dB) ––6800 fTOA == G2N5°DC –100 –100 –120 –120 –140 –140 0 20 40 60 80 100120140160180200220 30600 30650 30700 30750 30800 FREQUENCY AT VCC (Hz) FREQUENCY AT VCC (Hz) 2493 G37 2493 G38 2493fe 10 For more information www.linear.com/LTC2493

LTC2493 pin FuncTions f (Pin 1): Frequency Control Pin. Digital input that controls COM (Pin 7): The Common Negative Input (IN–) for All O the internal conversion clock rate. When f is connected Single-Ended Multiplexer Configurations. The voltage O to GND, the converter uses its internal oscillator running on CH0-CH3 and COM pins can have any value between at 307.2kHz. The conversion clock may also be overrid- GND – 0.3V to V + 0.3V. Within these limits, the two CC den by driving the f pin with an external clock in order to selected inputs (IN+ and IN– ) provide a bipolar input O change the output rate and the digital filter rejection null. range (V = IN+ – IN– ) from –0.5 • V to 0.5 • V . IN REF REF Outside this input range, the converter produces unique CA0, CA1 (Pins 2, 3): Chip Address Control Pins. These over-range and underrange output codes. pins are configured as a three-state (LOW, HIGH, floating) address control bits for the device’s I2C address. CH0 to CH3 (Pin 8-Pin 11): Analog Inputs. May be pro- grammed for single-ended or differential mode. SCL (Pin 4): Serial Clock Pin of the I2C Interface. The LTC2493 can only act as a slave and the SCL pin only V (Pin 12): Positive Supply Voltage. Bypass to GND with CC accepts an external serial clock. Data is shifted into the a 10µF tantalum capacitor in parallel with a 0.1µF ceramic SDA pin on the rising edges of the SCL clock and output capacitor as close to the part as possible. through the SDA pin on the falling edges of the SCL clock. REF+, REF– (Pin 13, Pin 14): Differential Reference Input. SDA (Pin 5): Bidirectional Serial Data Line of the I2C Inter- The voltage on these pins can have any value between face. In the transmitter mode (read), the conversion result GND and V as long as the reference positive input, REF+, CC is output through the SDA pin, while in the receiver mode remains more positive than the negative reference input, (write), the device channel select and configuration bits REF–, by at least 0.1V. The differential voltage (V = REF+ REF are input through the SDA pin. The pin is high impedance – REF–) sets the full-scale range for all input channels. during the data input mode and is an open-drain output When performing an on-chip temperature measurement, (requires an appropriate pull-up device to V ) during the the minimum value of REF = 2V. CC data output mode. Exposed Pad (Pin 15): Ground. This pin is ground and GND (Pin 6): Ground. Connect this pin to a common ground must be soldered to the PCB ground plane. For prototyping plane through a low impedance connection. purposes, this pin may remain floating. FuncTional block DiagraM INTERNAL VCC TEMP OSCILLATOR SENSOR GND AUTOCALIBRATION fO AND CONTROL (INT/EXT) REF+ REF– CH0 IN+ – + 1.7k CH1 DIFFERENTIAL SDA CH2 MUX IN– 3RD ORDER I2C SCL CH3 ∆∑ MODULATOR INTERFACE CA0 COM CA1 DECIMATING FIR ADDRESS 2493 BD 2493fe 11 For more information www.linear.com/LTC2493

LTC2493 applicaTions inForMaTion CONVERTER OPERATION POWER-ON RESET DEFAULT CONFIGURATION: Converter Operation Cycle IN+ = CH0, IN– = CH1 50Hz/60Hz REJECTION 1x OUTPUT The LTC2493 is a multichannel, low power, delta-sigma analog-to-digital converter with a 2-wire, I2C interface. Its operation is made up of four states (see Figure 1). The CONVERSION converter operating cycle begins with the conversion, followed by the sleep state and ends with the data input/ SLEEP output cycle. Initially, at power-up, the LTC2493 performs a conversion. Once the conversion is complete, the device enters the NO sleep state. While in the sleep state, power consumption ACKNOWLEDGE is reduced by two orders of magnitude. The part remains in the sleep state as long it is not addressed for a read/ YES write operation. The conversion result is held indefinitely DATA OUTPUT/INPUT in a static shift register while the part is in the sleep state. The device will not acknowledge an external request dur- ing the conversion state. After a conversion is finished, NO STOP OR READ the device is ready to accept a read/write request. Once 32 BITS the LTC2493 is addressed for a read operation, the device YES begins outputting the conversion result under the control 2493 F01 of the serial clock (SCL). There is no latency in the conver- sion result. The data output is 32 bits long and contains a Figure 1. State Transition Table 24-bit plus sign conversion result. Data is updated on the falling edges of SCL allowing the user to reliably latch data the user and has no effect on the operation cycle previ- on the rising edge of SCL. A new conversion is initiated by ously described. The advantage of continuous calibration a STOP condition following a valid write operation or an is extreme stability of offset and full-scale readings with incomplete read operation. The conversion automatically respect to time, supply voltage variation, input channel begins at the conclusion of a complete read cycle (all 32 and temperature drift. bits read out of the device). Easy Drive Input Current Cancellation Ease of Use The LTC2493 combines a high precision, delta-sigma ADC The LTC2493 data output has no latency, filter settling with an automatic, differential, input current cancellation delay, or redundant data associated with the conversion front end. A proprietary front end passive sampling network cycle. There is a one-to-one correspondence between the transparently removes the differential input current. This conversion and the output data. Therefore, multiplexing enables external RC networks and high impedance sen- multiple analog inputs is straightforward. Each conversion, sors to directly interface to the LTC2493 without external immediately following a newly selected input or mode, is amplifiers. The remaining common mode input current valid and accurate to the full specifications of the device. is eliminated by either balancing the differential input The LTC2493 automatically performs offset and full-scale impedances or setting the common mode input equal calibration every conversion cycle independent of the to the common mode reference (see the Automatic Dif- input channel selected. This calibration is transparent to ferential Input Current Cancellation section). This unique 2493fe 12 For more information www.linear.com/LTC2493

LTC2493 applicaTions inForMaTion architecture does not require on-chip buffers, thereby en- Input Voltage Range abling signals to swing beyond ground and V . Moreover, CC The LTC2493 input measurement range is –0.5•V to REF the cancellation does not interfere with the transparent +0.5•V in both differential and single-ended configura- REF offset and full-scale auto-calibration and the absolute ac- tions as shown in Figure 37. Highest linearity is achieved with curacy (full-scale + offset + linearity + drift) is maintained Fully Differential drive and a constant common-mode voltage even with external RC networks. (Figure 37b). Other drive schemes may incur an INL error of approximately 50ppm. This error can be calibrated out Power-Up Sequence using a three point calibration and a second-order curve fit. The LTC2493 automatically enters an internal reset state The analog inputs are truly differential with an absolute, when the power supply voltage, V , drops below ap- CC common mode range for the CH0-CH3 and COM input pins proximately 2.0V. This feature guarantees the integrity of extending from GND – 0.3V to V + 0.3V. Outside these the conversion result and input channel selection. CC limits, the ESD protection devices begin to turn on and When VCC rises above this threshold, the converter creates the errors due to input leakage current increase rapidly. an internal power-on reset (POR) signal with a duration Within these limits, the LTC2493 converts the bipolar of approximately 4ms. The POR signal clears all internal differential input signal V = IN+ – IN– (where IN+ and IN– IN registers. The conversion immediately following a POR are the selected input channels), from –FS = –0.5 • V REF cycle is performed on the input channel IN+ = CH0, IN– = to +FS = 0.5 • V where V = REF+ - REF–. Outside this REF REF CH1 with simultaneous 50Hz/60Hz rejection and 1x output range, the converter indicates the overrange or the under- rate. The first conversion following a POR cycle is accurate range condition using distinct output codes (see Table 1). within the specification of the device if the power supply In order to limit any fault current, resistors of up to 5k voltage is restored to (2.7V to 5.5V) before the end of the may be added in series with the input. The effect of series POR interval. A new input channel, rejection mode, speed resistance on the converter accuracy can be evaluated from mode, or temperature selection can be programmed into the curves presented in the Input Current/Reference Cur- the device during this first data input/output cycle. rent sections. In addition, series resistors will introduce a Reference Voltage Range temperature dependent error due to input leakage current. A 1nA input leakage current will develop a 1ppm offset This converter accepts a truly differential external refer- error on a 5k resistor if V = 5V. This error has a very ence voltage. The absolute/common mode voltage range REF strong temperature dependency. for the REF+ and REF– pins covers the entire operating range of the device (GND to VCC). For correct converter I2C INTERFACE operation, V must be positive (REF+ > REF–). REF The LTC2493 communicates through an I2C interface. The The LTC2493 differential reference input range is 0.1V to I2C interface is a 2-wire open-drain interface supporting V . For the simplest operation, REF+ can be shorted to CC multiple devices and multiple masters on a single bus. The V and REF– can be shorted to GND. The converter out- CC connected devices can only pull the data line (SDA) low put noise is determined by the thermal noise of the front and can never drive it high. SDA is required to be exter- end circuits and, as such, its value in nanovolts is nearly nally connected to the supply through a pull-up resistor. constant with reference voltage. A decrease in reference When the data line is not being driven, it is high. Data on voltage will not significantly improve the converter’s effec- the I2C bus can be transferred at rates up to 100kbits/s tive resolution. On the other hand, a decreased reference in the standard mode and up to 400kbits/s in the fast will improve the converter’s overall INL performance. mode. The V power should not be removed from the CC device when the I2C bus is active to avoid loading the I2C bus lines through the internal ESD protection diodes. 2493fe 13 For more information www.linear.com/LTC2493

LTC2493 applicaTions inForMaTion Each device on the I2C bus is recognized by a unique used for writing and reading from the device before the address stored in that device and can operate either as a initiation of a new conversion. transmitter or receiver, depending on the function of the device. In addition to transmitters and receivers, devices Data Transferring can also be considered as masters or slaves when perform- After the START condition, the I2C bus is busy and data ing data transfers. A master is the device which initiates a transfer can begin between the master and the addressed data transfer on the bus and generates the clock signals slave. Data is transferred over the bus in groups of nine to permit that transfer. Devices addressed by the master bits, one byte followed by one acknowledge (ACK) bit. The are considered a slave. master releases the SDA line during the ninth SCL clock The LTC2493 can only be addressed as a slave. Once cycle. The slave device can issue an ACK by pulling SDA addressed, it can receive configuration bits (channel low or issue a Not Acknowledge (NACK) by leaving the selection, rejection mode, speed mode) or transmit the SDA line high impedance (the external pull-up resistor will last conversion result. The serial clock line, SCL, is always hold the line high). Change of data only occurs while the an input to the LTC2493 and the serial data line SDA is clock line (SCL) is low. bidirectional. The device supports the standard mode and the fast mode for data transfer speeds up to 400kbits/s. DATA FORMAT Figure 2 shows the definition of the I2C timing. After a START condition, the master sends a 7-bit address followed by a read/write (R/W) bit. The R/W bit is 1 for The START and STOP Conditions a read request and 0 for a write request. If the 7-bit ad- A START (S) condition is generated by transitioning SDA dress matches the hard wired LTC2493’s address (one of from high to low while SCL is high. The bus is considered 9 pin-selectable addresses) the device is selected. When to be busy after the START condition. When the data the device is addressed during the conversion state, it will transfer is finished, a STOP (P) condition is generated by not acknowledge R/W requests and will issue a NACK by transitioning SDA from low to high while SCL is high. The leaving the SDA line high. If the conversion is complete, bus is free after a STOP is generated. START and STOP the LTC2493 issues an ACK by pulling the SDA line low. conditions are always generated by the master. The LTC2493 has two registers. The output register (32 When the bus is in use, it stays busy if a repeated START bits long) contains the last conversion result. The input (Sr) is generated instead of a STOP condition. The repeated register (16 bits long) sets the input channel, selects the START timing is functionally identical to the START and is temperature sensor, rejection mode, and speed mode. SDA tSU(DAT) tf tLOW tr tf tHD(SDA) tSP tr tBUF SCL tHD(SDA) tSU(STA) tSU(STO) S tHD(DAT) tHIGH Sr P S 2493 F02 Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus 2493fe 14 For more information www.linear.com/LTC2493

LTC2493 applicaTions inForMaTion DATA OUTPUT FORMAT The function of these bits is summarized in Table 2. The 24 bits following the MSB bit are the conversion result in The output register contains the last conversion result. binary two’s, complement format. The remaining six bits After each conversion is completed, the device automati- are sub LSBs below the 24-bit level. cally enters the sleep state where the supply current is reduced to 1µA. When the LTC2493 is addressed for a read As long as the voltage on the selected input channels (IN+ operation, it acknowledges (by pulling SDA low) and acts and IN–) remains between –0.3V and V + 0.3V (absolute CC as a transmitter. The master/receiver can read up to four maximum operating range) a conversion result is gener- bytes from the LTC2493. After a complete read operation ated for any differential input voltage V from –FS = –0.5 IN (4 bytes), a new conversion is initiated. The device will • V to +FS = 0.5 • V . For differential input voltages REF REF NACK subsequent read operations while a conversion is greater than +FS, the conversion result is clamped to the being performed. value corresponding to +FS. For differential input volt- ages below –FS, the conversion result is clamped to the The data output stream is 32 bits long and is shifted out value –FS – 1 LSB. on the falling edges of SCL (see Figure 3a). The first bit is the conversion result sign bit (SIG) (see Tables 1 and Table 2. LTC2493 Status Bits 2). This bit is high if V ≥ 0 and low if V < 0 (where V IN IN IN BIT 31 BIT 30 corresponds to the selected input signal IN+ – IN–). The INPUT RANGE SIG MSB second bit is the most significant bit (MSB) of the result. V ≥ FS 1 1 IN The first two bits (SIG and MSB) can be used to indicate 0V ≤ V < FS 1/ 0 0 IN over and under range conditions (see Table 2). If both bits –FS ≤ V < 0V 0 1 IN are high, the differential input voltage is equal to or above V < –FS 0 0 IN +FS. If both bits are set low, the input voltage is below –FS. Table 1. Output Data Format DIFFERENTIAL INPUT VOLTAGE BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 … BIT 6 BITS 5-0 V * SIG MSB LSB Sub LSBs IN V * ≥ FS** 1 1 0 0 0 … 0 00000 IN FS** – 1 LSB 1 0 1 1 1 … 1 XXXXX 0.5 • FS** 1 0 1 0 0 … 0 XXXXX 0.5 • FS** – 1 LSB 1 0 0 1 1 … 1 XXXXX 0 1/0† 0 0 0 0 … 0 XXXXX –1 LSB 0 1 1 1 1 … 1 XXXXX –0.5 • FS** 0 1 1 0 0 … 0 XXXXX –0.5 • FS** – 1 LSB 0 1 0 1 1 … 1 XXXXX –FS** 0 1 0 0 0 … 0 XXXXX V * < –FS** 0 0 1 1 1 … X XXXXX‡ IN * The differential input voltage VIN = IN+ – IN–. ** The full-scale voltage FS = 0.5 • VREF. Sub LSBs are below the 24-bit level. They may be included in averaging, or discarded without loss of resolution. † The sign bit changes state during the 0 output code when the device is operating in the 2x speed mode. ‡ The underrange output code is 0X3FFFFXXX in 2x mode. 2493fe 15 For more information www.linear.com/LTC2493

LTC2493 applicaTions inForMaTion INPUT DATA FORMAT If the first three bits are 000 or 100, the following data is ignored (don’t care) and the previously selected input The serial input word to the LTC2493 is 13 bits long and channel remains valid for the next conversion. is written into the device input register in two 8-bit words. The first word (SGL, ODD, A2, A1, A0) is used to select If the first three bits shifted into the device are 101, then the input channel. The second word of data (IM, FA, FB, the next five bits select the input channel for the next SPD) is used to select the frequency rejection, speed mode conversion cycle (see Table 3). (1×, 2×), and temperature measurement. Table 3. Channel Selection After power-up, the device initiates an internal reset cycle MUX ADDRESS CHANNEL SELECTION which sets the input channel to CH0-CH1 (IN+ = CH0, IN– = ODD/ CH1), the frequency rejection to simultaneous 50Hz/60Hz, SGL SIGN A2 A1 A0 0 1 2 3 COM and 1× output rate (auto-calibration enabled). The first *0 0 0 0 0 IN+ IN– conversion automatically begins at power-up using this 0 0 0 0 1 IN+ IN– default configuration. Once the conversion is complete, 0 1 0 0 0 IN– IN+ up to two words may be written into the device. 0 1 0 0 1 IN– IN+ The first three bits of the first input word consist of two 1 0 0 0 0 IN+ IN– preamble bits and one enable bit. Valid settings for these 1 0 0 0 1 IN+ IN– three bits are 000, 100, and 101. Other combinations 1 1 0 0 0 IN+ IN– should be avoided. 1 1 0 0 1 IN+ IN– *Default at power-up 1 … 7 8 9 1 2 … 9 1 2 3 4 5 6 7 8 9 SCL SDA 7-BIT ADDRESS R SIG MSB D31 LSB ACK BY ACK BY NACK BY START BY LTC2493 MASTER SUB LSBs MASTER MASTER SLEEP DATA OUTPUT 2493 F03a Figure 3a. Timing Diagram for Reading from the LTC2493 1 2 … 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL SDA 7-BIT ADDRESS W 1 0 EN SGL ODD A2 A1 A0 EN2 IM FA FB SPD ACK BY ACK BY (OPTIONAL 2ND BYTE) ACK BY START BY LTC2493 LTC2493 LTC2493 MASTER SLEEP DATA INPUT 2493 F03b Figure 3b. Timing Diagram for Writing to the LTC2493 2493fe 16 For more information www.linear.com/LTC2493

LTC2493 applicaTions inForMaTion The first input bit (SGL) following the 101 sequence de- set the rejection frequency. The final bit (SPD) is used to termines if the input selection is differential (SGL = 0) or select either the 1× output rate if SPD = 0 (auto-calibration single-ended (SGL = 1). For SGL = 0, two adjacent chan- is enabled and the offset is continuously calibrated and nels can be selected to form a differential input. For SGL removed from the final conversion result) or the 2× output = 1, one of four channels is selected as the positive input. rate if SPD = 1 (offset calibration disabled, multiplexing The negative input is COM for all single-ended operations. output rates up to 15Hz with no latency). When IM = 1 The remaining four bits (ODD, A2, A1, A0) determine (temperature measurement) SPD will be ignored and the which channel(s) is/are selected and the polarity (for a device will operate in 1× mode. differential input). The configuration remains valid until a new input word with Once the first word is written into the device, a second EN = 1 (the first three bits are 101 for the first word) and EN2 word may be input in order to select a configuration mode. = 1 (for the second write byte) is shifted into the device. The first bit of the second word is the enable bit for the conversion configuration (EN2). If this bit is set to 0, then Rejection Mode (FA, FB) the next conversion is performed using the previously selected converter configuration. The LTC2493 includes a high accuracy on-chip oscillator with no required external components. Coupled with an The second set of configuration data can be loaded into integrated fourth order digital lowpass filter, the LTC2493 the device by setting EN2 = 1 (see Table 4). The first bit rejects line frequency noise. In the default mode, the (IM) is used to select the internal temperature sensor. If LTC2493 simultaneously rejects 50Hz and 60Hz by at least IM = 1, the following conversion will be performed on 87dB. If more rejection is required, the LTC2493 can be the internal temperature sensor rather than the selected configured to reject 50Hz or 60Hz to better than 110dB. input channel. The next two bits (FA and FB) are used to Table 4. Converter Configuration 1 0 EN SGL ODD A2 A1 A0 EN2 IM FA FB SPD CONVERTER CONFIGURATION 1 0 0 X X X X X X X X X X Keep Previous 1 0 1 X X X X X 0 X X X X Keep Previous 0 0 1 X X X X X X X X X X Keep Previous 1 0 1 X X X X X 1 0 0 0 0 External Input (See Table 3) 50Hz/60Hz Rejection, 1× 1 0 1 X X X X X 1 0 0 1 0 External Input (See Table 3) 50Hz Rejection, 1× 1 0 1 X X X X X 1 0 1 0 0 External Input (See Table 3) 60Hz Rejection, 1× 1 0 1 X X X X X 1 0 0 0 1 External Input (See Table 3) 50Hz/60Hz Rejection, 2× 1 0 1 X X X X X 1 0 0 1 1 External Input (See Table 3) 50Hz Rejection, 2× 1 0 1 X X X X X 1 0 1 0 1 External Input (See Table 3) 60Hz Rejection, 2× 1 0 1 X X X X X 1 1 0 0 X Measure Temperature 50Hz/60Hz Rejection, 1× 1 0 1 X X X X X 1 1 0 1 X Measure Temperature 50Hz Rejection, 1× 1 0 1 X X X X X 1 1 1 0 X Measure Temperature 60Hz Rejection, 1× 1 0 1 X X X X X 1 X 1 1 X Reserved, Do Not Use 2493fe 17 For more information www.linear.com/LTC2493

LTC2493 applicaTions inForMaTion Speed Mode (SPD) the reference voltage (V ) is known. A 5V reference has REF a slope of 314 LSBs /°C. The temperature is calculated Every conversion cycle, two conversions are combined 24 from the output code (where DATAOUT is the decimal to remove the offset (default mode). This result is free 24 representation of the 24-bit result) for a 5V reference using from offset and drift. In applications where the offset is the following formula: not critical, the auto-calibration feature can be disabled with the benefit of twice the output rate. DATAOUT T = 24 inKelvin K While operating in the 2× mode (SPD = 1), the linearity 314 and full-scale errors are unchanged from the 2× mode If a different value of V is used, the temperature REF performance. In both the 2× and 2× mode there is no output is: latency. This enables input steps or multiplexer changes DATAOUT • V to settle in a single conversion cycle, easing system over- T = 24 REF inKelvin K head and increasing the effective conversion rate. During 1570 temperature measurements, the 1× mode is always used If the value of V is not known, the slope is determined independent of the value of SPD. REF by measuring the temperature sensor at a known tempera- Temperature Sensor ture TN (in K) and using the following formula: The LTC2493 includes an integrated temperature sen- DATAOUT SLOPE = 24 sor. The temperature sensor is selected by setting T N IM = 1. The ADC internally connects to the temperature This value of slope can be used to calculate further tem- sensor and performs a conversion. perature readings using: The digital output is proportional to the absolute tem- DATAOUT perature of the device. This feature allows the converter T = 24 K to perform cold junction compensation for external SLOPE thermocouples or continuously remove the temperature All Kelvin temperature readings can be converted to T effects of external sensors. C (°C) using the fundamental equation: The internal temperature sensor output is 28mV at 27°C T = T – 273 (300°K), with a slope of 93.5µV/°C independent of V C K REF (see Figures 4 and 5). Slope calibration is not required if 140000 5 VCC = 5V 120000 SVLROEFP =E 5=V 314 LSB24/K 43 100000 R (°C) 2 T24 80000 RO 1 U R DATAO 60000 LUTE E –10 O S 40000 AB –2 –3 20000 –4 0 –5 0 100 200 300 400 –55 –30 –5 20 45 70 95 120 TEMPERATURE (K) TEMPERATURE (°C) 2493 F04 2493 F05 Figure 4. Internal PTAT Digital Output vs Temperature Figure 5. Absolute Temperature Error 2493fe 18 For more information www.linear.com/LTC2493

LTC2493 applicaTions inForMaTion Initiating a New Conversion Table 5. Address Assignment CA1 CA0 ADDRESS When the LTC2493 finishes a conversion, it automatically LOW LOW 0010100 enters the sleep state. Once in the sleep state, the device is ready for a read operation. After the device acknowledges LOW HIGH 0010110 a read request, the device exits the sleep state and enters LOW Float 0010101 the data output state. The data output state concludes HIGH LOW 0100110 and the LTC2493 starts a new conversion once a STOP HIGH HIGH 0110100 condition is issued by the master or all 32 bits of data are HIGH Float 0100111 read out of the device. Float LOW 0010111 Float HIGH 0100101 During the data read cycle, a STOP command may be issued by the master controller in order to start a new conversion Float Float 0100100 and abort the data transfer. This STOP command must be issued during the ninth clock cycle of a byte read when measure the internal temperature, selecting the line fre- the bus is free (the ACK/NACK cycle). quency rejection (50Hz, 60Hz, or simultaneous 50Hz and 60Hz) and a 2× speed mode. LTC2493 Address Continuous Read The LTC2493 has two address pins (CA0, CA1). Each may be tied HIGH, LOW, or left floating enabling one of nine In applications where the input channel/configuration does possible addresses (see Table 5). not need to change for each cycle, the conversion can be continuously performed and read without a write cycle In addition to the configurable addresses listed in Table 5, (see Figure 7). The configuration/input channel remains the LTC2493 also contains a global address (1110111) unchanged from the last value written into the device. If which may be used for synchronizing multiple LTC2493s or the device has not been written to since power-up, the other LTC24XX delta-sigma I2C devices (see Synchronizing configuration is set to the default value. At the end of a Multiple LTC2493s with a Global Address Call section). read operation, a new conversion automatically begins. At the conclusion of the conversion cycle, the next result Operation Sequence may be read using the method described above. If the The LTC2493 acts as a transmitter or receiver, as shown conversion cycle is not concluded and a valid address in Figure 6. The device may be programmed to perform selects the device, the LTC2493 generates a NACK signal several functions. These include input channel selection, indicating the conversion cycle is in progress. S 7-BIT ADDRESS R/W ACK DATA Sr DATA TRANSFERRING P CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION 2493 F05 Figure 6. Conversion Sequence 2493fe 19 For more information www.linear.com/LTC2493

LTC2493 applicaTions inForMaTion Continuous Read/Write and 60Hz) is used but the channel is changed, a STOP or repeated START may be issued after the first byte (channel Once the conversion cycle is concluded, the LTC2493 selection data) is written into the device. can be written to and then read from using the repeated START (Sr) command. Discarding a Conversion Result and Initiating a New Figure 8 shows a cycle which begins with a data write, a Conversion with Optional Write repeated START, followed by a read and concluded with At the conclusion of a conversion cycle, a write cycle a STOP command. The following conversion begins after can be initiated. Once the write cycle is acknowledged, a all 32 bits are read out of the device or after a STOP com- STOP command will start a new conversion. If a new input mand. The following conversion will be performed using the channel or conversion configuration is required, this data newly programmed data. In cases where the same speed can be written into the device and a STOP command will (1×/2× mode) and rejection frequency (50Hz, 60Hz, 50Hz initiate the next conversion (see Figure 9). S 7-BIT ADDRESS R ACK READ P S 7-BIT ADDRESS R ACK READ P CONVERSION SLEEP DATA INPUT CONVERSION SLEEP DATA OUTPUT CONVERSION 2493 F07 Figure 7. Consecutive Reading with the Same Input/Configuration S 7-BIT ADDRESS W ACK WRITE Sr 7-BIT ADDRESS R ACK READ P CONVERSION SLEEP DATA INPUT ADDRESS DATA OUTPUT CONVERSION 2493 F08 Figure 8. Write, Read, START Conversion S 7-BIT ADDRESS W ACK WRITE (OPTIONAL) P CONVERSION SLEEP DATA INPUT CONVERSION 2493 F09 Figure 9. Start a New Conversion Without Reading Old Conversion Result 2493fe 20 For more information www.linear.com/LTC2493

LTC2493 applicaTions inForMaTion Synchronizing Multiple LTC2493s with a Global Figure 10). In order to synchronize multiple converters Address Call without changing the channel or configuration, a STOP may be issued after acknowledgement of the global write In applications where several LTC2493s (or other I2C command. Global read commands are not allowed and delta-sigma ADCs from Linear Technology Corporation) the converters will NACK a global read request. are used on the same I2C bus, all converters can be syn- chronized through the use of a global address call. Prior Driving the Input and Reference to issuing the global address call, all converters must have completed a conversion cycle. The master then is- The input and reference pins of the LTC2493 are connected sues a START, followed by the global address 1110111, directly to a switched capacitor network. Depending on and a write request. All converters will be selected and the relationship between the differential input voltage and acknowledge the request. The master then sends a write the differential reference voltage, these capacitors are byte (optional) followed by the STOP command. This switched between these four pins. Each time a capacitor will update the channel selection (optional) converter is switched between two of these pins, a small amount configuration (optional) and simultaneously initiate a start of charge is transferred. A simplified equivalent circuit is of conversion for all delta-sigma ADCs on the bus (see shown in Figure 11. SCL SDA LTC2493 LTC2493 … LTC2493 S GLOBAL ADDRESS W ACK WRITE (OPTIONAL) P ALL LTC2493s IN SLEEP CONVERSION OF ALL LTC2493s DATA INPUT 2493 F10 Figure 10. Synchronize Multiple LTC2493s with a Global Address Call INPUT INTERNAL MULTIPLEXER SWITCH IIN+ NETWORK I(IN+) =I(IN–) =VIN(CM)−VREF(CM) IN+ 100Ω 10k I(REF+A)VG ≈1.5VARVEGF+(VREF0(C.5M•)R–EVQIN(CM))– VIN2 AVG 0.5•REQ VREF•REQ IIN– where: IN– 100Ω 10k VREF=REF+−REF− ⎛REF+–REF−⎞ VREF(CM)=⎝⎜⎜ 2 ⎠⎟⎟ IREF+ C12EQµF VIN=IN+−IN−,WHEREIN+ANDIN−ARETHESELECTEDINPUTCHANNELS 10k REF+ VIN(CM)=⎛⎝⎜⎜IN+–2IN−⎞⎠⎟⎟ R =2.71MΩINTERNALOSCILLATOR60HzMODE IREF– EQ R =2.98MΩINTERNALOSCILLATOR50Hz/60Hz MODE EQ 10k REF– 2493 F11a REQ=(0.833•1012)/fEOSCEXTERNALOSCILLATOR SWITCHING FREQUENCY fSW = 123kHz INTERNAL OSCILLATOR fSW = 0.4 • fEOSC EXTERNAL OSCILLATOR Figure 11. Equivalent Analog Input Circuit 2493fe 21 For more information www.linear.com/LTC2493

LTC2493 applicaTions inForMaTion When using the LTC2493’s internal oscillator, the input input voltage (V ) and the common mode reference IN(CM) capacitor array is switched at 123kHz. The effect of the voltage (V ). REF(CM) charge transfer depends on the circuitry driving the input/ In applications where the input common mode voltage is reference pins. If the total external RC time constant is less equal to the reference common mode voltage, as in the than 580ns the errors introduced by the sampling process case of a balanced bridge, both the differential and com- are negligible since complete settling occurs. mon mode input current are zero. The accuracy of the Typically, the reference inputs are driven from a low converter is not compromised by settling errors. impedance source. In this case, complete settling occurs In applications where the input common mode voltage is even with large external bypass capacitors. The inputs constant but different from the reference common mode (CH0-CH3, COM), on the other hand, are typically driven voltage, the differential input current remains zero while from larger source resistances. Source resistances up the common mode input current is proportional to the to 10k may interface directly to the LTC2493 and settle difference between V and V . For a reference completely; however, the addition of external capacitors IN(CM) REF(CM) common mode voltage of 2.5V and an input common mode at the input terminals in order to filter unwanted noise of 1.5V, the common mode input current is approximately (anti-aliasing) results in incomplete settling. 0.74µA (in simultaneous 50Hz/60Hz rejection mode). This common mode input current does not degrade the accuracy Automatic Differential Input Current Cancellation if the source impedances tied to IN+ and IN– are matched. In applications where the sensor output impedance is Mismatches in source impedance lead to a fixed offset low (up to 10kΩ with no external bypass capacitor or up error but do not effect the linearity or full-scale reading. to 500Ω with 0.001µF bypass), complete settling of the A 1% mismatch in a 1k source resistance leads to a 74µV input occurs. In this case, no errors are introduced and shift in offset voltage. direct digitization is possible. In applications where the common mode input voltage For many applications, the sensor output impedance varies as a function of the input signal level (single-ended combined with external input bypass capacitors produces type sensors), the common mode input current varies RC time constants much greater than the 580ns required proportionally with input voltage. For the case of balanced for 1ppm accuracy. For example, a 10k bridge driving a input impedances, the common mode input current effects 0.1µF capacitor has a time constant an order of magnitude are rejected by the large CMRR of the LTC2493, leading greater than the required maximum. to little degradation in accuracy. Mismatches in source The LTC2493 uses a proprietary switching algorithm impedances lead to gain errors proportional to the dif- that forces the average differential input current to zero ference between the common mode input and common independent of external settling errors. This allows direct mode reference. 1% mismatches in 1k source resistances digitization of high impedance sensors without the need lead to gain errors on the order of 15ppm. Based on the for buffers. stability of the internal sampling capacitors and the ac- curacy of the internal oscillator, a one-time calibration will The switching algorithm forces the average input current remove this error. on the positive input (I +) to be equal to the average input IN current on the negative input (I –). Over the complete In addition to the input sampling current, the input ESD IN conversion cycle, the average differential input current protection diodes have a temperature dependent leakage (I + – I –) is zero. While the differential input current is current. This current, nominally 1nA (±10nA max), results IN IN zero, the common mode input current (I + + I –)/2 is in a small offset shift. A 1k source resistance will create a IN IN proportional to the difference between the common mode 1µV typical and a 10µV maximum offset voltage. 2493fe 22 For more information www.linear.com/LTC2493

LTC2493 applicaTions inForMaTion Reference Current for reference impedances of many kΩ (if C = 100pF REF up to 10k will not degrade the performance (see Figures Similar to the analog inputs, the LTC2493 samples the differential reference pins (REF+ and REF–) transferring 12 and 13)). small amounts of charge to and from these pins, thus In cases where large bypass capacitors are required on producing a dynamic reference current. If incomplete set- the reference inputs (C > .01µF), full-scale and linear- REF tling occurs (as a function the reference source resistance ity errors are proportional to the value of the reference and reference bypass capacitance) linearity and gain errors resistance. Every ohm of reference resistance produces are introduced. a full-scale error of approximately 0.5ppm (while operat- For relatively small values of external reference capacitance ing in simultaneous 50Hz/60Hz mode (see Figures 14 (C < 1nF), the voltage on the sampling capacitor settles and 15)). If the input common mode voltage is equal to REF 90 10 VCC = 5V 80 VREF = 5V 0 ppm) 576000 VfTVOAIINN ==+– G2==N5 31°D..C7255VV ppm) –––312000 CCRCRERFECE F=FR = E=0 F 0.1 0=.000 0011µµppFFFF R ( CREF = 0.01µF R ( RO 40 CREF = 0.001µF RO–40 FS ER 30 CRCEFR E=F 1 =0 00ppFF FS ER –50 VCC = 5V + 20 ––60 VREF = 5V 10 –70 VVIINN+– == 13..2755VV 0 –80 fO = GND TA = 25°C –10 –90 0 10 100 1k 10k 100k 0 10 100 1k 10k 100k RSOURCE (Ω) RSOURCE (Ω) 2493 F12 2493 F13 Figure 12. +FS Error vs R at V (Small C ) Figure 13. –FS Error vs R at V (Small C ) SOURCE REF REF SOURCE REF REF 500 0 VVCRCEF = = 5 5VV CREF = 1µF, 10µF 400 VVIINN+– == 31..7255VV –100 ppm) 300 fTOA == G2N5°DC CREF = 0.1µF ppm)–200 CREF = 0.01µF R ( R ( RO RO CREF = 1µF, 10µF R R +FS E 200 CREF = 0.01µF –FS E–300 VVCRCEF = = 5 5VV CREF = 0.1µF 100 –400 VVIINN+– == 13..2755VV fO = GND TA = 25°C 0 –500 0 200 400 600 800 1000 0 200 400 600 800 1000 RSOURCE (Ω) RSOURCE (Ω) 2493 F14 2493 F15 Figure 14. +FS Error vs R at V (Large C ) Figure 15. –FS Error vs R at V (Large C ) SOURCE REF REF SOURCE REF REF 2493fe 23 For more information www.linear.com/LTC2493

LTC2493 applicaTions inForMaTion the reference common mode voltage, a linearity error of The SINC4 digital filter provides excellent normal mode approximately 0.67ppm per 100Ω of reference resistance rejection at all frequencies except DC and integer multiples results (see Figure 16). In applications where the input of the modulator sampling frequency (f ) (see Figures S and reference common mode voltages are different, the 17 and 18). The modulator sampling frequency is f = S errors increase. A 1V difference in between common mode 15,360Hz while operating with its internal oscillator and input and common mode reference results in a 6.7ppm f = f /20 when operating with an external oscillator S EOSC INL error for every 100Ω of reference resistance. of frequency f . EOSC In addition to the reference sampling charge, the reference 0 ESD protection diodes have a temperature dependent leak- B) –10 age current. This leakage current, nominally 1nA (±10nA N (d –20 O max) results in a small gain error. A 100Ω reference TI –30 C E –40 resistance will create a 0.5µV full-scale error. J E E R –50 OD –60 Normal Mode Rejection and Anti-Aliasing M L –70 A M –80 One of the advantages delta-sigma ADCs offer over NOR –90 conventional ADCs is on-chip digital filtering. Combined UT –100 P with a large oversample ratio, the LTC2493 significantly IN –110 –120 simplifies anti-aliasing filter requirements. Additionally, 0 fS 2fS3fS4fS5fS6fS7fS8fS9fS10fS11fS12fS the input current cancellation feature allows external DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) lowpass filtering without degrading the DC performance 2493 F17 of the device. Figure 17. Input Normal Mode Rejection, Internal Oscillator and 50Hz Rejection Mode 10 0 VCC = 5V 68 VVRINE(FC M= )5 =V 2.5V R = 1k N (dB) ––1200 m OF V)REF 204 CTAR E=F 2=5 1°C0µF R = 500Ω ODE REJECTIO ––––34560000 NL (pp –2 R = 100Ω MAL M ––7800 I –4 R NO –90 –6 T U –100 P –8 IN –110 –10 –120 –0.5 –0.3 –0.1 0.1 0.3 0.5 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS10fS VIN/VREF DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2493 F16 2493 F18 Figure 16. INL vs Differential Input Voltage and Figure 18. Input Normal Mode Rejection, Internal Reference Source Resistance for CREF > 1µF Oscillator and 60Hz Rejection Mode 2493fe 24 For more information www.linear.com/LTC2493

LTC2493 applicaTions inForMaTion When using the internal oscillator, the LTC2493 is designed Traditional high order delta-sigma modulators suffer to reject line frequencies. As shown in Figure 19, rejec- from potential instabilities at large input signal levels. tion nulls occur at multiples of frequency f , where f is The proprietary architecture used for the LTC2493 third N N determined by the input control bits FA and FB (fN = 50Hz order modulator resolves this problem and guarantees or 60Hz or 55Hz for simultaneous rejection). Multiples stability with input signals 150% of full-scale. In many of the modulator sampling rate (fS = fN • 256) only reject industrial applications, it is not uncommon to have mi- noise to 15dB (see Figure 20); if noise sources are present crovolt level signals superimposed over unwanted error at these frequencies anti-aliasing will reduce their effects. sources with several volts if peak-to-peak noise. Figures 24 and 25 show measurement results for the rejection The user can expect to achieve this level of performance of a 7.5V peak-to-peak noise source (150% of full-scale) using the internal oscillator, as shown in Figures 21, 22, applied to the LTC2493. These curves show that the rejec- and 23. Measured values of normal mode rejection are tion performance is maintained even in extremely noisy shown superimposed over the theoretical values in all environments. three rejection modes. 0 fN = fEOSC/5120 B) –10 d N ( –20 O TI –30 C E –40 J E E R –50 OD –60 M L –70 A M –80 R NO –90 T U –100 P IN –110 –120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN 8fN INPUT SIGNAL FREQUENCY (Hz) 2493 F19 Figure 19. Input Normal Mode Rejection at DC 0 fN = fEOSC/5120 B) –10 d N ( –20 O TI –30 C E –40 J E E R –50 OD –60 M L –70 A M –80 R NO –90 T U –100 P IN –110 –120 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz) 2493 F20 Figure 20. Input Normal Mode Rejection at f = 256 • f S N 2493fe 25 For more information www.linear.com/LTC2493

LTC2493 applicaTions inForMaTion 0 0 MEASURED DATA VCC = 5V MEASURED DATA VCC = 5V N (dB) –20 CALCULATED DATA VVVRIINNE((FCP M-=P ))5 ==V 25.V5V N (dB) –20 CALCULATED DATA VVVRIINNE((FCP M-=P ))5 ==V 25.V5V DE REJECTIO ––4600 TA = 25°C DE REJECTIO ––4600 TA = 25°C O O M M MAL –80 MAL –80 R R O O N –100 N –100 –120 –120 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 0 12.5 25 37.5 50 62.5 75 87.5 100112.5125137.5150162.5175187.5200 INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) 2493 F21 2493 F22 Figure 21. Input Normal Mode Rejection vs Input Frequency with Figure 22. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% (60Hz Notch) Input Perturbation of 100% (50Hz Notch) 0 0 N (dB) –20 MCAELACSUULRAETDE DD ADTAATA VVVVCRIINNCE((F CP= M-= P5 ))5V ==V 25.V5V N (dB) –20 VV(1IINN5((0PP%--PP ))O ==F 57FV.U5LVL SCALE) VVVTACRIN CE=(F C = 2M= 55 )5°V =CV 2.5V DE REJECTIO ––4600 TA = 25°C DE REJECTIO ––4600 O O M M MAL –80 MAL –80 R R O O N –100 N –100 –120 –120 0 12.5 25 37.5 50 62.5 75 87.5 100112.5125137.5150162.5175187.5200 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) 2493 F23 2493 F24 Figure 23. Input Normal Mode Rejection vs Input Frequency with Figure 24. Measure Input Normal Mode Rejection vs Input Input Perturbation of 100% (50Hz/60Hz Notch) Frequency with Input Perturbation of 150% (60Hz Notch) 0 N (dB) –20 VV(1IINN5((0PP%--PP ))O ==F 57FV.U5LVL SCALE) VVVTACRIN CE=(F C = 2M= 55 )5°V =CV 2.5V O CTI –40 DE REJE –60 O M AL –80 M R O N –100 –120 0 12.5 25 37.5 50 62.5 75 87.5 100112.5125137.5150162.5175187.5200 INPUT FREQUENCY (Hz) 2493 F25 Figure 25. Measure Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% (50Hz Notch) 2493fe 26 For more information www.linear.com/LTC2493

LTC2493 applicaTions inForMaTion Using the 2× speed mode of the LTC2493 alters the rejec- and effective resolution as well as a shift in frequency rejec- tion characteristics around DC and multiples of f . The tion. When using the integrated temperature sensor, the S device bypasses the offset calibration in order to increase internal oscillator should be used or an external oscillator the output rate. The resulting rejection plots are shown f = 307.2kHz maximum. EOSC in Figures 26 and 27. 1× type frequency rejection can be A change in f results in a proportional change in the achieved using the 2× mode by performing a running aver- EOSC internal notch position. This leads to reduced differential age of the previous two conversion results (see Figure 28). mode rejection of line frequencies. The common mode rejection of line frequencies remains unchanged, thus fully Output Data Rate differential input signals with a high degree of symmetry When using its internal oscillator, the LTC2493 produces on both the IN+ and IN– pins will continue to reject line up to 15 samples per second (sps) with a notch frequency of frequency noise. 60Hz. The actual output data rate depends upon the length of the sleep and data output cycles which are controlled An increase in fEOSC also increases the effective dynamic by the user and can be made insignificantly short. When input and reference current. External RC networks will operating with an external conversion clock (f connected continue to have zero differential input current, but the O to an external oscillator), the LTC2493 output data rate time required for complete settling (580ns for f = EOSC can be increased. The duration of the conversion cycle is 307.2kHz) is reduced, proportionally. 41036/f . If f = 307.2kHz, the converter behaves EOSC EOSC Once the external oscillator frequency is increased as if the internal oscillator is used. above 1MHz (a more than 3× increase in output rate) An increase in f over the nominal 307.2kHz will trans- the effectiveness of internal auto-calibration circuits EOSC late into a proportional increase in the maximum output begins to degrade. This results in larger offset errors, data rate (up to a maximum of 100sps). The increase in full-scale errors, and decreased resolution, as seen in output rate leads to degradation in offset, full-scale error, Figures 29-36. 0 0 B)–20 B) –20 N (d N (d O O CTI–40 CTI –40 AL REJE–60 AL REJE –60 M M R R NO–80 NO –80 UT UT P P IN–100 IN–100 –120 –120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN 8fN 248 250 252 254 256 258 260 262 264 INPUT SIGNAL FREQUENCY (fN) INPUT SIGNAL FREQUENCY (fN) 2493 F26 2493 F27 Figure 26. Input Normal Mode Rejection 2× Speed Mode Figure 27. Input Normal Mode Rejection 2× Speed Mode 2493fe 27 For more information www.linear.com/LTC2493

LTC2493 applicaTions inForMaTion –70 50 3500 VIN(CM) = VREF(CM) VIN(CM) = VREF(CM) ODE REJECTION (dB)––––1189010000 NO AVERRAAVUGWENERINTAIHNGGE ROR (ppm OF V)REF324000 VVfOCI NC= ==E X0VVTR ECFL =O C5KV OR (ppm OF V)REF2312005500000000 VfOC C= =E XVTR ECFL =O C5KV M R R NORMAL ––112300 OFFSET E 100 TA = 25°C +FS ER1050000 TA = 25°C TA = 85°C TA = 85°C –140 –10 0 48 50 52 54 56 58 60 62 0 10 20 30 0 10 20 30 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) OUTPUT DATA RATE (READINGS/SEC) OUTPUT DATA RATE (READINGS/SEC) 2493 F28 2493 F29 2493 F30 Figure 28. Input Normal Mode Figure 29. Offset Error vs Output Data Figure 30. +FS Error vs Output Data Rejection 2× Speed Mode with and Rate and Temperature Rate and Temperature Without Running Averaging 0 24 22 TA = 85°C –500 TA = 25°C 22 TA = 85°C 20 TA = 25°C OF V)REF–1000 BITS)20 TA = 25°C BITS)18 TA = 85°C ROR (ppm ––12500000 OLUTION (1186 OLUTION (16 –FS ER––23500000 VVICNC( C=M V) R=E FV R=E 5FV(CM) RES1142 VVVfOICINN C=( =C=E M X0V)VT R= EC FVL R=OE C5FKV(CM) RES1142 VVfOICN C=( C=EM XV)T R= EC FVL R=OE C5FKV(CM) fO = EXT CLOCK RES = LOG 2 (VREF/NOISERMS) RES = LOG 2 (VREF/INLMAX) –3500 10 10 0 10 20 30 0 10 20 30 0 10 20 30 OUTPUT DATA RATE (READINGS/SEC) OUTPUT DATA RATE (READINGS/SEC) OUTPUT DATA RATE (READINGS/SEC) 2493 F31 2493 F32 2493 F33 Figure 31.–FS Error vs Output Data Figure 32. Resolution (Noise ≤ 1 LSB) Figure 33. Resolution (INL ≤ 1 LSB) RMS MAX Rate and Temperature vs Output Data Rate and Temperature vs Output Data Rate and Temperature 20 24 22 VVIINN( =C M0)V = VREF(CM) 22 VCC = VREF = 5V VCC = 5V, VREF = 2.5V OF V)REF 1150 TfOA == E2X5T° CCLOCK TS) 20 VCC = 5V, VREF = 2.5V TS)2108 VCC = VREF = 5V m BI BI pp N ( 18 N ( OFFSET ERROR ( –055 VCC V=C 5CV =, VVRREEFF == 25.V5V RESOLUTIO 111462 TVVfOAIINN ==( =C E2 MX05)VT° = CC VLROECFK(CM) RESOLUTIO111462 fTVVROAIIENN =F=( –=C E2 M=X05 )VT°G = CNC VLDROECFK(CM) RES = LOG 2 (VREF/NOISERMS) RES = LOG 2 (VREF/INLMAX) –10 10 10 0 10 20 30 0 10 20 30 0 10 20 30 40 50 60 70 80 90 100 OUTPUT DATA RATE (READINGS/SEC) OUTPUT DATA RATE (READINGS/SEC) OUTPUT DATA RATE (READINGS/SEC) 2493 F34 2493 F35 2493 F36 Figure 34. Offset Error vs Output Figure 35. Resolution Figure 36. Resolution Data Rate and Reference Voltage (Noise ≤ 1 LSB) vs Output Data (INL ≤ 1 LSB) vs Output Data RMS MAX Rate and Reference Voltage Rate and Reference Voltage 2493fe 28 For more information www.linear.com/LTC2493

LTC2493 applicaTions inForMaTion V + 0.3V CC VCC VCC V REF 2 VREF VREF –VREF 2 2 2 –V REF 2 GND GND –0.3V (a) Arbitrary (b) Fully Differential VCC VCC V REF 2 –V2REF VR2EF –0.3V GND GND –0.3V (c) Pseudo Differential Bipolar IN– or COM Biased (d) Pseudo-Differential Unipolar IN– or COM Grounded Selected IN+ Ch Selected IN– Ch or COM 2492 F37 Figure 37. Input Range Easy Drive ADCs Simplify Measurement of High error of the reference resistors themselves. No amplifier Impedance Sensors is required, making this an ideal solution in micropower applications. Delta-sigma ADCs, with their high accuracy and high noise immunity, are ideal for directly measuring many types Easy Drive also enables very low power, low bandwidth of sensors. Nevertheless, input sampling currents can amplifiers to drive the input to the LTC2493. As shown overwhelm high source impedances or low bandwidth, in Figure 38, CH2 is driven by the LT1494. The LT1494 micropower signal conditioning circuits. The LTC2493 has excellent DC specs for an amplifier with 1.5µA supply solves this problem by balancing the input currents, thus current (the maximum offset voltage is 150µV and the simplifying or eliminating the need for signal conditioning open-loop gain is 100,000). Its 2kHz bandwidth makes circuits. it unsuitable for driving conventional delta-sigma ADCs. Adding a 1k, 0.1µF filter solves this problem by providing a A common application for a delta-sigma ADC is thermistor charge reservoir that supplies the LTC2493 instantaneous measurement. Figure 38 shows two examples of thermis- current, while the 1k resistor isolates the capacitive load tor digitization benefiting from the Easy Drive technology. from the LT1494. The first circuit (applied to input channels CH0 and CH1) Conventional delta-sigma ADCs input sampling current uses balanced reference resistors in order to balance the lead to DC errors as a result of incomplete settling in the common mode input/reference voltage and balance the external RC network. differential input source resistance. If reference resistors R1 and R4 are exactly equal, the input current is zero and The Easy Drive technology cancels the differential input no errors result. If these resistors have a 1% tolerance, current. By balancing the negative input (CH3) with a 1k, the maximum error in measured resistance is 1.6Ω due 0.1µF network errors due to the common mode input to a shift in common mode voltage; far less than the 1% current are cancelled. 2493fe 29 For more information www.linear.com/LTC2493

LTC2493 package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DE Package 14-Lead PlaDsEti Pc aDcFkNa g(4emm × 3mm) 1(R4e-Lfeereandc eP LlTaCs tDicW DGF #N 0 5(4-0m8-m17 ×08 3 Rmevm B)) (Reference LTC DWG # 05-08-1708 Rev B) 0.70 ±0.05 3.60 ±0.05 3.30 ±0.05 2.20 ±0.05 1.70 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 3.00 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ±0.10 R = 0.115 0.40 ±0.10 TYP (2 SIDES) 8 14 R = 0.05 TYP 3.30 ±0.10 3.00 ±0.10 (2 SIDES) 1.70 ±0.10 PIN 1 NOTCH PIN 1 R = 0.20 OR TOP MARK 0.35 × 45° (SEE NOTE 6) CHAMFER (DE14) DFN 0806 REV B 7 1 0.200 REF 0.75 ±0.05 0.25 ±0.05 0.50 BSC 3.00 REF 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2493fe 30 For more information www.linear.com/LTC2493

LTC2493 revision hisTory (Revision history begins at Rev C) REV DATE DESCRIPTION PAGE NUMBER C 11/09 Update Tables 1 and 2 16 D 07/10 Revised Typical Application drawing 1 Added f pin to parameters of V in I2C Inputs and Digital Outputs section 4 O IHA Added information to I2C Interface section 14 E 11/14 Clarified performance vs f frequency, reduced external oscillator maximum frequency to 1MHz. 5, 8, 28 O Clarified Input Voltage Range. 4, 13, 29 Added underrange note to Table 1. 15 2493fe Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 31 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconneFcotior nm oof irtse ciinrcfouirtms aast dioensc wribwedw h.leinreeina rw.cilol nmot/ LinTfCrin2g4e9 o3n existing patent rights.

LTC2493 Typical applicaTion 5V 5V R1 51.1k 12 VCC fO 1 == EINXTTEERRNNAALL OOSSCCIILLLLAATTOORR C0.41µF R3 IIN+ = 0 10µF LTC2493 10k TO 100k 13 REF+ 1.7k 5 0.1µF 14 REF– SDA 2-WIRE C3 R4 IIN– = 0 SCL 4 I2C INTERFACE 0.1µF 51.1k 8 CH0 5V 9 2 CH1 CA0 9-PIN SELECTABLE 102k 5V 10 CH2 CA1 3 ADDRESSES 11 + CH3 1k 7 6 0.1µF LT1494 COM GND 10k TO 100k 2493 F38 – 0.1µF 1k 0.1µF Figure 38. Easy Drive ADCs Simplify Measurement of High Impedance Sensors relaTeD parTs PART NUMBER DESCRIPTION COMMENTS LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max Initial Accuracy, 5ppm/°C Drift LT1460 Micropower Series Reference 0.075% Max Initial Accuracy, 10ppm/°C Max Drift LT1790 Micropower SOT-23 Low Dropout Reference Family 0.05% Max Initial Accuracy, 10ppm/°C Max Drift LTC2400 24-Bit, No Latency ∆∑ ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2410 24-Bit, No Latency ∆∑ ADC with Differential Inputs 0.8µV Noise, 2ppm INL RMS LTC2440 24-Bit, High Speed, Low Noise ∆∑ ADC 3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs RMS LTC2442 24-Bit, High Speed, 2-/4-Channel ∆∑ ADC with Integrated 8kHz Output Rate, 200nV Noise, Simultaneous 50Hz/60Hz RMS Amplifier Rejection LTC2449 24-Bit, High Speed, 8-/16-Channel ∆∑ ADC 8kHz Output Rate, 200nV Noise, Simultaneous 50Hz/60Hz RMS Rejection LTC2480/LTC2482/ 16-Bit/24-Bit ∆∑ ADCs with Easy Drive Inputs, 600nV Noise, Pin Compatible 16-Bit and 24-Bit Versions RMS LTC2484 Programmable Gain, and Temperature Sensor LTC2481/LTC2483/ 16-Bit/24-Bit ∆∑ ADCs with Easy Drive Inputs, 600nV Noise, Pin Compatible 16-Bit and 24-Bit Versions RMS LTC2485 I2C Interface, Programmable Gain, and Temperature Sensor LTC2486/LTC2488/ 16-Bit/24-Bit 2-/4-Channel ∆∑ ADC with Easy Drive Inputs, SPI Pin-Compatible 16-Bit and 24-Bit Versions LTC2492 Interface, Programmable Gain, and Temperature Sensor LTC2487 16-Bit 2-/4-Channel ∆∑ ADC with Easy Drive Inputs and Pin-Compatible with LTC2493/LTC2489 I2C Interface, Temperature Sensor LTC2489 16-Bit 2-/4-Channel ∆∑ ADC with Easy Drive Inputs Pin-Compatible with LTC2487/LTC2493 LTC2495/LTC2497/ 16-Bit/24-Bit 8-/16-Channel ∆∑ ADC with Easy Drive Inputs and Pin-Compatible 16-Bit and 24-Bit Versions LTC2499 I2C Interface, Programmable Gain, and Temperature Sensor LTC2496/LTC2498 16-Bit/24-Bit 8-/16-Channel ∆∑ ADC with Easy Drive Inputs and Pin-Compatible with LTC2498/LTC2449 SPI Interface 2493fe 32 Linear Technology Corporation LT 1114 REV E • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2493 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2493  LINEAR TECHNOLOGY CORPORATION 2006

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: LTC2493IDE#PBF LTC2493CDE#PBF LTC2493IDE#TRPBF LTC2493CDE#TRPBF