LTC2440 24-Bit High Speed Differential ∆∑ ADC with Selectable Speed/Resolution FEATURES DESCRIPTION n Up to 3.5kHz Output Rate (External f ) The LTC®2440 is a high speed 24-bit No Latency ∆∑TM O n Selectable Speed/Resolution ADC with 5ppm INL and 5µV offset. It uses a proprietary n 2µV Noise at 880Hz Output Rate delta-sigma architecture enabling variable speed and reso- RMS n 200nV Noise at 6.9Hz Output Rate with lution with no latency. Ten speed/resolution combinations RMS Simultaneous 50/60Hz Rejection (6.9Hz/200nV to 3.5kHz/25µV ) are programmed RMS RMS n 0.0005% INL, No Missing Codes through a simple serial interface. Alternatively, by tying a n Autosleep Enables 20µA Operation at 6.9Hz single pin HIGH or LOW, a fast (880Hz/2µV ) or ultralow RMS n <5µV Offset (4.5V < V < 5.5V, –40°C to 85°C) noise (6.9Hz, 200nV , 50/60Hz rejection) speed/reso- CC RMS n Differential Input and Differential Reference with lution combination can be easily selected. The accuracy GND to V Common Mode Range (offset, full-scale, linearity, drift) and power dissipation CC n No Latency, Each Conversion is Accurate Even After are independent of the speed selected. Since there is no an Input Step latency, a speed/resolution change may be made between n Internal Oscillator—No External Components conversions with no degradation in performance. n Pin Compatible with the LTC2410 Following each conversion cycle, the LTC2440 automati- n 24-Bit ADC in Narrow 16-Lead SSOP Package cally enters a low power sleep state. Power dissipation may be reduced by increasing the duration of this sleep APPLICATIONS state. For example, running at the 3.5kHz conversion speed but reading data at a 100Hz rate draws 240µA average n High Speed Multiplexing current (1.1mW) while reading data at a 7Hz output rate n Weight Scales draws only 25µA (125µW).The LTC2440 communicates n Auto Ranging 6-Digit DVMs through a flexible 3-wire or 4-wire digital interface that is n Direct Temperature Measurement compatible with the LTC2410 and is available in a narrow n High Speed Data Acquisition 16-lead SSOP package. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and No Latency ∆∑ and SoftSpan are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION RMS Noise vs Speed Simple 24-Bit 2-Speed Acquisition System 100 VCC = 5V VREF = 5V 4.5V TO 5.5V VIN+ = VIN– = 0V VCC BUSY µV) 10 LTC2440 SE ( 2µV AT 880Hz REFERENCE VOLTAGE REF+ fO NOI 0.1V TO VCC 4 REF– SCK MS 200nV AT 6.9Hz ANALOG INPUT IN+ SDO 3S-PWI IINRTEERFACE VCC6.9Hz, 200nV NOISE, R 1 (50/60Hz REJECTION) –0.5VREF TO 0.5VREF IN– CS 50/60Hz REJECTION 10-SPEED SERIAL SDI PROGRAMMABLE 0.1 GND EXT 880Hz OUTPUT RATE, 1 10 100 1000 10000 2µV NOISE CONVERSION RATE (Hz) 2440 TA01 2440 TA01 2440 TA02 2440fe 1 For more information www.linear.com/LTC2440

LTC2440 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1,2) Supply Voltage (VCC) to GND .......................–0.3V to 6V TOP VIEW Analog Input Pins Voltage GND 1 16 GND to GND ......................................–0.3V to (V + 0.3V) CC VCC 2 15 BUSY Reference Input Pins Voltage REF+ 3 14 fO to GND ......................................–0.3V to (VCC + 0.3V) REF– 4 13 SCK Digital Input Voltage to GND .........–0.3V to (VCC + 0.3V) IN+ 5 12 SDO Digital Output Voltage to GND .......–0.3V to (V + 0.3V) IN– 6 11 CS CC Operating Temperature Range SDI 7 10 EXT LTC2440C ...............................................0°C to 70°C GND 8 9 GND LTC2440I ............................................–40°C to 85°C GN PACKAGE 16-LEAD PLASTIC SSOP Storage Temperature Range ..................–65°C to 150°C Lead Temperature (Soldering, 10 sec) ...................300°C TJMAX = 125°C, θJA = 110°C/W ORDER INFORMATION http://www.linear.com/product/LTC2440#orderinfo LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2440CGN#PBF LTC2440CGN#TRPBF 2440 Narrow 16-Lead SSOP 0°C to 70°C LTC2440IGN#PBF LTC2440IGN#TRPBF 2440I Narrow 16-Lead SSOP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Notes 3, 4) A PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) 0.1V ≤ V ≤ V , –0.5 • V ≤ V ≤ 0.5 • V , (Note 5) l 24 Bits REF CC REF IN REF Integral Nonlinearity V = 5V, REF+ = 5V, REF– = GND, V = 2.5V, (Note 6) l 5 15 ppm of V CC INCM REF REF+ = 2.5V, REF– = GND, V = 1.25V, (Note 6) 3 ppm of V INCM REF Offset Error 2.5V ≤ REF+ ≤ V , REF– = GND, GND ≤ IN+ = IN– ≤ V (Note 12) l 2.5 5 µV CC CC Offset Error Drift 2.5V ≤ REF+ ≤ V , REF– = GND, GND ≤ IN+ = IN– ≤ V 20 nV/°C CC CC Positive Full-Scale Error REF+ = 5V, REF– = GND, IN+ = 3.75V, IN– = 1.25V l 10 30 ppm of V REF REF+ = 2.5V, REF– = GND, IN+ = 1.875V, IN– = 0.625V l 10 50 ppm of V REF Positive Full-Scale Error Drift 2.5V ≤ REF+ ≤ V , REF– = GND, IN+ = 0.75REF+, IN– = 0.25 • REF+ 0.2 ppm of V /°C CC REF Negative Full-Scale Error REF+ = 5V, REF– = GND, IN+ = 1.25V, IN– = 3.75V l 10 30 ppm of V REF REF+ = 2.5V, REF– = GND, IN+ = 0.625V, IN– = 1.875V l 10 50 ppm of V REF Negative Full-Scale Error Drift 2.5V ≤ REF+ ≤ V , REF– = GND, IN+ = 0.25 • REF+, IN– = 0.75 • REF+ 0.2 ppm of V /°C CC REF Total Unadjusted Error 5V ≤ V ≤ 5.5V, REF+ = 2.5V, REF– = GND, V = 1.25V 15 ppm of V CC INCM REF 5V ≤ V ≤ 5.5V, REF+ = 5V, REF– = GND, V = 2.5V 15 ppm of V CC INCM REF REF+ = 2.5V, REF– = GND, V = 1.25V, (Note 6) 15 ppm of V INCM REF Input Common Mode Rejection DC 2.5V ≤ REF+ ≤ V , REF– = GND, GND ≤ IN– = IN+ ≤ V 120 dB CC CC 2440fe 2 For more information www.linear.com/LTC2440

LTC2440 ANALOG INPUT AND REFERENCE The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IN+ Absolute/Common Mode IN+ Voltage l GND – 0.3V V + 0.3V V CC IN– Absolute/Common Mode IN– Voltage l GND – 0.3V V + 0.3V V CC V Input Differential Voltage Range (IN+ – IN–) l –V /2 V /2 V IN REF REF REF+ Absolute/Common Mode REF+ Voltage l 0.1 V V CC REF– Absolute/Common Mode REF– Voltage l GND V – 0.1V V CC V Reference Differential Voltage Range (REF+ l 0.1 V V REF CC – REF–) CS(IN+) IN+ Sampling Capacitance 3.5 pF CS(IN–) IN– Sampling Capacitance 3.5 pF CS(REF+) REF+ Sampling Capacitance 3.5 pF CS(REF–) REF– Sampling Capacitance 3.5 pF IDC_LEAK(IN+, IN–, Leakage Current, Inputs and Reference CS = VCC, IN+ = GND, IN– = GND, l –100 10 100 nA REF+, REF–) REF+ = 5V, REF– = GND ISAMPLE(IN+, IN–, Average Input/Reference Current During Varies, See Applications Section REF+, REF–) Sampling DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V High Level Input Voltage 4.5V ≤ V ≤ 5.5V l 2.5 V IN CC CS, f , SDI O V Low Level Input Voltage 4.5V ≤ V ≤ 5.5V l 0.8 V IL CC CS, f , SDI O V High Level Input Voltage 4.5V ≤ V ≤ 5.5V (Note 8) l 2.5 V IN CC SCK V Low Level Input Voltage 4.5V ≤ V ≤ 5.5V (Note 8) l 0.8 V IL CC SCK I Digital Input Current 0V ≤ V ≤ V l –10 10 µA IN IN CC CS, f O I Digital Input Current 0V ≤ V ≤ V (Note 8) l –10 10 µA IN IN CC SCK C Digital Input Capacitance 10 pF IN CS, f O C Digital Input Capacitance (Note 8) 10 pF IN SCK V High Level Output Voltage I = –800µA l V – 0.5V V OH O CC SDO, BUSY V Low Level Output Voltage I = 1.6mA l 0.4 V OL O SDO, BUSY V High Level Output Voltage I = –800µA (Note 9) l V – 0.5V V OH O CC SCK V Low Level Output Voltage I = 1.6mA (Note 9) l 0.4 V OL O SCK I Hi-Z Output Leakage l –10 10 µA OZ SDO 2440fe 3 For more information www.linear.com/LTC2440

LTC2440 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Supply Voltage l 4.5 5.5 V CC ICC Supply Current Conversion Mode CS = 0V (Note 7) l 8 11 mA Sleep Mode CS = V (Note 7) l 8 30 µA CC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f External Oscillator Frequency Range l 0.1 12 MHz EOSC t External Oscillator High Period l 25 10000 ns HEO t External Oscillator Low Period l 25 10000 ns LEO t Conversion Time OSR = 256 (SDI = 0) l 0.99 1.13 1.33 ms CONV OSR = 32768 (SDI = 1) l 126 145 170 ms l 40 • OSR + 178 External Oscillator (Note 10, 13) ms f (kHz) EOSC f Internal SCK Frequency Internal Oscillator (Note 9) l 0.8 0.9 1 MHz ISCK External Oscillator (Notes 9, 10) fEOSC/10 Hz D Internal SCK Duty Cycle (Note 9) l 45 55 % ISCK f External SCK Frequency Range (Note 8) l 20 MHz ESCK t External SCK Low Period (Note 8) l 25 ns LESCK t External SCK High Period (Note 8) l 25 ns HESCK t Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 9, 11) l 30.9 35.3 41.6 µs DOUT_ISCK External Oscillator (Notes 9, 10) 320/fEOSC s t External SCK 32-Bit Data Output Time (Note 8) l 32/f s DOUT_ESCK ESCK t CS ↑ to SDO Low Z (Note 12) l 0 25 ns 1 t2 CS ↑ to SDO High Z (Note 12) l 0 25 ns t CS ↑ to SCK↑ (Note 9) l 5 µs 3 t4 CS ↑ to SCK ↑ (Notes 8, 12) l 25 ns t SCK ↑ to SDO Valid l 25 ns KQMAX t SDO Hold After SCK ↑ (Note 5) l 15 ns KQMIN t SCK Set-Up Before CS ↑ l 50 ns 5 t7 SDI Setup Before SCK ↑ (Note 5) l 10 ns t8 SDI Hold After SCK ↑ (Note 5) l 10 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings may Note 7: The converter uses the internal oscillator. cause permanent damage to the device. Exposure to any Absolute Maximum Note 8: The converter is in external SCK mode of operation such that the Rating condition for extended periods may affect device reliability and lifetime. SCK pin is used as a digital input. The frequency of the clock signal driving Note 2: All voltage values are with respect to GND. SCK during the data output is f and is expressed in Hz. ESCK Note 3: V = 4.5 to 5.5V unless otherwise specified. Note 9: The converter is in internal SCK mode of operation such that the CC V = REF+ – REF–, V = (REF+ + REF–)/2; SCK pin is used as a digital output. In this mode of operation, the SCK pin REF REFCM VIN = IN+ – IN–, VINCM = (IN+ + IN–)/2. has a total equivalent load capacitance of CLOAD = 20pF. Note 4: fO pin tied to GND or to external conversion clock source with Note 10: The external oscillator is connected to the fO pin. The external fEOSC = 10MHz unless otherwise specified. oscillator frequency, fEOSC, is expressed in kHz. Note 5: Guaranteed by design, not subject to test. Note 11: The converter uses the internal oscillator. fO = 0V. Note 6: Integral nonlinearity is defined as the deviation of a code from a Note 12: Guaranteed by design and test correlation. straight line passing through the actual endpoints of the transfer curve. Note 13: There is an internal reset that adds an additional 5 to 15 fO cycles The deviation is measured from the center of the quantization band. to the conversion time. 2440fe 4 For more information www.linear.com/LTC2440

LTC2440 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity Integral Nonlinearity f = 3.5kHz f = 1.76kHz Integral Nonlinearity f = 880Hz OUT OUT OUT 10 10 10 VCC = 5V VINCM = 2.5V VCC = 5V VINCM = 2.5V VCC = 5V VINCM = 2.5V OF V)REF 5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC OF V)REF 5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC OF V)REF 5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC m m m R (pp 0 R (pp 0 R (pp 0 O O O R R R R R R NL E –5 NL E –5 NL E –5 I I I –10 –10 –10 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 VIN (V) VIN (V) VIN (V) 2440 G01 2440 G02 2440 G03 Integral Nonlinearity f = 440Hz Integral Nonlinearity f = 220Hz Integral Nonlinearity f = 110Hz OUT OUT OUT 10 10 10 VCC = 5V VINCM = 2.5V VCC = 5V VINCM = 2.5V VCC = 5V VINCM = 2.5V OF V)REF 5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC OF V)REF 5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC OF V)REF 5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC m m m R (pp 0 R (pp 0 R (pp 0 O O O R R R R R R NL E –5 NL E –5 NL E –5 I I I –10 –10 –10 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 VIN (V) VIN (V) VIN (V) 2440 G04 2440 G05 2440 G06 Integral Nonlinearity Integral Nonlinearity f = 55Hz Integral Nonlinearity f = 27.5Hz f = 13.75Hz OUT OUT OUT 10 10 10 VCC = 5V VINCM = 2.5V VCC = 5V VINCM = 2.5V VCC = 5V VINCM = 2.5V m OF V)REF 5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC m OF V)REF 5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC m OF V)REF 5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC INL ERROR (pp –50 INL ERROR (pp –50 INL ERROR (pp –50 –10 –10 –10 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 VIN (V) VIN (V) VIN (V) 2440 G07 2440 G08 2440 G09 2440fe 5 For more information www.linear.com/LTC2440

LTC2440 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity Integral Nonlinearity f = 6.875Hz vs Conversion Rate Integral Nonlinearity vs V OUT INCM 10 10.0 10 VCC = 5V VINCM = 2.5V VCC = 5V –2.5V ≤ VIN ≤ 2.5V VREF = 5V fO = GND VREF = 5V VINCM = 2.5V VREF+ = 5V TA = 25°C VREF+ = 5V fO = GND VINCM = 3.75V OF V)REF 5 VREF– = GND OF V)REF7.5 VREF– = GND TA = 25°C OF V)REF 5 VINCM = 2.5V m m m pp 0 pp 5.0 pp 0 R ( R ( R ( O O O R R R VINCM = 1.25V R R R E E E INL –5 INL 2.5 INL –5 VCC = 5V OSR = 32768 VREF = 2.5V fO = GND VREF+ = 2.5V TA = 25°C VREF– = GND –10 0 –10 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 0 500 1000 1500 2000 2500 3000 3500 –1.25 –0.75 –0.25 0.25 0.75 1.25 VIN (V) CONVERSION RATE (Hz) VIN (V) 2440 G10 2440 G11 2440 G12 Integral Nonlinearity Integral Nonlinearity vs Temperature vs Temperature –Full-Scale Error vs V REF 10 10 20 VCC = 5V VINCM = 1.25V VCC = 5V VINCM = 2.5V INL ERROR (ppm OF V)REF –505 VVVRRREEEFFF +–T= ==A T2 A2G=.5 . N=5–V DV5255°°CCOfOS =R GT=NA 3 D=2 716285°C INL ERROR (ppm OF V)REF –505 VVVRRREEEFFF +–T= A== 5 T=5GVA VN– =2D 51°2COf5O°S C=R G=N 3D2T7A6 8= 25°C LL-SCALE ERROR (ppm OF V)REF–11000 U F – –10 –10 –20 –1.25 –0.75 –0.25 0.25 0.75 1.25 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 0 1 2 3 4 5 VIN (V) VIN (V) VREF (V) 2440 G13 2440 G14 2440 G15 +Full-Scale Error vs V –Full-Scale Error vs V +Full-Scale Error vs V REF CC CC 20 10 0 VREF = 2.5V OSR = 32768 m OF V)REF 10 m OF V)REF 879 m OF V)REF –––231 VVVRRINEECFFM+– === 2G1.N.52DV5V TfOA == G2N5°DC R (pp R (pp 6 R (pp –4 RO 0 RO 5 RO –5 R R R +FULL-SCALE E –10 FULL-SCALE E 4231 VVVRRREEEFFF +–= == 2 2G.5.N5VDV TOfOAS =R= G2=N5 3°D2C768 FULL-SCALE E ––––6879 VINCM = 1.25V –20 0 –10 0 1 2 3 4 5 4.5 4.7 4.9 5.1 5.3 5.5 4.5 4.7 4.9 5.1 5.3 5.5 VREF (V) VCC (V) VCC (V) 2440 G16 2440 G17 2440 G18 2440fe 6 For more information www.linear.com/LTC2440

LTC2440 TYPICAL PERFORMANCE CHARACTERISTICS Negative Full-Scale Error Positive Full-Scale Error vs Temperature vs Temperature Offset Error vs V CC 20 20 5.0 VCC = 4.5V VCC = 5.5V, 5V VREF = 2.5V OSR = 32768 R (ppm OF V)REF 11505 4.5V VVVVOfORRRISN =EEERCFFF MG +–== N == =34D 24G.257.N.5V26DV58V VVVVOfORRRISN =EEERCFFF MG +–== N == =35D 25GV27VN.56DV8 R (ppm OF V)REF 11505 5.5V ppm OF V)REF 2.5 VVVRRINEE+FF +–= ==V I2GN.N–5 DV= GND TfOA == G2N5°DC RO 0 RO 0 R ( 0 LE ER –5 5.5V LE ER –5 5V VVCRCEF = = 4 4.5.5VV VVCRCEF = = 5 5.5VV, 5V ERRO ULL-SCA –10 5V ULL-SCA –10 4.5V VVVRRINEECFFM+– === 4G2.N.52DV5V VVVRRINEECFFM+– === 5G2VN.5DV OFFSET –2.5 F –15 F –15 OSR = 32768 OSR = 32768 fO = GND fO = GND –20 –20 –5.0 –55 –25 5 35 65 95 125 –55 –25 5 35 65 95 125 4.5 4.7 4.9 5.1 5.3 5.5 TEMPERATURE (°C) TEMPERATURE (°C) VCC (V) 2440 G19 2440 G20 2440 G21 Offset Error vs Conversion Rate Offset Error vs V INCM 5.0 VCC = 5V VIN+ = VIN– = GND 5.0 VCC = 5V VIN+ = VIN– = VINCM V)REF2.5 VVVRRREEEFFF +–= == 5 5GVVND TfOA == G2N5°DC V)REF 2.5 VVVRRREEEFFF +–= == 5 5GVVND TOfOAS =R= G2=N5 3°D2C768 OF OF m m R (pp 0 R (pp 0 O O R R R R OFFSET E–2.5 OFFSET E–2.5 –5.0 –5.0 0 500 1000 1500 2000 2500 3000 3500 0 1 2 3 4 5 CONVERSION RATE (Hz) VINCM (V) 2440 G22 2440 G23 RMS Noise vs Temperature Offset Error vs Temperature 3.5 5.0 3.0 E (µV) 2.5 VVVCCCCCC === 545..V55VV OR (µV) 2.5 VCC = 5V VCC = 5.5V VCC = 4.5V S R MS NOI 2.0 VCC = 4.5V VCC = 5.5V, 5V SET ER 0 VCC = 4.5V VCC = 5.5V, 5V R 1.5 VVVRRREEEFFF +–= == 2 2G.5.N5VDV VVVRRREEEFFF +–= == 5 5GVVND OFF–2.5 VVVRRREEEFFF +–= == 2 2G.5.N5VDV VVVRRREEEFFF +–= == 5 5GVVND 1.0 VIN+ = VIN– = GND VIN+ = VIN– = GND VIN+ = VIN– = GND VIN+ = VIN– = GND OSR = 256 OSR = 256 OSR = 256 OSR = 256 fO = GND fO = GND fO = GND fO = GND 0.5 –5.0 –55 –25 5 35 65 95 125 –55 –25 5 35 65 95 125 TEMPERATURE (°C) TEMPERATURE (°C) 2440 G24 2440 G25 2440fe 7 For more information www.linear.com/LTC2440

LTC2440 PIN FUNCTIONS GND (Pins 1, 8, 9, 16): Ground. Multiple ground pins data. If EXT is tied low (pin compatible with the LTC2410), internally connected for optimum ground current flow the device is in the external SCK mode and data is shifted and V decoupling. Connect each one of these pins to a out the device under the control of a user applied serial CC ground plane through a low impedance connection. All four clock. If EXT is tied high, the internal serial clock mode pins must be connected to ground for proper operation. is selected. The device generates its own SCK signal and outputs this on the SCK pin. A framing signal BUSY (Pin 15) V (Pin 2): Positive Supply Voltage. Bypass to GND CC goes low indicating data is being output. (Pin 1) with a 10µF tantalum capacitor in parallel with 0.1µF ceramic capacitor as close to the part as possible. CS (Pin 11): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. REF+ (Pin 3), REF– (Pin 4): Differential Reference Input. Following each conversion the ADC automatically enters The voltage on these pins can have any value between the Sleep mode and remains in this low power state as GND and V as long as the reference positive input, REF+, CC long as CS is HIGH. A LOW-to-HIGH transition on CS is maintained more positive than the reference negative during the Data Output transfer aborts the data transfer input, REF–, by at least 0.1V. and starts a new conversion. IN+ (Pin 5), IN– (Pin 6): Differential Analog Input. The SDO (Pin 12): Three-State Digital Output. During the Data voltage on these pins can have any value between GND Output period, this pin is used as serial data output. When – 0.3V and V + 0.3V. Within these limits the converter CC the chip select CS is HIGH (CS = V ) the SDO pin is in a bipolar input range (V = IN+ – IN–) extends from –0.5 • CC IN high impedance state. During the Conversion and Sleep (V ) to 0.5 • (V ). Outside this input range the converter REF REF periods, this pin is used as the conversion status output. produces unique overrange and underrange output codes. The conversion status can be observed by pulling CS LOW. SDI (Pin 7): Serial Data Input. This pin is used to select SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal the speed/resolution of the converter. If SDI is grounded Serial Clock Operation mode, SCK is used as digital output (pin compatible with LTC2410) the device outputs data at for the internal serial interface clock during the Data Output 880Hz with 21 bits effective resolution. By tying SDI HIGH, period. In External Serial Clock Operation mode, SCK is the converter enters the ultralow noise mode (200nV ) RMS used as digital input for the external serial interface clock with simultaneous 50/60Hz rejection at 6.9Hz output rate. during the Data Output period. The Serial Clock Operation SDI may be driven logic HIGH or LOW anytime during the mode is determined by the logic level applied to the EXT pin. conversion or sleep state in order to change the speed/ resolution. The conversion immediately following the data f (Pin 14): Frequency Control Pin. Digital input that con- O output cycle will be valid and performed at the newly se- trols the internal conversion clock. When f is connected O lected output rate/resolution. SDI may also be programmed to V or GND, the converter uses its internal oscillator. CC by a serial input data stream under control of SCK during BUSY (Pin 15): Conversion in Progress Indicator. For the data output cycle. One of ten speed/resolution ranges compatibility with the LTC2410, this pin should not be (from 6.9Hz/200nV to 3.5kHz/21µV ) may be se- RMS RMS tied to ground. This pin is HIGH while the conversion lected. The first conversion following a new selection is is in progress and goes LOW indicating the conversion valid and performed at the newly selected speed/resolution. is complete and data is ready. It remains low during the EXT (Pin 10): Internal/External SCK Selection Pin. This pin sleep and data output states. At the conclusion of the data is used to select internal or external SCK for outputting output state, it goes HIGH indicating a new conversion has begun. 2440fe 8 For more information www.linear.com/LTC2440

LTC2440 FUNCTIONAL BLOCK DIAGRAM INTERNAL VCC OSCILLATOR GND AUTOCALIBRATION AND CONTROL fO (INT/EXT) IN+ + IN– – SDO ADC SCK SERIAL CS DECIMATING FIR INTERFACE SDI BUSY DAC 2440 F01 EXT + – REF+ REF– Figure 1. Functional Block Diagram TEST CIRCUITS VCC 1.69k SDO SDO 1.69k CLOAD = 20pF CLOAD = 20pF Hi-Z TO VOH VVOOLH TTOO VHOi-HZ 2440 TA03 HVOi-HZ TTOO VVOOLL VOL TO Hi-Z 2440 TA04 APPLICATIONS INFORMATION CONVERTER OPERATION CONVERT Converter Operation Cycle The LTC2440 is a high speed, delta-sigma analog-to-digital SLEEP converter with an easy to use 4-wire serial interface (see Figure 1). Its operation is made up of three states. The converter operating cycle begins with the conversion, FALSE CS = LOW followed by the low power sleep state and ends with the AND SCK data output (see Figure 2). The 4-wire interface consists of serial data input (SDI), serial data output (SDO), serial TRUE clock (SCK) and chip select (CS). The interface, timing, DATA OUTPUT operation cycle and data out format is compatible with 2440 F02 the LTC2410. Figure 2. LTC2440 State Transition Diagram 2440fe 9 For more information www.linear.com/LTC2440

LTC2440 APPLICATIONS INFORMATION Initially, the LTC2440 performs a conversion. Once the Power-Up Sequence conversion is complete, the device enters the sleep state. The LTC2440 automatically enters an internal reset state While in this sleep state, power consumption is reduced when the power supply voltage V drops below approxi- CC below 10µA. The part remains in the sleep state as long as mately 2.2V. This feature guarantees the integrity of the CS is HIGH. The conversion result is held indefinitely in a conversion result and of the serial interface mode selection. static shift register while the converter is in the sleep state. When the V voltage rises above this critical threshold, the CC Once CS is pulled LOW, the device begins outputting the converter creates an internal power-on-reset (POR) signal conversion result. There is no latency in the conversion with a duration of approximately 0.5ms. The POR signal result. The data output corresponds to the conversion clears all internal registers. Following the POR signal, the just performed. This result is shifted out on the serial data LTC2440 starts a normal conversion cycle and follows the out pin (SDO) under the control of the serial clock (SCK). succession of states described above. The first conversion Data is updated on the falling edge of SCK allowing the result following POR is accurate within the specifications user to reliably latch data on the rising edge of SCK (see of the device if the power supply voltage is restored within Figure 3). The data output state is concluded once 32-bits the operating range (4.5V to 5.5V) before the end of the are read out of the ADC or when CS is brought HIGH. The POR time interval. device automatically initiates a new conversion and the cycle repeats. Reference Voltage Range Through timing control of the CS, SCK and EXT pins, This converter accepts a truly differential external reference the LTC2440 offers several flexible modes of operation voltage. The absolute/common mode voltage specification (internal or external SCK). These various modes do not for the REF+ and REF– pins covers the entire range from require programming configuration registers; moreover, GND to V . For correct converter operation, the REF+ pin CC they do not disturb the cyclic operation described above. must always be more positive than the REF– pin. These modes of operation are described in detail in the The LTC2440 can accept a differential reference voltage Serial Interface Timing Modes section. from 0.1V to V . The converter output noise is determined CC by the thermal noise of the front-end circuits, and as such, Ease of Use its value in microvolts is nearly constant with reference The LTC2440 data output has no latency, filter settling voltage. A decrease in reference voltage will not signifi- delay or redundant data associated with the conversion cantly improve the converter’s effective resolution. On the cycle. There is a one-to-one correspondence between the other hand, a reduced reference voltage will improve the conversion and the output data. Therefore, multiplexing converter’s overall INL performance. multiple analog voltages is easy. Speed/resolution adjust- ments may be made seamlessly between two conversions Input Voltage Range without settling errors. The analog input is truly differential with an absolute/com- The LTC2440 performs offset and full-scale calibrations mon mode range for the IN+ and IN– input pins extending every conversion cycle. This calibration is transparent to from GND – 0.3V to V + 0.3V. Outside these limits, the CC the user and has no effect on the cyclic operation described ESD protection devices begin to turn on and the errors above. The advantage of continuous calibration is extreme due to input leakage current increase rapidly. Within these stability of offset and full-scale readings with respect to limits, the LTC2440 converts the bipolar differential input time, supply voltage change and temperature drift. signal, V = IN+ – IN–, from –FS = –0.5 • V to +FS = IN REF 0.5 • V where V = REF+ – REF–. Outside this range, REF REF 2440fe 10 For more information www.linear.com/LTC2440

LTC2440 APPLICATIONS INFORMATION the converter indicates the overrange or the underrange Bit 28 (fourth output bit) is the most significant bit (MSB) of condition using distinct output codes. the result. This bit in conjunction with Bit 29 also provides the underrange or overrange indication. If both Bit 29 and Output Data Format Bit 28 are HIGH, the differential input voltage is above +FS. If both Bit 29 and Bit 28 are LOW, the differential input The LTC2440 serial output data stream is 32-bits long. voltage is below –FS. The first 3-bits represent status information indicating the sign and conversion state. The next 24-bits are the The function of these bits is summarized in Table 1. conversion result, MSB first. The remaining 5-bits are Table 1. LTC2440 Status Bits sub LSBs beyond the 24-bit level that may be included in Bit 31 Bit 30 Bit 29 Bit 28 averaging or discarded without loss of resolution. In the Input Range EOC DMY SIG MSB case of ultrahigh resolution modes, more than 24 effective V ≥ 0.5 • V 0 0 1 1 IN REF bits of performance are possible (see Table 3). Under these 0V ≤ V < 0.5 • V 0 0 1 0 IN REF conditions, sub LSBs are included in the conversion result –0.5 • V ≤ V < 0V 0 0 0 1 and represent useful information beyond the 24-bit level. REF IN V < –0.5 • V 0 0 0 0 The third and fourth bit together are also used to indicate IN REF an underrange condition (the differential input voltage is Bits ranging from 28 to 5 are the 24-bit conversion result below –FS) or an overrange condition (the differential input MSB first. voltage is above +FS). For input conditions in excess of twice full scale (|V | ≥ V ), the converter may indicate Bit 5 is the Least Significant Bit (LSB). IN REF either overrange or underrange. Once the input returns to Bits ranging from 4 to 0 are sub LSBs below the 24-bit the normal operating range, the conversion result is im- level. Bits 4 to bit 0 may be included in averaging or dis- mediately accurate within the specifications of the device. carded without loss of resolution. Bit 31 (first output bit) is the end of conversion (EOC) Data is shifted out of the SDO pin under control of the indicator. This bit is available at the SDO pin during the serial clock (SCK), see Figure 3. Whenever CS is HIGH, conversion and sleep states whenever the CS pin is LOW. SDO remains high impedance. This bit is HIGH during the conversion and goes LOW In order to shift the conversion result out of the device, when the conversion is complete. CS must first be driven LOW. EOC is seen at the SDO pin Bit 30 (second output bit) is a dummy bit (DMY) and is of the device once CS is pulled LOW. EOC changes real always LOW. time from HIGH to LOW at the completion of a conversion. This signal may be used as an interrupt for an external Bit 29 (third output bit) is the conversion result sign microcontroller. Bit 31 (EOC) can be captured on the first indicator (SIG). If V is >0, this bit is HIGH. If V is <0, IN IN rising edge of SCK. Bit 30 is shifted out of the device on this bit is LOW. the first falling edge of SCK. The final data bit (Bit 0) is CS BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 5 BIT 0 SDO EOC “0” SIG MSB LSB24 Hi-Z SCK 1 2 3 4 5 26 27 32 BUSY SLEEP DATA OUTPUT CONVERSION 2440 F03 Figure 3. Output Data Timing 2440fe 11 For more information www.linear.com/LTC2440

LTC2440 APPLICATIONS INFORMATION shifted out on the falling edge of the 31st SCK and may Serial Clock Input/Output (SCK) be latched on the rising edge of the 32nd SCK pulse. On The serial clock signal present on SCK (Pin 13) is used to the falling edge of the 32nd SCK pulse, SDO goes HIGH synchronize the data transfer. Each bit of data is shifted indicating the initiation of a new conversion cycle. This out the SDO pin on the falling edge of the serial clock. bit serves as EOC (Bit 31) for the next conversion cycle. Table 2 summarizes the output data format. In the Internal SCK mode of operation, the SCK pin is an output and the LTC2440 creates its own serial clock. In As long as the voltage on the IN+ and IN– pins is main- the External SCK mode of operation, the SCK pin is used tained within the –0.3V to (V + 0.3V) absolute maximum CC as input. The internal or external SCK mode is selected operating range, a conversion result is generated for any by tying EXT (Pin 10) LOW for external SCK and HIGH differential input voltage V from –FS = –0.5 • V to IN REF for internal SCK. +FS = 0.5 • V . For differential input voltages greater REF than +FS, the conversion result is clamped to the value Serial Data Output (SDO) corresponding to the +FS + 1LSB. For differential input The serial data output pin, SDO (Pin 12), provides the voltages below –FS, the conversion result is clamped to result of the last conversion as a serial bit stream (MSB the value corresponding to –FS – 1LSB. first) during the data output state. In addition, the SDO pin is used as an end of conversion indicator during the SERIAL INTERFACE PINS conversion and sleep states. The LTC2440 transmits the conversion results and receives When CS (Pin 11) is HIGH, the SDO driver is switched the start of conversion command through a synchronous to a high impedance state. This allows sharing the serial 2-wire, 3-wire or 4-wire interface. During the conversion interface with other devices. If CS is LOW during the and sleep states, this interface can be used to assess convert or sleep state, SDO will output EOC. If CS is LOW the converter status and during the data output state it during the conversion phase, the EOC bit appears HIGH is used to read the conversion result and program the on the SDO pin. Once the conversion is complete, EOC speed/resolution. goes LOW. The device remains in the sleep state until the first rising edge of SCK occurs while CS = LOW. Table 2. LTC2440 Output Data Format Differential Input Voltage Bit 31 Bit 30 Bit 29 Bit 28 V * EOC DMY SIG MSB Bit 27 Bit 26 Bit 25 … Bit 0 IN V * ≥ 0.5 • V ** 0 0 1 1 0 0 0 … 0 IN REF 0.5 • V ** – 1LSB 0 0 1 0 1 1 1 … 1 REF 0.25 • V ** 0 0 1 0 1 0 0 … 0 REF 0.25 • V ** – 1LSB 0 0 1 0 0 1 1 … 1 REF 0 0 0 1 0 0 0 0 … 0 –1LSB 0 0 0 1 1 1 1 … 1 –0.25 • V ** 0 0 0 1 1 0 0 … 0 REF –0.25 • V ** – 1LSB 0 0 0 1 0 1 1 … 1 REF –0.5 • V ** 0 0 0 1 0 0 0 … 0 REF V * < –0.5 • V ** 0 0 0 0 1 1 1 … 1 IN REF *The differential input voltage V = IN+ – IN–. **The differential reference voltage V = REF+ – REF–. IN REF 2440fe 12 For more information www.linear.com/LTC2440

LTC2440 APPLICATIONS INFORMATION Chip Select Input (CS) Serial Data Input (SDI)—Serial Input Speed Selection The active LOW chip select, CS (Pin 11), is used to test the SDI may also be programmed by a serial input data conversion status and to enable the data output transfer stream under control of SCK during the data output cycle, as described in the previous sections. see Figure 4. One of ten speed/resolution ranges (from 6.9Hz/200nV to 3.5kHz/21µV ) may be selected, In addition, the CS signal can be used to trigger a new RMS RMS see Table 3. The conversion following a new selection is conversion cycle before the entire serial data transfer has valid and performed at the newly selected speed/resolution. been completed. The LTC2440 will abort any serial data transfer in progress and start a new conversion cycle any- BUSY time a LOW-to-HIGH transition is detected at the CS pin after the converter has entered the data output state (i.e., The BUSY output (Pin 15) is used to monitor the state of after the fifth falling edge of SCK occurs with CS = LOW). conversion, data output and sleep cycle. While the part is converting, the BUSY pin is HIGH. Once the conversion is Serial Data Input (SDI)—Logic Level Speed Selection complete, BUSY goes LOW indicating the conversion is complete and data out is ready. The part now enters the The serial data input (SDI, Pin 7) is used to select the LOW power sleep state. BUSY remains LOW while data is speed/resolution of the LTC2440. A simple 2-speed control shifted out of the device. It goes HIGH at the conclusion is selectable by either driving SDI HIGH or LOW. If SDI of the data output cycle indicating a new conversion has is grounded (pin compatible with LTC2410) the device begun. This rising edge may be used to flag the comple- outputs data at 880Hz with 21 bits effective resolution. By tion of the data read cycle. tying SDI HIGH, the converter enters the ultralow noise mode (200nV ) with simultaneous 50/60Hz rejection at RMS 6.9Hz output rate. SDI may be driven logic HIGH or LOW SERIAL INTERFACE TIMING MODES anytime during the conversion or sleep state in order to The LTC2440’s 2-wire, 3-wire or 4-wire interface is SPI change the speed/resolution. The conversion immediately and MICROWIRE compatible. This interface offers several following the data output cycle will be valid and performed flexible modes of operation. These include internal/external at the newly selected output rate/resolution. serial clock, 2-wire or 3-wire I/O, single cycle conversion Changing SDI logic state during the data output cycle and autostart. The following sections describe each of should be avoided as speed resolution other than 6.9Hz these serial interface timing modes in detail. In all these or 880Hz may be selected. For example, if SDI is changed cases, the converter can use the internal oscillator (fO = from logic 0 to logic 1 after the second rising edge of SCK, LOW) or an external oscillator connected to the fO pin. the conversion rate will change from 880Hz to 55Hz (the See Table 4 for a summary. following values are listed in Table 3: OSR4 = 0, OSR3 = 0, External Serial Clock, Single Cycle Operation OSR2 = 1, OSR1 = 1 and OSR0 = 1). If SDI remains HIGH, (SPI/MICROWIRE Compatible) the conversion rate will switch to the desired 6.9Hz speed immediately following the conversion at 55Hz. The 55Hz This timing mode uses an external serial clock to shift rate conversion cycle will be a valid result as well as the out the conversion result and a CS signal to monitor and first 6.9Hz result. On the other hand, if SDI is changed to a control the state of the conversion cycle, see Figure 5. 1 anytime before the first rising edge of SCK, the following The serial clock mode is selected by the EXT pin. To select conversion rate will become 6.9Hz. If SDI is changed to the external serial clock mode, EXT must be tied low. a 1 after the 5th rising edge of SCK, the next conversion will remain 880Hz while all subsequent conversions will The serial data output pin (SDO) is Hi-Z as long as CS is be at 6.9Hz. HIGH. At any time during the conversion cycle, CS may be pulled LOW in order to monitor the state of the converter. While CS is pulled LOW, EOC is output to the SDO pin. 2440fe 13 For more information www.linear.com/LTC2440

LTC2440 APPLICATIONS INFORMATION CS SCK SDI OSR4* OSR3 OSR2 OSR1 OSR0 BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 1 BIT 0 Hi-Z Hi-Z SDO EOC “0” SIG MSB LSB BUSY 2440 F04 *OSR4 BIT MUST BE AT FIRST SCK RISING EDGE DURING SERIAL DATA OUT CYCLE Figure 4. SDI Speed/Resolution Programming Table 3. SDI Speed/Resolution Programming RMS OSR4 OSR3 OSR2 OSR1 OSR0 NOISE ENOB OSR X 0 0 0 1 23µV 17 64 X 0 0 1 0 3.5µV 20 128 0 0 0 0 0 2µV 21.3 256* X 0 0 1 1 2µV 21.3 256 X 0 1 0 0 1.4µV 21.8 512 X 0 1 0 1 1µV 22.4 1024 X 0 1 1 0 750nV 22.9 2048 X 0 1 1 1 510nV 23.4 4096 X 1 0 0 0 375nV 24 8192 X 1 0 0 1 250nV 24.4 16384 X 1 1 1 1 200nV 24.6 32768** **Address allows tying SDI HIGH *Additional address to allow tying SDI LOW Table 4. LTC2440 Interface Timing Modes Conversion Data Connection SCK Cycle Output and Configuration Source Control Control Waveforms External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 5, 6 External SCK, 2-Wire I/O External SCK SCK Figure 7 ↑ ↑ Internal SCK, Single Cycle Conversion Internal CS CS Figures 8, 9 Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 10 2440fe 14 For more information www.linear.com/LTC2440

LTC2440 APPLICATIONS INFORMATION 4.5V TO 5.5V 1µF 2 15 VCC BUSY LTC2440 REFERENCE VOLTAGE 3 REF+ fO 14 == EINXTTEERRNNAALL OOSSCCIILLLLAATTOORR 0.1V TO VCC 4 REF– SCK 13 ANALOG INPUT RANGE 5 IN+ SDO 12 3S-PWI IINRTEERFACE –0.5VREF TO 0.5VREF 6 IN– CS 11 VCC 7 200nV NOISE, 50/60Hz REJECTION SDI 10-SPEED/RESOLUTION PROGRAMMABLE 1, 8, 9, 16 10 2µV NOISE, 880Hz OUTPUT RATE GND EXT CS TEST EOC TEST EOC TEST EOC BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 5 BIT 0 SDO EOC SIG MSB LSB SUB LSB Hi-Z Hi-Z Hi-Z SCK (EXTERNAL) BUSY CONVERSION SLEEP DATA OUTPUT CONVERSION 2440 F05 Figure 5. External Serial Clock, Single Cycle Operation EOC = 1 (BUSY = 1) while a conversion is in progress Typically, CS remains LOW during the data output state. and EOC = 0 (BUSY = 0) if the device is in the sleep state. However, the data output state may be aborted by pulling Independent of CS, the device automatically enters the CS HIGH anytime between the fifth falling edge (SDI must low power sleep state once the conversion is complete. be properly loaded each cycle) and the 32nd falling edge of SCK, see Figure 6. On the rising edge of CS, the device When the device is in the sleep state (EOC = 0), its con- aborts the data output state and immediately initiates a version result is held in an internal static shift register. new conversion. This is useful for systems not requiring The device remains in the sleep state until the first rising all 32 bits of output data, aborting an invalid conversion edge of SCK is seen. Data is shifted out the SDO pin on cycle or synchronizing the start of a conversion. each falling edge of SCK. This enables external circuitry to latch the output on the rising edge of SCK. EOC can be External Serial Clock, 2-Wire I/O latched on the first rising edge of SCK and the last bit of the conversion result can be latched on the 32nd rising This timing mode utilizes a 2-wire serial I/O interface. edge of SCK. On the 32nd falling edge of SCK, the device The conversion result is shifted out of the device by an begins a new conversion. SDO goes HIGH (EOC = 1) and externally generated serial clock (SCK) signal, see Figure BUSY goes HIGH indicating a conversion is in progress. 7. CS may be permanently tied to ground, simplifying the user interface or isolation barrier. The external serial clock At the conclusion of the data cycle, CS may remain LOW mode is selected by tying EXT LOW. and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z Since CS is tied LOW, the end-of-conversion (EOC) can and BUSY monitored for the completion of a conversion. be continuously monitored at the SDO pin during the As described above, CS may be pulled LOW at any time convert and sleep states. Conversely, BUSY (Pin 15) may in order to monitor the conversion status on the SDO pin. be used to monitor the status of the conversion cycle. EOC or BUSY may be used as an interrupt to an external 2440fe 15 For more information www.linear.com/LTC2440

LTC2440 APPLICATIONS INFORMATION 4.5V TO 5.5V 1µF 2 15 VCC BUSY LTC2440 REFERENCE VOLTAGE 3 REF+ fO 14 == EINXTTEERRNNAALL OOSSCCIILLLLAATTOORR 0.1V TO VCC 4 REF– SCK 13 ANALOG INPUT RANGE 5 IN+ SDO 12 3S-PWI IINRTEERFACE –0.5VREF TO 0.5VREF 6 IN– CS 11 VCC 7 200nV NOISE, 50/60Hz REJECTION SDI 10-SPEED/RESOLUTION PROGRAMMABLE 1, 8, 9, 16 10 2µV NOISE, 880Hz OUTPUT RATE GND EXT CS TEST EOC TEST EOC TEST EOC BIT 0 BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 9 BIT 8 SDO EOC EOC SIG MSB Hi-Z Hi-Z Hi-Z Hi-Z 1 5 SCK (EXTERNAL) BUSY SLEEP CONVERSION SLEEP DATA OUTPUT CONVERSION DATA OUTPUT 2410 F06 Figure 6. External Serial Clock, Reduced Data Output Length 4.5V TO 5.5V 1µF 2 15 VCC BUSY LTC2440 REFERENCE VOLTAGE 3 REF+ fO 14 == EINXTTEERRNNAALL OOSSCCIILLLLAATTOORR 0.1V TO VCC 4 REF– SCK 13 ANALOG INPUT RANGE 5 IN+ SDO 12 3S-PWI IINRTEERFACE –0.5VREF TO 0.5VREF 6 IN– CS 11 VCC 7 200nV NOISE, 50/60Hz REJECTION SDI 10-SPEED/RESOLUTION PROGRAMMABLE 1, 8, 9, 16 10 2µV NOISE, 880Hz OUTPUT RATE GND EXT CS BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 5 BIT 0 SDO EOC SIG MSB LSB24 SCK (EXTERNAL) BUSY CONVERSION SLEEP DATA OUTPUT CONVERSION 2440 F07 Figure 7. External Serial Clock, CS = 0 Operation (2-Wire) 2440fe 16 For more information www.linear.com/LTC2440

LTC2440 APPLICATIONS INFORMATION controller indicating the conversion result is ready. EOC Once CS is pulled LOW, SCK goes LOW and EOC is output = 1 (BUSY = 1) while the conversion is in progress and to the SDO pin. EOC = 1 while a conversion is in progress EOC = 0 (BUSY = 0) once the conversion enters the low and EOC = 0 if the device is in the sleep state. Alterna- power sleep state. On the falling edge of EOC/BUSY, the tively, BUSY (Pin 15) may be used to monitor the status conversion result is loaded into an internal static shift of the conversion in progress. BUSY is HIGH during the register. The device remains in the sleep state until the conversion and goes LOW at the conclusion. It remains first rising edge of SCK. Data is shifted out the SDO pin LOW until the result is read from the device. on each falling edge of SCK enabling external circuitry to When testing EOC, if the conversion is complete (EOC = latch data on the rising edge of SCK. EOC can be latched 0), the device will exit the sleep state and enter the data on the first rising edge of SCK. On the 32nd falling edge output state if CS remains LOW. In order to prevent the of SCK, SDO and BUSY go HIGH (EOC = 1) indicating a device from exiting the low power sleep state, CS must new conversion has begun. be pulled HIGH before the first rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the device Internal Serial Clock, Single Cycle Operation begins outputting data at time t after the falling edge EOCtest This timing mode uses an internal serial clock to shift of CS (if EOC = 0) or t after EOC goes LOW (if CS is EOCtest out the conversion result and a CS signal to monitor and LOW during the falling edge of EOC). The value of t EOCtest control the state of the conversion cycle, see Figure 8. is 500ns. If CS is pulled HIGH before time tE , the OCtest In order to select the internal serial clock timing mode, device remains in the sleep state. The conversion result the EXT pin must be tied HIGH. is held in the internal static shift register. The serial data output pin (SDO) is Hi-Z as long as CS is If CS remains LOW longer than t , the first rising EOCtest HIGH. At any time during the conversion cycle, CS may be edge of SCK will occur and the conversion result is serially pulled LOW in order to monitor the state of the converter. shifted out of the SDO pin. The data output cycle begins 4.5V TO 5.5V 1µF 2 15 VCC BUSY LTC2440 REFERENCE VOLTAGE 3 REF+ fO 14 == EINXTTEERRNNAALL OOSSCCIILLLLAATTOORR 0.1V TO VCC 4 REF– SCK 13 ANALOG INPUT RANGE 5 IN+ SDO 12 3S-PWI IINRTEERFACE –0.5VREF TO 0.5VREF 6 IN– CS 11 VCC 7 200nV NOISE, 50/60Hz REJECTION SDI 10-SPEED/RESOLUTION PROGRAMMABLE 1, 8, 9, 16 10 2µV NOISE, 880Hz OUTPUT RATE GND EXT VCC <tEOCtest CS TEST EOC TEST EOC BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 5 BIT 0 SDO EOC SIG MSB LSB24 Hi-Z Hi-Z Hi-Z Hi-Z SCK (INTERNAL) BUSY CONVERSION SLEEP DATA OUTPUT CONVERSION 2440 F08 Figure 8. Internal Serial Clock, Single Cycle Operation 2440fe 17 For more information www.linear.com/LTC2440

LTC2440 APPLICATIONS INFORMATION on this first rising edge of SCK and concludes after the new conversion. This is useful for systems not requiring 32nd rising edge. Data is shifted out the SDO pin on each all 32-bits of output data, aborting an invalid conversion falling edge of SCK. The internally generated serial clock cycle, or synchronizing the start of a conversion. is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be Internal Serial Clock, 2-Wire I/O, latched on the first rising edge of SCK and the last bit of Continuous Conversion the conversion result on the 32nd rising edge of SCK. This timing mode uses a 2-wire, all output (SCK and SDO) After the 32nd rising edge, SDO goes HIGH (EOC = 1), interface. The conversion result is shifted out of the device SCK stays HIGH and a new conversion starts. by an internally generated serial clock (SCK) signal, see Figure 10. CS may be permanently tied to ground, sim- Typically, CS remains LOW during the data output state. plifying the user interface or isolation barrier. The internal However, the data output state may be aborted by pull- serial clock mode is selected by tying EXT HIGH. ing CS HIGH anytime between the first and 32nd rising edge of SCK, see Figure 9. In order to properly select the During the conversion, the SCK and the serial data output OSR for the conversion following a data abort, five SCK pin (SDO) are HIGH (EOC = 1) and BUSY = 1. Once the rising edges must be seen prior to performing a data out conversion is complete, SCK, BUSY and SDO go LOW (EOC abort (pulling CS HIGH). If CS is pulled high prior to the = 0) indicating the conversion has finished and the device fifth SCK falling edge, the OSR selected depends on the has entered the low power sleep state. The part remains in number of SCK signals seen prior to data abort, where the sleep state a minimum amount of time (≈500ns) then subsequent nonaborted conversion cycles return to the immediately begins outputting data. The data output cycle programmed OSR. On the rising edge of CS, the device begins on the first rising edge of SCK and ends after the aborts the data output state and immediately initiates a 32nd rising edge. Data is shifted out the SDO pin on each 4.5V TO 5.5V 1µF 2 15 VCC BUSY LTC2440 REFERENCE VOLTAGE 3 REF+ fO 14 == EINXTTEERRNNAALL OOSSCCIILLLLAATTOORR 0.1V TO VCC 4 REF– SCK 13 ANALOG INPUT RANGE 5 IN+ SDO 12 3S-PWI IINRTEERFACE –0.5VREF TO 0.5VREF 6 IN– CS 11 VCC 7 200nV NOISE, 50/60Hz REJECTION SDI 10-SPEED/RESOLUTION PROGRAMMABLE 1, 8, 9, 16 10 2µV NOISE, 880Hz OUTPUT RATE GND EXT VCC >tEOCtest <tEOCtest CS TEST EOC TEST EOC TEST EOC BIT 0 BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 8 SDO EOC EOC SIG MSB Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 5 SCK (INTERNAL) BUSY SLEEP CONVERSION SLEEP DATA OUTPUT CONVERSION DATA OUTPUT 2440 F09 Figure 9. Internal Serial Clock, Reduced Data Output Length 2440fe 18 For more information www.linear.com/LTC2440

LTC2440 APPLICATIONS INFORMATION 4.5V TO 5.5V 1µF 2 15 VCC BUSY LTC2440 REFERENCE VOLTAGE 3 REF+ fO 14 == EINXTTEERRNNAALL OOSSCCIILLLLAATTOORR 0.1V TO VCC 4 REF– SCK 13 2-WIRE ANALOG INPUT RANGE 5 IN+ SDO 12 SPI INTERFACE –0.5VREF TO 0.5VREF 6 IN– CS 11 VCC 7 200nV NOISE, 50/60Hz REJECTION SDI 10-SPEED/RESOLUTION PROGRAMMABLE 1, 8, 9, 16 10 2µV NOISE, 880Hz OUTPUT RATE GND EXT VCC CS BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 5 BIT 0 SDO EOC SIG MSB LSB24 SCK (INTERNAL) BUSY CONVERSION DATA OUTPUT CONVERSION SLEEP 2410 F10 Figure 10. Internal Serial Clock, Continuous Operation falling edge of SCK. The internally generated serial clock f = f /OSR, see Figure 11 and Table 5. The rejection at N S is output to the SCK pin. This signal may be used to shift the frequency f ±14% is better than 80dB, see Figure 12. N the conversion result into external circuitry. EOC can be If f is grounded, f is set by the on-chip oscillator at O S latched on the first rising edge of SCK and the last bit of 1.8MHz (over supply and temperature variations). At an the conversion result can be latched on the 32nd rising OSR of 32,768, the first NULL is at f = 55Hz and the no N edge of SCK. After the 32nd rising edge, SDO goes HIGH latency output rate is f /8 = 6.9Hz. At the maximum OSR, N (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion. 0 Normal Mode Rejection and Antialiasing –20 B) One of the advantages delta-sigma ADCs offer over d conventional ADCs is on-chip digital filtering. Combined TION ( –40 C with a large oversampling ratio, the LTC2440 significantly JE –60 E R simplifies antialiasing filter requirements. E OD –80 M The LTC2440’s speed/resolution is determined by the MAL –100 over sample ratio (OSR) of the on-chip digital filter. The OR N–120 OSR ranges from 64 for 3.5kHz output rate to 32,768 for 6.9Hz output rate. The value of OSR and the sample rate f –140 S 0 60 120 180 240 determine the filter characteristics of the device. The first DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) NULL of the digital filter is at fN and multiples of fN where 2440 F11 Figure 11. LTC2440 Normal Mode Rejection (Internal Oscillator) 2440fe 19 For more information www.linear.com/LTC2440

LTC2440 APPLICATIONS INFORMATION the noise performance of the device is 200nV with Table 5. OSR vs Notch Frequency (fN) with Internal Oscillator RMS better than 80dB rejection of 50Hz ±2% and 60Hz ±2%. OSR NOTCH (f ) N Since the OSR is large (32,768) the wide band rejection 64 28.16kHz is extremely large and the antialiasing requirements are 128 14.08kHz simple. The first multiple of f occurs at 55Hz • 32,768 = 256 7.04kHz S 1.8MHz, see Figure 13. 512 3.52kHz 1024 1.76kHz The first NULL becomes f = 7.04kHz with an OSR of 256 N 2048 880Hz (an output rate of 880Hz) and fO grounded. While the NULL 4096 440Hz has shifted, the sample rate remains constant. As a result 8192 220Hz of constant modulator sampling rate, the linearity, offset 16384 110Hz and full-scale performance remains unchanged as does the first multiple of f . 32768* 55Hz S *Simultaneous 50/60 rejection –80 0 –20 B) –90 B) d d ON ( ON ( –40 TI–100 TI C C E E J J –60 E E E R–110 E R 1.8MHz OD OD –80 M M L –120 L MA MA–100 OR OR REJECTION > 120dB N–130 N–120 –140 –140 47 49 51 53 55 57 59 61 63 0 1000000 2000000 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2440 F12 1440 F13 Figure 12. LTC2440 Normal Mode Rejection (Internal Oscillator) Figure 13. LTC2440 Normal Mode Rejection (Internal Oscillator) 2440fe 20 For more information www.linear.com/LTC2440

LTC2440 APPLICATIONS INFORMATION The sample rate f and NULL f , my also be adjusted by Reduced Power Operation S N driving the f pin with an external oscillator. The sample O In addition to adjusting the speed/resolution of the rate is f = f /5, where f is the frequency of the S EOSC EOSC LTC2440, the speed/resolution/power dissipation may clock applied to f . Combining a large OSR with a reduced O also be adjusted using the automatic sleep mode. During sample rate leads to notch frequencies f near DC while N the conversion cycle, the LTC2440 draws 8mA supply maintaining simple antialiasing requirements. A 100kHz current independent of the programmed speed. Once the clock applied to f results in a NULL at 0.6Hz plus all O conversion cycle is completed, the device automatically harmonics up to 20kHz, see Figure 14. This is useful in enters a low power sleep state drawing 8µA. The device applications requiring digitalization of the DC component remains in this state as long as CS is HIGH and data is not of a noisy input signal and eliminates the need of placing shifted out. By adjusting the duration of the sleep state a 0.6Hz filter in front of the ADC. (hold CS HIGH longer) and the duration of the conversion An external oscillator operating from 100kHz to 12MHz can cycle (programming OSR) the DC power dissipation can be implemented using the LTC1799 (resistor set SOT-23 be reduced, see Figure 16. oscillator), see Figure 22. By floating pin 4 (DIV) of the For example, if the OSR is programmed at the fastest rate LTC1799, the output oscillator frequency is: (OSR = 64, t = 0.285ms) and the sleep state is 10ms, CONV  10k  the effective output rate is approximately 100Hz while the fOSC =10MHz(cid:127)  average supply current is reduced to 240µA. By further 10(cid:127)RSET extending the sleep state to 100ms, the effective output The normal mode rejection characteristic shown in rate of 10Hz draws on average 30µA. Noise, power, and Figure 14 is achieved by applying the output of the LTC1799 speed can be optimized by adjusting the OSR (Noise/ (with RSET = 100k) to the fO pin on the LTC2440 with SDI Speed) and sleep mode duration (Power). tied HIGH (OSR = 32768). 0 B) –20 d ON ( –40 TI C E EJ –60 R E OD –80 M L MA–100 R O N–120 –140 0 2 4 6 8 10 DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2440 F14 Figure 14. LTC2440 Normal Mode Rejection (External Oscillator at 90kHz) 2440fe 21 For more information www.linear.com/LTC2440

LTC2440 APPLICATIONS INFORMATION CONVERTER SLEEP CONVERT SLEEP CONVERT SLEEP STATE DATA DATA OUT OUT CS SUPPLY 8µA 8mA 8µA 8µA 8mA CURRENT 2440 F15 Figure 15. Reduced Power Timing Mode LTC2440 Input Structure When using the internal oscillator, fSW is 1.8MHz and the equivalent resistance is approximately 110kΩ. Modern delta sigma converters have switched capacitor front ends that repeatedly sample the input voltage over Driving the Input and Reference some time period. The sampling process produces a small Because of the small current pulses, excessive lead length current pulse at the input and reference terminals as the at the analog or reference input may allow reflections or capacitors are charged. The LTC2440 switches the input ringing to occur, affecting the conversion accuracy. The and reference to a 5pF sample capacitor at a frequency key to preserving the accuracy of the LTC2440 is com- of 1.8MHz. A simplified equivalent circuit is shown in plete settling of these sampling glitches at both the input Figure 16. and reference terminals. There are several recommended The average input and reference currents can be expressed methods of doing this. in terms of the equivalent input resistance of the sample capacitor, where: Req = 1/(f • Ceq) SW VCC IREF+ ILEAK RS5W0 0(TΩYP) VREF+ ILEAK VCC IIN+ ILEAK RS5W0 0(TΩYP) VIN+ ILEAK C5pEQF VCC (TYP) IIN– (CEQ = 3.5pF SAMPLE CAP + PARASITICS) ILEAK RS5W0 0(TΩYP) VIN– ILEAK VCC IREF– ILEAK RS5W0 0(TΩYP) VREF– 2440 F16 ILEAK SWITCHING FREQUENCY fSW = 1.8MHz INTERNAL OSCILLATOR fSW = fEOSC/5 EXTERNAL OSCILLATOR Figure 16. LTC2440 Input Structure 2440fe 22 For more information www.linear.com/LTC2440

LTC2440 APPLICATIONS INFORMATION Direct Connection to Low Impedance Sources Buffering the LTC2440 If the ADC can be located physically close to the sensor, Many applications will require buffering, particularly it can be directly connected to sensors or other sources where high impedance sources are involved or where the with impedances up to 350Ω with no other components device being measured is located some distance from the required (see Figure 17). LTC2440. When buffering the LTC2440 a few simple steps should be followed. 4.5V to 5.5V Figure 19 shows a network suitable for coupling the inputs of a LTC2440 to a LTC2051 chopper-stabilized op amp. 1µF The 3µV offset and low noise of the LTC2051 make it a IN+ REF+ good choice for buffering the LTC2440. Many other op amps will work, with varying performance characteristics. LTC2440 IN– REF– The LTC2051 is configured to be able to drive the 1µF ca- pacitors at the inputs of the LTC2440. The 1µF capacitors 2440 F17 should be located close to the ADC input pins. The measured total unadjusted error of Figure 19 is well Figure 17. Direct Connection to Low Impedance (<350Ω) Source within the specifications of the LTC2440 by itself. Most is Possible if the Sensor is Located Close to the ADC. autozero amplifiers will degrade the overall resolution to some degree because of the extremely low input noise Longer Connections to Low Impedance Sources of the LTC2440, however the LTC2051 is a good general purpose buffer. The measured input referred noise of two If longer lead lengths are unavoidable, adding an input LTC2051s buffering both LTC2440 inputs is approximately capacitor close to the ADC input pins will average the double that of the LTC2440 by itself, which reduces the charging pulses and prevent reflections or ringing (see effective resolution by 1 bit for all oversample ratios. Adding Figure 18). Averaging the current pulses results in a DC gain to the LTC2051 will increase gain and offset errors input current that should be taken into account. The re- and will not appreciably increase the overall resolution, sulting 110kΩ input impedance will result in a gain error so it has limited benefit. of 0.44% for a 350Ω bridge (within the full scale specs of many bridges) and a very low 12.6ppm error for a 2Ω Procedure For Coupling Any Amplifier to the LTC2440 thermocouple connection. The LTC2051 is suitable for a wide range of DC and low 4.5V to 5.5V frequency measurement applications. If another ampli- 1µF fier is to be selected, a general procedure for evaluating 1µF the suitability of an amplifier for use with the LTC2440 is IN+ VREF+ VCC suggested here: LTC2440 1. Perform a thorough error and noise analysis on the IN– amplifier and gain setting components to verify that the GND REMOTE 1µF amplifier will perform as intended. THERMOCOUPLE 2440 F18 2. Measure the large signal response of the overall circuit. The capacitive load may affect the maximum slew rate of Figure 18. Input Capacitors Allow Longer Connection the amplifier. Verify that the slew rate is adequate for the Between the Low Impedance Source and the ADC. 2440fe 23 For more information www.linear.com/LTC2440

LTC2440 APPLICATIONS INFORMATION fastest expected input signal. Figure 20 shows the large For more information on testing high linearity ADCs, refer signal response of the circuit in Figure 19. to Linear Technology Design Solutions 11. 3. Measure noise performance of the complete circuit. A Input Bandwidth and Frequency Rejection good technique is to build one amplifier for each input, even if only one will be used in the end application. Bias The combined effect of the internal SINC4 digital filter and both amplifier outputs to midscale, with the inputs tied the digital and analog autocalibration circuits determines together. Verify that the noise is as expected, taking into the LTC2440 input bandwidth and rejection characteristics. account the bandwidth of the LTC2440 inputs for the The digital filter’s response can be adjusted by setting OSR being used, the amplifier’s broadband voltage noise the oversample ratio (OSR) through the SPI interface or and 1/f corner (if any) and any additional noise due to the by supplying an external conversion clock to the fO pin. amplifier’s current noise and source resistance. 8-12V 5V LT1236-5 4.7µF 0.01µF 10µF VCC BUSY 15 5k REF+ fO 14 LTC2440 C1 R1 0.1µF 4 REF– SCK 13 – 0.01µF SDO 12 10Ω 5 IN+ CS 11 IN+ + R2 C2 1µF 6 IN– SDI 7 1/2 LTC2051HV 1, 8, 9, 16 10 EXT 5k C4 R4 – 0.01µF 2440 F19 10Ω R5 C5 IN– + 1µF 1/2 LTC2051HV C2, C5 TAIYO YUDEN JMK107BJ105MA Figure 19. Buffering the LTC2440 from High Impedance Sources Using a Chopper Amplifier mV/DIV mV/DIV 00 2 1 100µs/DIV 5ns/DIV 2440 F20 2440 F21 Figure 20. Large Signal Input Settling Time Indicates Figure 21. Dynamic Input Current is Attenuated by Load Completed Settling with Selected Load Capacitance. Capacitance and Completely Settled Before the Next Conversion Sample Resulting in No Reduction in Performance. 2440fe 24 For more information www.linear.com/LTC2440

LTC2440 APPLICATIONS INFORMATION Table 6 lists the properties of the LTC2440 with various the modulator sample rate of 1.8MHz) exceeds 120dB. combinations of oversample ratio and clock frequency. This is 8 times the maximum conversion rate. Understanding these properties is the key to fine tuning the characteristics of the LTC2440 to the application. Effective Noise Bandwidth The LTC2440 has extremely good input noise rejection from Maximum Conversion Rate the first notch frequency all the way out to the modulator The maximum conversion rate is the fastest possible rate sample rate (typically 1.8MHz). Effective noise bandwidth at which conversions can be performed. is a measure of how the ADC will reject wideband input noise up to the modulator sample rate. The example on First Notch Frequency the following page shows how the noise rejection of the This is the first notch in the SINC4 portion of the digital filter LTC2440 reduces the effective noise of an amplifier driv- ing its input. and depends on the f clock frequency and the oversample O ratio. Rejection at this frequency and its multiples (up to Table 6. Performance vs Oversample Ratio Maximum Conversion Rate First Notch Frequency Effective Noise BW –3dB Point (sps) (Hz) (Hz) (Hz) Oversample Ratio ADC ENOB Internal External fO Internal External fO Internal External Internal External fO (OSR) Noise* (VREF = 5V)* Clock (fO/x) Clock (fO/x) 9MHz clock (fO/x) Clock (fO/x) 64 23µV 17 2816.35 f /2738 28125 f /320 3148 f /2860 1696 f /5310 O O O O 128 3.5µV 20 1455.49 f /5298 14062.5 f /640 1574 f /5720 848 f /10600 O O O O 256 2µV 21.3 740.18 f /10418 7031.3 f /1280 787 f /11440 424 f /21200 O O O O 512 1.4µV 21.8 373.28 f /20658 3515.6 f /2560 394 f /22840 212 f /42500 O O O O 1024 1µV 22.4 187.45 f /41138 1757.8 f /5120 197 f /45690 106 f /84900 O O O O 2048 750nV 22.9 93.93 f /82098 878.9 f /10200 98.4 f /91460 53 f /170000 O O O O 4096 510nV 23.4 47.01 f /164018 439.5 f /20500 49.2 f /183000 26.5 f /340000 O O O O 8192 375nV 24 23.52 f /327858 219.7 f /41000 24.6 f /366000 13.2 f /679000 O O O O 16384 250nV 24.4 11.76 f /655538 109.9 f /81900 12.4 f /731000 6.6 f /1358000 O O O O 32768 200nV 24.6 5.88 f /1310898 54.9 f /163800 6.2 f /1463000 3.3 f /2717000 O O O O *ADC noise increases by approximately √2 when OSR is decreased by a factor of 2 for OSR 32768 to OSR 256. The ADC noise at OSR 128 and OSR 64 include effects from internal modulator quantization noise. 2440fe 25 For more information www.linear.com/LTC2440

LTC2440 APPLICATIONS INFORMATION Example: The total noise is the RMS sum of this noise with the 200nV noise of the ADC at OSR = 32768. If an amplifier (e.g. LT1219) driving the input of an LTC2440 has wideband noise of 33nV/√Hz, band-limited to 1.8MHz, √82nV2 + 200nV2 = 216nV. the total noise entering the ADC input is: In this way, the digital filter with its variable oversampling 33nV/√Hz • √1.8MHz = 44.3µV. ratio can greatly reduce the effects of external noise sources. When the ADC digitizes the input, its digital filter filters Using Non-Autozeroed Amplifiers for Lowest Noise out the wideband noise from the input signal. The noise Applications reduction depends on the oversample ratio which defines the effective bandwidth of the digital filter. Ultralow noise applications may require the use of low noise bipolar amplifiers that are not autozeroed. Because At an oversample of 256, the noise bandwidth of the ADC the LTC2440 has such exceptionally low offset, offset drift is 787Hz which reduces the total amplifier noise to: and 1/f noise, the offset drift and 1/f noise in the ampli- 33nV/√Hz • √787Hz = 0.93µV. fiers may need to be compensated for to retain the system performance of which the ADC is capable. The total noise is the RMS sum of this noise with the 2µV noise of the ADC at OSR=256. The circuit of Figure 23 uses low noise bipolar amplifiers and correlated double sampling to achieve a resolution of √0.93µ/V2 + 2µV2 = 2.2µV. 14nV, or 19 effective bits over a 10mV span. Each measure- Increasing the oversampling ratio to 32768 reduces the ment is the difference between two ADC readings taken noise bandwidth of the ADC to 6.2Hz which reduces the with opposite polarity bridge excitation. This cancels 1/f total amplifier noise to: noise below 3.4Hz and eliminates errors due to parasitic thermocouples. Allow 750µs settling time after switching 33nV/√Hz • √6.2Hz = 82nV. excitation polarity. 2440fe 26 For more information www.linear.com/LTC2440

LTC2440 TYPICAL APPLICATIONS 4.5V TO 5.5V 1µF 2 15 VCC BUSY LTC1799 REFERENCE VOLTAGE 3 REFL+TC2440 fO 14 50Ω 5 OUT V+ 1 RSET 0.1V TO VCC 4 REF– SCK 13 0.1µF ANALOG INPUT RANGE 5 IN+ SDO 12 3S-PWI IINRTEERFACE GND 2 –0.5VREF TO 0.5VREF 6 IN– CS 11 7 VCC SDI 1, 8, 9, 16 10 4 3 GND EXT NC DIV SET 2440 TA05 Figure 22. Simple External Clock Source 2440fe 27 For more information www.linear.com/LTC2440

LTC2440 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC2440#packaging for the most recent package drawings. GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641 Rev B) .189 – .196* .045 ±.005 (4.801 – 4.978) .009 (0.229) 16 15 14 13 12 11 109 REF .254 MIN .150 – .165 .229 – .244 .150 – .157** (5.817 – 6.198) (3.810 – 3.988) .0165 ±.0015 .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 .015 ±.004 × 45° .0532 – .0688 .004 – .0098 (0.38 ±0.10) (1.35 – 1.75) (0.102 – 0.249) .007 – .0098 0° – 8° TYP (0.178 – 0.249) .016 – .050 .008 – .012 .0250 (0.406 – 1.270) (0.203 – 0.305) (0.635) GN16 REV B 0212 NOTE: TYP BSC 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE 4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 2440fe 28 For more information www.linear.com/LTC2440

LTC2440 REVISION HISTORY (Revision history begins at Rev E) REV DATE DESCRIPTION PAGE NUMBER E 01/17 Updated Max value for f . 4 EOSC Updated formula for t . 4 CONV Updated Note 13. 4 Revised Table 6. Performance vs Oversample Ratio. 25 2440fe 29 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconneFcotrio mn oof rites icnirfcourimts aasti doens cwriwbewd .hlienreeianr w.cilol nmot/ LinTfrCin2g4e4 o0n existing patent rights.

LTC2440 TYPICAL APPLICATION VREF 3 100k 4 +7V VREF TOP_P 5,6,7,8 LT1461-5 10µF 0.1µF TOP_N 2 + 1 100k 2X LT1677 10Ω – 4 0.047µF REF+ 1k 0.1% IN+ 1µF 100Ω 0.1% LTC2440 1k 0.1% IN– 1µF VREF – 0.047µF 10Ω REF– 3 100k + 4 2440 F22 BOTTOM_P 2X SILICONIX SI9801 5,6,7,8 BOTTOM_N 2 1 100k Figure 23. Bridge Reversal Eliminates 1/f Noise and Offset Drift of a Low Noise, Non-Autozeroed, Bipolar Amplifier. Circuit Gives 14nV Noise Level or 19 Effective Bits over a 10mV Span RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1025 Micropower Thermocouple Cold Junction Compensator 80µA Supply Current, 0.5°C Initial Accuracy LTC1043 Dual Precision Instrumentation Switched Capacitor Precise Charge, Balanced Switching, Low Power Building Block LTC1050 Precision Chopper Stabilized Op Amp No External Components 5µV Offset, 1.6µV Noise P-P LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max, 5ppm/°C Drift LT1461 Micropower Series Reference, 2.5V 0.04% Max, 3ppm/°C Max Drift LTC1592 Ultraprecise 16-Bit SoftSpanTM DAC Six Programmable Output Ranges LTC1655 16-Bit Rail-to-Rail Micropower DAC ±1LSB DNL, 600µA, Internal Reference, SO-8 LTC1799 Resistor Set SOT-23 Oscillator Single Resistor Frequency Set LTC2053 Rail-to-Rail Instrumentation Amplifier 10µV Offset with 50nV/°C Drift, 2.5µV Noise 0.01Hz to 10Hz P-P LTC2400 24-Bit, No Latency ∆∑ ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2401/LTC2402 1-/2-Channel, 24-Bit, No Latency ∆∑ ADC in MSOP 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2404/LTC2408 4-/8-Channel, 24-Bit, No Latency ∆∑ ADC 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2410/LTC2413 24-Bit, No Latency ∆∑ ADC 800nV Noise, 5ppm INL/Simultaneous 50Hz/60Hz Rejection RMS LTC2411 24-Bit, No Latency ∆∑ ADC in MSOP 1.45µV Noise, 6ppm INL RMS LTC2420/LTC2424/ 1-/4-/8-Channel, 20-Bit, No Latency ∆∑ ADCs 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400/ LTC2428 LTC2404/LTC2408 2440fe 30 Linear Technology Corporation LT 0117 REV E • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2440 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2440  LINEAR TECHNOLOGY CORPORATION 2002