LTC2420 m 20-Bit Power No Latency DS TM ADC in SO-8 FEATURES DESCRIPTIOU n 20-Bit ADC in SO-8 Package The LTC®2420 is a micropower 20-bit A/D converter with n 8ppm INL, No Missing Codes at 20 Bits an integrated oscillator, 8ppm INL and 1.2ppm RMS n 4ppm Full-Scale Error noise that operates from 2.7V to 5.5V. It uses delta-sigma n 0.5ppm Offset technology and provides a digital filter that settles in a n 1.2ppm Noise single cycle for multiplexed applications. Through a single n Digital Filter Settles in a Single Cycle. Each pin, the LTC2420 can be configured for better than 110dB Conversion Is Accurate, Even After an Input Step rejection at 50Hz or 60Hz – 2%, or it can be driven by an n Fast Mode: 16-Bit Noise, 12 Bits TUE at 100sps external oscillator for a user-defined rejection frequency n Internal Oscillator—No External Components in the range 1Hz to 800Hz. The internal oscillator requires Required no external frequency setting components. n 110dB Min, 50Hz/60Hz Notch Filter The converter accepts any external reference voltage from n Reference Input Voltage: 0.1V to V CC 0.1V to V . With its extended input conversion range of CC n Live Zero—Extended Input Range Accommodates –12.5% V to 112.5% V , the LTC2420 smoothly REF REF 12.5% Overrange and Underrange resolves the offset and overrange problems of preceding n Single Supply 2.7V to 5.5V Operation sensors or signal conditioning circuits. n Low Supply Current (200m A) and Auto Shutdown n Pin Compatible with 24-Bit LTC2400 The LTC2420 communicates through a flexible 3-wire digital interface which is compatible with SPI and APPLICATIOU S MICROWIRETM protocols. n Weight Scales , LTC and LT are registered trademarks of Linear Technology Corporation. No Latency SD is a trademark of Linear Technology Corporation. n Direct Temperature Measurement MICROWIRE is a trademark of National Semiconductor Corporation. n Gas Analyzers n Strain Gauge Transducers n Instrumentation n Data Acquisition n Industrial Process Control n 4-Digit DVMs TYPICAL APPLICATIOU Total Unadjusted Error (3V Supply) 10 VCC = 3V 8 VREF = 2.5V 2.7V TO 5.5V 6 1µF VCC 1 VCC FO 8 === IEINNXTTTEEERRRNNNAAALLL OOCSSLCCO//C56K00 HHSzzO RRUEERJJCEEECCTTIIOONN m) 42 p p LTC2420 R ( 0 O REVFEORLETNAGCEE 2 VREF SCK 7 ERR –2 0.1V TO VCC –4 3-WIRE TA = –55°C, –45°C, 25°C, 90°C ANALOG 3 6 SPI INTERFACE –6 –0.12VREIFN TPOU T1 .R12AVNRGEEF 4 VGINND SDCOS 5 –8 –10 0 0.5 1.0 1.5 2.0 2.5 2420 TA01 INPUT VOLTAGE (V) 2420 G01 1

LTC2420 ABSOLUTE WMAXIWMUWM RATINUGS PACKAGE/ORDER INUFORWMATIOUN (Notes 1, 2) ORDER PART NUMBER Supply Voltage (VCC) to GND.......................–0.3V to 7V TOP VIEW Analog Input Voltage to GND.......–0.3V to (V + 0.3V) CC VCC 1 8 FO LTC2420CS8 Reference Input Voltage to GND..–0.3V to (V + 0.3V) CC VREF 2 7 SCK LTC2420IS8 Digital Input Voltage to GND........–0.3V to (V + 0.3V) CC VIN 3 6 SDO Digital Output Voltage to GND .....–0.3V to (V + 0.3V) CC GND 4 5 CS S8 PART MARKING Operating Temperature Range S8 PACKAGE LTC2420C ...............................................0(cid:176) C to 70(cid:176) C 8-LEAD PLASTIC SO 2420 LTC2420I............................................ –40(cid:176) C to 85(cid:176) C TJMAX = 125(cid:176)C, q JA = 130(cid:176)C/W 2420I Storage Temperature Range................. –65(cid:176) C to 150(cid:176) C Consult factory for Military grade parts. Lead Temperature (Soldering, 10 sec)..................300(cid:176) C COUNVERTER CHARACTERISTICS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25(cid:176) C. (Notes 3, 4) A PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) 0.1V £ V £ V , (Note 5) l 20 Bits REF CC Integral Nonlinearity V = 2.5V (Note 6) l 4 10 ppm of V REF REF V = 5V (Note 6) l 8 20 ppm of V REF REF Integral Nonlinearity (Fast Mode) V = 5V, V = 2.5V, 100 Samples/Second, f = 2.048MHz l 40 250 ppm of V REF REF O REF Offset Error 2.5V £ V £ V l 0.5 10 ppm of V REF CC REF Offset Error (Fast Mode) 2.5V < V < 5V, 100 Samples/Second, f = 2.048MHz 3 ppm of V REF O REF Offset Error Drift 2.5V £ V £ V 0.04 ppm of V /(cid:176) C REF CC REF Full-Scale Error 2.5V £ V £ V l 4 10 ppm of V REF CC REF Full-Scale Error (Fast Mode) 2.5V < V < 5V, 100 Samples/Second, f = 2.048MHz 10 ppm of V REF O REF Full-Scale Error Drift 2.5V £ V £ V 0.04 ppm of V /(cid:176) C REF CC REF Total Unadjusted Error V = 2.5V 8 ppm of V REF REF V = 5V 16 ppm of V REF REF Output Noise V = 0V (Note 13) 6 m V IN RMS Output Noise (Fast Mode) V = 5V, 100 Samples/Second, f = 2.048MHz 20 m V REF O RMS Normal Mode Rejection 60Hz – 2% (Note 7) l 110 130 dB Normal Mode Rejection 50Hz – 2% (Note 8) l 110 130 dB Power Supply Rejection, DC V = 2.5V, V = 0V 100 dB REF IN Power Supply Rejection, 60Hz – 2% V = 2.5V, V = 0V, (Notes 7, 15) 110 dB REF IN Power Supply Rejection, 50Hz – 2% V = 2.5V, V = 0V, (Notes 8, 15) 110 dB REF IN 2

LTC2420 AU ALOG IU PUT AU D REFEREU CE The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25(cid:176) C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Voltage Range (Note 14) l –0.125 • V 1.125 • V V IN REF REF V Reference Voltage Range l 0.1 V V REF CC C Input Sampling Capacitance 1 pF S(IN) C Reference Sampling Capacitance 1.5 pF S(REF) I Input Leakage Current CS = V l –100 1 100 nA IN(LEAK) CC I Reference Leakage Current V = 2.5V, CS = V l –100 1 100 nA REF(LEAK) REF CC DIGITAL I U PUTS AU D DIGITAL OUTPUTS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25(cid:176) C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V High Level Input Voltage 2.7V £ V £ 5.5V l 2.5 V IH CC CS, F 2.7V £ V £ 3.3V 2.0 V O CC V Low Level Input Voltage 4.5V £ V £ 5.5V l 0.8 V IL CC CS, F 2.7V £ V £ 5.5V 0.6 V O CC V High Level Input Voltage 2.7V £ V £ 5.5V (Note 9) l 2.5 V IH CC SCK 2.7V £ V £ 3.3V (Note 9) 2.0 V CC V Low Level Input Voltage 4.5V £ V £ 5.5V (Note 9) l 0.8 V IL CC SCK 2.7V £ V £ 5.5V (Note 9) 0.6 V CC I Digital Input Current 0V £ V £ V l –10 10 m A IN IN CC CS, F O I Digital Input Current 0V £ V £ V (Note 9) l –10 10 m A IN IN CC SCK C Digital Input Capacitance 10 pF IN CS, F O C Digital Input Capacitance (Note 9) 10 pF IN SCK V High Level Output Voltage I = –800m A l V – 0.5 V OH O CC SDO V Low Level Output Voltage I = 1.6mA l 0.4 V OL O SDO V High Level Output Voltage I = –800m A (Note 10) l V – 0.5 V OH O CC SCK V Low Level Output Voltage I = 1.6mA (Note 10) l 0.4 V OL O SCK I High-Z Output Leakage l –10 10 m A OZ SDO POWER REQUIREW E U TS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25(cid:176) C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Supply Voltage l 2.7 5.5 V CC I Supply Current CC Conversion Mode CS = 0V (Note 12) l 200 300 m A Sleep Mode CS = V (Note 12) l 20 30 m A CC 3

LTC2420 TI W I U G CHARACTERISTICS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25(cid:176) C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f External Oscillator Frequency Range 20-Bit Effective Resolution l 2.56 307.2 kHz EOSC 12-Bit Effective Resolution l 2.56 2.048 MHz t External Oscillator High Period l 0.2 390 m s HEO t External Oscillator Low Period l 0.2 390 m s LEO t Conversion Time F = 0V l 130.86 133.53 136.20 ms CONV O F = V l 157.03 160.23 163.44 ms O CC External Oscillator (Note 11) l 20510/f (in kHz) ms EOSC f Internal SCK Frequency Internal Oscillator (Note 10) 19.2 kHz ISCK External Oscillator (Notes 10, 11) f /8 kHz EOSC D Internal SCK Duty Cycle (Note 10) 45 55 % ISCK f External SCK Frequency Range (Note 9) l 2000 kHz ESCK t External SCK Low Period (Note 9) l 250 ns LESCK t External SCK High Period (Note 9) l 250 ns HESCK t Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 12) l 1.23 1.25 1.28 ms DOUT_ISCK External Oscillator (Notes 10, 11) l 192/f (in kHz) ms EOSC t External SCK 24-Bit Data Output Time (Note 9) l 24/f (in kHz) ms DOUT_ESCK ESCK t CS fl to SDO Low Z l 0 150 ns 1 t2 CS › to SDO High Z l 0 150 ns t3 CS fl to SCK fl (Note 10) l 0 150 ns t4 CS fl to SCK › (Note 9) l 50 ns t SCK fl to SDO Valid l 200 ns KQMAX t SDO Hold After SCK fl (Note 5) l 15 ns KQMIN t SCK Set-Up Before CS fl l 50 ns 5 t SCK Hold After CS fl l 50 ns 6 Note 1: Absolute Maximum Ratings are those values beyond which the Note 9: The converter is in external SCK mode of operation such that life of the device may be impaired. the SCK pin is used as digital input. The frequency of the clock signal Note 2: All voltage values are with respect to GND. driving SCK during the data output is fESCK and is expressed in kHz. Note 3: All voltages are with respect to GND. V = 2.7 to 5.5V unless Note 10: The converter is in internal SCK mode of operation such that CC otherwise specified. R = 0W . the SCK pin is used as digital output. In this mode of operation the SOURCE SCK pin has a total equivalent load capacitance C = 20pF. Note 4: Internal Conversion Clock source with the F pin tied LOAD O to GND or to VCC or to external conversion clock source with Note 11: The external oscillator is connected to the FO pin. The external fEOSC = 153600Hz unless otherwise specified. oscillator frequency, fEOSC, is expressed in kHz. Note 5: Guaranteed by design, not subject to test. Note 12: The converter uses the internal oscillator. F = 0V or F = V . Note 6: Integral nonlinearity is defined as the deviation of a code from O O CC a straight line passing through the actual endpoints of the transfer Note 13: The output noise includes the contribution of the internal curve. The deviation is measured from the center of the quantization calibration operations. band. Note 14: For reference voltage values V > 2.5V the extended input REF Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz – 2% of –0.125 • VREF to 1.125 • VREF is limited by the absolute maximum (external oscillator). rating of the Analog Input Voltage pin (Pin 3). For 2.5V < VREF £ Note 8: F = V (internal oscillator) or f = 128000Hz – 2% 0.267V + 0.89 • VCC the input voltage range is –0.3V to 1.125 • VREF. O CC EOSC For 0.267V + 0.89 • V < V £ V the input voltage range is –0.3V (external oscillator). CC REF CC to V + 0.3V. CC Note 15: V (DC) = 4.1V, V (AC) = 2.8V . CC CC P-P 4

LTC2420 TYPICAL PERFORW AU CE CHARACTERISTICS Negative Input Extended Total Total Unadjusted Error (3V Supply) INL (3V Supply) Unadjusted Error (3V Supply) 10 10 10 VCC = 3V VCC = 3V VCC = 3V TA = 90°C 8 VREF = 2.5V 8 VREF = 2.5V 8 VREF = 2.5V TA = 25°C 6 6 6 4 4 4 TA = –45°C m) 2 m) 2 m) 2 p p p p p p R ( 0 R ( 0 R ( 0 O O O RR –2 RR –2 RR –2 TA = –55°C E E E –4 –4 –4 –6 TA = –55°C, –45°C, 25°C, 90°C –6 TA = –55°C, –45°C, 25°C, 90°C –6 –8 –8 –8 –10 –10 –10 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 0 –0.05 –0.10 –0.15 –0.20 –0.25 –0.30 INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V) 2420 G01 2420 G02 2420 G03 Positive Input Extended Total Unadjusted Error (3V Supply) Total Unadjusted Error (5V Supply) INL (5V Supply) 10 10 10 VCC = 3V VCC = 5V VCC = 5V 8 VREF = 2.5V 8 VREF = 5V 8 VREF = 5V 6 6 6 4 4 4 m) 2 m) 2 m) 2 p p p p p p R ( 0 R ( 0 R ( 0 O O O RR –2 RR –2 RR –2 E E E –4 –4 –4 TA = –55°C, –45°C, 25°C, 90°C TA = –55°C, –45°C, 25°C, 90°C TA = –55°C, –45°C, 25°C, 90°C –6 –6 –6 –8 –8 –8 –10 –10 –10 2.50 2.55 2.60 2.65 2.70 2.75 2.80 0 1 2 3 4 5 0 1 2 3 4 5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V) 2420 G04 2420 G05 2420 G06 Negative Input Extended Total Positive Input Extended Total Unadjusted Error (5V Supply) Unadjusted Error (5V Supply) Offset Error vs Reference Voltage 10 VCC = 5V TA = 25°C 10 VCC = 5V 150 VCC = 5V 8 VREF = 5V TA = 90°C 8 VREF = 5V TA = 25°C 6 TA = –45°C 6 120 4 TA = –55°C 4 pm) ERROR (ppm) –220 ERROR (ppm) –220 SET ERROR (p 6900 –4 –4 FF TA = –55°C O –6 –6 30 –8 –8 TA = 90°C TA = 25°C TA = –45°C –10 –10 0 0 –0.05 –0.10 –0.15 –0.20 –0.25 –0.30 5.00 5.05 5.10 5.15 5.20 5.25 5.30 0 1 2 3 4 5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) REFERENCE VOLTAGE (V) 2420 G07 2420 G08 2420 G09 5

LTC2420 TYPICAL PERFORW AU CE CHARACTERISTICS RMS Noise vs Reference Voltage Offset Error vs V RMS Noise vs V CC CC 60 10 10.0 VCC = 5V VREF = 2.5V VREF = 2.5V TA = 25°C TA = 25°C TA = 25°C 50 MS NOISE (ppm OF V)REF 234000 OFFSET ERROR (ppm) –550 RMS NOISE (ppm) 275...550 R 10 0 –10 0 0 1 2 3 4 5 2.7 3.2 3.7 4.2 4.7 5.2 5.5 2.7 3.2 3.7 4.2 4.7 5.2 5.5 REFERENCE VOLTAGE (V) VCC (V) VCC (V) 2420 G10 2420 G11 2420 G12 Noise Histogram RMS Noise vs Code Out Offset Error vs Temperature 350 5.00 10 VCC = 5 VCC = 5V VCC = 5V 300 VVRINE F= =0 5 VVRINE F= =0 .53VV TO 5.3V VVRINE F= =0 V5V READINGS 220500 E (ppm)3.75 TA = 25°C OR (ppm) 5 NUMBER OF 110500 RMS NOIS12..2550 OFFSET ERR –50 50 0 0 –10 –2 0 2 4 6 0 7FFFFF FFFFFF –55 –30 –5 20 45 70 95 120 OUTPUT CODE (ppm) CODE OUT (HEX) TEMPERATURE (°C) 2420G13 2420 G14 2420 G15 Full-Scale Error Full-Scale Error vs Temperature vs Reference Voltage Full-Scale Error vs V CC 10 0 10 VCC = 5V VREF = 2.5V VREF = 5V VIN = 2.5V VIN = 5V –25 TA = 25°C m) 5 m) m) 5 R (pp R (pp –50 R (pp O O O R R R ULL-SCALE ER –50 ULL-SCALE ER––10705 ULL-SCALE ER –50 F F F –125 VCC = 5V VIN = VREF –10 –150 –10 –55 –30 –5 20 45 70 95 120 0 1 2 3 4 5 2.7 3.2 3.7 4.2 4.7 5.2 5.5 TEMPERATURE (°C) REFERENCE VOLTAGE (V) VCC (V) 2420 G16 2420 G17 2420 G18 6

LTC2420 TYPICAL PERFORW AU CE CHARACTERISTICS Conversion Current vs Temperature Sleep Current vs Temperature Rejection vs Frequency at V CC 230 30 –20 VCC = 4.1V 220 VCC = 5.5V –40 TVAIN = = 2 05V°C µURRENT (A) 122910000 VCC = 4.1V mURRENT (A) 20 VVCCCC = = 2 5.7VV TION (dB) –60 FO = 0 UPPLY C 180 VCC = 2.7V UPPLY C 10 REJEC –80 S 170 S –100 160 150 0 –120 –55 –30 –5 20 45 70 95 120 –55 –30 –5 20 45 70 95 120 1 50 100 150 200 250 TEMPERATURE (°C) TEMPERATURE (°C) FREQUENCY AT VCC (Hz) 2420 G19 2420 G20 2420 G21 Rejection vs Frequency at V Rejection vs Frequency at V Rejection vs Frequency at V CC CC IN 0 0 0 VCC = 4.1V VCC = 4.1V VCC = 5V VIN = 0V VIN = 0V VREF = 5V –20 TA = 25°C –20 TA = 25°C –20 VIN = 2.5V FO = 0 FO = 0 FO = 0 B)–40 B)–40 B)–40 N (d N (d N (d CTIO–60 CTIO–60 CTIO–60 REJE–80 REJE–80 REJE–80 –100 –100 –100 –120 –120 –120 15200 15250 15300 15350 15400 15450 15500 1 100 10k 1M 1 50 100 150 200 250 FREQUENCY AT VCC (Hz) FREQUENCY AT VCC (Hz) FREQUENCY AT VIN (Hz) 2420 G22 2420 G23 2420 G24 Rejection vs Frequency at V Rejection vs Frequency at V Rejection vs Frequency at V IN IN IN –60 0 0 VCC = 5V –70 –20 VVRINE F= =2 .55VV –20 –80 FO = 0 –40 N (dB) –90 N (dB)–40 N (dB) –60 REJECTIO ––110100 REJECTIO––8600 REJECTIO –80 –100 –120 –100 –130 –120 SAMPLE RATE = 15.36kHz – 2% –140 –120 –140 –12 –8 –4 0 4 8 12 15100 15200 15300 15400 15500 0 fS/2 fS INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%) FREQUENCY AT VIN (Hz) INPUT FREQUENCY 2420 G25 2420 G26 2420 F27 7

LTC2420 TYPICAL PERFORW AU CE CHARACTERISTICS INL vs Output Rate INL vs Output Rate Resolution vs Output Rate 20 20 24 VCC = 5V VCC = 3V VCC = 5V TA = 25°C VREF = 5V VREF = 2.5V VREF = 5V TA = 90°C 18 FO = EXTERNAL 18 FO = EXTERNAL fO = EXTERNAL TA = –45°C S) S) 22 BIT BIT TS) TUE RESOLUTION ( 1146 TA = –4T5A° =C 25°C TA = 90°C TUE RESOLUTION ( 1146 TA = T2A5 °=C –45°C TA = 90°C RESOLUTION (BI 1280 12 12 10 10 16 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 0 7.5 25 50 75 100 OUTPUT RATE (Hz) OUTPUT RATE (Hz) OUTPUT RATE (Hz) 2420 G28 2420 G29 2420 G30 PIUN FUUNCTIOUNS V (Pin 1): Positive Supply Voltage. Bypass to GND SDO (Pin 6): Three-State Digital Output. During the data CC (Pin␣4) with a 10m F tantalum capacitor in parallel with output period this pin is used for serial data output. When 0.1m F ceramic capacitor as close to the part as possible. the chip select CS is HIGH (CS = V ), the SDO pin is in a CC high impedance state. During the Conversion and Sleep V (Pin 2): Reference Input. The reference voltage range REF periods, this pin can be used as a conversion status out- is 0.1V to V . CC put. The conversion status can be observed by pulling CS VIN (Pin 3): Analog Input. The input voltage range is LOW. –0.125 • V to 1.125 • V . For V > 2.5V the input REF REF REF SCK (Pin 7): Bidirectional Digital Clock Pin. In Internal voltage range may be limited by the pin absolute maxi- Serial Clock Operation mode, SCK is used as digital output mum rating of –0.3V to V + 0.3V. CC for the internal serial interface clock during the data output GND (Pin 4): Ground. Shared pin for analog ground, period. In External Serial Clock Operation mode, SCK is digital ground, reference ground and signal ground. Should used as digital input for the external serial interface. A be connected directly to a ground plane through a mini- weak internal pull-up is automatically activated in Internal mum length trace or it should be the single-point-ground Serial Clock Operation mode. The Serial Clock mode is in a single point grounding system. determined by the level applied to SCK at power up and the falling edge of CS. CS (Pin 5): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. F (Pin 8): Frequency Control Pin. Digital input that O Following each conversion, the ADC automatically enters controls the ADC’s notch frequencies and conversion the Sleep mode and remains in this low power state as time. When the F pin is connected to V (F = V ), the O CC O CC long as CS is HIGH. A LOW on CS wakes up the ADC. A converter uses its internal oscillator and the digital filter’s LOW-to-HIGH transition on this pin disables the SDO first null is located at 50Hz. When the F pin is connected O digital output. A LOW-to-HIGH transition on CS during the to GND (F = OV), the converter uses its internal oscillator O Data Output transfer aborts the data transfer and starts a and the digital filter first null is located at 60Hz. When F O new conversion. is driven by an external clock signal with a frequency f , EOSC the converter uses this signal as its clock and the digital filter first null is located at a frequency f /2560. EOSC 8

LTC2420 FUU CTIOU AL BLOCK DIAGRAW INTERNAL VCC OSCILLATOR GND AUTOCALIBRATION AND CONTROL FO (INT/EXT) VIN ∫ ∫ ∫ SDO ∑ SERIAL ADC SCK INTERFACE CS VREF DECIMATING FIR DAC 2420 FD TEST CIRCUITS VCC 3.4k SDO SDO 3.4k CLOAD = 20pF CLOAD = 20pF Hi-Z TO VOH Hi-Z TO VOL VOL TO VOH VOH TO VOL VOH TO Hi-Z 2420 TC01 VOL TO Hi-Z 2420 TC02 9

LTC2420 APPLICATIOUS IUFORWATIOU The LTC2420 is pin compatible with the LTC2400. The two Once CS is pulled LOW, the device begins outputting the devices are designed to allow the user to incorporate conversion result. There is no latency in the conversion either device in the same design with no modifications. result. The data output corresponds to the conversion just While the LTC2420 output word length is 24 bits (as performed. This result is shifted out on the serial data out opposed to the 32-bit output of the LTC2400), its output pin (SDO) under the control of the serial clock (SCK). Data clock timing can be identical to the LTC2400. As shown in is updated on the falling edge of SCK allowing the user to Figure 1, the LTC2420 data output is concluded on the reliably latch data on the rising edge of SCK, see Figure 4. falling edge of the 24th serial clock (SCK). In order to The data output state is concluded once 24 bits are read maintain drop-in compatibility with the LTC2400, it is out of the ADC or when CS is brought HIGH. The device possible to clock the LTC2420 with an additional 8 serial automatically initiates a new conversion cycle and the clock pulses. This results in 8 additional output bits which cycle repeats. are always logic HIGH. Through timing control of the CS and SCK pins, the LTC2420 offers several flexible modes of operation Converter Operation Cycle (internal or external SCK and free-running conversion The LTC2420 is a low power, delta-sigma analog-to- modes). These various modes do not require digital converter with an easy to use 3-wire serial interface. programming configuration registers; moreover, they do Its operation is simple and made up of three states. The converter operating cycle begins with the conversion, CONVERT followed by a low power sleep state and concluded with the data output (see Figure 2). The 3-wire interface con- SLEEP sists of serial data output (SDO), a serial clock (SCK) and a chip select (CS). Initially, the LTC2420 performs a conversion. Once the 1 CS AND conversion is complete, the device enters the sleep state. SCK While in this sleep state, power consumption is reduced by 0 an order of magnitude. The part remains in the sleep state as long as CS is logic HIGH. The conversion result is held DATA OUTPUT indefinitely in a static shift register while the converter is 2420 F02 in the sleep state. Figure 2. LTC2420 State Transition Diagram CS 8 8 8 8 (OPTIONAL) SCK SDO EOC = 1 EOC = 0 DATA OUT EOC = 1 4 STATUS BITS 20 DATA BITS LAST 8 BITS ALWAYS 1 CONVERSION SLEEP DATA OUTPUT CONVERSION 2420 F01 Figure 1. LTC2420 Compatible Timing with the LTC2400 10

LTC2420 APPLICATIOUS IUFORWATIOU not disturb the cyclic operation described above. These signal clears all internal registers. Following the POR modes of operation are described in detail in the Serial signal, the LTC2420 starts a normal conversion cycle and Interface Timing Modes section. follows the normal succession of states described above. The first conversion result following POR is accurate Conversion Clock within the specifications of the device. A major advantage delta-sigma converters offer over Reference Voltage Range conventional type converters is an on-chip digital filter (commonly known as Sinc or Comb filter). For high The LTC2420 can accept a reference voltage from 0V to resolution, low frequency applications, this filter is typi- V . The converter output noise is determined by the CC cally designed to reject line frequencies of 50Hz or 60Hz thermal noise of the front-end circuits, and as such, its plus their harmonics. In order to reject these frequencies value in microvolts is nearly constant with reference in excess of 110dB, a highly accurate conversion clock is voltage. A decrease in reference voltage will not signifi- required. The LTC2420 incorporates an on-chip highly cantly improve the converter’s effective resolution. On the accurate oscillator. This eliminates the need for external other hand, a reduced reference voltage will improve the frequency setting components such as crystals or oscilla- overall converter INL performance. The recommended tors. Clocked by the on-chip oscillator, the LTC2420 range for the LTC2420 voltage reference is 100mV to V . CC rejects line frequencies (50Hz or 60Hz – 2%) a minimum of 110dB. Input Voltage Range The converter is able to accommodate system level offset Ease of Use and gain errors as well as system level overrange situa- The LTC2420 data output has no latency, filter settling or tions due to its extended input range, see Figure 3. The redundant data associated with the conversion cycle. LTC2420 converts input signals within the extended input There is a one-to-one correspondence between the range of –0.125 • V to 1.125 • V . REF REF conversion and the output data. Therefore, multiplexing For large values of V , this range is limited by the REF an analog input voltage is easy. absolute maximum voltage range of –0.3V to (V + 0.3V). CC The LTC2420 performs offset and full-scale calibrations Beyond this range, the input ESD protection devices begin every conversion cycle. This calibration is transparent to to turn on and the errors due to the input leakage current the user and has no effect on the cyclic operation de- increase rapidly. scribed above. The advantage of continuous calibration is Input signals applied to V may extend below ground by IN extreme stability of offset and full-scale readings with re- –300mV and above V by 300mV. In order to limit any CC spect to time, supply voltage change and temperature drift. Power-Up Sequence VCC + 0.3V The LTC2420 automatically enters an internal reset state 9/8VREF when the power supply voltage V drops below approxi- VREF CC mately 2.2V. This feature guarantees the integrity of the ABSOLUTE NORMAL EXTENDED MAXIMUM conversion result and of the serial interface mode selec- 1/2VREF INPUT INPUT INPUT RANGE RANGE tion which is performed at the initial power-up. (See the RANGE 2-wire I/O sections in the Serial Interface Timing Modes 0 section.) –1/8VREF When the V voltage rises above this critical threshold, CC –0.3V the converter creates an internal power-on-reset (POR) 2420 F03 signal with duration of approximately 0.5ms. The POR Figure 3. LTC2420 Input Range 11

LTC2420 APPLICATIOUS IUFORWATIOU fault current, a resistor of up to 25k may be added in series Bit 20 (fourth output bit) is the extended input range (EXR) with the V pin without affecting the performance of the indicator. If the input is within the normal input range IN device. In the physical layout, it is important to maintain 0␣£ ␣V £ V , this bit is LOW. If the input is outside the IN REF the parasitic capacitance of the connection between this normal input range, V > V or V < 0, this bit is HIGH. IN REF IN series resistance and the V pin as low as possible; IN The function of these bits is summarized in Table 1. therefore, the resistor should be located as close as practical to the V pin. The effect of the series resistance Table 1. LTC2420 Status Bits IN on the converter accuracy can be evaluated from the Bit 23 Bit 22 Bit 21 Bit 20 Input Range EOC DMY SIG EXR curves presented in the Analog Input/Reference Current V > V 0 0 1 1 section. In addition, a series resistor will introduce a IN REF temperature dependent offset error due to the input leak- 0 < VIN £ VREF 0 0 1 0 age current. A 1nA input leakage current will develop a VIN = 0+/0– 0 0 1/0 0 1ppm offset error on a 5k resistor if VREF = 5V. This error VIN < 0 0 0 0 1 has a very strong temperature dependency. Bit 19 (fifth output bit) is the most significant bit (MSB). Output Data Format Bits 19-0 are the 20-bit conversion result MSB first. The LTC2420 serial output data stream is 24 bits long. The Bit 0 is the least significant bit (LSB). first 4 bits represent status information indicating the Data is shifted out of the SDO pin under control of the serial sign, input range and conversion state. The next 20 bits are clock (SCK), see Figure 4. Whenever CS is HIGH, SDO the conversion result, MSB first. remains high impedance and any SCK clock pulses are Bit 23 (first output bit) is the end of conversion (EOC) ignored by the internal data out shift register. indicator. This bit is available at the SDO pin during the In order to shift the conversion result out of the device, CS conversion and sleep states whenever the CS pin is LOW. must first be driven LOW. EOC is seen at the SDO pin of the This bit is HIGH during the conversion and goes LOW device once CS is pulled LOW. EOC changes real time from when the conversion is complete. HIGH to LOW at the completion of a conversion. This Bit 22 (second output bit) is a dummy bit (DMY) and is signal may be used as an interrupt for an external micro- always LOW. controller. Bit 23 (EOC) can be captured on the first rising edge of SCK. Bit 22 is shifted out of the device on the first Bit 21 (third output bit) is the conversion result sign indi- falling edge of SCK. The final data bit (Bit 0) is shifted out cator (SIG). If V is >0, this bit is HIGH. If V is <0, this IN IN on the falling edge of the 23rd SCK and may be latched on bit is LOW. The sign bit changes state during the zero code. CS BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 4 BIT 0 SDO EOC “0” SIG EXT MSB LSB20 Hi-Z SCK 1 2 3 4 5 19 20 24 SLEEP DATA OUTPUT CONVERSION 2420 F04 Figure 4. Output Data Timing 12

LTC2420 APPLICATIOUS IUFORWATIOU the rising edge of the 24th SCK pulse. On the falling edge change during the sleep or data output states will not of the 24th SCK pulse, SDO goes HIGH indicating a new disturb the converter operation. If the selection is made conversion cycle has been initiated. This bit serves as EOC during the conversion state, the result of the conversion in (Bit 23) for the next conversion cycle. Table 2 summarizes progress may be outside specifications but the following the output data format. conversions will not be affected. As long as the voltage on the V pin is maintained within When a fundamental rejection frequency different from IN the –0.3V to (V + 0.3V) absolute maximum operating 50Hz or 60Hz is required or when the converter must be CC range, a conversion result is generated for any input value synchronized with an outside source, the LTC2420 can from –0.125 • V to 1.125 • V . For input voltages operate with an external conversion clock. The converter REF REF greater than 1.125 • V , the conversion result is clamped automatically detects the presence of an external clock REF to the value corresponding to 1.125 • V . For input signal at the F pin and turns off the internal oscillator. The REF O voltages below –0.125 • V , the conversion result is frequency f of the external signal must be at least REF EOSC clamped to the value corresponding to –0.125 • V . 2560Hz (1Hz notch frequency) to be detected. The exter- REF nal clock signal duty cycle is not significant as long as the Frequency Rejection Selection (FO Pin Connection) minimum and maximum specifications for the high and low periods t and t are observed. The LTC2420 internal oscillator provides better than 110dB HEO LEO normal mode rejection at the line frequency and its har- While operating with an external conversion clock of a monics for 50Hz – 2% or 60Hz – 2%. For 60Hz rejection, FO frequency fEOSC, the LTC2420 provides better than 110dB (Pin 8) should be connected to GND (Pin 4) while for 50Hz normal mode rejection in a frequency range f /2560 EOSC rejection the FO pin should be connected to VCC (Pin␣1). – 4% and its harmonics. The normal mode rejection as a function of the input frequency deviation from f /2560 The selection of 50Hz or 60Hz rejection can also be made EOSC is shown in Figure 5. by driving F to an appropriate logic level. A selection O Table 2. LTC2420 Output Data Format Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 … Bit 0 Input Voltage EOC DMY SIG EXR MSB LSB V > 9/8 • V 0 0 1 1 0 0 0 1 1 ... 1 IN REF 9/8 • V 0 0 1 1 0 0 0 1 1 ... 1 REF V + 1LSB 0 0 1 1 0 0 0 0 0 ... 0 REF V 0 0 1 0 1 1 1 1 1 ... 1 REF 3/4V + 1LSB 0 0 1 0 1 1 0 0 0 ... 0 REF 3/4V 0 0 1 0 1 0 1 1 1 ... 1 REF 1/2V + 1LSB 0 0 1 0 1 0 0 0 0 ... 0 REF 1/2V 0 0 1 0 0 1 1 1 1 ... 1 REF 1/4V + 1LSB 0 0 1 0 0 1 0 0 0 ... 0 REF 1/4V 0 0 1 0 0 0 1 1 1 ... 1 REF 0+/0– 0 0 1/0* 0 0 0 0 0 0 ... 0 –1LSB 0 0 0 1 1 1 1 1 1 ... 1 –1/8 • V 0 0 0 1 1 1 1 0 0 ... 0 REF V < –1/8 • V 0 0 0 1 1 1 1 0 0 ... 0 IN REF *The sign bit changes state during the 0 code. 13

LTC2420 APPLICATIOUS IUFORWATIOU –60 Table 3 summarizes the duration of each state as a –70 function of FO. –80 B) –90 SERIAL INTERFACE d N ( TIO –100 The LTC2420 transmits the conversion results and re- C E EJ –110 ceives the start of conversion command through a syn- R –120 chronous 3-wire interface. During the conversion and sleep states, this interface can be used to assess the –130 converter status and during the data output state it is used –140 –12 –8 –4 0 4 8 12 to read the conversion result. INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%) 2420 F05 Serial Clock Input/Output (SCK) Figure 5. LTC2420 Normal Mode Rejection When The serial clock signal present on SCK (Pin 7) is used to Using an External Oscillator of Frequency f EOSC synchronize the data transfer. Each bit of data is shifted out the SDO pin on the falling edge of the serial clock. Whenever an external clock is not present at the F pin, the O converter automatically activates its internal oscillator and In the Internal SCK mode of operation, the SCK pin is an enters the Internal Conversion Clock mode. The LTC2420 output and the LTC2420 creates its own serial clock by operation will not be disturbed if the change of conversion dividing the internal conversion clock by 8. In the External clock source occurs during the sleep state or during the SCK mode of operation, the SCK pin is used as input. The data output state while the converter uses an external internal or external SCK mode is selected on power-up and serial clock. If the change occurs during the conversion then reselected every time a HIGH-to-LOW transition is state, the result of the conversion in progress may be detected at the CS pin. If SCK is HIGH or floating at power- outside specifications but the following conversions will up or during this transition, the converter enters the inter- not be affected. If the change occurs during the data output nal SCK mode. If SCK is LOW at power-up or during this state and the converter is in the Internal SCK mode, the transition, the converter enters the external SCK mode. serial clock duty cycle may be affected but the serial data stream will remain valid. Table 3. LTC2420 State Duration State Operating Mode Duration CONVERT Internal Oscillator F = LOW 133ms O (60Hz Rejection) F = HIGH 160ms O (50Hz Rejection) External Oscillator F = External Oscillator 20510/f s O EOSC with Frequency f kHz EOSC (f /2560 Rejection) EOSC SLEEP As Long As CS = HIGH Until CS = 0 and SCK DATA OUTPUT Internal Serial Clock F = LOW/HIGH As Long As CS = LOW But Not Longer Than 1.26ms O (Internal Oscillator) (24 SCK cycles) F = External Oscillator with As Long As CS = LOW But Not Longer Than 256/f ms O EOSC Frequency f kHz (24 SCK cycles) EOSC External Serial Clock with As Long As CS = LOW But Not Longer Than 24/f ms SCK Frequency f kHz (24 SCK cycles) SCK 14

LTC2420 APPLICATIOUS IUFORWATIOU Serial Data Output (SDO) SERIAL INTERFACE TIMING MODES The serial data output pin, SDO (Pin 6), drives the serial The LTC2420’s 3-wire interface is SPI and MICROWIRE data during the data output state. In addition, the SDO pin compatible. This interface offers several flexible modes of is used as an end of conversion indicator during the operation. These include internal/external serial clock, conversion and sleep states. 2- or 3-wire I/O, single cycle conversion and autostart. The following sections describe each of these serial interface When CS (Pin 5) is HIGH, the SDO driver is switched to a timing modes in detail. In all these cases, the converter high impedance state. This allows sharing the serial can use the internal oscillator (F = LOW or F = HIGH) or interface with other devices. If CS is LOW during the O O an external oscillator connected to the F pin. Refer to convert or sleep state, SDO will output EOC. If CS is LOW O Table 4 for a summary. during the conversion phase, the EOC bit appears HIGH on the SDO pin. Once the conversion is complete, EOC goes External Serial Clock, Single Cycle Operation LOW. The device remains in the sleep state until the first (SPI/MICROWIRE Compatible) rising edge of SCK occurs while CS is LOW. This timing mode uses an external serial clock to shift out Chip Select Input (CS) the conversion result and a CS signal to monitor and control the state of the conversion cycle, see Figure 6. The active LOW chip select, CS (Pin 5), is used to test the conversion status and to enable the data output transfer as The serial clock mode is selected on the falling edge of CS. described in the previous sections. To select the external serial clock mode, the serial clock pin (SCK) must be LOW during each CS falling edge. In addition, the CS signal can be used to trigger a new conversion cycle before the entire serial data transfer has The serial data output pin (SDO) is Hi-Z as long as CS is been completed. The LTC2420 will abort any serial data HIGH. At any time during the conversion cycle, CS may be transfer in progress and start a new conversion cycle any- pulled LOW in order to monitor the state of the converter. time a LOW-to-HIGH transition is detected at the CS pin While CS is pulled LOW, EOC is output to the SDO pin. EOC after the converter has entered the data output state (i.e., = 1 while a conversion is in progress and EOC = 0 if the after the first rising edge of SCK occurs while CS is LOW). device is in the sleep state. Independent of CS, the device automatically enters the low power sleep state once the Finally, CS can be used to control the free-running modes conversion is complete. of operation, see Serial Interface Timing Modes section. Grounding CS will force the ADC to continuously convert When the device is in the sleep state (EOC = 0), its at the maximum output rate selected by F . Tying a conversion result is held in an internal static shift regis- O capacitor to CS will reduce the output rate and power ter. The device remains in the sleep state until the first dissipation by a factor proportional to the capacitor’s rising edge of SCK is seen while CS is LOW. Data is shifted value, see Figures 13 to 15. out the SDO pin on each falling edge of SCK. This enables Table 4. LTC2420 Interface Timing Modes Conversion Data Connection SCK Cycle Output and Configuration Source Control Control Waveforms External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 6, 7 External SCK, 2-Wire I/O External SCK SCK Figure 8 Internal SCK, Single Cycle Conversion Internal CS fl CS fl Figures 9, 10 Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 11 Internal SCK, Autostart Conversion Internal C Internal Figure 12 EXT 15

LTC2420 APPLICATIOUS IUFORWATIOU 2.7V TO 5.5V 1µF VCC = 50Hz REJECTION VCC FO = EXTERNAL OSCILLATOR = 60Hz REJECTION LTC2420 0.1V TOV VRCECF VREF SCK –0.12VREF TO 1.12VRVEINF VIN SDO GND CS CS TEST EOC TEST EOC TEST EOC BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 4 BIT 0 SDO EOC SIG EXR MSB LSB20 Hi-Z Hi-Z Hi-Z SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION 2420 F06 Figure 6. External Serial Clock, Single Cycle Operation external circuitry to latch the output on the rising edge of External Serial Clock, 2-Wire I/O SCK. EOC can be latched on the first rising edge of SCK This timing mode utilizes a 2-wire serial I/O interface. The and the last bit of the conversion result can be latched on conversion result is shifted out of the device by an exter- the 24th rising edge of SCK. On the 24th falling edge of nally generated serial clock (SCK) signal, see Figure 8. CS SCK, the device begins a new conversion. SDO goes HIGH may be permanently tied to ground (Pin 4), simplifying the (EOC = 1) indicating a conversion is in progress. user interface or isolation barrier. At the conclusion of the data cycle, CS may remain LOW The external serial clock mode is selected at the end of the and EOC monitored as an end-of-conversion interrupt. power-on reset (POR) cycle. The POR cycle is concluded Alternatively, CS may be driven HIGH setting SDO to Hi-Z. approximately 0.5ms after V exceeds 2.2V. The level CC As described above, CS may be pulled LOW at any time in applied to SCK at this time determines if SCK is internal or order to monitor the conversion status. external. SCK must be driven LOW prior to the end of POR Typically, CS remains LOW during the data output state. in order to enter the external serial clock timing mode. However, the data output state may be aborted by pulling Since CS is tied LOW, the end-of-conversion (EOC) can be CS HIGH anytime between the first rising edge and the continuously monitored at the SDO pin during the convert 24th falling edge of SCK, see Figure 7. On the rising edge and sleep states. EOC may be used as an interrupt to an of CS, the device aborts the data output state and imme- external controller indicating the conversion result is diately initiates a new conversion. This is useful for sys- ready. EOC = 1 while the conversion is in progress and EOC tems not requiring all 24 bits of output data, aborting an = 0 once the conversion enters the low power sleep state. invalid conversion cycle or synchronizing the start of a On the falling edge of EOC, the conversion result is loaded conversion. 16

LTC2420 APPLICATIOUS IUFORWATIOU 2.7V TO 5.5V 1µF VCC= 50Hz REJECTION VCC FO = EXTERNAL OSCILLATOR = 60Hz REJECTION LTC2420 0.1V TOV VRCECF VREF SCK –0.12VREF TO 1.12VRVEINF VIN SDO GND CS CS TEST EOC TEST EOC TEST EOC BIT 0 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 9 BIT 8 SDO EOC EOC SIG EXR MSB Hi-Z Hi-Z Hi-Z Hi-Z SCK (EXTERNAL) SLEEP CONVERSION SLEEP DATA OUTPUT CONVERSION DATA OUTPUT 2420 F07 Figure 7. External Serial Clock, Reduced Data Output Length 2.7V TO 5.5V 1µF VCC = 50Hz REJECTION VCC FO = EXTERNAL OSCILLATOR = 60Hz REJECTION LTC2420 0.1V TOV VRCECF VREF SCK –0.12VREF TO 1.12VRVEINF VIN SDO GND CS CS BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 4 BIT 0 SDO EOC SIG EXR MSB LSB20 SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION 2420 F07 Figure 8. External Serial Clock, CS = 0 Operation 17

LTC2420 APPLICATIOUS IUFORWATIOU into an internal static shift register. The device remains in to the SDO pin. EOC = 1 while a conversion is in progress the sleep state until the first rising edge of SCK. Data is and EOC = 0 if the device is in the sleep state. shifted out the SDO pin on each falling edge of SCK When testing EOC, if the conversion is complete (EOC = 0), enabling external circuitry to latch data on the rising edge the device will exit the sleep state and enter the data output of SCK. EOC can be latched on the first rising edge of SCK. state if CS remains LOW. In order to prevent the device On the 24th falling edge of SCK, SDO goes HIGH (EOC = 1) from exiting the low power sleep state, CS must be pulled indicating a new conversion has begun. HIGH before the first rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the device begins Internal Serial Clock, Single Cycle Operation outputting data at time t after the falling edge of CS EOCtest This timing mode uses an internal serial clock to shift out (if EOC = 0) or t after EOC goes LOW (if CS is LOW EOCtest the conversion result and a CS signal to monitor and during the falling edge of EOC). The value of t is 23m s EOCtest control the state of the conversion cycle, see Figure 9. if the device is using its internal oscillator (F = logic LOW 0 or HIGH). If F is driven by an external oscillator of In order to select the internal serial clock timing mode, the O frequency f , then t is 3.6/f . If CS is pulled serial clock pin (SCK) must be floating (Hi-Z) or pulled EOSC EOCtest EOSC HIGH before time t , the device remains in the sleep HIGH prior to the falling edge of CS. The device will not EOCtest state. The conversion result is held in the internal static enter the internal serial clock mode if SCK is driven LOW shift register. on the falling edge of CS. An internal weak pull-up resistor is active on the SCK pin during the falling edge of CS; If CS remains LOW longer than t , the first rising EOCtest therefore, the internal serial clock timing mode is auto- edge of SCK will occur and the conversion result is serially matically selected if SCK is not externally driven. shifted out of the SDO pin. The data output cycle begins on this first rising edge of SCK and concludes after the 24th The serial data output pin (SDO) is Hi-Z as long as CS is rising edge. Data is shifted out the SDO pin on each falling HIGH. At any time during the conversion cycle, CS may be edge of SCK. The internally generated serial clock is output pulled LOW in order to monitor the state of the converter. to the SCK pin. This signal may be used to shift the Once CS is pulled LOW, SCK goes LOW and EOC is output 2.7V TO 5.5V VCC 1µF VCC = 50Hz REJECTION VCC FO == E6X0HTEz RRNEAJELC OTSIOCNILLATOR 10k LTC2420 0.1V TOV VRCECF VREF SCK –0.12VREF TO 1.12VRVEINF VIN SDO GND CS <tEOCtest CS TEST EOC TEST EOC BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 4 BIT 0 SDO EOC SIG EXR MSB LSB20 Hi-Z Hi-Z Hi-Z Hi-Z SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION 2420 F09 Figure 9. Internal Serial Clock, Single Cycle Operation 18

LTC2420 APPLICATIOUS IUFORWATIOU conversion result into external circuitry. EOC can be if the device is in the internal SCK timing mode. However, latched on the first rising edge of SCK and the last bit of the certain applications may require an external driver on SCK. conversion result on the 24th rising edge of SCK. After the If this driver goes Hi-Z after outputting a LOW signal, the 24th rising edge, SDO goes HIGH (EOC = 1), SCK stays LTC2420’s internal pull-up remains disabled. Hence, SCK HIGH, and a new conversion starts. remains LOW. On the next falling edge of CS, the device is switched to the external SCK timing mode. By adding an Typically, CS remains LOW during the data output state. external 10k pull-up resistor to SCK, this pin goes HIGH However, the data output state may be aborted by pulling once the external driver goes Hi-Z. On the next CS falling CS HIGH anytime between the first and 24th rising edge of edge, the device will remain in the internal SCK timing SCK, see Figure 10. On the rising edge of CS, the device mode. aborts the data output state and immediately initiates a new conversion. This is useful for systems not requiring A similar situation may occur during the sleep state when all 24 bits of output data, aborting an invalid conversion CS is pulsed HIGH-LOW-HIGH in order to test the conver- cycle, or synchronizing the start of a conversion. If CS is sion status. If the device is in the sleep state (EOC = 0), SCK pulled HIGH while the converter is driving SCK LOW, the will go LOW. Once CS goes HIGH (within the time period internal pull-up is not available to restore SCK to a logic defined above as t ), the internal pull-up is activated. EOCtest HIGH state. This will cause the device to exit the internal For a heavy capacitive load on the SCK pin, the internal serial clock mode on the next falling edge of CS. This can pull-up may not be adequate to return SCK to a HIGH level be avoided by adding an external 10k pull-up resistor to before CS goes low again. This is not a concern under the SCK pin or by never pulling CS HIGH when SCK is LOW. normal conditions where CS remains LOW after detecting EOC = 0. This situation is easily overcome by adding an Whenever SCK is LOW, the LTC2420’s internal pull-up at external 10k pull-up resistor to the SCK pin. pin SCK is disabled. Normally, SCK is not externally driven 2.7V TO 5.5V VCC 1µF VCC = 50Hz REJECTION VCC FO == E6X0HTEz RRNEAJELC OTSIOCNILLATOR 10k LTC2420 0.1V TOV VRCECF VREF SCK –0.12VREF TO 1.12VRVEINF VIN SDO GND CS >tEOCtest <tEOCtest CS TEST EOC TEST EOC TEST EOC BIT 0 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 8 SDO EOC EOC SIG EXR MSB Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z SCK (INTERNAL) SLEEP CONVERSION SLEEP DATA OUTPUT CONVERSION DATA OUTPUT 2420 F10 Figure 10. Internal Serial Clock, Reduced Data Output Length 19

LTC2420 APPLICATIOUS IUFORWATIOU Internal Serial Clock, 2-Wire I/O, then immediately begins outputting data. The data output Continuous Conversion cycle begins on the first rising edge of SCK and ends after the 24th rising edge. Data is shifted out the SDO pin on This timing mode uses a 2-wire, all output (SCK and SDO) each falling edge of SCK. The internally generated serial interface. The conversion result is shifted out of the device clock is output to the SCK pin. This signal may be used by an internally generated serial clock (SCK) signal, see to shift the conversion result into external circuitry. EOC Figure 11. CS may be permanently tied to ground (Pin 4), can be latched on the first rising edge of SCK and the last simplifying the user interface or isolation barrier. bit of the conversion result can be latched on the 24th The internal serial clock mode is selected at the end of the rising edge of SCK. After the 24th rising edge, SDO goes power-on reset (POR) cycle. The POR cycle is concluded HIGH (EOC = 1) indicating a new conversion is in progress. approximately 0.5ms after VCC exceeds 2.2V. An internal SCK remains HIGH during the conversion. weak pull-up is active during the POR cycle; therefore, the internal serial clock timing mode is automatically selected Internal Serial Clock, Autostart Conversion if SCK is not externally driven LOW (if SCK is loaded such This timing mode is identical to the internal serial clock, that the internal pull-up cannot pull the pin HIGH, the 2-wire I/O described above with one additional feature. external SCK mode will be selected). Instead of grounding CS, an external timing capacitor is During the conversion, the SCK and the serial data output tied to CS. pin (SDO) are HIGH (EOC = 1). Once the conversion is While the conversion is in progress, the CS pin is held complete, SCK and SDO go LOW (EOC = 0) indicating the HIGH by an internal weak pull-up. Once the conversion is conversion has finished and the device has entered the complete, the device enters the low power sleep state and low power sleep state. The part remains in the sleep state an internal 25nA current source begins discharging the a minimum amount of time (1/2 the internal SCK period) 2.7V TO 5.5V 1µF VCC = 50Hz REJECTION VCC FO = EXTERNAL OSCILLATOR = 60Hz REJECTION LTC2420 0.1V TOV VRCECF VREF SCK –0.12VREF TO 1.12VRVEINF VIN SDO GND CS CS BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 4 BIT 0 SDO EOC SIG EXR MSB LSB20 SCK (INTERNAL) CONVERSION DATA OUTPUT CONVERSION SLEEP 2420 F11 Figure 11. Internal Serial Clock, Continuous Operation 20

LTC2420 APPLICATIOUS IUFORWATIOU capacitor tied to CS, see Figure 12. The time the converter without disturbing the converter operation using a regular spends in the sleep state is determined by the value of the oscilloscope probe. When using this configuration, it is external timing capacitor, see Figures 13 and 14. Once the important to minimize the external leakage current at the voltage at CS falls below an internal threshold (» 1.4V), the CS pin by using a low leakage external capacitor and device automatically begins outputting data. The data properly cleaning the PCB surface. output cycle begins on the first rising edge of SCK and ends on the 24th rising edge. Data is shifted out the SDO 7 pin on each falling edge of SCK. The internally generated 6 serial clock is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. 5 After the 24th rising edge, CS is pulled HIGH and a new SEC) 4 conversion is immediately started. This is useful in appli- (LE P M 3 cations requiring periodic monitoring and ultralow power. SA t Figure 15 shows the average supply current as a function 2 VCC = 5V of capacitance on CS. 1 VCC = 3V It should be noticed that the external capacitor discharge 0 1 10 100 1000 10000 100000 current is kept very small in order to decrease the con- CAPACITANCE ON CS (pF) verter power dissipation in the sleep state. In the autostart 2420 F13 mode the analog voltage on the CS pin cannot be observed Figure 13. CS Capacitance vs f SAMPLE 2.7V TO 5.5V 1µF VCC = 50Hz REJECTION VCC FO = EXTERNAL OSCILLATOR = 60Hz REJECTION LTC2420 0.1V TOV VRCECF VREF SCK –0.12VREF TO 1.12VRVEINF VIN SDO GND CS CEXT VCC CS GND BIT 23 BIT 22 BIT 21 BIT 0 SDO EOC SIG Hi-Z Hi-Z SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION 2420 F12 Figure 12. Internal Serial Clock, Autostart Operation 21

LTC2420 APPLICATIOUS IUFORWATIOU 8 The digital output signals (SDO and SCK in Internal SCK mode of operation) are less of a concern because they are 7 not generally active during the conversion state. 6 ATE (Hz) 5 VCC = 5V VCC = 3V Iimn poordrtearn tto t op mreisneimrviez et hthee L gTrCo2u4n2d0 p’sa tahc icmupraecdya,n icte i sw vheicrhy R 4 E L may appear in series with the input and/or reference signal P M 3 SA and to reduce the current which may flow through this path. 2 The GND pin should be connected to a low resistance 1 ground plane through a minimum length trace. The use of 0 multiple via holes is recommended to further reduce the 0 10 100 1000 10000 100000 connection resistance. The LTC2420’s power supply cur- CAPACITANCE ON CS (pF) 2420 F14 rent flowing through the 0.01W resistance of the common ground pin will develop a 2.5m V offset signal. For a refer- Figure 14. CS Capacitance vs Output Rate ence voltage V = 2.5V, this represents a 1ppm offset REF error. 300 In an alternative configuration, the GND pin of the converter 250 VCC = 5V )S can be the single-point-ground in a single point grounding M R µA200 system. The input signal ground, the reference signal NT ( VCC = 3V ground, the digital drivers ground (usually the digital RE150 R ground) and the power supply ground (the analog ground) U C LY 100 should be connected in a star configuration with the com- P P U mon point located as close to the GND pin as possible. S 50 The power supply current during the conversion state 0 should be kept to a minimum. This is achieved by restrict- 1 10 100 1000 10000 100000 CAPACITANCE ON CS (pF) ing the number of digital signal transitions occurring 2420 F15 during this period. Figure 15. CS Capacitance vs Supply Current While a digital input signal is in the range 0.5V to (V ␣–␣0.5V), the CMOS input receiver draws additional The internal serial clock mode is selected every time the CC current from the power supply. It should be noted that, voltage on the CS pin crosses an internal threshold volt- when any one of the digital input signals (F , CS and SCK age. An internal weak pull-up at the SCK pin is active while O in External SCK mode of operation) is within this range, the CS is discharging; therefore, the internal serial clock LTC2420 power supply current may increase even if the timing mode is automatically selected if SCK is floating. It signal in question is at a valid logic level. For micropower is important to ensure there are no external drivers pulling operation and in order to minimize the potential errors due SCK LOW while CS is discharging. to additional ground pin current, it is recommended to drive all digital input signals to full CMOS levels DIGITAL SIGNAL LEVELS [V < 0.4V and V > (V – 0.4V)]. IL OH CC The LTC2420’s digital interface is easy to use. Its digital Severe ground pin current disturbances can also occur inputs (F , CS and SCK in External SCK mode of operation) O due to the undershoot of fast digital input signals. Under- accept standard TTL/CMOS logic levels and the internal shoot and overshoot can occur because of the imped- hysteresis receivers can tolerate edge rates as slow as ance mismatch at the converter pin when the transition 100m s. However, some considerations are required to take time of an external control signal is less than twice the advantage of exceptional accuracy and low supply current. 22

LTC2420 APPLICATIOUS IUFORWATIOU propagation delay from the driver to LTC2420. For refer- corresponding to a 6.5m s sampling period. Fourteen time ence, on a regular FR-4 board, signal propagation veloc- constants are required each time a capacitor is switched in ity is approximately 183ps/inch for internal traces and order to achieve 1ppm settling accuracy. 170ps/inch for surface traces. Thus, a driver generating Therefore, the equivalent time constant at V and V IN REF a control signal with a minimum transition time of 1ns should be less than 6.5m s/14 = 460ns in order to achieve must be connected to the converter pin through a trace 1ppm accuracy. shorter than 2.5 inches. This problem becomes particu- larly difficult when shared control lines are used and Input Current (V ) IN multiple reflections may occur. The solution is to care- If complete settling occurs on the input, conversion re- fully terminate all transmission lines close to their char- sults will be uneffected by the dynamic input current. If the acteristic impedance. settling is incomplete, it does not degrade the linearity Parallel termination near the LTC2420 pin will eliminate performance of the device. It simply results in an offset/ this problem but will increase the driver power dissipation. full-scale shift, see Figure 17. To simplify the analysis of A series resistor between 27W and 56W placed near the input dynamic current, two separate cases are assumed: driver or near the LTC2420 pin will also eliminate this large capacitance at V (C > 0.01m F) and small capaci- IN IN problem without additional power dissipation. The actual tance at V (C < 0.01m F). IN IN resistor value depends upon the trace impedance and If the total capacitance at V (see Figure 18) is small connection topology. IN (<0.01m F), relatively large external source resistances (up Driving the Input and Reference to 80k for 20pF parasitic capacitance) can be tolerated without any offset/full-scale error. Figures 19 and 20 show The analog input and reference of the typical delta-sigma a family of offset and full-scale error curves for various analog-to-digital converter are applied to a switched ca- small valued input capacitors (C < 0.01m F) as a function IN pacitor network. This network consists of capacitors switch- of input source resistance. ing between the analog input (V ), ground (Pin 4) and the IN reference (V ). The result is small current spikes seen at REF both V and V . A simplified input equivalent circuit is IN REF shown in Figure 16. The key to understanding the effects of this dynamic input current is based on a simple first order RC time constant TUE model. Using the internal oscillator, the LTC2420’s inter- nal switched capacitor network is clocked at 153,600Hz VCC IREF(LEAK) R5SkW VREF IREF(LEAK) 0 VREF/2 VREF VCC VIN 2420 F17 IIN AVERAGE INPUT CURRENT: IIN(LEAK) R5SkW IIN = 0.25(VIN – 0.5 • VREF)fCEQ Figure 17. Offset/Full-Scale Shift VIN IIN(LEAK) 1CpEQF (TYP) RSOURCE RSW VIN 5k INTPUT GND SWITCHING FREQUENCY 2420 F16 SIGNAL CIN C@ P2A0RpF LTC2420 f = 153.6kHz FOR INTERNAL OSCILLATOR (fO = LOGIC LOW OR HIGH) SOURCE f = fEOSC FOR EXTERNAL OSCILLATORS 2420 F18 Figure 16. LTC2420 Equivalent Analog Input Circuit Figure 18. An RC Network at V IN 23

LTC2420 APPLICATIOUS IUFORWATIOU 50 35 VCC = 5V CIN = 22µF 40 TVVARIN E= F= 2 =05 V5°CV 30 CCCIIINNN === 110µ0.1µFµFF m) m) 25 CIN = 0.01µF pp pp CIN = 0.001µF OR ( 30 CIN = 0pF OR ( 20 VCC = 5V RR CIN = 100pF RR VREF = 5V OFFSET E 20 CICNI N= =1 000.001pµFF OFFSET E 1150 VTAIN = = 2 05V°C 10 5 0 0 1 10 100 1k 10k 100k 0 200 400 600 800 1000 RSOURCE (Ω) RSOURCE (Ω) 2420 F19 2420 F21 Figure 19. Offset vs R (Small C) Figure 21. Offset vs R (Large C) SOURCE SOURCE 10 5 0 0 m) m) –5 VCC = 5V FULL-SCALE ERROR (pp––––43210000 TVVVACRIN CE= F = = 2 = 555 V5°VCVCCININ C= I= N1C 10 I=N00 000=ppp 0FFF.01µF FULL-SCALE ERROR (pp –––––1221355000 CCCCCCIIIIIINNNNNN ====== 21100020µ...100µµFµ10FFµ1FµFF VTVARIN E= F= 2 =05 V5°CV –50 –35 1 10 100 1k 10k 100k 0 200 400 600 800 1000 RSOURCE (Ω) RSOURCE (Ω) 2420 F20 2420 F22 Figure 20. Full-Scale Error vs R (Small C) Figure 22. Full-Scale Error vs R (Large C) SOURCE SOURCE For large input capacitor values (C > 0.01m F), the input Reference Current (V ) IN REF spikes are averaged by the capacitor into a DC current. The Similar to the analog input, the reference input has a gain shift becomes a linear function of input source dynamic input current. This current has negligible effect resistance independent of input capacitance, see Figures on the offset. However, the reference current at V = V 21 and 22. The equivalent input impedance is 16.6MW . IN REF is similar to the input current at full-scale. For large values This results in – 150nA of input dynamic current at the of reference capacitance (C > 0.01m F), the full-scale VREF extreme values of V (V = 0V and V = V , when IN IN IN REF error shift is 0.03ppm/W of external reference resistance V = 5V). This corresponds to a 0.3ppm shift in offset REF independent of the capacitance at V , see Figure 23. If and full-scale readings for every 10W of input source REF the capacitance tied to V is small (C < 0.01m F), an REF VREF resistance. input resistance of up to 80k (20pF parasitic capacitance In addition to the input current spikes, the input ESD at V ) may be tolerated, see Figure 24. REF protection diodes have a temperature dependent leakage Unlike the analog input, the integral nonlinearity of the current. This leakage current, nominally 1nA (– 10nA device can be degraded with excessive external RC time max), results in a fixed offset shift of 10m V for a 10k source constants tied to the reference input. If the capacitance at resistance. 24

LTC2420 APPLICATIOUS IUFORWATIOU 60 50 CVREF = 22µF VCC = 5V 50 CCVVRREEFF == 110µµFF 40 VTAR E=F 2=5 5°CV m) CVREF = 0.1µF LL-SCALE ERROR (pp 32410000 VVVTACRIN CE= F = = 2 = 555 V5CC°VCVVVRREEFF == 00..00101µµFF INL ERROR (ppm) 2130000 CVCRCVEVRFRE E=F F =0 = .10 10100µ00FppFF U F 0 –10 CVREF = 0pF –10 –20 0 200 400 600 800 1000 1 10 100 1k 10k 100k RESISTANCE AT VREF (Ω) RESISTANCE AT VREF (Ω) 2420 F23 2420 F25 Figure 23. Full-Scale Error vs R (Large C) Figure 25. INL Error vs R (Small C) VREF VREF 500 10 340000 VVTVACRIN CE= F = = 2 = 555 V5°VCV CVREF = 1000pF 468 CCCCCVVVVVRRRRREEEEEFFFFF ===== 21100µ20..10µµFµ1FFµFF LTAGE 200 CCVRVREFE F= = 0 1.0010µpFF ROR (ppm) 20 CVREF = 0.001µF VVCRCEF = = 5 5VV VO 100 ER –2 TA = 25°C L N 0 I –4 CVREF = 0pF –6 –100 –8 –200 –10 1 10 100 1k 10k 100k 0 200 400 600 800 1000 RESISTANCE AT VREF (Ω) RESISTANCE AT VREF (Ω) 2420 F24 2420 F26 Figure 24. Full-Scale Error vs R (Small C) Figure 26. INL Error vs R (Large C) VREF VREF node V is small (C < 0.01m F), the reference input ANTIALIASING REF VREF can tolerate large external resistances without reduction One of the advantages delta-sigma ADCs offer over con- in INL, see Figure 25. If the external capacitance is large ventional ADCs is on-chip digital filtering. Combined with (C > 0.01m F), the linearity will be degraded by VREF a large oversampling ratio, the LTC2420 significantly 0.015ppm/W independent of capacitance at V , see REF simplifies antialiasing filter requirements. Figure 26. The digital filter provides very high rejection except at In addition to the dynamic reference current, the V ESD REF integer multiples of the modulator sampling frequency protection diodes have a temperature dependent leakage (f ), see Figure 27. The modulator sampling frequency is current. This leakage current, nominally 1nA (– 10nA max), S 256 • F , where F is the notch frequency (typically 50Hz results in a fixed full-scale shift of 10m V for a 10k source O O or 60Hz). The bandwidth of signals not rejected by the resistance. digital filter is narrow (» 0.2%) compared to the bandwidth of the frequencies rejected. 25

LTC2420 APPLICATIOUS IUFORWATIOU 0 800Hz NOTCH (100 SAMPLES/SECOND) –20 60Hz NOTCH (7.5 SAMPLES/SECOND) LTC2420 –40 1 8 B) VCC FO JECTION (d ––6800 234 VVRINEF SSDCOK 765 RE GND CS EXTERNAL 2.048MHz CLOCK SOURCE –100 INTERNAL 153.6kHz OSCILLATOR 2420 F28 –120 Figure 28. Selectable 100 Samples/Second Turbo Mode –140 0 fS/2 fS INPUT FREQUENCY 256 2420 F27 VREF = 5V 12 BITS Figure 27. Sinc4 Filter Rejection pm) 224 p R ( 192 O R As a result of the oversampling ratio (256) and the digital R 160 E 13 BITS D filter, minimal (if any) antialias filtering is required in front TE 128 S U of the LTC2420. If passive RC components are placed in J D 96 A front of the LTC2420 the input dynamic current should be UN 14 BITS L 64 considered (see Input Current section). In cases where TA O T 32 large effective RC time constants are used, an external 16 BITS buffer amplifier may be required to minimize the effects of 0 0 50 100 150 input dynamic current. OUTPUT RATE (SAMPLES/SEC) 2420 F29 The modulator contained within the LTC2420 can handle Figure 29. Total Error vs Output Rate (V = 5V) large-signal level perturbations without saturating. Signal REF levels up to 40% of V do not saturate the analog modu- REF output data rate (ODR) and the frequency applied to the F O lator. These signals are limited by the input ESD protection pin (F ) is: O to 300mV below ground and 300mV above V . CC ODR = F /20480 O Operation at Higher Data Output Rates For output data rates up to 50 samples/second, the total The LTC2420 typically operates with an internal oscillator unadjusted error (TUE) is better than 16 bits, and better of 153.6kHz. This corresponds to a notch frequency of than 12 bits at 100 samples/second. As shown in Figure 60Hz and an output rate of 7.5 samples/second. The 30, for output data rates of 100 samples/second, the TUE internal oscillator is enabled if the F pin is logic LOW is better than 15 bits for V below 2.5V. Figure 31 shows O REF (logic HIGH for a 50Hz notch). It is possible to drive the F an unaveraged total unadjusted error for the LTC2420 op- O pin with an external oscillator for higher data output rates. erating at 100 samples/second with V = 2.5V. Figure 32 REF As shown in Figure 28, an external clock of 2.048MHz shows the same device operating with a 5V reference and applied to the F pin results in a notch frequency of 800Hz an output data rate of 7.5 samples/second. O with a data output rate of 100 samples/second. At 100 samples/second, the LTC2420 can be used to Figure 29 shows the total unadjusted error (Offset Error + capture transient data. This is useful for monitoring set- Full-Scale Error + INL + DNL) as a function of the output tling or auto gain ranging in a system. The LTC2420 can data rate with a 5V reference. The relationship between the monitor signals at an output rate of 100 samples/second. 26

LTC2420 APPLICATIOUS IUFORWATIOU 256 OUTPUT RATE = 100sps 12 BITS m) 224 p p R ( 192 O R R 160 E ED 13 BITS T 128 S U J AD 96 N U 14 BITS L 64 A OT 15 BITS T 32 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V) 2420 F30 Figure 30. Total Error vs V (Output Rate = 100sps) REF 10 6 VCC = 5V VCC = 5V TOTAL UNADJUSTED ERROR (ppm)–––––––213213005005555 VREF = 2.5V TOTAL UNADJUSTED ERROR (ppm) ––––2024684 VREF = 5V –40 –10 0 2.5 0 5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) 2420 F31 2420 F32 Figure 31. Total Unadjusted Error at Figure 32. Total Unadjusted Error at 100 Samples/Second (No Averaging) 7.5 Samples/Second (No Averaging) After acquiring 100 samples/second data the F pin may As shown in Figure 33, the LTC2420 can capture transient O be driven LOW enabling 60Hz rejection to 110dB and the data with 90dB of dynamic range (with a 300mV input P-P highest possible DC accuracy. The no latency architecture signal at 2Hz). The exceptional DC performance of the of the LTC2420 allows consecutive readings (one at 100 LTC2420 enables signals to be digitized independent of a samples/second the next at 7.5 samples/second) without large DC offset. Figures 34a and 34b show the dynamic interaction between the two readings. performance with a 15Hz signal superimposed on a 2V DC level. The same signal with no DC level is shown in Figures 34c and 34d. 27

LTC2420 APPLICATIOUS IUFORWATIOU 0.20 0 TS) 0.15 500ms fIN = 2Hz 21H00zsps OL –20 0V OFFSET V O 0.10 T ALIZED 0.05 DE (dB) –40 M 0 U –60 R T O NI UT (N–0.05 MAG –80 P T–0.10 U O C –100 D–0.15 A –0.20 –120 TIME FREQUENCY (Hz) 2420 F33a 2420 F33b 33a. Digitized Waveform 33b. Output FFT Figure 33. Transient Signal Acquisiton 2.20 0 VIN = 300mVP-P + 2V DC 15Hz S) 100sps T2.15 OL –20 2V OFFSET V O 2.10 T ALIZED 2.05 DE (dB) –40 M2.00 U –60 R T O NI UT (N1.95 MAG –80 P T1.90 U O C –100 D1.85 A 1.80 –120 TIME FREQUENCY (Hz) 2420 F34a 2420 F34b 34a. Digitized Waveform with 2V DC Offset 34b. FFT Waveform with 2V DC Offset 0.20 0 VIN = 300mVP-P + 0V DC 15Hz S) 100sps T 0.15 OL –20 0V OFFSET V O 0.10 T ALIZED 0.05 DE (dB) –40 M 0.00 U –60 R T O NI UT (N–0.05 MAG –80 P T–0.10 U O C –100 D–0.15 A –0.20 –120 TIME FREQUENCY (Hz) 2420 F34c 2420 F34d 34c. Digitized Waveform with No Offset 34d. FFT Waveform with No Offset Figure 34. Using the LTC2420’s High Accuracy Wide Dynamic Range to Digitize a 300mV 15Hz Waveform with a Large DC Offset (V = 5V, V = 5V) P-P CC REF 28

LTC2420 TYPICAL APPLICATIOU S SYNCHRONIZATION OF MULTIPLE LTC2420s Increasing the Output Rate Using Multiple LTC2420s Since the LTC2420’s absolute accuracy (total unadjusted A second application uses multiple LTC2420s to increase error) is 10ppm, applications utilizing multiple matched the effective output rate by 4· , see Figure 36. In this case, ADCs are possible. four LTC2420s are interleaved under the control of sepa- rate CS signals. This increases the effective output rate Simultaneous Sampling with Two LTC2420s from 7.5Hz to 30Hz (up to a maximum of 400Hz). Addi- tionally, the one-shot output spectrum is unfolded allow- One such application is synchronizing multiple LTC2420s, ing further digital signal processing of the conversion see Figure 35. The start of conversion is synchronized to results. SCK and SDO may be common to all four LTC2420s. the rising edge of CS. In order to synchronize multiple The four CS rising edges equally divide one LTC2420 LTC2420s, CS is a common input to all the ADCs. conversion cycle (7.5Hz for 60Hz notch frequency). In To prevent the converters from autostarting a new con- order to synchronize the start of conversion to CS, 23 or version at the end of data output read, 23 or fewer SCK less SCK clock pulses must be applied to each ADC. clock signals are applied to the LTC2420 instead of 24 (the 24th falling edge would start a conversion). The exact Both the synchronous and 4· output rate applications use timing and frequency for the SCK signal is not critical the external serial clock and single cycle operation with since it is only shifting out the data. In this case, two reduced data output length (see Serial Interface Timing LTC2420’s simultaneously start and end their conversion Modes section and Figure 7). An external oscillator clock cycles under the external control of CS. is applied commonly to the F pin of each LTC2420 in O order to synchronize the sampling times. Both circuits may be extended to include more LTC2420s. SCK2 SCK1 EXTERNAL OSCILLATOR (153,600HZ) LTC2420 LTC2420 #1 #2 VCC FO VCC FO µCONTROLLER VREF SCK VREF SCK VIN SDO VIN SDO GND CS GND CS CS SDO1 SDO2 VREF (0.1V TO VCC) CS SCK1 23 OR LESS CLOCK CYCLES SCK2 23 OR LESS CLOCK CYCLES SDO1 SDO2 2420 F35 Figure 35. Synchronous Conversion—Extendable 29

LTC2420 TYPICAL APPLICATIOU S VREF (0.1V TO VCC) EXTERNAL OSCILLATOR (153,600HZ) LTC2420 LTC2420 LTC2420 LTC2420 #1 #2 #3 #4 VCC FO VCC FO VCC FO VCC FO VREF SCK VREF SCK VREF SCK VREF SCK VIN SDO VIN SDO VIN SDO VIN SDO GND CS GND CS GND CS GND CS µCONTROLLER SCK SDO CS1 CS2 CS3 CS4 CS1 CS2 CS3 CS4 23 OR LESS SCK CLOCK PULSES SDO 2420 F36 Figure 36. 4· Output Rate LTC2420 System 30

LTC2420 TYPICAL APPLICATIOU S Single-Chip Instrumentation Amplifier reduces the magnitude of averaged noise by 30% and for the LTC2420 improves resolution by 0.5 bit without compromising linearity. Resistor R2 performs two functions: it isolates The circuit in Figure 37 is a simple solution for processing C1 from the LTC2420’s input and limits the LTC2420’s differential signals in pressure transducer, weigh scale or input current should its input voltage drop below –300mV strain gauge applications that can operate on a supply or swing above V + 300mV. voltage range of – 5V to – 15V. The circuit uses an LT®1920 CC single-chip instrumentation amplifier to perform a differ- The LT1920 is the choice for applications where low cost ential to single-ended conversion. The amplifier’s output is important. For applications where more precision is voltage is applied to the LTC2420’s input and converted to required, the LT1167 is a pin-to-pin alternative choice with a digital value with an overall accuracy exceeding 17 bits a lower offset voltage, lower input bias current and higher (0.0008%). Key circuit performance results are shown in gain accuracy than the LT1920. The LT1920’s maximum Table 5. total input-referred offset (V ) is 135m V for a gain of OST 100. At the same gain, the LT1167’s V is 63m V. At gains The practical gain range for this topology as shown is from OST of 10 or 100, the LT1920’s maximum gain error is 0.3% 5 to 100 because the LTC2420’s wide dynamic range and its maximum gain nonlinearity is 30ppm. At the same makes gains below 5 virtually unnecessary, whereas gains gains, the LT1167’s maximum gain error is 0.1% and its up to 100 significantly reduce the input referred noise. maximum gain nonlinearity is 15ppm. Table 6 summa- The optional passive RC lowpass filter between the rizes the performance of Figure 37’s circuit using the amplifier’s output and the LTC2420’s input attenuates LT1167. high frequency noise and its effects. Typically, the filter 5V 0.1µF VREFIN VS+ 0.1µF 1 DIFFEREINNTPIUATL RG** 218 VRIGN+LT19207 6 4 R71Ω* 1R02k* 3 2VINVREVFCCLTC2420 SDCOS 56 CSHERIPIA SLE DLEACTTA OUT 3 VRIGN– 4 0.1µF C1µ1*F GND FO SCK 7 SERIAL CLOCK 2420 F37 VS– † 4 8 † † SINGLE POINT “STAR” GROUND *OPTIONAL—SEE TEXT **RG = 49.4k/(AV – 1): USE 5.49k FOR AV = 10; 499Ω FOR AV = 100 †USE SHORT LEAD LENGTHS Figure 37. The LT1920 is a Simple Solution That Converts a Differential Input to a Ground Referred Single-Ended Signal for the LTC2420 31

LTC2420 TYPICAL APPLICATIOU S Table 5. Typical Performance of the LTC2420 ADC When Used with the LT1920 Instrumentation Amplifiers in Figure 34’s Differential Digitizing Circuit V = – 5V V = – 15V S S PARAMETER A = 10 A = 100 A = 10 A = 100 TOTAL (UNITS) V V V V Differential Input Voltage Range –30 to 400 –3 to 40 –30 to 500 –3 to 50 mV Zero Error –160 –2650 –213 –2625 m V Maximum Input Current 2.0 nA Nonlinearity – 8.2 – 7.4 – 6.5 – 6.1 ppm Noise (Without Averaging) 1.8* 0.25* 1.5* 0.27* m V RMS Noise (Averaged 64 Readings) 0.2* 0.03* 0.19* 0.03* m V RMS Resolution (with Averaged Readings) 21 20.6 21.3 20.5 Bits Overall Accuracy (Uncalibrated) 17.2 17.3 17.5 18.2 Bits Common Mode Rejection Ratio ‡ 120 dB Common Mode Range 2/–1.5** 2.2/–1.7** 11.5/–11** 11.7/–11.2** V *Input referred noise for the respective gain. **Typical values based on single lab tested sample of each amplifier. Table 6. Typical Performance of the LTC2420 ADC When Used with the LT1167 Instrumentation Amplifiers in Figure 34’s Differential Digitizing Circuit V = – 5V V = – 15V S S PARAMETER A = 10 A = 100 A = 10 A = 100 TOTAL (UNITS) V V V V Differential Input Voltage Range –30 to 400 –3 to 40 –30 to 500 –3 to 50 mV Zero Error –94 –1590 –110 –1470 m V Maximum Input Current 0.5 nA Nonlinearity – 4.1 – 4.4 – 4.1 – 3.7 ppm Noise (Without Averaging) 1.4* 0.19* 1.5* 0.18* m V RMS Noise (Averaged 64 Readings) 0.18* 0.02* 0.19* 0.02* m V RMS Resolution (with Averaged Readings) 21.4 21.0 21.3 21.1 Bits Overall Accuracy (Uncalibrated) 18.2 18.1 18.2 19.4 Bits Common Mode Rejection Ratio ‡ 120 dB Common Mode Range 2/–1.5** 2.2/–1.7** 11.5/–11** 11.7/–11.2** V *Input referred noise for the respective gain. **Typical values based on single lab tested sample of each amplifier. 32

LTC2420 TYPICAL APPLICATIOU S Using a Low Power Precision Reference where the noise of the amplifier begins to dominate, the input referred noise is essentially that of the instrumenta- The circuit in Figure 38 shows the connections and by- tion amplifier. The linearity of the instrumentation ampli- passing for an LT1461-2.5 as a 2.5V reference. The fier does, however, degrade at higher gains. As a result, if LT1461 is a bandgap reference capable of 3ppm/(cid:176) C tem- the full linearity of the LTC2420 is desired, gain in the perature stability yet consumes only 45m A of current. The instrumentation amplifier should be limited to less than 1k resistor between the reference and the ADC reduces the 100, possibly requiring averaging multiple samples to transient load changes associated with sampling and extend the resolution below the noise floor. The noise level produces optimal results. This reference will not impact of the LT1167 at gains greater than 100 is on the order of the noise level of the LTC2420 if signals are less than 60% 50nV , although, 1/f noise and temperature effects may full scale, and only marginally increases noise approach- RMS degrade this below 0.1Hz. The introduction of a filter ing full scale. Even lower power references can be used if between the amplifier and the LTC2420 may improve only the lower end of the LTC2420 input range is required. noise levels under some circumstances by reducing noise bandwidth. Note that temperature offset drift effects enve- A Differential to Single-Ended Analog Front End lope detection in the input of the LT1167 if exposed to RFI, Figure 39 shows the LT1167 as a means of sensing thermocouple voltages in connectors, resistors and sol- differential signals. The noise performance of the LT1167 dered junctions can all compromise results, appearing as is such that for gains less than 200, the noise floor of the drift or noise. Turbulent airflow over this circuitry should LTC2420 remains the dominant noise source. At the point be avoided. 1k TO 5V IN OUT LTC2420 0.1µF + 10µF REF LT1461-2.5 16V CER TANT GND 2420 F38 Figure 38. Low Power Reference 5V + 5V 3.5k 10µF · 4 2 + OPTIONAL 1 1 2 6 22Ω 5k 3 RG LT1167 LTC2420 8 3 – 5 1µF 4 –5V 49.4kΩ 2428 F39 AV = RG + 1 RECOMMENDED RG: 500Ω, 0.1% 5ppm/°C Figure 39. A Differential to Single-Ended Analog Front End 33

LTC2420 TYPICAL APPLICATIOU S 2.048MHz Oscillator for 100sps Output Ratio relaxation oscillators using the 74HC14 or similar de- vices. The circuit can be tuned over a 3:1 range with only The oscillator circuit shown in Figure 40 can be used to one resistor and can be gated. The use of transmission drive the F pin, boosting the conversion rate of the O gates could be used to shift the frequency in order to LTC2420 for applications that do not require a notch at provide setable conversion rates. 50Hz or 60Hz. This oscillator is not sensitive to hysteresis voltage of a Schmitt trigger device as are simpler 1k 10k 1k U1-F 47k 12 13 2N3904 HALT 5k 47k 5pF 270pF U1-A U1-B U1-C 1 2 3 4 5 6 10pF U1-E 11 10 3100s0msmpsp,s F, OFO = = 6 21.40.448kHMzHz 9 U1-D 8 TO LTC2420 U1: 74HC14 OR EQUIVALENT FO PIN 2420 F40 Figure 40. 2.048MHz Oscillator for 100sps Output Rate 34

LTC2420 PACKAGE I U FORW ATIOU Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.228 – 0.244 0.150 – 0.157** (5.791 – 6.197) (3.810 – 3.988) 1 2 3 4 0.010 – 0.020 · 45(cid:176) 0.053 – 0.069 (0.254 – 0.508) (1.346 – 1.752) 0.004 – 0.010 0.008 – 0.010 (0.203 – 0.254) 0°– 8° TYP (0.101 – 0.254) 0.016 – 0.050 0.014 – 0.019 0.050 (0.406 – 1.270) (0.355 – 0.483) (1.270) TYP BSC *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE SO8 1298 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 35 However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC2420 TYPICAL APPLICATIOU The circuit shown in Figure 41 enables pseudodifferential In order to measure absolute temperature with a thermo- measurements of several bridge transducers and abso- couple, cold junction compensation must be performed. lute temperature measurement. The LTC1391 is an Channel 6 measures the output of the thermocouple while 8-to-1 analog multiplexer. channel 7 measures the output of the cold junction sensor (diode, thermistor, etc.). This enables digital cold junc- Consecutive readings are performed on each side of the tion compensation of the thermocouple output. The tem- bridge by selecting the appropriate channel on the perature measurement may then be used to compensate LTC1391. Each output is digitized and the results digitally the temperature effects of the bridge transducers. subtracted to obtain the pseudodifferential result. Several bridge transducers may be digitized in this manner. THERMOCOUPLE CH0 VCC VREF VCC CH1 FO LTC1391 THERMISTOR CH2 LTC2420 CH3 OUT VIN SCK CH4 SDO CH5 GND CS CH6 2420 F41 CH7 GND Figure 41. Pseudodifferential Multichannel Bridge Digitizer and Digital Cold Junction Compensation RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1019 Precision Bandgap Voltage Reference, 2.5V, 5V 3ppm/(cid:176) C Drift, 0.05% Max LT1025 Micropower Thermocouple Cold Junction Compensator 0.5(cid:176) C Initial Accuracy, 80m A Supply Current LTC1043 Dual Precision Instrumentation Switched Capacitor Precise Charge, Balanced Switching, Low Power Building Block LTC1050 Precision Chopper Stabilized Op Amp No External Components 5m V Offset, 1.6m V Noise P-P LT1236A-5 Precision Bandgap Voltage Reference, 5V 0.05% Max, 5ppm/(cid:176) C Drift LTC1391 8-Channel Multiplexer Low R : 45W , Low Charge Injection, Serial Interface ON LT1460 Micropower Series Voltage Reference 0.075% Max, 10ppm/(cid:176) C Max Drift, 2.5V, 5V and 10V Versions LTC2400 24-Bit m Power, No Latency SD ADC in SO-8 4ppm INL, 10ppm TUE, 200m A, Pin Compatible with LTC2420 LTC2401/LTC2402 1-/2-Channel, 24-Bit No Latency SD ADCs 24 Bits in MSOP Package LTC2404/LTC2408 4-/8-Channel, 24-Bit No Latency SD ADC 4ppm INL, 10ppm TUE, 200m A LTC2410 24-Bit No Latency DS ADC with Differential Inputs 800nV Noise, Differential Reference, 2.7V to 5.5V Operation LTC2411 24-Bit No Latency DS ADC with Differential Inputs/Reference 1.6m V Noise, Fully Differential, 10-Lead MSOP Package LTC2413 24-Bit No Latency DS ADC Simultaneous 50Hz to 60Hz Rejection 0.16ppm Noise LTC2424/LTC2428 4-/8-Channel 20-Bit No Latency SD ADCs 8ppm INL, 1.2ppm Noise, Fast Mode 36 Linear Technology Corporation 2420f LT/LCG 1000 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)4 32-1900 l FAX: (408) 434-0507 l w ww.linear-tech.com ª LINEAR TECHNOLOGY CORPORATION 2000

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: LTC2420IS8#PBF LTC2420CS8#PBF LTC2420CS8#TR LTC2420CS8#TRPBF LTC2420IS8#TR LTC2420IS8#TRPBF LTC2420IS8 LTC2420CS8