LTC2410 24-Bit No Latency ∆Σ™ ADC with Differential Input and Differential Reference FEATURES DESCRIPTION n Differential Input and Differential Reference with The LTC®2410 is a 2.7V to 5.5V micropower 24-bit dif- GND to V Common Mode Range ferential ∆Σ analog to digital converter with an integrated CC n 2ppm INL, No Missing Codes oscillator, 2ppm INL and 0.16ppm RMS noise. It uses n 2.5ppm Full-Scale Error delta-sigma technology and provides single cycle settling n 0.1ppm Offset time for multiplexed applications. Through a single pin, n 0.16ppm Noise the LTC2410 can be configured for better than 110dB n Single Conversion Settling Time for Multiplexed input differential mode rejection at 50Hz or 60Hz ±2%, or Applications it can be driven by an external oscillator for a user defined n Internal Oscillator—No External Components rejection frequency. The internal oscillator requires no Required external frequency setting components. n 110dB Min, 50Hz or 60Hz Notch Filter The converter accepts any external differential reference n 24-Bit ADC in Narrow SSOP-16 Package voltage from 0.1V to V for flexible ratiometric and re- CC (SO-8 Footprint) mote sensing measurement configurations. The full-scale n Single Supply 2.7V to 5.5V Operation differential input range is from –0.5V to 0.5V . The REF REF n Low Supply Current (200µA) and Auto Shutdown reference common mode voltage, V , and the input REFCM n Fully Differential Version of LTC2400 common mode voltage, V , may be independently set INCM anywhere within the GND to V range of the LTC2410. The CC APPLICATIONS DC common mode input rejection is better than 140dB. n Direct Sensor Digitizer The LTC2410 communicates through a flexible 3-wire n Weight Scales digital interface which is compatible with SPI and MI- n Direct Temperature Measurement CROWIRE protocols. n Gas Analyzers L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and No n Strain-Gauge Transducers Latency ∆Σ is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Instrumentation n Data Acquisition n Industrial Process Control n 6-Digit DVMs TYPICAL APPLICATION 2.7V TO 5.5V VCC 1µF 1µF VCC = INTERNAL OSC/50Hz REJECTION 2 VCC FO 14 = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION 2 3 LTC2410 REF+ VCC 12 SDO 0R.E1VFVEO TRLOET NAVGCCEEC 34 RREEFF+– SCK 13 1I0M0PΩEB DTROAID N1GC0EEk 65 IINN+– LTC2410 13 SCK 3S-PWI IINRTEERFACE 3-WIRE 11 CS AN–A0L.O5VGR IENFP TUOT 0R.5AVNRGEEF 56 IINN+– SDCOS 1121 SPI INTERFACE 4 REF–GND1, 7, 8 FO14 1, 7, 8, 9, 10, 15, 16 9, 10, GND 2410 TA01 15, 16 2410 TA02 2410fa 1 For more information www.linear.com/LTC2410

LTC2410 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) TOP VIEW Supply Voltage (V ) to GND .......................–0.3V to 7V CC Analog Input Pins Voltage GND 1 16 GND to GND ......................................–0.3V to (V + 0.3V) VCC 2 15 GND CC Reference Input Pins Voltage REF+ 3 14 FO REF– 4 13 SCK to GND ......................................–0.3V to (V + 0.3V) CC IN+ 5 12 SDO Digital Input Voltage to GND .........–0.3V to (V + 0.3V) CC IN– 6 11 CS Digital Output Voltage to GND .......–0.3V to (V + 0.3V) CC GND 7 10 GND Operating Temperature Range GND 8 9 GND LTC2410C ...............................................0°C to 70°C GN PACKAGE LTC2410I .............................................–40°C to 85°C 16-LEAD PLASTIC SSOP Storage Temperature Range ..................–65°C to 150°C TJMAX = 125°C, θJA = 110°C/W Lead Temperature (Soldering, 10 sec) ...................300°C ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2410CGN#PBF LTC2410CGN#TRPBF 2410 16-Lead Plastic SSOP 0°C to 70°C LTC2410IGN#PBF LTC2410IGN#TRPBF 2410I 16-Lead Plastic SSOP –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Notes 3, 4) A PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) 0.1V ≤ V ≤ V , –0.5 • V ≤ V ≤ 0.5 • V (Note 5) l 24 Bits REF CC REF IN REF Integral Nonlinearity 5V ≤ V ≤ 5.5V, REF+ = 2.5V, REF– = GND, V = 1.25V (Note 6) 1 ppm of V CC INCM REF 5V ≤ V ≤ 5.5V, REF+ = 5V, REF– = GND, V = 2.5V (Note 6) l 2 14 ppm of V CC INCM REF REF+ = 2.5V, REF– = GND, V = 1.25V (Note 6) 5 ppm of V INCM REF Offset Error 2.5V ≤ REF+ ≤ V , REF– = GND, l 0.5 0.25 µV CC GND ≤ IN+ = IN– ≤ V (Note 14) CC Offset Error Drift 2.5V ≤ REF+ ≤ V , REF– = GND, 10 nV/°C CC GND ≤ IN+ = IN– ≤ V CC Positive Full-Scale Error 2.5V ≤ REF+ ≤ V , REF– = GND, l 2.5 12 ppm of V CC REF IN+ = 0.75REF+, IN– = 0.25 • REF+ Positive Full-Scale Error Drift 2.5V ≤ REF+ ≤ V , REF– = GND, 0.03 ppm of V /°C CC REF IN+ = 0.75REF+, IN– = 0.25 • REF+ Negative Full-Scale Error 2.5V ≤ REF+ ≤ V , REF– = GND, l 2.5 12 ppm of V CC REF IN+ = 0.25 • REF+, IN– = 0.75 • REF+ Negative Full-Scale Error Drift 2.5V ≤ REF+ ≤ V , REF– = GND, 0.03 ppm of V /°C CC REF IN+ = 0.25 • REF+, IN– = 0.75 • REF+ 2410fa 2 For more information www.linear.com/LTC2410

LTC2410 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Notes 3, 4) A PARAMETER CONDITIONS MIN TYP MAX UNITS Total Unadjusted Error 5V ≤ V ≤ 5.5V, REF+ = 2.5V, REF– = GND, V = 1.25V 3 ppm of V CC INCM REF 5V ≤ V ≤ 5.5V, REF+ = 5V, REF– = GND, V = 2.5V 3 ppm of V CC INCM REF REF+ = 2.5V, REF– = GND, V = 1.25V, (Note 6) 4 ppm of V INCM REF Output Noise 5V ≤ V ≤ 5.5V, REF+ = 5V, REF– = GND, 0.8 µV CC RMS GND ≤ IN– = IN+ ≤ V , (Note 13) CC CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Notes 3, 4) A PARAMETER CONDITIONS MIN TYP MAX UNITS Input Common Mode Rejection DC 2.5V ≤ REF+ ≤ V , REF– = GND, l 130 140 dB CC GND ≤ IN– = IN+ ≤ V CC Input Common Mode Rejection 2.5V ≤ REF+ ≤ V , REF– = GND, l 140 dB CC 60Hz ±2% GND ≤ IN– = IN+ ≤ V , (Note 7) CC Input Common Mode Rejection 2.5V ≤ REF+ ≤ V , REF– = GND, l 140 dB CC 50Hz ±2% GND ≤ IN– = IN+ ≤ V , (Note 8) CC Input Normal Mode Rejection (Note 7) l 110 140 dB 60Hz ±2% Input Normal Mode Rejection (Note 8) l 110 140 dB 50Hz ±2% Reference Common Mode 2.5V ≤ REF+ ≤ V , GND ≤ REF– ≤ 2.5V, l 130 140 dB CC Rejection DC V = 2.5V, IN– = IN+ = GND REF Power Supply Rejection, DC REF+ = 2.5V, REF– = GND, IN– = IN+ = GND 120 dB Power Supply Rejection, 60Hz ±2% REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 7) 120 dB Power Supply Rejection, 50Hz ±2% REF+ = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 8) 120 dB ANALOG INPUT AND REFERENCE The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IN+ Absolute/Common Mode IN+ Voltage l GND – 0.3V V + 0.3V V CC IN– Absolute/Common Mode IN– Voltage l GND – 0.3V V + 0.3V V CC V Input Differential Voltage Range l –V /2 V /2 V IN REF REF (IN+ – IN–) REF+ Absolute/Common Mode REF+ Voltage l 0.1 V V CC REF– Absolute/Common Mode REF– Voltage l GND V – 0.1V V CC V Reference Differential Voltage Range l 0.1 V V REF CC (REF+ – REF–) C (IN+) IN+ Sampling Capacitance 18 pF S C (IN–) IN– Sampling Capacitance 18 pF S C (REF+) REF+ Sampling Capacitance 18 pF S C (REF–) REF– Sampling Capacitance 18 pF S I (IN+) IN+ DC Leakage Current CS = V , IN+ = GND l –10 1 10 nA DC_LEAK CC I (IN–) IN– DC Leakage Current CS = V , IN– = GND l –10 1 10 nA DC_LEAK CC I (REF+) REF+ DC Leakage Current CS = V , REF+ = 5V l –10 1 10 nA DC_LEAK CC I (REF–) REF– DC Leakage Current CS = V , REF– = GND l –10 1 10 nA DC_LEAK CC 2410fa 3 For more information www.linear.com/LTC2410

LTC2410 DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V High Level Input Voltage 2.7V ≤ V ≤ 5.5V l 2.5 V IH CC CS, F 2.7V ≤ V ≤ 3.3V 2.0 V O CC V Low Level Input Voltage 4.5V ≤ V ≤ 5.5V l 0.8 V IL CC CS, F 2.7V ≤ V ≤ 5.5V 0.6 V O CC V High Level Input Voltage 2.7V ≤ V ≤ 5.5V (Note 9) l 2.5 V IH CC SCK 2.7V ≤ V ≤ 3.3V (Note 9) 2.0 V CC V Low Level Input Voltage 4.5V ≤ V ≤ 5.5V (Note 9) l 0.8 V IL CC SCK 2.7V ≤ V ≤ 5.5V (Note 9) 0.6 V CC I Digital Input Current 0V ≤ V ≤ V l –10 10 µA IN IN CC CS, F O I Digital Input Current 0V ≤ V ≤ V (Note 9) l –10 10 µA IN IN CC SCK C Digital Input Capacitance 10 pF IN CS, F O C Digital Input Capacitance (Note 9) 10 pF IN SCK V High Level Output Voltage I = –800µA l V – 0.5V V OH O CC SDO V V Low Level Output Voltage I = 1.6mA l 0.4 V OL O SDO V V High Level Output Voltage I = –800µA (Note 10) l V – 0.5V V OH O CC SCK V V Low Level Output Voltage I = 1.6mA (Note 10) l 0.4 V OL O SCK V I Hi-Z Output Leakage l –10 10 µA OZ SDO POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Supply Voltage l 2.7 5.5 V CC I Supply Current CC Conversion Mode CS = 0V (Note 12) l 200 300 µA l Sleep Mode CS = V (Note 12) 20 30 µA CC 2410fa 4 For more information www.linear.com/LTC2410

LTC2410 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f External Oscillator Frequency Range l 2.56 500 kHz EOSC t External Oscillator High Period l 0.25 390 µs HEO t External Oscillator Low Period l 0.25 390 µs LEO t Conversion Time F = 0V l 130.86 133.53 136.20 ms CONV O F = V l 157.03 160.23 163.44 ms O CC External Oscillator (Note 11) l 20510/fEOSC (in kHz) ms f Internal SCK Frequency Internal Oscillator (Note 10) 19.2 kHz ISCK External Oscillator (Notes 10, 11) f /8 kHz EOSC D Internal SCK Duty Cycle (Note 10) l 45 55 % ISCK f External SCK Frequency Range (Note 9) l 2000 kHz ESCK t External SCK Low Period (Note 9) l 250 ns LESCK t External SCK High Period (Note 9) l 250 ns HESCK t Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 10, 12) l 1.64 1.67 1.70 ms DOUT_ISCK External Oscillator (Notes 10, 11) l 256/fEOSC (in kHz) ms t External SCK 32-Bit Data Output Time (Note 9) l 32/f (in kHz) ms DOUT_ESCK ESCK t1 CS ↓ to SDO Low Z l 0 200 ns t2 CS ↑ to SDO High Z l 0 200 ns t3 CS ↓ to SCK ↓ (Note 10) l 0 200 ns t4 CS ↓ to SCK ↑ (Note 9) l 50 ns tKQMAX SCK ↓ to SDO Valid l 220 ns tKQMIN SDO Hold After SCK ↓ (Note 5) l 15 ns t5 SCK Set-Up Before CS ↓ l 50 ns t6 SCK Hold After CS ↓ l 50 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 8: F = V (internal oscillator) or f = 128000Hz ±2% (external O CC EOSC may cause permanent damage to the device. Exposure to any Absolute oscillator). Maximum Rating condition for extended periods may affect device Note 9: The converter is in external SCK mode of operation such that the reliability and lifetime. SCK pin is used as digital input. The frequency of the clock signal driving Note 2: All voltage values are with respect to GND. SCK during the data output is f and is expressed in kHz. ESCK Note 3: V = 2.7 to 5.5V unless otherwise specified. Note 10: The converter is in internal SCK mode of operation such that the CC V = REF+ – REF–, V = (REF+ + REF–)/2; SCK pin is used as digital output. In this mode of operation the SCK pin REF REFCM V = IN+ – IN–, V = (IN+ + IN–)/2. has a total equivalent load capacitance C = 20pF. IN INCM LOAD Note 4: F pin tied to GND or to V or to external conversion clock source Note 11: The external oscillator is connected to the F pin. The external O CC O with f = 153600Hz unless otherwise specified. oscillator frequency, f , is expressed in kHz. EOSC EOSC Note 5: Guaranteed by design, not subject to test. Note 12: The converter uses the internal oscillator. Note 6: Integral nonlinearity is defined as the deviation of a code from a FO = 0V or FO = VCC. straight line passing through the actual endpoints of the transfer curve. Note 13: The output noise includes the contribution of the internal The deviation is measured from the center of the quantization band. calibration operations. Note 7: F = 0V (internal oscillator) or f = 153600Hz ±2% (external Note 14: Guaranteed by design and test correlation. O EOSC oscillator). 2410fa 5 For more information www.linear.com/LTC2410

vs Temperature LTC2410 TYPICAL PERFORMANCE CHARACTERISTICS Total Unadjusted Error vs Total Unadjusted Error vs Total Unadjusted Error vs Temperature (V = 5V, Temperature (V = 5V, Temperature (V = 2.7V, CC CC CC V = 5V) V = 2.5V) V = 2.5V) REF REF REF 1.5 1.5 10 VRCECF += =5 V2.5V 8 1.0 1.0 REF– = GND 6 VREF = 2.5V V)REF 0.5 V)REF0.5 VFOIN =C MG N=D 1.25V V)REF 42 TA = 90°C F F F m O 0 m O 0 TA = 90°C m O 0 TA = 25°C p p p TUE (p ––01..50 RVVVRFOCRIEEN CEFF=CF +– =M G = == 5N = 5V5GD V2VN.5DV TATT AA= ==– 492505°°°CCC TUE (p––01..50 TTAA == 2–54°5C°C TUE (p ––––2468 RVVVRCRIEENCEFFCF +–=M = == 2 = 2.2G 7.1.5NV5.V2DV5V TA = –45°C FO = GND –1.5 –1.5 –10 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –1 –0.5 0 0.5 1 –1 –0.5 0 0.5 1 VIN (V) VIN (V) VIN (V) 2410 G01 2410 G02 2410 G03 Integral Nonlinearity vs Integral Nonlinearity vs Integral Nonlinearity vs Temperature (V = 5V, Temperature (V = 5V, Temperature (V = 2.7V, CC CC CC V = 5V) V = 2.5V) V = 2.5V) REF REF REF 1.5 1.5 10 m OF V)REF 10..05 RVVVRFOCRIEEN CEFF=CF +– =M G = == 5N = 5V5GD V2VN.5DV TAT =A =2 5–°4C5°C m OF V)REF10..05 TTATA =A = –= 2 49550°°C°CC m OF V)REF 8642 RVRCEECFF +–= ==2 .2G7.NV5DV VVFORIN E=CF M G= N =2D .15.V25V p p p R (p 0 TA = 90°C R (p 0 R (p 0 INL ERRO –0.5 INL ERRO–0.5 RVVRCREECEFFF +–= = ==5 2V2G..5N5VDV INL ERRO –––246 TTAA == 2950°°CC –1.0 –1.0 VINCM = 1.25V TA = –45°C FO = GND –8 –1.5 –1.5 –10 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 –1 –0.5 0 0.5 1 –1 –0.5 0 0.5 1 VIN (V) VIN (V) VIN (V) 2410 G04 2410 G05 2410 G06 Noise Histogram (Output Rate = Noise Histogram (Output Rate = Noise Histogram (Output Rate = 7.5Hz, V = 5V, V = 5V) 22.5Hz, V = 5V, V = 5V) 7.5Hz, V = 5V, V = 2.5V) CC REF CC REF CC REF 12 12 12 10,000 CONSECUTIVE GAUSSIAN 10,000 CONSECUTIVE GAUSSIAN 10,000 CONSECUTIVE GAUSSIAN READINGS DISTRIBUTION READINGS DISTRIBUTION READINGS DISTRIBUTION 10 VCC = 5V m = 0.105ppm 10 VCC = 5V m = 0.067ppm 10 VCC = 5V m = 0.033ppm %) VREF = 5V σ = 0.153ppm %) VREF = 5V σ = 0.151ppm %) VREF = 2.5V σ = 0.293ppm GS ( 8 VRIENF =+ 0=V 5V GS ( 8 VRIENF =+ 0=V 5V GS ( 8 VRIENF =+ 0=V 2.5V DIN REF– = GND DIN REF– = GND DIN REF– = GND F REA 6 IINN+– == 22..55VV F REA 6 IINN+– == 22..55VV F REA 6 IINN+– == 11..2255VV R O FO = GND R O FO = 460800Hz R O FO = GND BE 4 TA = 25°C BE 4 TA = 25°C BE 4 TA = 25°C M M M U U U N N N 2 2 2 0 0 0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 –1.6 –0.8 0 0.8 1.6 OUTPUT CODE (ppm OF VREF) OUTPUT CODE (ppm OF VREF) OUTPUT CODE (ppm OF VREF) 2410 G07 2410 G08 2410 G10 2410fa 6 For more information www.linear.com/LTC2410

LTC2410 TYPICAL PERFORMANCE CHARACTERISTICS Noise Histogram (Output Rate = Noise Histogram (Output Rate = Noise Histogram (Output Rate = 22.5Hz, V = 5V, V = 2.5V) 7.5Hz, V = 2.7V, V = 2.5V) 22.5Hz, V = 2.7V, V = 2.5V) CC REF CC REF CC REF 12 12 12 10,000 CONSECUTIVE GAUSSIAN 10,000 CONSECUTIVE GAUSSIAN 10,000 CONSECUTIVE GAUSSIAN READINGS DISTRIBUTION READINGS DISTRIBUTION READINGS DISTRIBUTION 10 VCC = 5V m = 0.014ppm 10 VCC = 2.7V m = 0.079ppm 10 VCC = 2.7V m = 0.177ppm %) VREF = 2.5V σ = 0.292ppm %) VREF = 2.5V σ = 0.298ppm %) VREF = 2.5V σ = 0.297ppm GS ( 8 VRIENF =+ 0=V 2.5V GS ( 8 VRIENF =+ 0=V 2.5V GS ( 8 VRIENF =+ 0=V 2.5V DIN REF– = GND DIN REF– = GND DIN REF– = GND F REA 6 IINN+– == 11..2255VV F REA 6 IINN+– == 11..2255VV F REA 6 IINN+– == 11..2255VV R O FO = 460800Hz R O FO = GND R O FO = 460800Hz BE 4 TA = 25°C BE 4 TA = 25°C BE 4 TA = 25°C M M M U U U N N N 2 2 2 0 0 0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 OUTPUT CODE (ppm OF VREF) OUTPUT CODE (ppm OF VREF) OUTPUT CODE (ppm OF VREF) 2410 G11 2410 G13 2410 G14 Long-Term Noise Histogram (Time = 60 Hrs, V = 5V, Consectutive ADC Readings vs RMS Noise vs Input Differential CC V = 5V) Time Voltage REF 12 1.0 0.5 GAUSSIAN DISTRIBUTION m = 0.101837ppm 0.8 VCC = 5V NUMBER OF READINGS (%) 108642 RIIFTVARVRσVNNOADCRI EEEN=+– CEFAFC== F =0==D+– = GC2 . = I01==2255ONN V5 ..5°V5G55NGD4CVVVVNSS5ED1C5pUpTmIVE ADC READING (ppm OF V)REF ––––0000000.......64202468 VVFVOCRIN CE= F = = G = 05N V5VDV RTRAEE FF=+– 2 ==5 °5GCVND IINN+– == 22..55VV RMS NOISE (ppm OF V)REF0000....4321 RVTRVFOARIEEN EFF==CF+– M G2 === 5N = 5°5GD CV2VN.5DV 0 –1.0 0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 0 5 10 15 20 25 30 35 40 45 50 55 60 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2 2.5 OUTPUT CODE (ppm OF VREF) TIME (HOURS) INPUT DIFFERENTIAL VOLTAGE (V) 2410 G16 2410 G17 2410 G18 RMS Noise vs V RMS Noise vs Temperature (T ) RMS Noise vs V INCM A CC 885205 885205 VRCECF += =5 V5V 885205 RREEFF+– == 2G.N5DV 800 800 RIINNE+–F ==– =22 ..G55VVND 800 VIINNR+–E F== =GG 2NN.DD5V E (nV) 775 VCC = 5V E (nV) 775 VFOIN = = G 0NVD E (nV) 775 FTOA == G25N°DC NOIS 750 RREEFF+– == 5GVND NOIS 750 NOIS 750 MS 725 VREF = 5V MS 725 MS 725 R IN+ = VINCM R R 700 IN– = VINCM 700 700 VIN = 0V 675 FO = GND 675 675 TA = 25°C 650 650 650 –0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 –50 –25 0 25 50 75 100 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VINCM (V) TEMPERATURE (°C) VCC (V) 2410 G19 2410 G20 2410 G21 2410fa 7 For more information www.linear.com/LTC2410

LTC2410 TYPICAL PERFORMANCE CHARACTERISTICS RMS Noise vs V Offset Error vs V Offset Error vs Temperature (T ) REF INCM A 850 0.3 0.3 VCC = 5V 825 REF– = GND 800 IINN+– == GGNNDD V)REF 0.2 V)REF 0.2 RMS NOISE (nV) 777767520750505 FTOA == G25N°DC OFFSET ERROR (ppm OF ––000...1012 RVIVIVFRNNOCRIEEN+– CEFF= F ===+– = G = 0==VV5N V 5IIV5GNNDVVCCNMMD OFFSET ERROR (ppm OF ––000...1012 RIIVVRNNCIEEN+–CFF ===+–= 0==225V ..V5G55VVVND TA = 25°C FO = GND 650 –0.3 –0.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 –0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 –50 –25 0 25 50 75 100 VREF (V) VINCM (V) TEMPERATURE (°C) 2410 G22 2410 G23 2410 G24 +Full-Scale Error vs Offset Error vs V Offset Error vs V Temperature (T ) CC REF A 0.3 0.3 3 )REF 0.2 )REF 0.2 F V)REF 2 V V O m OF 0.1 m OF 0.1 ppm 1 pp pp R ( OR ( 0 REF+ = 2.5V OR ( 0 RRO 0 RR REF– = GND RR VCC = 5V E E VCC = 5V OFFSET E ––00..12 VIFINNOR+– E= F== G =GGN 2NND.DD5V OFFSET E ––00..12 IIFRNNOE+– F= ==– G =GGN NNGDDDND FULL-SCAL ––12 RIIRNNEE+–FF ==+– ==2G .N5G5DVVND TA = 25°C TA = 25°C + FO = GND –0.3 –0.3 –3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 –45 –30 –15 0 15 30 45 60 75 90 VCC (V) VREF (V) TEMPERATURE (°C) 2410 G25 2410 G26 2410 G27 –Full-Scale Error vs +Full-Scale Error vs V –Full-Scale Error vs V Temperature (T ) CC REF A 3 3 3 VCC = 5V R (ppm OF V)REF 21 R (ppm OF V)REF 21 R (ppm OF V)REF 21 RIIFRNNOEE+– FF= ==+– G ==G2N .N5G5DDVVND RO 0 RO 0 RO 0 +FULL-SCALE ER ––12 RVIFTIRNNOAREE+– EFF== F==+– G2 ===1G5N .2°N2G2DC.D.55N5VVDV +FULL-SCALE ER ––12 IFTVRIRNNOACEE+– CFF== ==+– =G2 ==0G55N .°NVVG5DCD RN(cid:127)E DRFEF+ –FULL-SCALE ER ––12 –3 –3 –3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 –45 –30 –15 0 15 30 45 60 75 90 VCC (V) VREF (V) TEMPERATURE (°C) 2410 G28 2410 G29 2410 G30 2410fa 8 For more information www.linear.com/LTC2410

LTC2410 TYPICAL PERFORMANCE CHARACTERISTICS –Full-Scale Error vs V –Full-Scale Error vs V PSRR vs Frequency at V CC REF CC 3 3 0 REF+ = 2.5V VCC = 5V VCC = 4.1VDC ± 1.4V ALE ERROR (ppm OF V)REF –2101 RVIFTINNOARE+– EF== F==– G2 ==G15N .2°NG2DC.D55NVVD ALE ERROR (ppm OF V)REF –2101 IITRFRNNOAEE+– FF== ==+– G2 ==G05N .°NVG5DCD RN(cid:127)E DRFEF+ REJECTION (dB) ––––24680000 RIIFTRNNOAEE+– FF== ==+– G2 ==GG5N °NN2GDCDD.N5DV SC SC –100 L- L- L L U –2 U –2 F F –120 – – –3 –3 –140 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0.01 0.1 1 10 100 VCC (V) VREF (V) FREQUENCY AT VCC (Hz) 2410 G31 2410 G32 2410 G33 PSRR vs Frequency at V PSRR vs Frequency at V PSRR vs Frequency at V CC CC CC 0 0 0 –20 VRCECF += =4 .21.V5DVC ± 1.4V –20 RREEFF+– == 2G.N5DV –10 VRCECF += =4 .21.V5DVC 0.7V REF– = GND IN+ = GND –20 REF– = GND IN+ = GND IN– = GND IN+ = GND TION (dB) ––4600 IFTNOA– == = G2 G5N°NDCD TION (dB) ––4600 FTOA == G25N°DC TION (dB) –––345000 IFTNOA– == = G2 G5N°NDCD JEC –80 JEC –80 JEC –60 E E E R R R –100 –100 –70 –80 –120 –120 –90 –140 –140 –100 0 30 60 90 120 150 180 210 240 1 10 100 1k 10k 100k 1M 7600 7620 7640 7660 7680 7700 7720 7740 FREQUENCY AT VCC (Hz) FREQUENCY AT VCC (Hz) FREQUENCY AT VCC (Hz) 2410 G34 2410 G35 2410 G36 Conversion Current vs Conversion Current vs Temperature (T ) Output Data Rate Sleep Current vs Temperature (T ) A A 220 1100 23 FO = GND VCC = 5V FO = GND CS = GND 1000 REF+ = 5V CS = VCC Y CURRENT (µA)221109000 SSCDKO == NNCC VVCCCC == 54..51VV Y CURRENT (µA)987650000000000 RIITFCSSNNOASCDE+– F KO=== –== =E2= G =GG X5 NNN °NNTGCDCCEDDNRDNAL OSC Y CURRENT (µA) 22212109 SSCDKO == V NNCCCC = 4.1V VCC = 5.5V L L L UPP180 UPP400 UPP 18 VCC = 2.7V S S S VCC = 2.7V 300 170 17 200 160 100 16 –45 –30 –15 0 15 30 45 60 75 90 0 5 10 15 20 25 –45 –30 –15 0 15 30 45 60 75 90 TEMPERATURE (°C) 2410 G37 OUTPUT DATA RATE (READINGS/SEC)2410 G38 TEMPERATURE (°C) 2410 G39 2410fa 9 For more information www.linear.com/LTC2410

LTC2410 PIN FUNCTIONS GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple SDO (Pin 12): Three-State Digital Output. During the Data ground pins internally connected for optimum ground Output period, this pin is used as serial data output. When current flow and V decoupling. Connect each one of the chip select CS is HIGH (CS = V ) the SDO pin is in a CC CC these pins to a ground plane through a low impedance high impedance state. During the Conversion and Sleep connection. All seven pins must be connected to ground periods, this pin is used as the conversion status output. for proper operation. The conversion status can be observed by pulling CS LOW. V (Pin 2): Positive Supply Voltage. Bypass to GND SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal CC (Pin 1) with a 10µF tantalum capacitor in parallel with Serial Clock Operation mode, SCK is used as digital output 0.1µF ceramic capacitor as close to the part as possible. for the internal serial interface clock during the Data Output period. In External Serial Clock Operation mode, SCK is REF+ (Pin 3), REF– (Pin 4): Differential Reference Input. used as digital input for the external serial interface clock The voltage on these pins can have any value between during the Data Output period. A weak internal pull-up is GND and V as long as the reference positive input, REF+, CC automatically activated in Internal Serial Clock Operation is maintained more positive than the reference negative mode. The Serial Clock Operation mode is determined by input, REF–, by at least 0.1V. the logic level applied to the SCK pin at power up or during IN+ (Pin 5), IN– (Pin 6): Differential Analog Input. The the most recent falling edge of CS. voltage on these pins can have any value between F (Pin 14): Frequency Control Pin. Digital input that GND – 0.3V and V + 0.3V. Within these limits the con- O CC controls the ADC’s notch frequencies and conversion verter bipolar input range (V = IN+ – IN–) extends from IN time. When the F pin is connected to V (F = V ), the –0.5 • (V ) to 0.5 • (V ). Outside this input range the O CC O CC REF REF converter uses its internal oscillator and the digital filter converter produces unique overrange and underrange first null is located at 50Hz. When the F pin is connected output codes. O to GND (F = OV), the converter uses its internal oscillator O CS (Pin 11): Active LOW Digital Input. A LOW on this pin and the digital filter first null is located at 60Hz. When F is O enables the SDO digital output and wakes up the ADC. driven by an external clock signal with a frequency f , EOSC Following each conversion the ADC automatically enters the converter uses this signal as its system clock and the the Sleep mode and remains in this low power state as digital filter first null is located at a frequency f /2560. EOSC long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. 2410fa 10 For more information www.linear.com/LTC2410

LTC2410 FUNCTIONAL BLOCK DIAGRAM INTERNAL VCC OSCILLATOR GND AUTOCALIBRATION AND CONTROL FO (INT/EXT) IN+ + IN– –∫ ∫ ∫ SDO ∑ SERIAL ADC SCK INTERFACE REF+ CS REF– DECIMATING FIR – + DAC 2410 FD Figure 1. Functional Block Diagram TEST CIRCUIT VCC 1.69k SDO SDO 1.69k CLOAD = 20pF CLOAD = 20pF 2410 TA03 2410 TA04 Hi-Z TO VOH Hi-Z TO VOL VOL TO VOH VOH TO VOL VOH TO Hi-Z VOL TO Hi-Z 2410fa 11 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION CONVERTER OPERATION Through timing control of the CS and SCK pins, the LTC2410 offers several flexible modes of operation Converter Operation Cycle (internal or external SCK and free-running conversion modes). These various modes do not require programming The LTC2410 is a low power, delta-sigma analog-to-digital configuration registers; moreover, they do not disturb the converter with an easy to use 3-wire serial interface (see cyclic operation described above. These modes of opera- Figure 1). Its operation is made up of three states. The tion are described in detail in the Serial Interface Timing converter operating cycle begins with the conversion, Modes section. followed by the low power sleep state and ends with the data output (see Figure 2). The 3-wire interface consists Conversion Clock of serial data output (SDO), serial clock (SCK) and chip select (CS). A major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital filter Initially, the LTC2410 performs a conversion. Once the (commonly implemented as a Sinc or Comb filter). For conversion is complete, the device enters the sleep state. high resolution, low frequency applications, this filter is While in this sleep state, power consumption is reduced typically designed to reject line frequencies of 50 or 60Hz by an order of magnitude. The part remains in the sleep plus their harmonics. The filter rejection performance is state as long as CS is HIGH. The conversion result is held directly related to the accuracy of the converter system indefinitely in a static shift register while the converter is clock. The LTC2410 incorporates a highly accurate on-chip in the sleep state. oscillator. This eliminates the need for external frequency Once CS is pulled LOW, the device begins outputting the setting components such as crystals or oscillators. Clocked conversion result. There is no latency in the conversion by the on-chip oscillator, the LTC2410 achieves a mini- result. The data output corresponds to the conversion mum of 110dB rejection at the line frequency (50Hz or just performed. This result is shifted out on the serial data 60Hz ±2%). out pin (SDO) under the control of the serial clock (SCK). Data is updated on the falling edge of SCK allowing the Ease of Use user to reliably latch data on the rising edge of SCK (see The LTC2410 data output has no latency, filter settling Figure 3). The data output state is concluded once 32 bits delay or redundant data associated with the conversion are read out of the ADC or when CS is brought HIGH. The cycle. There is a one-to-one correspondence between the device automatically initiates a new conversion and the conversion and the output data. Therefore, multiplexing cycle repeats. multiple analog voltages is easy. The LTC2410 performs offset and full-scale calibrations CONVERT every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation described SLEEP above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. FALSE CS = LOW AND Power-Up Sequence SCK The LTC2410 automatically enters an internal reset state TRUE when the power supply voltage V drops below approxi- CC DATA OUTPUT mately 2.2V. This feature guarantees the integrity of the 2410 F02 conversion result and of the serial interface mode selec- Figure 2. LTC2410 State Transition Diagram tion. (See the 2-wire I/O sections in the Serial Interface Timing Modes section.) 2410fa 12 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION When the V voltage rises above this critical threshold, the Input signals applied to IN+ and IN– pins may extend by CC converter creates an internal power-on-reset (POR) signal 300mV below ground and above V . In order to limit any CC with a duration of approximately 0.5ms. The POR signal fault current, resistors of up to 5k may be added in series clears all internal registers. Following the POR signal, the with the IN+ and IN– pins without affecting the perfor- LTC2410 starts a normal conversion cycle and follows the mance of the device. In the physical layout, it is important succession of states described above. The first conversion to maintain the parasitic capacitance of the connection result following POR is accurate within the specifications between these series resistors and the corresponding of the device if the power supply voltage is restored within pins as low as possible; therefore, the resistors should the operating range (2.7V to 5.5V) before the end of the be located as close as practical to the pins. The effect of POR time interval. the series resistance on the converter accuracy can be evaluated from the curves presented in the Input Current/ Reference Voltage Range Reference Current sections. In addition, series resistors will introduce a temperature dependent offset error due This converter accepts a truly differential external reference to the input leakage current. A 1nA input leakage current voltage. The absolute/common mode voltage specification for the REF+ and REF– pins covers the entire range from will develop a 1ppm offset error on a 5k resistor if VREF = GND to V . For correct converter operation, the REF+ pin 5V. This error has a very strong temperature dependency. CC must always be more positive than the REF– pin. Output Data Format The LTC2410 can accept a differential reference voltage The LTC2410 serial output data stream is 32 bits long. from 0.1V to V . The converter output noise is determined CC The first 3 bits represent status information indicating by the thermal noise of the front-end circuits, and as such, the sign and conversion state. The next 24 bits are the its value in nanovolts is nearly constant with reference conversion result, MSB first. The remaining 5 bits are voltage. A decrease in reference voltage will not signifi- sub LSBs beyond the 24-bit level that may be included cantly improve the converter’s effective resolution. On the in averaging or discarded without loss of resolution. The other hand, a reduced reference voltage will improve the third and fourth bit together are also used to indicate an converter’s overall INL performance. A reduced reference underrange condition (the differential input voltage is voltage will also improve the converter performance when below –FS) or an overrange condition (the differential operated with an external conversion clock (external F O input voltage is above +FS). signal) at substantially higher output data rates (see the Output Data Rate section). Bit 31 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the Input Voltage Range conversion and sleep states whenever the CS pin is LOW. This bit is HIGH during the conversion and goes LOW The analog input is truly differential with an absolute/ common mode range for the IN+ and IN– input pins when the conversion is complete. extending from GND – 0.3V to VCC + 0.3V. Outside Bit 30 (second output bit) is a dummy bit (DMY) and is these limits, the ESD protection devices begin to turn always LOW. on and the errors due to input leakage current increase Bit 29 (third output bit) is the conversion result sign rapidly. Within these limits, the LTC2410 converts the indicator (SIG). If V is >0, this bit is HIGH. If V is <0, bipolar differential input signal, V = IN+ – IN–, from IN IN IN this bit is LOW. –FS = –0.5 • V to +FS = 0.5 • V where V = REF REF REF REF+ – REF–. Outside this range, the converter indicates Bit 28 (fourth output bit) is the most significant bit (MSB) of the overrange or the underrange condition using distinct the result. This bit in conjunction with Bit 29 also provides output codes. the underrange or overrange indication. If both Bit 29 and Bit 28 are HIGH, the differential input voltage is above +FS. 2410fa 13 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION If both Bit 29 and Bit 28 are LOW, the differential input Data is shifted out of the SDO pin under control of the voltage is below –FS. serial clock (SCK), see Figure 3. Whenever CS is HIGH, SDO remains high impedance and any externally gener- The function of these bits is summarized in Table 1. ated SCK clock pulses are ignored by the internal data Table 1. LTC2410 Status Bits out shift register. Bit 31 Bit 30 Bit 29 Bit 28 In order to shift the conversion result out of the device, Input Range EOC DMY SIG MSB CS must first be driven LOW. EOC is seen at the SDO pin V ≥ 0.5 • V 0 0 1 1 IN REF of the device once CS is pulled LOW. EOC changes real 0V ≤ V < 0.5 • V 0 0 1 0 IN REF time from HIGH to LOW at the completion of a conversion. –0.5 • V ≤ V < 0V 0 0 0 1 REF IN This signal may be used as an interrupt for an external V < –0.5 • V 0 0 0 0 IN REF microcontroller. Bit 31 (EOC) can be captured on the first rising edge of SCK. Bit 30 is shifted out of the device on Bits 28-5 are the 24-bit conversion result MSB first. the first falling edge of SCK. The final data bit (Bit 0) is Bit 5 is the least significant bit (LSB). shifted out on the falling edge of the 31st SCK and may Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 be latched on the rising edge of the 32nd SCK pulse. On may be included in averaging or discarded without loss the falling edge of the 32nd SCK pulse, SDO goes HIGH of resolution. indicating the initiation of a new conversion cycle. This bit serves as EOC (Bit 31) for the next conversion cycle. Table 2 summarizes the output data format. CS BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 5 BIT 0 SDO EOC “0” SIG MSB LSB24 Hi-Z SCK 1 2 3 4 5 26 27 32 SLEEP DATA OUTPUT CONVERSION 2410 F03 Figure 3. Output Data Timing Table 2. LTC2410 Output Data Format Differential Input Voltage Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 … Bit 0 V * EOC DMY SIG MSB IN V * ≥ 0.5 • V ** 0 0 1 1 0 0 0 … 0 IN REF 0.5 • V ** – 1LSB 0 0 1 0 1 1 1 … 1 REF 0.25 • V ** 0 0 1 0 1 0 0 … 0 REF 0.25 • V ** – 1LSB 0 0 1 0 0 1 1 … 1 REF 0 0 0 1 0 0 0 0 … 0 –1LSB 0 0 0 1 1 1 1 … 1 –0.25 • V ** 0 0 0 1 1 0 0 … 0 REF –0.25 • V ** – 1LSB 0 0 0 1 0 1 1 … 1 REF –0.5 • V ** 0 0 0 1 0 0 0 … 0 REF V * < –0.5 • V ** 0 0 0 0 1 1 1 … 1 IN REF *The differential Input voltage V = IN+ – IN–. IN **The differential reference voltage V = REF+ – REF–. REF 2410fa 14 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION As long as the voltage on the IN+ and IN– pins is main- –80 tained within the –0.3V to (V + 0.3V) absolute maximum –85 CC operating range, a conversion result is generated for any dB) –90 N ( –95 differential input voltage V from –FS = –0.5 • V to O IN REF TI –100 C +FS = 0.5 • VREF. For differential input voltages greater EJE –105 than +FS, the conversion result is clamped to the value E R –110 D O –115 corresponding to the +FS + 1LSB. For differential input M L –120 A voltages below –FS, the conversion result is clamped to RM –125 O the value corresponding to –FS – 1LSB. N –130 –135 –140 Frequency Rejection Selection (FO) –12 –8 –4 0 4 8 12 DIFFERENTIAL INPUT SIGNAL FREQUENCY The LTC2410 internal oscillator provides better than DEVIATION FROM NOTCH FREQUENCY fEOSC/2560(%) 2410 F04 110dB normal mode rejection at the line frequency and all its harmonics for 50Hz ±2% or 60Hz ±2%. For 60Hz Figure 4. LTC2410 Normal Mode Rejection When rejection, F should be connected to GND while for 50Hz Using an External Oscillator of Frequency fEOSC O rejection the F pin should be connected to V . O CC tor and enters the Internal Conversion Clock mode. The The selection of 50Hz or 60Hz rejection can also be made LTC2410 operation will not be disturbed if the change of by driving F to an appropriate logic level. A selection O conversion clock source occurs during the sleep state change during the sleep or data output states will not or during the data output state while the converter uses disturb the converter operation. If the selection is made an external serial clock. If the change occurs during the during the conversion state, the result of the conversion in conversion state, the result of the conversion in progress progress may be outside specifications but the following may be outside specifications but the following conver- conversions will not be affected. sions will not be affected. If the change occurs during the When a fundamental rejection frequency different from data output state and the converter is in the Internal SCK 50Hz or 60Hz is required or when the converter must be mode, the serial clock duty cycle may be affected but the synchronized with an outside source, the LTC2410 can serial data stream will remain valid. operate with an external conversion clock. The converter Table 3 summarizes the duration of each state and the automatically detects the presence of an external clock achievable output data rate as a function of F . signal at the F pin and turns off the internal oscillator. O O The frequency f of the external signal must be at least EOSC 2560Hz (1Hz notch frequency) to be detected. The external SERIAL INTERFACE PINS clock signal duty cycle is not significant as long as the The LTC2410 transmits the conversion results and receives minimum and maximum specifications for the high and the start of conversion command through a synchronous low periods t and t are observed. HEO LEO 3-wire interface. During the conversion and sleep states, While operating with an external conversion clock of a this interface can be used to assess the converter status frequency f , the LTC2410 provides better than 110dB and during the data output state it is used to read the EOSC normal mode rejection in a frequency range f /2560 conversion result. EOSC ±4% and its harmonics. The normal mode rejection as a function of the input frequency deviation from f /2560 Serial Clock Input/Output (SCK) EOSC is shown in Figure 4. The serial clock signal present on SCK (Pin 13) is used to Whenever an external clock is not present at the F pin, synchronize the data transfer. Each bit of data is shifted O the converter automatically activates its internal oscilla- out the SDO pin on the falling edge of the serial clock. 2410fa 15 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION Table 3. LTC2410 State Duration State Operating Mode Duration CONVERT Internal Oscillator F = LOW 133ms, Output Data Rate ≤ 7.5 Readings/s O (60Hz Rejection) F = HIGH 160ms, Output Data Rate ≤ 6.2 Readings/s O (50Hz Rejection) External Oscillator F = External Oscillator 20510/f s, Output Data Rate ≤ f /20510 Readings/s O EOSC EOSC with Frequency f kHz EOSC (f /2560 Rejection) EOSC SLEEP As Long As CS = HIGH Until CS = LOW and SCK DATA OUTPUT Internal Serial Clock F = LOW/HIGH As Long As CS = LOW But Not Longer Than 1.67ms O (Internal Oscillator) (32 SCK cycles) F = External Oscillator with As Long As CS = LOW But Not Longer Than 256/f ms O EOSC Frequency f kHz (32 SCK cycles) EOSC External Serial Clock with As Long As CS = LOW But Not Longer Than 32/f ms SCK Frequency f kHz (32 SCK cycles) SCK In the Internal SCK mode of operation, the SCK pin is an Chip Select Input (CS) output and the LTC2410 creates its own serial clock by The active LOW chip select, CS (Pin 11), is used to test the dividing the internal conversion clock by 8. In the External conversion status and to enable the data output transfer SCK mode of operation, the SCK pin is used as input. The as described in the previous sections. internal or external SCK mode is selected on power-up and then reselected every time a HIGH-to-LOW transition In addition, the CS signal can be used to trigger a new is detected at the CS pin. If SCK is HIGH or floating at conversion cycle before the entire serial data transfer has power-up or during this transition, the converter enters the been completed. The LTC2410 will abort any serial data internal SCK mode. If SCK is LOW at power-up or during transfer in progress and start a new conversion cycle any- this transition, the converter enters the external SCK mode. time a LOW-to-HIGH transition is detected at the CS pin after the converter has entered the data output state (i.e., Serial Data Output (SDO) after the first rising edge of SCK occurs with CS = LOW). The serial data output pin, SDO (Pin 12), provides the Finally, CS can be used to control the free-running modes result of the last conversion as a serial bit stream (MSB of operation, see Serial Interface Timing Modes section. first) during the data output state. In addition, the SDO Grounding CS will force the ADC to continuously convert at pin is used as an end of conversion indicator during the the maximum output rate selected by F . Tying a capacitor O conversion and sleep states. to CS will reduce the output rate and power dissipation by a factor proportional to the capacitor’s value, see Figures When CS (Pin 11) is HIGH, the SDO driver is switched 12 to 14. to a high impedance state. This allows sharing the serial interface with other devices. If CS is LOW during the convert or sleep state, SDO will output EOC. If CS is LOW SERIAL INTERFACE TIMING MODES during the conversion phase, the EOC bit appears HIGH on The LTC2410’s 3-wire interface is SPI and MICROWIRE the SDO pin. Once the conversion is complete, EOC goes compatible. This interface offers several flexible modes LOW. The device remains in the sleep state until the first of operation. These include internal/external serial clock, rising edge of SCK occurs while CS = LOW. 2- or 3-wire I/O, single cycle conversion and autostart. The 2410fa 16 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION following sections describe each of these serial interface The serial data output pin (SDO) is Hi-Z as long as CS is timing modes in detail. In all these cases, the converter HIGH. At any time during the conversion cycle, CS may be can use the internal oscillator (F = LOW or F = HIGH) pulled LOW in order to monitor the state of the converter. O O or an external oscillator connected to the F pin. Refer to While CS is pulled LOW, EOC is output to the SDO pin. O Table 4 for a summary. EOC = 1 while a conversion is in progress and EOC = 0 if the device is in the sleep state. Independent of CS, the External Serial Clock, Single Cycle Operation device automatically enters the low power sleep state once (SPI/MICROWIRE Compatible) the conversion is complete. This timing mode uses an external serial clock to shift When the device is in the sleep state (EOC = 0), its con- out the conversion result and a CS signal to monitor and version result is held in an internal static shift register. control the state of the conversion cycle, see Figure 5. The device remains in the sleep state until the first rising edge of SCK is seen while CS is LOW. Data is shifted out The serial clock mode is selected on the falling edge of the SDO pin on each falling edge of SCK. This enables CS. To select the external serial clock mode, the serial external circuitry to latch the output on the rising edge of clock pin (SCK) must be LOW during each CS falling edge. Table 4. LTC2410 Interface Timing Modes Conversion Data Connection SCK Cycle Output and Configuration Source Control Control Waveforms External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 5, 6 External SCK, 2-Wire I/O External SCK SCK Figure 7 Internal SCK, Single Cycle Conversion Internal CS ↓ CS ↓ Figures 8, 9 Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 10 Internal SCK, Autostart Conversion Internal C Internal Figure 11 EXT 2.7V TO 5.5V 1µF VCC = 50Hz REJECTION 2 VCC FO 14 = EXTERNAL OSCILLATOR = 60Hz REJECTION LTC2410 0R.E1VFVEO TRLOET NAVGCCEEC 34 RREEFF+– SCK 13 3-WIRE ANALOG INPUT RANGE 5 IN+ SDO 12 SPI INTERFACE –0.5VREF TO 0.5VREF 6 IN– CS 11 1, 7, 8, 9, 10, 15, 16 GND CS TEST EOC TEST EOC TEST EOC BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 5 BIT 0 SDO EOC SIG MSB LSB SUB LSB Hi-Z Hi-Z Hi-Z SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION 2410 F05 Figure 5. External Serial Clock, Single Cycle Operation 2410fa 17 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION SCK. EOC can be latched on the first rising edge of SCK externally generated serial clock (SCK) signal, see Figure and the last bit of the conversion result can be latched on 7. CS may be permanently tied to ground, simplifying the the 32nd rising edge of SCK. On the 32nd falling edge of user interface or isolation barrier. SCK, the device begins a new conversion. SDO goes HIGH The external serial clock mode is selected at the end of the (EOC = 1) indicating a conversion is in progress. power-on reset (POR) cycle. The POR cycle is concluded At the conclusion of the data cycle, CS may remain LOW approximately 0.5ms after V exceeds 2.2V. The level CC and EOC monitored as an end-of-conversion interrupt. applied to SCK at this time determines if SCK is internal Alternatively, CS may be driven HIGH setting SDO to Hi-Z. or external. SCK must be driven LOW prior to the end of As described above, CS may be pulled LOW at any time POR in order to enter the external serial clock timing mode. in order to monitor the conversion status. Since CS is tied LOW, the end-of-conversion (EOC) can Typically, CS remains LOW during the data output state. be continuously monitored at the SDO pin during the However, the data output state may be aborted by pull- convert and sleep states. EOC may be used as an interrupt ing CS HIGH anytime between the first rising edge and to an external controller indicating the conversion result the 32nd falling edge of SCK, see Figure 6. On the rising is ready. EOC = 1 while the conversion is in progress and edge of CS, the device aborts the data output state and EOC = 0 once the conversion enters the low power sleep immediately initiates a new conversion. This is useful for state. On the falling edge of EOC, the conversion result systems not requiring all 32 bits of output data, aborting is loaded into an internal static shift register. The device an invalid conversion cycle or synchronizing the start of remains in the sleep state until the first rising edge of SCK. a conversion. Data is shifted out the SDO pin on each falling edge of SCK enabling external circuitry to latch data on the rising External Serial Clock, 2-Wire I/O edge of SCK. EOC can be latched on the first rising edge of SCK. On the 32nd falling edge of SCK, SDO goes HIGH This timing mode utilizes a 2-wire serial I/O interface. (EOC = 1) indicating a new conversion has begun. The conversion result is shifted out of the device by an 2.7V TO 5.5V 1µF VCC = 50Hz REJECTION 2 VCC FO 14 = EXTERNAL OSCILLATOR = 60Hz REJECTION LTC2410 REFERENCE 3 REF+ SCK 13 0.1VVO TLOT AVGCEC 4 REF– 3-WIRE ANALOG INPUT RANGE 5 IN+ SDO 12 SPI INTERFACE –0.5VREF TO 0.5VREF 6 IN– CS 11 1, 7, 8, 9, 10, 15, 16 GND CS TEST EOC TEST EOC TEST EOC BIT 0 BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 9 BIT 8 SDO EOC EOC SIG MSB Hi-Z Hi-Z Hi-Z Hi-Z SCK (EXTERNAL) SLEEP CONVERSION SLEEP DATA OUTPUT CONVERSION DATA OUTPUT 2410 F06 Figure 6. External Serial Clock, Reduced Data Output Length 2410fa 18 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION Internal Serial Clock, Single Cycle Operation In order to select the internal serial clock timing mode, the serial clock pin (SCK) must be floating (Hi-Z) or pulled This timing mode uses an internal serial clock to shift HIGH prior to the falling edge of CS. The device will not out the conversion result and a CS signal to monitor and enter the internal serial clock mode if SCK is driven LOW control the state of the conversion cycle, see Figure 8. on the falling edge of CS. An internal weak pull-up resis- 2.7V TO 5.5V 1µF VCC = 50Hz REJECTION 2 VCC FO 14 = EXTERNAL OSCILLATOR = 60Hz REJECTION LTC2410 0R.E1VFVEO TRLOET NAVGCCEEC 34 RREEFF+– SCK 13 2-WIRE INTERFACE ANALOG INPUT RANGE 5 IN+ SDO 12 –0.5VREF TO 0.5VREF 6 IN– CS 11 1, 7, 8, 9, 10, 15, 16 GND CS BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 5 BIT 0 SDO EOC SIG MSB LSB24 SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION 2410 F07 Figure 7. External Serial Clock, CS = 0 Operation (2-Wire) 2.7V TO 5.5V VCC 1µF VCC = 50Hz REJECTION 2 VCC FO 14 == E6X0HTEz RRNEAJELC OTSIOCNILLATOR 10k LTC2410 0R.E1VFVEO TRLOET NAVGCCEEC 34 RREEFF+– SCK 13 3-WIRE ANALOG INPUT RANGE 5 IN+ SDO 12 SPI INTERFACE –0.5VREF TO 0.5VREF 6 IN– CS 11 1, 7, 8, 9, 10, 15, 16 GND <tEOCtest CS TEST EOC TEST EOC BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 5 BIT 0 SDO EOC SIG MSB LSB24 Hi-Z Hi-Z Hi-Z Hi-Z SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION 2410 F08 Figure 8. Internal Serial Clock, Single Cycle Operation 2410fa 19 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION tor is active on the SCK pin during the falling edge of CS; remains in the sleep state. The conversion result is held therefore, the internal serial clock timing mode is automati- in the internal static shift register. cally selected if SCK is not externally driven. If CS remains LOW longer than t , the first rising EOCtest The serial data output pin (SDO) is Hi-Z as long as CS is edge of SCK will occur and the conversion result is serially HIGH. At any time during the conversion cycle, CS may be shifted out of the SDO pin. The data output cycle begins pulled LOW in order to monitor the state of the converter. on this first rising edge of SCK and concludes after the Once CS is pulled LOW, SCK goes LOW and EOC is output 32nd rising edge. Data is shifted out the SDO pin on each to the SDO pin. EOC = 1 while a conversion is in progress falling edge of SCK. The internally generated serial clock and EOC = 0 if the device is in the sleep state. is output to the SCK pin. This signal may be used to shift the conversion result into external circuitry. EOC can be When testing EOC, if the conversion is complete (EOC = latched on the first rising edge of SCK and the last bit of 0), the device will exit the sleep state and enter the data the conversion result on the 32nd rising edge of SCK. output state if CS remains LOW. In order to prevent the After the 32nd rising edge, SDO goes HIGH (EOC = 1), device from exiting the low power sleep state, CS must SCK stays HIGH and a new conversion starts. be pulled HIGH before the first rising edge of SCK. In the internal SCK timing mode, SCK goes HIGH and the Typically, CS remains LOW during the data output state. device begins outputting data at time t after the However, the data output state may be aborted by pulling EOCtest falling edge of CS (if EOC = 0) or t after EOC goes CS HIGH anytime between the first and 32nd rising edge EOCtest LOW (if CS is LOW during the falling edge of EOC). The of SCK, see Figure 9. On the rising edge of CS, the device value of t is 23µs if the device is using its internal aborts the data output state and immediately initiates a EOCtest oscillator (F = logic LOW or HIGH). If F is driven by an new conversion. This is useful for systems not requiring O O external oscillator of frequency f , then t is 3.6/ all 32 bits of output data, aborting an invalid conversion EOSC EOCtest f . If CS is pulled HIGH before time t , the device cycle, or synchronizing the start of a conversion. If CS is EOSC EOCtest 2.7V TO 5.5V VCC 1µF VCC = 50Hz REJECTION 2 VCC FO 14 == E6X0HTEz RRNEAJELC OTSIOCNILLATOR 10k LTC2410 REFERENCE 3 REF+ SCK 13 0.1VVO TLOT AVGCEC 4 REF– 3-WIRE ANALOG INPUT RANGE 5 IN+ SDO 12 SPI INTERFACE –0.5VREF TO 0.5VREF 6 IN– CS 11 1, 7, 8, 9, 10, 15, 16 GND >tEOCtest <tEOCtest CS TEST EOC TEST EOC TEST EOC BIT 0 BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 8 SDO EOC EOC SIG MSB Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z SCK (INTERNAL) SLEEP CONVERSION SLEEP DATA OUTPUT CONVERSION DATA OUTPUT 2410 F09 Figure 9. Internal Serial Clock, Reduced Data Output Length 2410fa 20 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION pulled HIGH while the converter is driving SCK LOW, the to a HIGH level before CS goes low again. This is not a internal pull-up is not available to restore SCK to a logic concern under normal conditions where CS remains LOW HIGH state. This will cause the device to exit the internal after detecting EOC = 0. This situation is easily overcome serial clock mode on the next falling edge of CS. This can by adding an external 10k pull-up resistor to the SCK pin. be avoided by adding an external 10k pull-up resistor to the SCK pin or by never pulling CS HIGH when SCK is LOW. Internal Serial Clock, 2-Wire I/O, Continuous Conversion Whenever SCK is LOW, the LTC2410’s internal pull-up at pin SCK is disabled. Normally, SCK is not externally driven This timing mode uses a 2-wire, all output (SCK and SDO) if the device is in the internal SCK timing mode. However, interface. The conversion result is shifted out of the device certain applications may require an external driver on SCK. by an internally generated serial clock (SCK) signal, see If this driver goes Hi-Z after outputting a LOW signal, the Figure 10. CS may be permanently tied to ground, sim- LTC2410’s internal pull-up remains disabled. Hence, SCK plifying the user interface or isolation barrier. remains LOW. On the next falling edge of CS, the device is The internal serial clock mode is selected at the end of the switched to the external SCK timing mode. By adding an power-on reset (POR) cycle. The POR cycle is concluded external 10k pull-up resistor to SCK, this pin goes HIGH approximately 0.5ms after V exceeds 2.2V. An internal CC once the external driver goes Hi-Z. On the next CS falling weak pull-up is active during the POR cycle; therefore, the edge, the device will remain in the internal SCK timing mode. internal serial clock timing mode is automatically selected A similar situation may occur during the sleep state when if SCK is not externally driven LOW (if SCK is loaded such CS is pulsed HIGH-LOW-HIGH in order to test the conver- that the internal pull-up cannot pull the pin HIGH, the sion status. If the device is in the sleep state (EOC = 0), external SCK mode will be selected). SCK will go LOW. Once CS goes HIGH (within the time During the conversion, the SCK and the serial data output period defined above as t ), the internal pull-up is EOCtest pin (SDO) are HIGH (EOC = 1). Once the conversion is activated. For a heavy capacitive load on the SCK pin, complete, SCK and SDO go LOW (EOC = 0) indicating the the internal pull-up may not be adequate to return SCK 2.7V TO 5.5V 1µF VCC = 50Hz REJECTION 2 VCC FO 14 = EXTERNAL OSCILLATOR = 60Hz REJECTION LTC2410 REFERENCE 3 REF+ SCK 13 0.1VVO TLOT AVGCEC 4 REF– 2-WIRE INTERFACE ANALOG INPUT RANGE 5 IN+ SDO 12 –0.5VREF TO 0.5VREF 6 IN– CS 11 1, 7, 8, 9, 10, 15, 16 GND CS BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 5 BIT 0 SDO EOC SIG MSB LSB24 SCK (INTERNAL) CONVERSION DATA OUTPUT CONVERSION SLEEP 2410 F10 Figure 10. Internal Serial Clock, CS = 0 Continuous Operation 2410fa 21 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION conversion has finished and the device has entered the While the conversion is in progress, the CS pin is held low power sleep state. The part remains in the sleep state HIGH by an internal weak pull-up. Once the conversion is a minimum amount of time (1/2 the internal SCK period) complete, the device enters the low power sleep state and then immediately begins outputting data. The data output an internal 25nA current source begins discharging the cycle begins on the first rising edge of SCK and ends after capacitor tied to CS, see Figure 11. The time the converter the 32nd rising edge. Data is shifted out the SDO pin on spends in the sleep state is determined by the value of the each falling edge of SCK. The internally generated serial external timing capacitor, see Figures 12 and 13. Once the clock is output to the SCK pin. This signal may be used to voltage at CS falls below an internal threshold (≈1.4V), shift the conversion result into external circuitry. EOC can the device automatically begins outputting data. The data be latched on the first rising edge of SCK and the last bit output cycle begins on the first rising edge of SCK and of the conversion result can be latched on the 32nd rising ends on the 32nd rising edge. Data is shifted out the SDO edge of SCK. After the 32nd rising edge, SDO goes HIGH pin on each falling edge of SCK. The internally generated (EOC = 1) indicating a new conversion is in progress. SCK serial clock is output to the SCK pin. This signal may be remains HIGH during the conversion. used to shift the conversion result into external circuitry. After the 32nd rising edge, CS is pulled HIGH and a new Internal Serial Clock, Autostart Conversion conversion is immediately started. This is useful in appli- cations requiring periodic monitoring and ultralow power. This timing mode is identical to the internal serial clock, Figure 14 shows the average supply current as a function 2-wire I/O described above with one additional feature. of capacitance on CS. Instead of grounding CS, an external timing capacitor is tied to CS. 2.7V TO 5.5V 1µF VCC = 50Hz REJECTION 2 VCC FO 14 = EXTERNAL OSCILLATOR = 60Hz REJECTION LTC2410 REFERENCE 3 REF+ SCK 13 0.1VVO TLOT AVGCEC 4 REF– 2-WIRE INTERFACE ANALOG INPUT RANGE 5 IN+ SDO 12 –0.5VREF TO 0.5VREF 6 IN– CS 11 1, 7, 8, 9, 10, 15, 16 GND CEXT VCC CS GND BIT 31 BIT 30 BIT 29 BIT 0 SDO EOC SIG Hi-Z Hi-Z SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION 2410 F11 Figure 11. Internal Serial Clock, Autostart Operation 2410fa 22 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION 7 It should be noticed that the external capacitor discharge current is kept very small in order to decrease the con- 6 verter power dissipation in the sleep state. In the autostart 5 mode, the analog voltage on the CS pin cannot be observed C) SE 4 without disturbing the converter operation using a regular (PLE oscilloscope probe. When using this configuration, it is M 3 A S important to minimize the external leakage current at t 2 the CS pin by using a low leakage external capacitor and VCC = 5V 1 properly cleaning the PCB surface. VCC = 3V 0 The internal serial clock mode is selected every time the 1 10 100 1000 10000 100000 voltage on the CS pin crosses an internal threshold voltage. CAPACITANCE ON CS (pF) 2410 F12 An internal weak pull-up at the SCK pin is active while CS Figure 12. CS Capacitance vs t is discharging; therefore, the internal serial clock timing SAMPLE mode is automatically selected if SCK is floating. It is important to ensure there are no external drivers pulling 8 SCK LOW while CS is discharging. 7 6 PRESERVING THE CONVERTER ACCURACY E (Hz) 5 VCC = 5V AT VCC = 3V The LTC2410 is designed to reduce as much as possible R 4 E the conversion result sensitivity to device decoupling, PCB L P M 3 A layout, anti-aliasing circuits, line frequency perturbations S 2 and so on. Nevertheless, in order to preserve the extreme 1 accuracy capability of this part, some simple precautions are desirable. 0 0 10 100 1000 10000 100000 CAPACITANCE ON CS (pF) Digital Signal Levels 2410 F13 The LTC2410’s digital interface is easy to use. Its digital Figure 13. CS Capacitance vs Output Rate inputs (F , CS and SCK in External SCK mode of operation) O accept standard TTL/CMOS logic levels and the internal 300 hysteresis receivers can tolerate edge rates as slow as 100µs. However, some considerations are required to 250 VCC = 5V )S take advantage of the exceptional accuracy and low supply M AR200 current of this converter. NT ( VCC = 3V RRE150 The digital output signals (SDO and SCK in Internal SCK U C mode of operation) are less of a concern because they are Y PPL100 not generally active during the conversion state. U S 50 While a digital input signal is in the range 0.5V to (V  – 0.5V), the CMOS input receiver draws additional 0 CC 1 10 100 1000 10000 100000 current from the power supply. It should be noted that, CAPACITANCE ON CS (pF) when any one of the digital input signals (F , CS and SCK O 2410 F14 in External SCK mode of operation) is within this range, Figure 14. CS Capacitance vs Supply Current the LTC2410 power supply current may increase even if 2410fa 23 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION the signal in question is at a valid logic level. For micro- input terminals may result into a DC offset error. Such power operation, it is recommended to drive all digital perturbations may occur due to asymmetric capacitive input signals to full CMOS levels [V < 0.4V and V > coupling between the F signal trace and the converter IL OH O (V – 0.4V)]. input and/or reference connection traces. An immediate CC solution is to maintain maximum possible separation be- During the conversion period, the undershoot and/or tween the F signal trace and the input/reference signals. overshoot of a fast digital signal connected to the LTC2410 O When the F signal is parallel terminated near the converter, pins may severely disturb the analog to digital conversion O substantial AC current is flowing in the loop formed by process. Undershoot and overshoot can occur because of the F connection trace, the termination and the ground the impedance mismatch at the converter pin when the O return path. Thus, perturbation signals may be inductively transition time of an external control signal is less than coupled into the converter input and/or reference. In this twice the propagation delay from the driver to LTC2410. situation, the user must reduce to a minimum the loop For reference, on a regular FR-4 board, signal propagation area for the F signal as well as the loop area for the dif- velocity is approximately 183ps/inch for internal traces and O ferential input and reference connections. 170ps/inch for surface traces. Thus, a driver generating a control signal with a minimum transition time of 1ns must Driving the Input and Reference be connected to the converter pin through a trace shorter than 2.5 inches. This problem becomes particularly difficult The input and reference pins of the LTC2410 converter when shared control lines are used and multiple reflec- are directly connected to a network of sampling capaci- tions may occur. The solution is to carefully terminate all tors. Depending upon the relation between the differential transmission lines close to their characteristic impedance. input voltage and the differential reference voltage, these capacitors are switching between these four pins transfer- Parallel termination near the LTC2410 pin will eliminate ring small amounts of charge in the process. A simplified this problem but will increase the driver power dissipa- equivalent circuit is shown in Figure 15. tion. A series resistor between 27Ω and 56Ω placed near the driver or near the LTC2410 pin will also eliminate this For a simple approximation, the source impedance RS problem without additional power dissipation. The actual driving an analog input pin (IN+, IN–, REF+ or REF–) can resistor value depends upon the trace impedance and be considered to form, together with RSW and CEQ (see connection topology. Figure 15), a first order passive network with a time constant τ = (R + R ) • C . The converter is able to S SW EQ An alternate solution is to reduce the edge rate of the sample the input signal with better than 1ppm accuracy if control signals. It should be noted that using very slow the sampling period is at least 14 times greater than the edges will increase the converter power supply current input circuit time constant τ. The sampling process on during the transition time. The multiple ground pins used the four input analog pins is quasi-independent so each in this package configuration, as well as the differential time constant should be considered by itself and, under input and reference architecture, reduce substantially the worst-case circumstances, the errors may add. converter’s sensitivity to ground currents. When using the internal oscillator (F = LOW or HIGH), O Particular attention must be given to the connection of the LTC2410’s front-end switched-capacitor network is the F signal when the LTC2410 is used with an external O clocked at 76800Hz corresponding to a 13µs sampling conversion clock. This clock is active during the conver- period. Thus, for settling errors of less than 1ppm, the sion time and the normal mode rejection provided by the driving source impedance should be chosen such that τ ≤ internal digital filter is not very high at this frequency. A 13µs/14 = 920ns. When an external oscillator of frequency normal mode signal of this frequency at the converter f is used, the sampling period is 2/f and, for a EOSC EOSC reference terminals may result into DC gain and INL errors. settling error of less than 1ppm, τ ≤ 0.14/f . EOSC A normal mode signal of this frequency at the converter 2410fa 24 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION Input Current RSOURCE IN+ If complete settling occurs on the input, conversion re- sults will be unaffected by the dynamic input current. An VINCM + 0.5VIN CIN C≅P2A0RpF LTC2410 incomplete settling of the input signal sampling process may result in gain and offset errors, but it will not degrade RSOURCE IN– the INL performance of the converter. Figure 15 shows the mathematical expressions for the average bias currents VINCM – 0.5VIN CIN C≅P2A0RpF 2410 F16 flowing through the IN+ and IN– pins as a result of the sampling charge transfers when integrated over a sub- Figure 16. An RC Network at IN+ and IN– stantial time period (longer than 64 internal clock cycles). The effect of this input dynamic current can be analyzed 50 CIN = 0.01µF using the test circuit of Figure 16. The CPAR capacitor CIN = 0.001µF 40 includes the LTC2410 pin capacitance (5pF typical) plus )REF CIN = 100pF the capacitance of the test fixture used to obtain the results F V CIN = 0pF shown in Figures 17 and 18. A careful implementation can m O 30 p p bring the total input capacitance (CIN + CPAR) closer to 5pF OR ( 20 VRCECF += =5 V5V thus achieving better performance than the one predicted RR REF– = GND S E IN+ = 5V by Figures 17 and 18. For simplicity, two distinct situations +F 10 IN– = 2.5V can be considered. FO = GND TA = 25°C 0 For relatively small values of input capacitance (C < IN 1 10 100 1k 10k 100k 0.01µF), the voltage on the sampling capacitor settles RSOURCE (Ω) almost completely and relatively large values for the source 2410 F17 Figure 17. +FS Error vs R at IN+ or IN– (Small C ) impedance result in only small errors. Such values for C SOURCE IN IN VCC IREF+ ILEAK RSW2 0(TkYP) I(IN+) =VIN+VINCM−VREFCM VREF+ AVG 0.5•REQ ILEAK I(IN−) =−VIN+VINCM−VREFCM VCC AVG 0.5•REQ IIN+ ILEAK RSW2 0(TkYP) I(REF+)AVG=1.5•VREF0−.5V•INRCEMQ+VREFCM−VREFVI•2NREQ VIN+ ILEAK C18EQpF I(REF−)AVG=−1.5•VREF0.−5V•IRNECQM+VREFCM+VREFVI•2NREQ VCC (TYP) where: VIIINN–– IILLEEAAKK RSW2 0(TkYP) VVRREEFFC=MR=EFR+E−FR+E+2FR−EF− VCC VIN=IN+−IN− IREF– ILEAK RSW2 0(TkYP) VINCM=IN+−2IN− VREF– ILEAK 2410 F15 REQ=3.61MΩINTERNALOSCILLATOR60HzNotch(FO=LOW) REQ=4.32MΩINTERNALOSCILLATOR50HzNotch(FO=HIGH) SWITCHING FREQUENCY REQ=(0.555•1012)/fEOSCEXTERNALOSCILLATOR fSW = 76800Hz INTERNAL OSCILLATOR (FO = LOW OR HIGH) fSW = 0.5 (cid:127) fEOSC EXTERNAL OSCILLATOR Figure 15. LTC2410 Equivalent Analog Input Circuit 2410fa 25 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION 0 input resistance is 0.28 • 1012/f Ω and each ohm of EOSC VRCECF += =5 V5V source resistance driving IN+ or IN– will result in V)REF–10 RIINNE+–F ==– =G2 .NG5DVND r1e.7si8s t•a 1n0c–e6 o •n f EthOeS Ctwppom i ngpauint peirnros ri.s T ahded ietfivfeec wt oitfh t rhees spoeuctr ctoe pm OF –20 FTOA == G25N°DC this gain error. The typical +FS and –FS errors as a func- R (p tion of the sum of the source resistance seen by IN+ and ERRO–30 CIN = 0.01µF IN– for large values of CIN are shown in Figures 19 and 20. FS CIN = 0.001µF ––40 In addition to this gain error, an offset error term may CIN = 100pF also appear. The offset error is proportional with the CIN = 0pF –50 mismatch between the source impedance driving the two 1 10 100 1k 10k 100k RSOURCE (Ω) input pins IN+ and IN– and with the difference between the 2410 F18 input and reference common mode voltages. While the Figure 18. –FS Error vs RSOURCE at IN+ or IN– (Small CIN) input drive circuit nonzero source impedance combined with the converter average input current will not degrade will deteriorate the converter offset and gain performance the INL performance, indirect distortion may result from without significant benefits of signal filtering and the user the modulation of the offset error by the common mode is advised to avoid them. Nevertheless, when small val- component of the input signal. Thus, when using large ues of C are unavoidably present as parasitics of input IN C capacitor values, it is advisable to carefully match the IN multiplexers, wires, connectors or sensors, the LTC2410 source impedance seen by the IN+ and IN– pins. When can maintain its exceptional accuracy while operating F = LOW (internal oscillator and 60Hz notch), every 1Ω O with relative large values of source resistance as shown in mismatch in source impedance transforms a full-scale Figures 17 and 18. These measured results may be slightly common mode input signal into a differential mode input different from the first order approximation suggested signal of 0.28ppm. When F = HIGH (internal oscillator O earlier because they include the effect of the actual second and 50Hz notch), every 1Ω mismatch in source imped- order input network together with the nonlinear settling ance transforms a full-scale common mode input signal process of the input amplifiers. For small C values, the IN into a differential mode input signal of 0.23ppm. When F settling on IN+ and IN– occurs almost independently and O is driven by an external oscillator with a frequency f , EOSC there is little benefit in trying to match the source imped- every 1Ω mismatch in source impedance transforms a full- ance for the two pins. scale common mode input signal into a differential mode Larger values of input capacitors (CIN > 0.01µF) may be input signal of 1.78 • 10–6 • fEOSCppm. Figure 21 shows the required in certain configurations for anti-aliasing or gen- typical offset error due to input common mode voltage for eral input signal filtering. Such capacitors will average the various values of source resistance imbalance between the input sampling charge and the external source resistance IN+ and IN– pins when large CIN values are used. will see a quasi constant input differential impedance. If possible, it is desirable to operate with the input signal When F = LOW (internal oscillator and 60Hz notch), the O common mode voltage very close to the reference signal typical differential input resistance is 1.8MΩ which will common mode voltage as is the case in the ratiometric generate a gain error of approximately 0.28ppm for each measurement of a symmetric bridge. This configuration ohm of source resistance driving IN+ or IN–. When F = O eliminates the offset error caused by mismatched source HIGH (internal oscillator and 50Hz notch), the typical dif- impedances. ferential input resistance is 2.16MΩ which will generate The magnitude of the dynamic input current depends upon a gain error of approximately 0.23ppm for each ohm of source resistance driving IN+ or IN–. When F is driven the size of the very stable internal sampling capacitors and O upon the accuracy of the converter sampling clock. The by an external oscillator with a frequency f (exter- EOSC accuracy of the internal clock over the entire temperature nal conversion clock operation), the typical differential 2410fa 26 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION 300 and power supply range is typical better than 0.5%. Such VRCECF += =5 V5V CIN = 1µF, 10µF a specification can also be easily achieved by an external 240 REF– = GND clock. When relatively stable resistors (50ppm/°C) are used V)REF IINN+– == 31..7255VV for the external source impedance seen by IN+ and IN–, R (ppm OF 180 FTOA == G25N°DC CIN = 0.1µF tehrreo erxsp weciltl ebde d irnisfti gonf itfhicea dnyt n(aabmoiuc tc 1u%rre onft ,t ohfefisre rte asnpde cgtaivine O 120 R values over the entire temperature and voltage range). Even R E +FS 60 CIN = 0.01µF for the most stringent applications, a one-time calibration operation may be sufficient. 0 In addition to the input sampling charge, the input ESD 0 1002003004005006007008009001000 protection diodes have a temperature dependent leakage RSOURCE (Ω) 2410 F19 current. This current, nominally 1nA (±10nA max), results Figure 19. +FS Error vs R at IN+ or IN– (Large C ) SOURCE IN in a small offset shift. A 100Ω source resistance will create a 0.1µV typical and 1µV maximum offset voltage. 0 CIN = 0.01µF Reference Current –60 )REF In a similar fashion, the LTC2410 samples the differential V m OF –120 reference pins REF+ and REF– transferring small amount R (pp VCC = 5V CIN = 0.1µF of charge to and from the external driving circuits thus RRO –180 RREEFF+– == 5GVND producing a dynamic reference current. This current does S E IN+ = 1.25V not change the converter offset, but it may degrade the –F –240 IN– = 3.75V gain and INL performance. The effect of this current can FTOA == G25N°DC CIN = 1µF, 10µF be analyzed in the same two distinct situations. –300 0 1002003004005006007008009001000 For relatively small values of the external reference capaci- RSOURCE (Ω) tors (C < 0.01µF), the voltage on the sampling capacitor REF 2410 F20 Figure 20. –FS Error vs R at IN+ or IN– (Large C ) settles almost completely and relatively large values for SOURCE IN the source impedance result in only small errors. Such 120 VCC = 5V values for CREF will deteriorate the converter offset and 100 A REF+ = 5V )REF 8600 RINE+F =– =IN G–N =D VINCM gfialtienr ipnegr faonrdm tahnec eu sweirt hiso uatd sviigsneidfi ctoa natv boeidn etfhitesm o.f reference V B OF 40 m C Larger values of reference capacitors (C > 0.01µF) p 20 REF p D R ( 0 may be required as reference filters in certain configura- O E ERR –20 F tions. Such capacitors will average the reference sampling T –40 E charge and the external source resistance will see a quasi FFS –60 G FO = GND O –80 TA = 25°C constant reference differential impedance. When FO = LOW –100 RSOURCEIN– = 500Ω (internal oscillator and 60Hz notch), the typical differential CIN = 10µF –120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 reference resistance is 1.3MΩ which will generate a gain VINCM (V) error of approximately 0.38ppm for each ohm of source A: ∆RIN = +400Ω E: ∆RIN = –100Ω resistance driving REF+ or REF–. When F = HIGH (internal B: ∆RIN = +200Ω F: ∆RIN = –200Ω O C: ∆RIN = +100Ω G: ∆RIN = –400Ω oscillator and 50Hz notch), the typical differential refer- D: ∆RIN = 0Ω 2410 F21 ence resistance is 1.56MΩ which will generate a gain Figure 21. Offset Error vs Common Mode Voltage error of approximately 0.32ppm for each ohm of source (V = IN+ = IN–) and Input Source Resistance Imbalance INCM resistance driving REF+ or REF–. When F is driven by (∆R = R + – R –) for Large C Values (C ≥ 1µF) O IN SOURCEIN SOURCEIN IN IN 2410fa 27 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION an external oscillator with a frequency f (external = HIGH (internal oscillator and 50Hz notch), every 100Ω EOSC conversion clock operation), the typical differential ref- of source resistance driving REF+ or REF– translates into erence resistance is 0.20 • 1012/f Ω and each ohm about 1.1ppm additional INL error. When F is driven by EOSC O of source resistance driving REF+ or REF– will result in an external oscillator with a frequency f , every 100Ω EOSC 2.47 • 10–6 • f gain error. The effect of the source of source resistance driving REF+ or REF– translates EOSCppm resistance on the two reference pins is additive with respect into about 8.73 • 10–6 • f additional INL error. EOSCppm to this gain error. The typical +FS and –FS errors for vari- Figure 26 shows the typical INL error due to the source ous combinations of source resistance seen by the REF+ resistance driving the REF+ or REF– pins when large C REF and REF– pins and external capacitance C connected values are used. The effect of the source resistance on REF to these pins are shown in Figures 22, 23, 24 and 25. the two reference pins is additive with respect to this INL error. In general, matching of source impedance for the In addition to this gain error, the converter INL perfor- REF+ and REF– pins does not help the gain or the INL er- mance is degraded by the reference source impedance. ror. The user is thus advised to minimize the combined When F = LOW (internal oscillator and 60Hz notch), every O source impedance driving the REF+ and REF– pins rather 100Ω of source resistance driving REF+ or REF– trans- than to try to match it. lates into about 1.34ppm additional INL error. When F O 0 50 VCC = 5V CREF = 0.01µF REF+ = 5V CREF = 0.001µF –10 REF– = GND 40 pm OF V)REF–20 IIFTNNOA+ –== == G2 525NV.°5DCV pm OF V)REF 30 CRCEFR E=F 1 =0 00ppFF p p R ( R ( VCC = 5V O–30 O 20 REF+ = 5V +FS ERR–40 CCRREFE F= = 0 0.0.0011µµFF –FS ERR 10 RIINNE+–F =–= =G2 .NG5DVND CREF = 100pF FO = GND CREF = 0pF TA = 25°C –50 0 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k RSOURCE (Ω) RSOURCE (Ω) 2410 F22 2410 F23 Figure 22. +FS Error vs R at REF+ or REF– (Small C ) Figure 23. –FS Error vs R at REF+ or REF– (Small C ) SOURCE IN SOURCE IN 0 450 CREF = 0.01µF VRCECF += =5 V5V CREF = 1µF, 10µF –90 360 REF– = GND V)REF V)REF IINN+– == 13..2755VV pm OF –180 CREF = 0.1µF pm OF 270 FTOA == G25N°DC p p R ( VCC = 5V R ( CREF = 0.1µF RRO –270 RREEFF+– == 5GVND RRO 180 +FS E –360 IINN+– == 31..7255VV –FS E 90 CREF = 0.01µF FO = GND CREF = 1µF, 10µF TA = 25°C –450 0 0 1002003004005006007008009001000 0 1002003004005006007008009001000 RSOURCE (Ω) RSOURCE (Ω) 2410 F24 2410 F25 Figure 24. +FS Error vs R at REF+ or REF– (Large C ) Figure 25. –FS Error vs R at REF+ or REF– (Large C ) SOURCE REF SOURCE REF 2410fa 28 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION data output phases which are controlled by the user and 15 12 RSOURCE = 1000Ω which can be made insignificantly short. When operated 9 RSOURCE = 500Ω with an external conversion clock (FO connected to an V)REF 63 einxctreeransael do sacsi dlleastoirre)d, .t hTeh eL dTuCr2a4ti1o0n oouf tthpeu tc odnavtae rrsaitoen c pahna bsee F pm O 0 is 20510/fEOSC. If fEOSC = 153600Hz, the converter behaves L (p –3 RSOURCE = 100Ω as if the internal oscillator is used and the notch is set at IN –6 60Hz. There is no significant difference in the LTC2410 –9 performance between these two operation modes. –12 –15 An increase in fEOSC over the nominal 153600Hz will –0.5–0.4–0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5 translate into a proportional increase in the maximum VINDIF/VREFDIF output data rate. This substantial advantage is neverthe- VCC = 5V FO = GND REF+ = 5V CREF = 10µF less accompanied by three potential effects, which must REF– = GND TA = 25°C VINCM = 0.5 (cid:127) (IN+ + IN–) = 2.5V 2410 F26 be carefully considered. Figure 26. INL vs Differential Input Voltage (V = IN+ = IN–) IN First, a change in f will result in a proportional change and Reference Source Resistance (R at REF+ and REF–) EOSC SOURCE for Large C Values (C ≥ 1µF) in the internal notch position and in a reduction of the REF REF converter differential mode rejection at the power line The magnitude of the dynamic reference current depends frequency. In many applications, the subsequent per- upon the size of the very stable internal sampling capacitors formance degradation can be substantially reduced by and upon the accuracy of the converter sampling clock. The relying upon the LTC2410’s exceptional common mode accuracy of the internal clock over the entire temperature rejection and by carefully eliminating common mode to and power supply range is typical better than 0.5%. Such differential mode conversion sources in the input circuit. a specification can also be easily achieved by an external The user should avoid single-ended input filters and should clock. When relatively stable resistors (50ppm/°C) are maintain a very high degree of matching and symmetry used for the external source impedance seen by REF+ in the circuits driving the IN+ and IN– pins. and REF–, the expected drift of the dynamic current gain Second, the increase in clock frequency will increase error will be insignificant (about 1% of its value over the proportionally the amount of sampling charge transferred entire temperature and voltage range). Even for the most through the input and the reference pins. If large external stringent applications a one-time calibration operation input and/or reference capacitors (C , C ) are used, IN REF may be sufficient. the previous section provides formulae for evaluating the In addition to the reference sampling charge, the refer- effect of the source resistance upon the converter perfor- ence pins ESD protection diodes have a temperature de- mance for any value of f . If small external input and/ EOSC pendent leakage current. This leakage current, nominally or reference capacitors (C , C ) are used, the effect of IN REF 1nA (±10nA max), results in a small gain error. A 100Ω the external source resistance upon the LTC2410 typical source resistance will create a 0.05µV typical and 0.5µV performance can be inferred from Figures 17, 18, 22 and maximum full-scale error. 23 in which the horizontal axis is scaled by 153600/f . EOSC Third, an increase in the frequency of the external oscillator Output Data Rate above 460800Hz (a more than 3× increase in the output data When using its internal oscillator, the LTC2410 can produce rate) will start to decrease the effectiveness of the internal up to 7.5 readings per second with a notch frequency of auto-calibration circuits. This will result in a progressive 60Hz (FO = LOW) and 6.25 readings per second with a degradation in the converter accuracy and linearity. Typical notch frequency of 50Hz (FO = HIGH). The actual output measured performance curves for output data rates up to data rate will depend upon the length of the sleep and 25 readings per second are shown in Figures 27, 28, 29, 2410fa 29 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION 30, 31, 32, 33 and 34. In order to obtain the highest pos- 500 sible level of accuracy from this converter at output data 450 VCC = 5V REF+ = 5V rates above 7.5 readings per second, the user is advised )REF400 REF– = GND ttoh em maaxximimizuem th aem pboiwenetr ospueprpaltyin vgo tletamgpe eursaetudr ea.n Idn tcoe rlitmaiint pm OF V335000 VFVOIINN =C = ME 0 X=VT 2E.R5NVAL OSCILLATOR p circumstances, a reduction of the differential reference R (250 O voltage may be beneficial. ERR200 ET 150 S F F100 Input Bandwidth O 50 The combined effect of the internal Sinc4 digital filter and 0 TA = 25°C TA = 85°C 0 5 10 15 20 25 of the analog and digital autocalibration circuits determines OUTPUT DATA RATE (READINGS/SEC) the LTC2410 input bandwidth. When the internal oscillator 2410 F27 is used with the notch set at 60Hz (F = LOW), the 3dB O Figure 27. Offset Error vs Output Data Rate and Temperature input bandwidth is 3.63Hz. When the internal oscillator is used with the notch set at 50Hz (F = HIGH), the 3dB O input bandwidth is 3.02Hz. If an external conversion clock 7000 gtheen e3rdaBto irn pouf tf rbeaqnudewncidyt hfE iOsS 0C. 2is3 c6o •n 1n0e–c6te •d f EtoO StCh.e FO pin, )REF65000000 RIVRNCEE+CFF +=–= ==35 .V5G7V5NVD Due to the complex filtering and calibration algorithms F V IN– = 1.25V utilized, the converter input bandwidth is not modeled pm O 4000 FO = EXTERNAL OSCILLATOR p very accurately by a first order filter with the pole located OR ( 3000 R at the 3dB frequency. When the internal oscillator is used, ER S 2000 the shape of the LTC2410 input bandwidth is shown in +F Figure 35 for F = LOW and F = HIGH. When an external 1000 O O oscillator of frequency fEOSC is used, the shape of the 0 TA = 25°C TA = 85°C 0 5 10 15 20 25 LTC2410 input bandwidth can be derived from Figure 35, OUTPUT DATA RATE (READINGS/SEC) F = LOW curve in which the horizontal axis is scaled by O 2410 F28 f /153600. EOSC Figure 28. +FS Error vs Output Data Rate and Temperature The conversion noise (800nV typical for V = 5V) can RMS REF be modeled by a white noise source connected to a noise 0 free converter. The noise spectral density is 62.75nV√Hz TA = 25°C TA = 85°C –1000 for an infinite bandwidth source and 86.1nV√Hz for a single 0.5MHz pole source. From these numbers, it is clear that )REF–2000 V F particular attention must be given to the design of external O m –3000 p amplification circuits. Such circuits face the simultaneous p requirements of very low bandwidth (just a few Hz) in RROR (–4000 VRCECF += =5 V5V order to reduce the output referred noise and relatively S E–5000 REF– = GND –F IN+ = 1.25V high bandwidth (at least 500kHz) necessary to drive the –6000 IN– = 3.75V input switched-capacitor network. A possible solution is FO = EXTERNAL OSCILLATOR –7000 a high gain, low bandwidth amplifier stage followed by a 0 5 10 15 20 25 high bandwidth unity-gain buffer. OUTPUT DATA RATE (READINGS/SEC) 2410 F29 When external amplifiers are driving the LTC2410, the Figure 29. –FS Error vs Output Data Rate and Temperature ADC input referred system noise calculation can be 2410fa 30 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION 24 22 23 TA = 25°C TA = 25°C 22 20 21 TA = 85°C TA = 85°C TS) 20 TS) 18 BI BI N ( 19 N ( 16 RESOLUTION = LOG2(VREF/INLMAX) OLUTIO 1187 VRCECF += =5 V5V OLUTIO 14 VCC = 5V ES 16 REF– = GND ES REF+ = 5V R 15 VINCM = 2.5V R 12 REF– = GND VIN = 0V VINCM = 2.5V 14 FO = EXTERNAL OSCILLATOR 10 –2.5V < VIN < 2.5V 13 RESOLUTION = LOG2(VREF/NOISERMS) FO = EXTERNAL OSCILLATOR 12 8 0 5 10 15 20 25 0 5 10 15 20 25 OUTPUT DATA RATE (READINGS/SEC) OUTPUT DATA RATE (READINGS/SEC) 2410 F30 2410 F31 Figure 30. Resolution (Noise ≤ 1LSB) Figure 31. Resolution (INL ≤ 1LSB) RMS RMS vs Output Data Rate and Temperature vs Output Data Rate and Temperature 250 24 225 VCC = 5V 23 VREF = 5V )REF200 VRIENFC+M = = G 2N.5DV 2221 ppm OF V117550 TFVOAIN == = E2 0X5V°TCERNAL OSCILLATOR N (BITS) 2109 VREF = 2.5V OR (125 UTIO 18 VCC = 5V RR100 OL 17 REF– = GND OFFSET E 7550 RES 111654 VTFVOAIINN ==C = ME2 0 X5=V°T C2E.R5NVAL OSCILLATOR 25 VREF = 2.5V VREF = 5V 13 RESOLUTION = LOG2(VREF/NOISERMS) 0 12 0 5 10 15 20 25 0 5 10 15 20 25 OUTPUT DATA RATE (READINGS/SEC) OUTPUT DATA RATE (READINGS/SEC) 2410 F32 2410 F33 Figure 32. Offset Error vs Output Figure 33. Resolution (Noise ≤ 1LSB) RMS Data Rate and Reference Voltage vs Output Data Rate and Temperature 22 0.0 VREF = 2.5V –0.5 20 VREF = 5V N (dB) ––11..05 TION (BITS) 1186 RLOESGO2(LVURTEIFO/INN L=M AX) ATTENUATIO –––223...050 FO = HIGH FO = LOW RESOLU 1142 VTAC C= =2 55°VC SIGNAL ––34..50 REF– = GND UT –4.5 10 V–FOI0N .=5C MVE X(cid:127)= TV 0ER.R5ENF (cid:127) A <RL VE OIFN+S <C I0L.L5A (cid:127)T VORREF INP ––55..05 8 –6.0 0 5 10 15 20 25 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 OUTPUT DATA RATE (READINGS/SEC) DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) 2410 F34 2410 F35 Figure 34. Resolution (INL ≤ 1LSB) Figure 35. Input Signal Bandwidth MAX vs Output Data Rate and Reference Voltage Using the Internal Oscillator 2410fa 31 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION simplified by Figure 36. The noise of an amplifier driving 100 the LTC2410 input pin can be modeled as a band limited white noise source. Its bandwidth can be approximated Hz) bcoy rntheer fbraenqduwenidctyh fo. fT ah es ianmglpel ifpieorle n looiwsep asspse cftirltaelr d wenitshi tay D NOISEWIDTH ( 10 FO = LOW is ni. From Figure 3i 6, using fi as the x-axis selector, we EFERRET BAND FO = HIGH coaf nt hfien din opnu tth de ryiv-ainxgis athmep nloifiiseer. eTqhuiisv ableanntd bwainddthw iidntchl ufrdeeqsi INPUT RUIVALEN 1 Q the band limiting effects of the ADC internal calibration E and filtering. The noise of the driving amplifier referred 0.1 to the converter input and including all these effects can 0.1 1 10 100 1k 10k 100k 1M INPUT NOISE SOURCE SINGLE POLE be calculated as N = n • √freq. The total system noise i i EQUIVALENT BANDWIDTH (Hz) 2410 F36 (referred to the LTC2410 input) can now be obtained by Figure 36. Input Referred Noise Equivalent Bandwidth summing as square root of sum of squares the three ADC of an Input Connected White Noise Source input referred noise sources: the LTC2410 internal noise (800nV), the noise of the IN+ driving amplifier and the 0 noise of the IN– driving amplifier. B) –10 FO = HIGH d N ( –20 If the FO pin is driven by an external oscillator of frequency TIO –30 C f , Figure 36 can still be used for noise calculation if E –40 EOSC EJ the x-axis is scaled by fEOSC/153600. For large values of ODE R ––5600 the ratio f /153600, the Figure 36 plot accuracy begins M EOSC L –70 A to decrease, but in the same time the LTC2410 noise floor M –80 R rises and the noise contribution of the driving amplifiers NO –90 T U –100 lose significance. P IN –110 –120 Normal Mode Rejection and Anti-aliasing 0 fS 2fS3fS4fS5fS6fS7fS8fS9fS10fS11fS12fS DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) One of the advantages delta-sigma ADCs offer over 2410 F37 conventional ADCs is on-chip digital filtering. Combined Figure 37. Input Normal Mode Rejection, with a large oversampling ratio, the LTC2410 significantly Internal Oscillator and 50Hz Notch simplifies anti-aliasing filter requirements. 0 The Sinc4 digital filter provides greater than 120dB normal FO = LOW OR B) –10 FO = EXTERNAL OSCILLATOR, mode rejection at all frequencies except DC and integer N (d –20 fEOSC = 10 (cid:127) fS O multiples of the modulator sampling frequency (f ). The TI –30 S C E –40 LTC2410’s auto-calibration circuits further simplify the EJ E R –50 anti-aliasing requirements by additional normal mode OD –60 M signal filtering both in the analog and digital domain. L –70 A M –80 Independent of the operating mode, f = 256 • f = 2048 R S N NO –90 • f where f in the notch frequency and f is T OUTMAX N OUTMAX U –100 P the maximum output data rate. In the internal oscillator IN –110 mode with a 50Hz notch setting, f = 12800Hz and with a –120 S 0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS10fS 60Hz notch setting f = 15360Hz. In the external oscillator DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz) S mode, f = f /10. 2410 F38 S EOSC Figure 38. Input Normal Mode Rejection, Internal Oscillator and 60Hz Notch or External Oscillator 2410fa 32 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION The combined normal mode rejection performance is the normal mode rejection of the LTC2410 operating with shown in Figure 37 for the internal oscillator with 50Hz an internal oscillator and a 60Hz notch setting are shown notch setting (F = HIGH) and in Figure 38 for the internal in Figure 41 superimposed over the theoretical calculated O oscillator with 60Hz notch setting (F = LOW) and for curve. Similarly, typical measured values of the normal O the external oscillator mode. The regions of low rejection mode rejection of the LTC2410 operating with an internal occurring at integer multiples of f have a very narrow oscillator and a 50Hz notch setting are shown in Figure S bandwidth. Magnified details of the normal mode rejection 42 superimposed over the theoretical calculated curve. curves are shown in Figure 39 (rejection near DC) and As a result of these remarkable normal mode specifica- Figure 40 (rejection at f = 256f ) where f represents S N N tions, minimal (if any) anti-alias filtering is required in front the notch frequency. These curves have been derived for of the LTC2410. If passive RC components are placed in the external oscillator mode but they can be used in all front of the LTC2410, the input dynamic current should operating modes by appropriately selecting the f value. N be considered (see Input Current section). In cases where The user can expect to achieve in practice this level of large effective RC time constants are used, an external performance using the internal oscillator as it is demon- buffer amplifier may be required to minimize the effects strated by Figures 41 and 42. Typical measured values of of dynamic input current. 0 0 B) –10 B) –10 N (d –20 N (d –20 CTIO –30 CTIO –30 ODE REJE –––456000 ODE REJE –––456000 M M AL –70 AL –70 M –80 M –80 R R NO –90 NO –90 UT –100 UT –100 P P IN–110 IN–110 –120 –120 0 fN 2fN 3fN 4fN 5fN 6fN 7fN 8fN 250fN 252fN 254fN 256fN 258fN 260fN 262fN INPUT SIGNAL FREQUENCY (Hz) INPUT SIGNAL FREQUENCY (Hz) 2410 F39 2410 F40 Figure 39. Input Normal Mode Rejection Figure 40. Input Normal Mode Rejection 0 0 MEASURED DATA VCC = 5V MEASURED DATA VCC = 5V ON (dB) –20 CALCULATED DATA RVRIEENFFC+–M == = 5G 2VN.5DV ON (dB) –20 CALCULATED DATA RVRIEENFFC+–M == = 5G 2VN.5DV CTI –40 VIN(P-P) = 5V CTI –40 VIN(P-P) = 5V DE REJE –60 TFOA == G25N°DC DE REJE –60 TFOA == 52V5°C O O M M AL –80 AL –80 M M R R O O N–100 N–100 –120 –120 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 0 12.5 25 37.5 50 62.5 75 87.5 100112.5125137.5150162.5175187.5200 INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) 2410 F41 2410 F42 Figure 41. Input Normal Mode Rejection vs Input Frequency Figure 42. Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 100% Full Scale (60Hz Notch) with Input Perturbation of 100% Full Scale (50Hz Notch) 2410fa 33 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION Traditional high order delta-sigma modulators, while pro- imposed over the more traditional normal mode rejection viding very good linearity and resolution, suffer from poten- ratio results obtained with a 5V peak-to-peak (full scale) tial instabilities at large input signal levels. The proprietary input signal. In Figure 43, the LTC2410 uses the internal architecture used for the LTC2410 third order modulator oscillator with the notch set at 60Hz (F = LOW) and in O resolves this problem and guarantees a predictable stable Figure 44 it uses the internal oscillator with the notch set behavior at input signal levels of up to 150% of full scale. at 50Hz (F = HIGH). It is clear that the LTC2410 rejection O In many industrial applications, it is not uncommon to have performance is maintained with no compromises in this to measure microvolt level signals superimposed over extreme situation. When operating with large input signal volt level perturbations and LTC2410 is eminently suited levels, the user must observe that such signals do not for such tasks. When the perturbation is differential, the violate the device absolute maximum ratings. specification of interest is the normal mode rejection for large input signal levels. With a reference voltage V  = 5V, REF SYNCHRONIZATION OF MULTIPLE LTC2410S the LTC2410 has a full-scale differential input range of Since the LTC2410’s absolute accuracy (total unadjusted 5V peak-to-peak. Figures 43 and 44 show measurement error) is 5ppm, applications utilizing multiple synchronized results for the LTC2410 normal mode rejection ratio with a ADCs are possible. 7.5V peak-to-peak (150% of full scale) input signal super- 0 VIN(P-P) = 5V VCC = 5V dB) –20 V(1IN5(0P%-P )O =F 7F.U5LVL SCALE) RREEFF+– == 5GVND ON ( VINCM = 2.5V CTI –40 FO = GND EJE TA = 25°C E R –60 D O M L –80 A M R O N –100 –120 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 INPUT FREQUENCY (Hz) 2410 F43 Figure 43. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (60Hz Notch) 0 VIN(P-P) = 5V VCC = 5V dB) –20 V(1IN5(0P%-P )O =F 7F.U5LVL SCALE) RREEFF+– == 5GVND ON ( VINCM = 2.5V CTI –40 FO = 5V EJE TA = 25°C E R –60 D O M L –80 A M R O N –100 –120 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 INPUT FREQUENCY (Hz) 2410 F44 Figure 44. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (50Hz Notch) 2410fa 34 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION Simultaneous Sampling with Two LTC2410s four LTC2410s are interleaved under the control of separate CS signals. This increases the effective output rate from One such application is synchronizing multiple LTC2410s, 7.5Hz to 30Hz (up to a maximum of 60Hz). Additionally, see Figure 45. The start of conversion is synchronized the one-shot output spectrum is unfolded allowing further to the rising edge of CS. In order to synchronize mul- digital signal processing of the conversion results. SCK and tiple LTC2410s, CS is a common input to all the ADCs. SDO may be common to all four LTC2410s. The four CS To prevent the converters from autostarting a new conver- rising edges equally divide one LTC2410 conversion cycle sion at the end of data output read, 31 or fewer SCK clock (7.5Hz for 60Hz notch frequency). In order to synchronize signals are applied to the LTC2410 instead of 32 (the 32nd the start of conversion to CS, 31 or less SCK clock pulses falling edge would start a conversion). The exact timing must be applied to each ADC. and frequency for the SCK signal is not critical since it is only shifting out the data. In this case, two LTC2410’s Both the synchronous and 4× output rate applications use simultaneously start and end their conversion cycles under the external serial clock and single cycle operation with the external control of CS. reduced data output length (see Serial Interface Timing Modes section and Figure 6). An external oscillator clock Increasing the Output Rate Using Mulitple LTC2410s is applied commonly to the FO pin of each LTC2410 in order to synchronize the sampling times. Both circuits A second application uses multiple LTC2410s to increase may be extended to include more LTC2410s. the effective output rate by 4×, see Figure 46. In this case, SCK2 SCK1 EXTERNAL OSCILLATOR (153,600HZ) LTC2410 LTC2410 #1 #2 VCC FO VCC FO REF+ SCK REF+ SCK CONTROLLER REF– SDO REF– SDO IN+ CS IN+ CS IN– IN– GND GND CS SDO1 SDO2 VREF+ VREF– CS SCK1 31 OR LESS CLOCK CYCLES SCK2 31 OR LESS CLOCK CYCLES SDO1 SDO2 2410 F45 Figure 45. Synchronous Conversion—Extendable 2410fa 35 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION VREF+ VREF– EXTERNAL OSCILLATOR (153,600HZ) LTC2410 LTC2410 LTC2410 LTC2410 #1 #2 #3 #4 VCC FO VCC FO VCC FO VCC FO REF+ SCK REF+ SCK REF+ SCK REF+ SCK REF– SDO REF– SDO REF– SDO REF– SDO IN+ CS IN+ CS IN+ CS IN+ CS IN– IN– IN– IN– GND GND GND GND CONTROLLER SCK SDO CS1 CS2 CS3 CS4 CS1 CS2 CS3 CS4 31 OR LESS SCK CLOCK PULSES SDO 2410 F46 Figure 46. Using Multiple LTC2410s to Increase Output Data Rate BRIDGE APPLICATIONS issue. For those systems that require accurate measure- ment of a small incremental change on a significant tare Typical strain gauge based bridges deliver only 2mV/Volt weight, the lack of history effects in the LTC2400 family of excitation. As the maximum reference voltage of the is of great benefit. LTC2410 is 5V, remote sensing of applied excitation without additional circuitry requires that excitation be limited to For those applications that cannot be fulfilled by the 5V. This gives only 10mV full scale input signal, which LTC2410 alone, compensating for error in external amplifi- can be resolved to 1 part in 10000 without averaging. cation can be done effectively due to the “no latency” feature For many solid state sensors, this is still better than the of the LTC2410. No latency operation allows samples of the sensor. Averaging 64 samples however reduces the noise amplifier offset and gain to be interleaved with weighing level by a factor of eight, bringing the resolving power to measurements. The use of correlated double sampling 1 part in 80000, comparable to better weighing systems. allows suppression of 1/f noise, offset and thermocouple Hysteresis and creep effects in the load cells are typically effects within the bridge. Correlated double sampling in- much greater than this. Most applications that require volves alternating the polarity of excitation and dealing with strain measurements to this level of accuracy are measur- the reversal of input polarity mathematically. Alternatively, ing slowly changing phenomena, hence the time required bridge excitation can be increased to as much as ±10V, to average a large number of readings is usually not an 2410fa 36 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION if one of several precision attenuation techniques is used devices, RFI suppression and wiring. The LTC2410 exhibits to produce a precision divide operation on the reference extremely low temperature dependent drift. As a result, signal. Another option is the use of a reference within the exposure to external ambient temperature ranges does 5V input range of the LTC2410 and developing excitation not compromise performance. The incorporation of any via fixed gain, or LTC1043 based voltage multiplication, amplification considerably complicates thermal stability, as along with remote feedback in the excitation amplifiers, input offset voltages and currents, temperature coefficient as shown in Figures 52 and 53. of gain settling resistors all become factors. Figure 47 shows an example of a simple bridge connection. The circuit in Figure 48 shows an example of a simple Note that it is suitable for any bridge application where amplification scheme. This example produces a differ- measurement speed is not of the utmost importance. ential output with a common mode voltage of 2.5V, as For many applications where large vessels are weighed, determined by the bridge. The use of a true three amplifier the average weight over an extended period of time is of instrumentation amplifier is not necessary, as the LTC2410 concern and short term weight is not readily determined has common mode rejection far beyond that of most am- due to movement of contents, or mechanical resonance. plifiers. The LTC1051 is a dual autozero amplifier that can Often, large weighing applications involve load cells be used to produce a gain of 15 before its input referred located at each load bearing point, the output of which noise dominates the LTC2410 noise. This example shows can be summed passively prior to the signal processing a gain of 34, that is determined by a feedback network built circuitry, actively with amplification prior to the ADC, or using a resistor array containing 8 individual resistors. The can be digitized via multiple ADC channels and summed resistors are organized to optimize temperature tracking in mathematically. The mathematical summation of the out- the presence of thermal gradients. The second LTC1051 put of multiple LTC2410’s provides the benefit of a root buffers the low noise input stage from the transient load square reduction in noise. The low power consumption steps produced during conversion. of the LTC2410 makes it attractive for multidrop com- The gain stability and accuracy of this approach is very munication schemes where the ADC is located within the good, due to a statistical improvement in resistor matching. load-cell housing. A gain of 34 may seem low, when compared to common A direct connection to a load cell is perhaps best incorpo- practice in earlier generations of load-cell interfaces, how- rated into the load-cell body, as minimizing the distance ever the accuracy of the LTC2410 changes the rationale. to the sensor largely eliminates the need for protection Achieving high gain accuracy and linearity at higher gains may prove difficult, while providing little benefit in terms LT1019 of noise reduction. + R1 At a gain of 100, the gain error that could result from 2 typical open-loop gain of 160dB is –1ppm, however, 3 REF+VREFSDO 12 worst-case is at the minimum gain of 116dB, giving a BR3I5D0GΩE 4 REF– SCK 13 gain error of –158ppm. Worst-case gain error at a gain 5 IN+ CS 11 of 34, is –54ppm. The use of the LTC1051A reduces the worst-case gain error to –33ppm. The advantage of gain LTC2410 higher than 34, then becomes dubious, as the input re- 6 IN– FO 14 ferred noise sees little improvement1 and gain accuracy GND is potentially compromised. R2 1, 7, 8, 9, 10, 15, 16 Note that this 4-amplifier topology has advantages over the typical integrated 3-amplifier instrumentation amplifier 2410 F47 R1 AND R2 CAN BE USED TO INCREASE TOLERABLE AC COMPONENT ON REF SIGNALS in that it does not have the high noise level common in the output stage that usually dominates when an instru- Figure 47. Simple Bridge Connection 2410fa 37 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION mentation amplifier is used at low gain. If this amplifier Remote Half Bridge Interface is used at a gain of 10, the gain error is only 10ppm and As opposed to full bridge applications, typical half bridge input referred noise is reduced to 0.1µV . The buffer RMS applications must contend with nonlinearity in the bridge stages can also be configured to provide gain of up to 50 output, as signal swing is often much greater. Applications with high gain stability and linearity. include RTD’s, thermistors and other resistive elements Figure 49 shows an example of a single amplifier used to that undergo significant changes over their span. For single produce single-ended gain. This topology is best used in variable element bridges, the nonlinearity of the half bridge applications where the gain setting resistor can be made output can be eliminated completely; if the reference arm to match the temperature coefficient of the strain gauges. of the bridge is used as the reference to the ADC, as shown If the bridge is composed of precision resistors, with only in Figure 50. The LTC2410 can accept inputs up to 1/2 one or two variable elements, the reference arm of the V . Hence, the reference resistor R1 must be at least REF bridge can be made to act in conjunction with the feedback 2x the highest value of the variable resistor. resistor to determine the gain. If the feedback resistor is In the case of 100Ω platinum RTD’s, this would suggest incorporated into the design of the load cell, using resistors a value of 800Ω for R1. Such a low value for R1 is not which match the temperature coefficient of the load-cell advisable due to self-heating effects. A value of 25.5k is elements, good results can be achieved without the need shown for R1, reducing self-heating effects to acceptable for resistors with a high degree of absolute accuracy. The levels for most sensors. common mode voltage in this case, is again a function of the bridge output. Differential gain as used with a 350Ω The basic circuit shown in Figure 50 shows connections bridge is A = (R1+ R2)/(R1+175Ω). Common mode gain for a full 4-wire connection to the sensor, which may be V is half the differential gain. The maximum differential signal located remotely. The differential input connections will that can be used is 1/4 V , as opposed to 1/2 V in reject induced or coupled 60Hz interference, however, REF REF the 2-amplifier topology above. 1Input referred noise for AV = 34 is approximately 0.05µVRMS, whereas at a gain of 50, it would be 0.048µVRMS. 5VREF 5V 0.1µF 3 8 + 0.1µF 1 0.1µF U1A 5V 2 – 2 8 2 350Ω 4 – BRIDGE U2A 1 3 REF+VCC SDO 12 1 15 14 4 5 12 3 + 4 4 REF– SCK 13 RN1 16 6 11 7 10 8 9 5 IN+ CS 11 2 3 13 6 6 LTC2410 – – U1B 7 U2B 7 6 IN– FO 14 5 5 GND + + 1, 7, 8, 9, 10, 15, 16 2410 F48 RN1 = 5k × 8 RESISTOR ARRAY U1A, U1B, U2A, U2B = 1/2 LTC1051 Figure 48. Using Autozero Amplifiers to Reduce Input Referred Noise 2410fa 38 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION the reference inputs do not have the same rejection. If The circuit shown in Figure 51 shows a more rigorous 60Hz or other noise is present on the reference input, a example of Figure 50, with increased noise suppression low pass filter is recommended as shown in Figure 51. and more protection for remote applications. Note that you cannot place a large capacitor directly at Figure 52 shows an example of gain in the excitation cir- the junction of R1 and R2, as it will store charge from cuit and remote feedback from the bridge. The LTC1043’s the sampling process. A better approach is to produce a provide voltage multiplication, providing ±10V from a 5V low pass filter decoupled from the input lines with a high reference with only 1ppm error. The amplifiers are used value resistor (R3). at unity gain and introduce very little error due to gain The use of a third resistor in the half bridge, between the error or due to offset voltages. A 1µV/°C offset voltage variable and fixed elements gives essentially the same drift translates into 0.05ppm/°C gain error. Simpler alter- result as the two resistor version, but has a few benefits. natives, with the amplifiers providing gain using resistor If, for example, a 25k reference resistor is used to set the arrays for feedback, can produce results that are similar excitation current with a 100Ω RTD, the negative reference to bridge sensing schemes via attenuators. Note that the input is sampling the same external node as the positive amplifiers must have high open-loop gain or gain error input and may result in errors if used with a long cable. will be a source of error. The fact that input offset voltage For short cable applications, the errors may be acceptalby has relatively little effect on overall error may lead one to low. If instead the single 25k resistor is replaced with a use low performance amplifiers for this application. Note 10k 5% and a 10k 0.1% reference resistor, the noise level that the gain of a device such as an LF156, (25V/mV over introduced at the reference, at least at higher frequencies, temperature) will produce a worst-case error of –180ppm will be reduced. A filter can be introduced into the network, at a noise gain of 3, such as would be encountered in an in the form of one or more capacitors, or ferrite beads, inverting gain of 2, to produce –10V from a 5V reference. as long as the sampling pulses are not translated into an error. The reference voltage is also reduced, but this is not undesirable, as it will decrease the value of the LSB, although, not the input referred noise level. 5V + 10µF 0.1µF 5V 350Ω BRIDGE 2 0.1µV 3 + 7 3 REF+VCC 175Ω LTC1050S8 6 + 4 REF– 2 + – 4 1µF 20k 5 IN+ 1µF R1 R2 4.99k 46.4k LTC2410 20k 6 IN– GND 1, 7, 8, 9, 10, 15, 16 ( R1 + R2 ) AV = 9.95 = 2410 F49 R1 + 175Ω Figure 49. Bridge Amplification Using a Single Amplifier 2410fa 39 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION The error associated with the 10V excitation would be Figure 54 shows the use of an LTC2410 with a differential –80ppm. Hence, overall reference error could be as high multiplexer. This is an inexpensive multiplexer that will as 130ppm, the average of the two. contribute some error due to leakage if used directly with the output from the bridge, or if resistors are inserted as Figure 53 shows a similar scheme to provide excitation a protection mechanism from overvoltage. Although the using resistor arrays to produce precise gain. The circuit bridge output may be within the input range of the A/D and is configured to provide 10V and –5V excitation to the multiplexer in normal operation, some thought should be bridge, producing a common mode voltage at the input to given to fault conditions that could result in full excitation the LTC2410 of 2.5V, maximizing the AC input range for voltage at the inputs to the multiplexer or ADC. The use of applications where induced 60Hz could reach amplitudes amplification prior to the multiplexer will largely eliminate up to 2V . RMS errors associated with channel leakage developing error The last two example circuits could be used where mul- voltages in the source impedance. tiple bridge circuits are involved and bridge output can be multiplexed onto a single LTC2410, via an inexpensive multiplexer such as the 74HC4052. VS 2.7V TO 5.5V 2 R1 3 REF+VCC 205.1.5%k 4 REF– LTC2410 PLATINUM 5 IN+ 10R0TΩD 6 IN– GND 1, 7, 8, 9, 10, 15, 16 2410 F50 Figure 50. Remote Half Bridge Interface 5V 5V 2 R2 0.110%k + 3 REF+VCC R1 1R03k 1µF LTC1050 560Ω 4 REF– 10k, 5% 5% – LTC2410 PLATINUM 10k 5 IN+ 10R0TΩD 10k 6 IN– GND 1, 7, 8, 9, 10, 15, 16 2410 F51 Figure 51. Remote Half Bridge Sensing with Noise Suppression on Reference 2410fa 40 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION 15V 15V 15V U1 LTC1043 4 7 3 10V 200Ω 8 7 5V + LT1236-5 10V Q1 20Ω 6 + + LTC1150 2N3904 1µF 11 47µF 0.1µF 2 – * 4 12 –15V 33Ω 14 13 0.1µF 10µF + 1k 17 10V 350Ω 0.1µF 5V BRIDGE 2 VCC LTC2410 3 REF+ –10V 4 REF– 33Ω 5 IN+ 6 IN– 15V U2 GND LTC1043 Q2 7 3 5 6 1, 7, 8, 9, + 10, 15, 16 2N3906 6 LTC1150 2 20Ω 2 – * –15V 4 3 –15V 15 18 0.1µF 1k *FLYING CAPACITORS ARE 5V 1µF FILM (MKP OR EQUIVALENT) U2 LTC1043 4 SEE LTC1043 DATA SHEET FOR 8 7 DETAILS ON UNUSED HALF OF U1 11 1µF * FILM 12 200Ω 14 13 –10V 17 –10V 2410 F52 Figure 52. LTC1043 Provides Precise 4× Reference for Excitation Voltages 2410fa 41 For more information www.linear.com/LTC2410

LTC2410 APPLICATIONS INFORMATION 15V 3 5V + LT1236-5 Q1 20Ω 1 1/2 + 2N3904 LT1112 C3 C1 2 47µF 0.1µF – C1 22Ω 0.1µF RN1 10k 10V 5V 1 2 3 2 RN1 350Ω BRIDGE 4 10k VCC TWO ELEMENTS LTC2410 VARYING 3 REF+ 4 REF– 5 IN+ –5V 6 IN– 8 RN1 RN1 GND 10k 7 10k 1, 7, 8, 9, 10, 15, 16 5 6 15V C2 33Ω 0.1µF RN1 IS CADDOCK T914 10K-010-02 ×2 8 6 – Q2, Q3 20Ω 7 1/2 2N3906 LT1112 ×2 5 + 4 –15V –15V 2410 F53 Figure 53. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier 5V 5V + 16 2 1124 47µF 3 REF+VCC 15 4 REF– 11 LTC2410 74HC4052 1 5 13 5 IN+ TO OTHER 2 3 6 IN– DEVICES 6 GND 4 1, 7, 8, 9, 10, 15, 16 8 9 10 A0 A1 2410 F54 Figure 54. Use a Differential Multiplexer to Expand Channel Capability 2410fa 42 For more information www.linear.com/LTC2410

LTC2410 TYPICAL APPLICATIONS Sample Driver for LTC2410 SPI Interface The performance of the LTC2410 can be verified using the demonstration board DC291A, see Figure 57 for the The LTC2410 has a very simple serial interface that makes schematic. This circuit uses the computer’s serial port to interfacing to microprocessors and microcontrollers very generate power and the SPI digital signals necessary for easy. starting a conversion and reading the result. It includes The listing in Figure 56 is a simple assembler routine for a Labview application software program (see Figure 58) the 68HC11 microcontroller. It uses PORT D, configur- which graphically captures the conversion results. It can ing it for SPI data transfer between the controller and be used to determine noise performance, stability and the LTC2410. Figure 55 shows the simple 3-wire SPI with an external source, linearity. As exemplified in the connection. schematic, the LTC2410 is extremely easy to use. This demonstration board and associated software is available The code begins by declaring variables and allocating four by contacting Linear Technology. memory locations to store the 32-bit conversion result. This is followed by initializing PORT D’s SPI configuration. The program then enters the main sequence. It activates the LTC2410’s serial interface by setting the SS output low, sending a logic low to CS. It next waits in a loop for a logic low on the data line, signifying end-of-conversion. After the loop is satisfied, four SPI transfers are completed, retrieving the conversion. The main sequence ends by set- ting SS high. This places the LTC2410’s serial interface in a high impedance state and initiates another conversion. 68HC11 13 SCK SCK (PD4) 12 LTC2410 SDO MISO (PD2) 11 CS SS (PD5) 2410 F55 Figure 55. Connecting the LTC2410 to a 68HC11 MCU Using the SPI Serial Interface 2410fa 43 For more information www.linear.com/LTC2410

LTC2410 TYPICAL APPLICATIONS ***************************************************** * This example program transfers the LTC2410’s 32-bit output * * conversion result into four consecutive 8-bit memory locations. * ***************************************************** *68HC11 register definition PORTD EQU $1008 Port D data register * “ – , – , SS* ,CSK ;MOSI,MISO,TxD ,RxD” DDRD EQU $1009 Port D data direction register SPSR EQU $1028 SPI control register * “SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0” SPSR EQU $1029 SPI status register * “SPIF,WCOL, – ,MODF; – , – , – , – “ SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter * * RAM variables to hold the LTC2410’s 32 conversion result * DIN1 EQU $00 This memory location holds the LTC2410’s bits 31 - 24 DIN2 EQU $01 This memory location holds the LTC2410’s bits 23 - 16 DIN3 EQU $02 This memory location holds the LTC2410’s bits 15 - 08 DIN4 EQU $03 This memory location holds the LTC2410’s bits 07 - 00 * ********************** * Start GETDATA Routine * ********************** * ORG $C000 Program start location INIT1 LDS #$CFFF Top of C page RAM, beginning location of stack LDAA #$2F –,–,1,0;1,1,1,1 * –, –, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X STAA PORTD Keeps SS* a logic high when DDRD, bit 5 is set LDAA #$38 –,–,1,1;1,0,0,0 STAA DDRD SS*, SCK, MOSI are configured as Outputs * MISO, TxD, RxD are configured as Inputs *DDRD’s bit 5 is a 1 so that port D’s SS* pin is a general output LDAA #$50 STAA SPCR The SPI is configured as Master, CPHA = 0, CPOL = 0 * and the clock rate is E/2 * (This assumes an E-Clock frequency of 4MHz. For higher E- * Clock frequencies, change the above value of $50 to a value * that ensures the SCK frequency is 2MHz or less.) GETDATA PSHX PSHY PSHA LDX #$0 The X register is used as a pointer to the memory locations * that hold the conversion data LDY #$1000 BCLR PORTD, Y %00100000 This sets the SS* output bit to a logic * low, selecting the LTC2410 * 2410fa 44 For more information www.linear.com/LTC2410

LTC2410 TYPICAL APPLICATIONS ********************************** * The next short loop waits for the * * LTC2410’s conversion to finish before * * starting the SPI data transfer * ********************************** * CONVEND LDAA PORTD Retrieve the contents of port D ANDA #%00000100 Look at bit 2 * Bit 2 = Hi; the LTC2410’s conversion is not * complete * Bit 2 = Lo; the LTC2410’s conversion is complete BNE CONVEND Branch to the loop’s beginning while bit 2 remains high * * ******************** * The SPI data transfer * ******************** * TRFLP1 LDAA #$0 Load accumulator A with a null byte for SPI transfer STAA SPDR This writes the byte in the SPI data register and starts * the transfer WAIT1 LDAA SPSR This loop waits for the SPI to complete a serial transfer/exchange by reading the SPI Status Register BPL WAIT1 The SPIF (SPI transfer complete flag) bit is the SPSR’s MSB * and is set to one at the end of an SPI transfer. The branch * will occur while SPIF is a zero. LDAA SPDR Load accumulator A with the current byte of LTC2410 data that was just received STAA 0,X Transfer the LTC2410’s data to memory INX Increment the pointer CPX #DIN4+1 Has the last byte been transferred/exchanged? BNE TRFLP1 If the last byte has not been reached, then proceed to the * next byte for transfer/exchange BSET PORTD,Y %00100000 This sets the SS* output bit to a logic high, * de-selecting the LTC2410 PULA Restore the A register PULY Restore the Y register PULX Restore the X register RTS Figure 56. This is an Example of 68HC11 Code That Captures the LTC2410’s Conversion Results Over the SPI Serial Interface Shown in Figure 55 2410fa 45 For more information www.linear.com/LTC2410

LTC2410 TYPICAL APPLICATIONS D1 BAV74LT1 VCC JP1 U1 VCC JP2 U2 2 1 J1 JUMPER LT1460ACN8-2.5 JUMPER LT1236ACN8-5 R1 VEXT 1 3 6 VOUT VIN 2 1 2 6 VOUT VIN 2 10Ω 3 1 2 + C1 GND + C2 + C3 GND + C4 1 JG2ND 10µF 4 22µF 10µF 4 100µF 35V 25V 35V 16V R2 P1 3 DB9 1 JP3 JUMPER U3E U3F 6 1 3 74HC14 74HC14 R3 2 2 10 11 12 13 51k 7 JP4 3 VCC JUMPER 8 J3 1 1 3 4 BANANA JACK VCC C6 + C5 2 9 VEJX4T 1 GNJD5 1 0.1µF 1305µVF 2 11 74UH3CB14 74UH3CA14 R4 5 BANANA JACK VCC CS 4 3 2 1 51k REJF6+ 1 34 REF+ FO 1143 REF– SCK BRAENFJ7A–NA 1JACK 56 VVIINN+– LTC24U140CGN GSDNOD 111265 5 74UH3CC14 6 9 74UH3CD14 8 49R.59 R3k6 GND BANANA JACK 10 1 J8 1 GND R7 VIN+ GND GND GND GND 22k 3Q1 1 7 8 9 MMBT3904LT1 BANJ9ANA 1JACK 1 JP5 R518k 2 VIN– JUMPER BANANA JACK 2 NOTES: VCC J10 1 INSTALL JUMBER JP1 AT PIN 1 AND PIN 2 BYPASS CAP C7 GND INSTALL JUMBER JP2 AT PIN 1 AND PIN 2 FOR U3 0.1µF INSTALL JUMBER JP3 AT PIN 1 AND PIN 2 2410 F57 Figure 57. 24-Bit A/D Demo Board Schematic Figure 58. Display Graphic 2410fa 46 For more information www.linear.com/LTC2410

LTC2410 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641 Rev B) .189 – .196* .045 ±.005 (4.801 – 4.978) .009 (0.229) 16 15 14 13 12 11 109 REF .254 MIN .150 – .165 .229 – .244 .150 – .157** (5.817 – 6.198) (3.810 – 3.988) .0165 ±.0015 .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 .015 ±.004 × 45° .0532 – .0688 .004 – .0098 (0.38 ±0.10) (1.35 – 1.75) (0.102 – 0.249) .007 – .0098 0° – 8° TYP (0.178 – 0.249) .016 – .050 .008 – .012 .0250 (0.406 – 1.270) (0.203 – 0.305) (0.635) GN16 REV B 0212 NOTE: TYP BSC 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE 4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 2410fa 47 For more information www.linear.com/LTC2410

LTC2410 PCB LAYOUT AND FILM Silkscreen Top Top Layer 2410fa 48 For more information www.linear.com/LTC2410

LTC2410 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 08/15 Updated f maximum to 500kHz and all associated information. 5, 9, 30, 31 EOSC Removed 52.5Hz noise histograms. 6, 7 2410fa 49 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconneFcotior nm oof irtse ciinrcfouirtms aast dioensc wribwedw h.leinreeina rw.cilol nmot/ LinTfCrin2g4e1 o0n existing patent rights.

LTC2410 PCB LAYOUT AND FILM Bottom Layer RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1019 Precision Bandgap Reference, 2.5V, 5V 3ppm/°C Drift, 0.05% Max LT1025 Micropower Thermocouple Cold Junction Compensator 80µA Supply Current, 0.5°C Initial Accuracy LTC1043 Dual Precision Instrumentation Switched Capacitor Precise Charge, Balanced Switching, Low Power Building Block LTC1050 Precision Chopper Stabilized Op Amp No External Components 5µV Offset, 1.6µV Noise P-P LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max, 5ppm/°C Drift LT1460 Micropower Series Reference 0.075% Max, 10ppm/°C Max Drift, 2.5V, 5V and 10V Versions LTC2400 24-Bit, No Latency ∆Σ ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2401/LTC2402 1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP 0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2404/LTC2408 4-/8-Channel, 24-Bit, No Latency ∆Σ ADC 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA LTC2411 24-Bit, No Latency ∆Σ ADC in MSOP 1.45µVRMS Noise, 4ppm INL LTC2413 24-Bit, No Latency ∆Σ ADC Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise LTC2420 20-Bit, No Latency ∆Σ ADC in SO-8 1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400 LTC2424/LTC2428 4-/8-Channel, 20-Bit, No Latency ∆Σ ADCs 1.2ppm Noise, 8ppm INL Pin Compatible with LTC2404/LTC2408 2410fa 50 Linear Technology Corporation LT 0815 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2410 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2410  LINEAR TECHNOLOGY CORPORATION 2000

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: LTC2410CGN#PBF LTC2410CGN LTC2410CGN#TR LTC2410CGN#TRPBF LTC2410IGN#TR LTC2410IGN LTC2410IGN#TRPBF LTC2410IGN#PBF