LTC2360/LTC2361/LTC2362 100ksps/250ksps/500ksps, 12-Bit Serial ADCs in TSOT-23 FEATURES DESCRIPTION n 12-Bit Resolution The LTC®2360/LTC2361/LTC2362 are 100ksps/250ksps/ n Low Noise: 73dB SNR 500ksps, 12-bit, sampling A/D converters that draw only n Low Power Dissipation: 1.5mW at 100ksps 0.5mA, 0.75mA and 1.1mA, respectively, from a single n 100ksps/250ksps/500ksps Sampling Rates 3V supply. The supply current drops at lower sampling n Single Supply 2.35V to 3.6V Operation rates because these devices automatically power down n No Data Latency after conversions. The full-scale input of the LTC2360/ n Sleep Mode with 0.1μA Typical Supply Current LTC2361/LTC2362 is 0V to V or V . These ADCs are DD REF n Dedicated External Reference (TSOT23-8) available in tiny 6- and 8-lead TSOT-23 packages. n 1V to 3.6V Digital Output Supply (TSOT23-8) The serial interface, tiny TSOT-23 package and extremely n SPI/MICROWIRE™ Compatible Serial I/O high sample rate-to-power ratio make the LTC2360/ n Guaranteed Operation from –40°C to 125°C LTC2361/LTC2362 ideal for compact, low power, high n Tiny 6- and 8-Lead TSOT-23 Packages speed systems. APPLICATIONS The high impedance single-ended analog input and the ability to operate with reduced spans (down to 1.4V full n Communication Systems scale) allow direct connection to sensors and transducers in n Data Acquisition Systems many applications, eliminating the need for gain stages. n Handheld Portable Devices n Uninterrupted Power Supplies L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Battery-Operated Systems n Automotive TYPICAL APPLICATION 12-Bit TSOT23-6/-8 ADC Family DATA OUTPUT RATE 3Msps 1Msps 500ksps 250ksps 100ksps Part Number LTC2366 LTC2365 LTC2362 LTC2361 LTC2360 Single 3V Supply, 500ksps, 12-Bit Sampling ADC Supply Current vs Sample Rate 1200 3V VDD = 3.6V TA = 25°C 2.2μF 1000 A) LTC2362 T (μ 800 VDD CONV EN LTC2361 SERIAL DATA LINK TO RR VREF SCK ASIC, PLD, MPU, DSP CU 600 OR SHIFT REGISTORS LY LTC2362 GND SDO UPP 400 ANALO0GV ITNOP U3VT AIN OVDD D1VIG TITOA VLD ODUTPUT SUPPLY S LTC2360 200 2.2μF 236012 TA01a 0 1 10 100 1000 SAMPLE RATE (ksps) 236012 TA01b 236012fa 1

LTC2360/LTC2361/LTC2362 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (V ) ..................................................4V Operating Temperature Range DD Supply Voltage (OV ) ................Min (V + 0.3V, 4.0V) LTC2360C/LTC2361C/LTC2362C ..............0°C to 70°C DD DD V and Analog Input Voltage LTC2360I/LTC2361I/LTC2362I ..............–40°C to 85°C REF (Note 3) .........................................–0.3V to (V + 0.3V) LTC2360H/LTC2361H/LTC2362H (Note 12) ..–40°C to 125°C DD Digital Input Voltage ......................–0.3V to (V + 0.3V) Storage Temperature Range ...................–65°C to 150°C DD Digital Output Voltage ...................–0.3V to (V + 0.3V) Lead Temperature (Soldering, 10 sec) ..................300°C DD Power Dissipation ...............................................100mW PIN CONFIGURATION TOP VIEW TOP VIEW VDD 1 8 CONV VDD 1 6 CONV VREF 2 7 SCK GND 2 5 SDO GND 3 6 SDO AIN 4 5 OVDD AIN 3 4 SCK TS8 PACKAGE S6 PACKAGE 8-LEAD PLASTIC TSOT-23 6-LEAD PLASTIC TSOT-23 TJMAX = 150°C, θJA = 250°C/W TJMAX = 150°C, θJA = 250°C/W ORDER INFORMATION Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2362CTS8#TRMPBF LTC2362CTS8#TRPBF LTDBV 8-Lead Plastic TSOT23 0°C to 70°C LTC2362ITS8#TRMPBF LTC2362ITS8#TRPBF LTDBV 8-Lead Plastic TSOT23 -40°C to 85°C LTC2362HTS8#TRMPBF LTC2362HTS8#TRPBF LTDBV 8-Lead Plastic TSOT23 -40°C to 125°C LTC2362CS6#TRMPBF LTC2362CS6#TRPBF LTDGP 6-Lead Plastic TSOT23 0°C to 70°C LTC2362IS6#TRMPBF LTC2362IS6#TRPBF LTDGP 6-Lead Plastic TSOT23 -40°C to 85°C LTC2362HS6#TRMPBF LTC2362HS6#TRPBF LTDGP 6-Lead Plastic TSOT23 -40°C to 125°C LTC2361CTS8#TRMPBF LTC2361CTS8#TRPBF LTDGM 8-Lead Plastic TSOT23 0°C to 70°C LTC2361ITS8#TRMPBF LTC2361ITS8#TRPBF LTDGM 8-Lead Plastic TSOT23 -40°C to 85°C LTC2361HTS8#TRMPBF LTC2361HTS8#TRPBF LTDGM 8-Lead Plastic TSOT23 -40°C to 125°C LTC2361CS6#TRMPBF LTC2361CS6#TRPBF LTDGN 6-Lead Plastic TSOT23 0°C to 70°C LTC2361IS6#TRMPBF LTC2361IS6#TRPBF LTDGN 6-Lead Plastic TSOT23 -40°C to 85°C LTC2361HS6#TRMPBF LTC2361HS6#TRPBF LTDGN 6-Lead Plastic TSOT23 -40°C to 125°C LTC2360CTS8#TRMPBF LTC2360CTS8#TRPBF LTDGJ 8-Lead Plastic TSOT23 0°C to 70°C LTC2360ITS8#TRMPBF LTC2360ITS8#TRPBF LTDGJ 8-Lead Plastic TSOT23 -40°C to 85°C LTC2360HTS8#TRMPBF LTC2360HTS8#TRPBF LTDGJ 8-Lead Plastic TSOT23 -40°C to 125°C LTC2360CS6#TRMPBF LTC2360CS6#TRPBF LTDGK 6-Lead Plastic TSOT23 0°C to 70°C LTC2360IS6#TRMPBF LTC2360IS6#TRPBF LTDGK 6-Lead Plastic TSOT23 -40°C to 85°C LTC2360HS6#TRMPBF LTC2360HS6#TRPBF LTDGK 6-Lead Plastic TSOT23 -40°C to 125°C TRM = 500 pieces. *Temperature grades are identifi ed by a label on the shipping container. Consult LTC Marketing for information on lead based fi nish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/ 236012fa 2

LTC2360/LTC2361/LTC2362 CONVERTER CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. (Note 4) A PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) l 12 Bits Integral Linearity Error (Notes 5, 6) l ±0.25 ±1 LSB Differential Linearity Error (Note 6) l ±0.25 ±1 LSB Transition Noise (Note 7) 0.25 LSB RMS Offset Error (Note 6) l 1 ±3.5 LSB Gain Error (Note 6) l 0.1 ±2 LSB Total Unadjusted Error (Note 6) l 1.1 ±3.5 LSB ANALOG INPUT The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Analog Input Voltage S6 Package l –0.05 V + 0.05 V IN DD TS8 Package l –0.05 V + 0.05 REF I Analog Input Leakage Current CONV = High l ±1 μA IN C Analog Input Capacitance Between Conversions 20 pF IN During Conversions 4 pF V Reference Input Voltage TS8 Package l 1.4 V + 0.05 V REF DD I Reference Input Leakage Current TS8 Package l ±1 μA REF C Reference Input Capacitance TS8 Package 20 pF REF t Sample-and-Hold Aperture Delay Time 1 ns AP t Sample-and-Hold Aperture Delay Time Jitter 0.3 ns JITTER DYNAMIC ACCURACY The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SINAD Signal-to-(Noise + Distortion) Ratio f = 49kHz for LTC2360/LTC2361, 72 dB IN f = 100kHz for LTC2362 IN SNR Signal-to-Noise Ratio f = 49kHz for LTC2360/LTC2361, 73 dB IN f = 100kHz for LTC2362 IN THD Total Harmonic Distortion f = 49kHz for LTC2360/LTC2361, –85 dB IN f = 100kHz for LTC2362 IN SFDR Spurious Free Dynamic Range f = 49kHz for LTC2360/LTC2361, 86 dB IN f = 100kHz for LTC2362 IN IMD Intermodulation Distortion f = 97kHz, f = 100kHz for LTC2362 –75 dB IN1 IN2 f = 47kHz, f = 49kHz for LTC2360/LTC2361 IN1 IN2 Full-Power Bandwidth at 3dB 10 MHz at 0.1dB 2 MHz Full-Linear Bandwidth SINAD ≥ 68dB 1 MHz 236012fa 3

LTC2360/LTC2361/LTC2362 DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V High Level Input Voltage 2.7V < V ≤ 3.6V l 2 V IH DD 2.35V ≤ V ≤ 2.7V l 1.7 V DD V Low Level Input Voltage 2.7V < V ≤ 3.6V l 0.8 V IL DD 2.35V ≤ V ≤ 2.7V l 0.7 V DD I High Level Input Current V = V l 2.5 μA IH IN DD I Low Level Input Current V = 0V l –2.5 μA IL IN C Digital Input Capacitance 2 pF IN V High Level Output Voltage V = 2.35V to 3.6V, I = 200μA l V – 0.2 V OH DD SOURCE DD V Low Level Output Voltage V = 2.35V to 3.6V, I = 200μA l 0.2 V OL DD SINK I Hi-Z Output Leakage CONV = V l ±3 μA OZ DD C Hi-Z Output Capacitance CONV = V 4 pF OZ DD I Output Source Current V = 0V –10 mA SOURCE OUT I Output Sink Current V = V 10 mA SINK OUT DD POWER REQUIREMENT The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Supply Voltage l 2.35 3.0 3.6 V DD OV Digital Output Supply Voltage l 1.0V V V DD DD I Supply Current DD Operational Mode, LTC2362 f = 500ksps l 1.1 2 mA SMPL Operational Mode, LTC2361 f = 250ksps l 0.75 1.5 mA SMPL Operational Mode, LTC2360 f = 100ksps l 0.5 1 mA SMPL Sleep Mode 0°C to 70°C l 0.1 2 μA Sleep Mode –40°C to 85°C l 0.1 2 μA Sleep Mode –40°C to 125°C l 0.1 5 μA P Power Dissipation D Operational Mode, LTC2362 f = 500ksps l 3.3 7.2 mW SMPL Operational Mode, LTC2361 f = 250ksps l 2.25 5.4 mW SMPL Operational Mode, LTC2360 f = 100ksps l 1.5 3.6 mW SMPL Sleep Mode 0°C to 70°C l 0.3 7.2 μW Sleep Mode –40°C to 85°C l 0.3 7.2 μW Sleep Mode –40°C to 125°C l 0.3 18 μW 236012fa 4

LTC2360/LTC2361/LTC2362 TIMING CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. (Note 4) A LTC2360 LTC2361 LTC2362 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS f Maximum Sampling Frequency (Notes 8, 9) l 100 250 500 kHz SMPL(MAX) f Shift Clock Frequency (Notes 8, 9) l 10 25 50 MHz SCK t Shift Clock Period l 100 40 20 ns SCK t Minimum Throughput Time, t + t l 10 4 2 μs THROUGHPUT ACQ CONV t Acquisition Time l 2 1 0.5 μs ACQ t Conversion Time l 8 3 1.5 μs CONV t Minimum Positive CONV Pulse Width (Note 8) l 8 3 1.5 μs 1 t2 SCK↑ Setup Time After CONV↓ (Note 8) l 16 16 16 ns t3 SDO Enabled Time After CONV↓ (Notes 8, 9) l 16 16 16 ns t4 SDO Data Valid Access Time After SCK↓ (Notes 8, 9, 10) l 8 8 8 ns t SCK Low Time (Note 11) l 40% 40% 40% t 5 SCK t SCK High Time (Note 11) l 40% 40% 40% t 6 SCK t7 SDO Data Valid Hold Time After SCK↓ (Notes 8, 9, 10) l 4 4 4 ns t8 SDO Into Hi-Z State Time After CONV↑ (Notes 8, 9) 6 6 6 ns Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 6: Linearity, offset and gain specifi cations apply for a single-ended may cause permanent damage to the device. Exposure to any Absolute AIN input with respect to GND. Maximum Rating condition for extended periods may affect device Note 7: Typical RMS noise at code transitions. reliability and lifetime. Note 8: Guaranteed by characterization. All input signals are specifi ed with Note 2: All voltage values are with respect to GND. t = t = 2ns (10% to 90% of V ) and timed from a voltage level of 1.6V. r f DD Note 3: When pins AIN and VREF are taken below GND or above VDD, Note 9: All timing specifi cations given are with a 10pF capacitance load. they will be clamped by internal diodes. These products can handle input With a capacitance load greater than this value, a digital buffer or latch currents greater than 100mA below GND or above VDD without latch-up. must be used. Note 4: VDD = OVDD = VREF = 2.35V to 3.6V, fSMPL = fSMPL(MAX) and Note 10: The time required for the output to cross the VIH or VIL voltage. f = f unless otherwise specifi ed. SCK SCK(MAX) Note 11: Guaranteed by design, not subject to test. Note 5: Integral linearity is defi ned as the deviation of a code from a Note 12: High temperatures degrade operating lifetimes. Operating lifetime straight line passing through the actual endpoints of the transfer curve. is derated at temperatures greater than 105°C. The deviation is measured from the center of the quantization band. 236012fa 5

LTC2360/LTC2361/LTC2362 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, V = OV = V (LTC2360, Note 4) A DD DD REF Integral Nonlinearity Differential Nonlinearity Integral and Differential Nonlinearity vs Output Code vs Output Code vs Reference Voltage (TS8 Package) 1 1 1 VDD = 3V VDD = 3V 0.8 0.8 0.8 VDD = 3.6V 0.6 0.6 B) 0.6 0.4 0.4 R (LS 0.4 MAX DNL O INL (LSB)–00..202 DNL (LSB)–00..202 ARITY ERR–00..202 MAX INL MIN INL E –0.4 –0.4 LIN–0.4 MIN DNL N O –0.6 –0.6 N–0.6 –0.8 –0.8 –0.8 –1 –1 –1 0 512 1024153620482560307235844096 0 512 1024153620482560307235844096 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 OUTPUT CODE OUTPUT CODE REFERENCE VOLTAGE (V) 236012 G01 236012 G02 236012 G03 Reference Current vs Sample Histogram for 16384 Conversions Supply Current vs Sample Rate Rate (TS8 Package) 10000 500 20.0 VDD = 3V VDD = 3.6V VDD = 3.6V 8000 400 16.0 COUNT 46000000 LY CURRENT (μA)230000 NCE CURRENT (μA)182..00 P E P R U E S EF 2000 100 R 4.0 0 0 0.0 2045 2046 2047 2048 2049 2050 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 CODE SAMPLING FREQUENCY (ksps) SAMPLE RATE (ksps) 236012 G04 236012 G05 236012 G06 SINAD vs Input Frequency THD vs Input Frequency 48kHz Sine Wave 8192 FFT Plot 74 –78 0 VDD = 3.6V VDD = 3V –80 –20 fSMPL = 100ksps 73 VDD = 3.0V VDD = 2.35V –82 VDD = 2.35V B)–40 SINAD (dB) 7721 THD (dB) ––8846 VDD = 3.6V AGNITUDE (d––6800 M –88 –100 70 –90 –120 VDD = 3.0V 69 –92 –140 1 10 100 1 10 100 0 10 20 30 40 50 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) 236012 G07 236012 G08 2306012 G09 236012fa 6

LTC2360/LTC2361/LTC2362 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, V = OV = V (LTC2361, Note 4) A DD DD REF Integral Nonlinearity Differential Nonlinearity Integral and Differential Nonlinearity vs Output Code vs Output Code vs Reference Voltage (TS8 Package) 1 1 1 VDD = 3V VDD = 3V VDD = 3.6V 0.8 0.8 0.8 0.6 0.6 SB) 0.6 MAX DNL L 0.4 0.4 R ( 0.4 O INL (LSB)–00..202 DNL (LSB)–00..202 ARITY ERR–00..202 MAX INL MIN INL E N –0.4 –0.4 LI–0.4 MIN DNL N O –0.6 –0.6 N–0.6 –0.8 –0.8 –0.8 –1 –1 –1 0 512 1024153620482560307235844096 0 512 1024153620482560307235844096 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 OUTPUT CODE OUTPUT CODE REFERENCE VOLTAGE (V) 236012 G10 236012 G11 236012 G12 Reference Current vs Sample Histogram for 16384 Conversions Supply Current vs Sample Rate Rate (TS8 Package) 10000 800 50.0 VDD = 3V VDD = 3.6V VDD = 3.6V 8000 40.0 T (μA)600 NT (μA) COUNT 46000000 LY CURREN400 NCE CURRE2300..00 P E P R U E S200 EF 2000 R10.0 0 0 0.0 2045 2046 2047 2048 2049 2050 0 50 100 150 200 250 0 50 100 150 200 250 CODE SAMPLE RATE (ksps) SAMPLE RATE (ksps) 236012 G13 236012 G14 236012 G15 SINAD vs Input Frequency THD vs Input Frequency 124kHz Sine Wave 8192 FFT Plot 74 –71 0 VDD = 3.6V VDD = 3.0V –73 –20 VfSDMDP =L =3 V250ksps 73 –75 –77 –40 NAD (dB) 72 VDD = 2.35V HD (dB) ––7891 VDD = 2.35V NITUDE (dB)––6800 SI 71 T –83 G A M –85 VDD = 3.6V –100 70 –87 –120 –89 69 –91 VDD = 3.0V –140 1 10 100 1000 1 10 100 1000 0 25 50 75 100 125 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) 2306012 G16 236012 G17 2306012 G18 236012fa 7

LTC2360/LTC2361/LTC2362 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, V = OV = V (LTC2362, Note 4) A DD DD REF Integral Nonlinearity Differential Nonlinearity Integral and Differential Nonlinearity vs Output Code vs Output Code vs Reference Voltage (TS8 Package) 1 1 1 VDD = 3V VDD = 3V 0.8 0.8 0.8 VDD = 3.6V 0.6 0.6 B) 0.6 0.4 0.4 R (LS 0.4 MAX DNL O INL (LSB)–00..202 DNL (LSB)–00..202 ARITY ERR–00..202 MAX INL MIN INL E N –0.4 –0.4 LI–0.4 MIN DNL N O –0.6 –0.6 N–0.6 –0.8 –0.8 –0.8 –1 –1 –1 0 512 1024153620482560307235844096 0 512 1024153620482560307235844096 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 OUTPUT CODE OUTPUT CODE REFERENCE VOLTAGE (V) 236012 G19 236012 G20 236012 G21 Reference Current vs Sample Histogram for 16384 Conversions Supply Current vs Sample Rate Rate (TS8 Package) 10000 1200 80.0 VDD = 3V VDD = 3.6V VDD = 3.6V 1000 8000 COUNT 46000000 LY CURRENT (μA) 680000 NCE CURRENT (μA)6400..00 PP 400 RE U E S EF20.0 2000 R 200 0 0 0.0 2045 2046 2047 2048 2049 2050 0 100 200 300 400 500 0 50 100150200250300350400450500 CODE SAMPLE RATE (ksps) SAMPLE RATE (ksps) 236012 G22 236012 G23 236012 G24 SINAD vs Input Frequency THD vs Input Frequency 248kHz Sine Wave 8192 FFT Plot 74 –67 0 VDD = 3.6V –20 VfSDMDP =L =3 V500ksps –71 73 VDD = 3.0V –40 –75 B) d SINAD (dB) 7721 VDD = 2.35V THD (dB)–79 VDD = 2.35V AGNITUDE (––6800 –83 M VDD = 3.0V –100 VDD = 3.6V 70 –87 –120 69 –91 –140 1 10 100 1000 1 10 100 1000 0 50 100 150 200 250 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) 2306012 G25 2306012 G26 2306012 G27 236012fa 8

LTC2360/LTC2361/LTC2362 PIN FUNCTIONS S6 Package TS8 Package V (Pin 1): Positive Supply. The V range is 2.35V to V (Pin 1): Positive Supply. The V range is 2.35V to DD DD DD DD 3.6V. V also defi nes the input span of the ADC, 0V to 3.6V. Bypass to GND and to a solid ground plane with a DD V . Bypass to GND and to a solid ground plane with a 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel DD 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel with 0.1μF ceramic). with 0.1μF ceramic). V (Pin 2): Reference Input. V defi nes the input REF REF GND (Pin 2): Ground. The GND pin must be tied directly span of the ADC, 0V to V . The V range is 1.4V to REF REF to a solid ground plane. V . Bypass to GND and to a solid ground plane with a DD 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel A (Pin 3): Analog Input. A is a single-ended input with IN IN with 0.1μF ceramic). respect to GND with a range from 0V to V . DD GND (Pin 3): Ground. The GND pin must be tied directly SCK (Pin 4): Shift Clock Input. The SCK serial clock syn- to a solid ground plane. chronizes the serial data transfer. SDO data transitions on the falling edge of SCK. A (Pin 4): Analog Input. A is a single-ended input with IN IN respect to GND with a range from 0V to V . SDO (Pin 5): Three-State Serial Data Output. The A/D REF conversion result is shifted out on SDO as a serial data OV (Pin 5): Output Driver Supply for SDO. The OV DD DD stream with MSB fi rst. The data stream consists of 12 bits range is 1V to V . Bypass to GND and to a solid ground DD of conversion data followed by trailing zeros. plane with a 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel with 0.1μF ceramic). OV can be driven separately CONV (Pin 6): Convert Input. This active high signal starts DD from V and OV can be higher than V . a conversion on the rising edge. The device automatically DD DD DD powers down after conversion. A logic low on this input SDO (Pin 6): Three-State Serial Data Output. The A/D enables the SDO pin, allowing the data to be shifted out. conversion result is shifted out on SDO as a serial data stream with MSB fi rst. The data stream consists of 12 bits of conversion data followed by trailing zeros. SCK (Pin 7): Shift Clock Input. The SCK serial clock syn- chronizes the serial data transfer. SDO data transitions on the falling edge of SCK. CONV (Pin 8): Convert Input. This active high signal starts a conversion on the rising edge. The device automatically powers down after conversion. A logic low on this input enables the SDO pin, allowing the data to be shifted out. 236012fa 9

LTC2360/LTC2361/LTC2362 BLOCK DIAGRAM 2.2μF 2.2μF + + 1 5 VDD OVDD ANALOG AIN INPUT RANGE 4 THREE-STATE 0V TO VREF S AND H 12-BIT ADC SERIAL SDO 6 OUTPUT PORT VREF 2 SCK 2.2μF GND TIMING 7 LOGIC CONV 3 8 TS8 PACKAGE 236012 BD TIMING DIAGRAMS t8 t7 CONV 1.6V SCK 1.6V Hi-Z SDO VIH 236012 F01 SDO VIL 236012 F02 Figure 1. SDO Into Hi-Z State After CONV Rising Edge Figure 2. SDO Data Valid Hold Time After SCK Falling Edge t4 SCK 1.6V VIH SDO VIL 236012 F03 Figure 3. SDO Data Valid Acess Time After SCK Falling Edge 236012fa 10

LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION DC PERFORMANCE DYNAMIC PERFORMANCE The noise of an ADC can be evaluated in two ways: sig- The LTC2360/LTC2361/LTC2362 have excellent high speed nal-to-noise ratio (SNR) in the frequency domain and sampling capability. Fast fourier transform (FFT) test histogram in the time domain. The LTC2360/LTC2361/ techniques are used to test the ADCs’ frequency response, LTC2362 excel in both. Figure 5 demonstrates that the distortion and noise at the rated throughput. By applying LTC2360/LTC2361/LTC2362 have an SNR of over 73dB. a low distortion sine wave and analyzing the digital output The noise in the time domain histogram is the transition using an FFT algorithm, the ADCs’ spectral content can noise associated with a 12-bit resolution ADC which can be examined for frequencies outside the fundamental. be measured with a fi xed DC signal applied to the input of Figures 5 and 6 show typical LTC2361 and LTC2362 FFT the ADC. The resulting output codes are collected over a plots respectively. large number of conversions. The shape of the distribu- tion of codes will give an indication of the magnitude of the transition noise. In Figure 4, the distribution of output codes is shown for a DC input that has been digitized 16384 times. The distribution is Gaussian and the RMS code transition is about 0.32LSB. This corresponds to a noise level of 73dB relative to a full scale of 3V. 10000 VDD = 3V 8000 6000 T N U O C 4000 2000 0 2045 2046 2047 2048 2049 2050 CODE 236012 F04 Figure 4. Histogram for 16384 Conversions 0 0 VDD = 3V VDD = 3V –20 fSMPL = 250ksps –20 fSMPL = 500ksps fIN = 124kHz fIN = 248kHz SINAD = 73dB SINAD = 73dB –40 THD = –84dB –40 THD = –81dB B) B) d d E ( –60 E ( –60 D D U U T T NI –80 NI –80 G G A A M M –100 –100 –120 –120 –140 –140 0 25 50 75 100 125 0 50 100 150 200 250 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) 236012 F05 236012 F06 Figure 5. LTC2361 FFT Plot Figure 6. LTC2362 FFT Plot 236012fa 11

LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION Signal-to-Noise plus Distortion Ratio rate of 500kHz, the LTC2362 maintains ENOB above 11 bits up to the Nyquist input frequency of 250kHz (refer The signal-to-noise plus distortion ratio (SINAD) is the to Figure 7). ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other fre- Total Harmonic Distortion quency components at the A/D output. The output is band limited to frequencies from above DC and below half the The total harmonic distortion (THD) is the ratio of the RMS sampling frequency. Figure 6 shows a typical FFT with a sum of all harmonics of the input signal to the fundamental 500kHz sampling rate and a 248kHz input. The dynamic itself. The out-of-band harmonics alias into the frequency performance is excellent for input frequencies up to and band between DC and half the sampling frequency. THD beyond the Nyquist frequency of 250kHz. is expressed as: Effective Number of Bits V 2+V 2+V 2+...V 2 THD=20log 2 3 4 n V The effective number of bits (ENOB) is a measurement of 1 the resolution of an ADC and is directly related to SINAD where V is the RMS amplitude of the fundamental by the equation: 1 frequency and V through V are the amplitudes of the 2 n SINAD–1.76 second through nth harmonics. THD vs Input Frequency ENOB= 6.02 is shown in Figure 8. The LTC2362 has excellent distortion performance up to the Nyquist frequency and beyond. where ENOB is the effective number of bits of resolution and SINAD is expressed in dB. At the maximum sampling 74 12 –67 VDD = 3.6V 73 –71 VDD = 3.0V 72 11.67 –75 SINAD (dB) 7701 VDD = 2.35V 11.34ENOB THD (dB)–79 VDD = 2.35V –83 69 VDD = 3.0V VDD = 3.6V –87 68 11 67 –91 1 10 100 1000 1 10 100 1000 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) 2306012 F07 2306012 F08 Figure 7. LTC2362 ENOB and SINAD vs Input Frequency Figure 8. LTC2362 THD vs Input Frequency 236012fa 12

LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION Intermodulation Distortion Peak Harmonic or Spurious Noise If the ADC input signal consists of more than one spectral The peak harmonic or spurious noise is the largest spectral component, the ADC transfer function nonlinearity can component excluding the input signal and DC. This value produce intermoduation distortion (IMD) in addition to is expressed in decibels relative to the RMS value of a THD. IMD is the change in one sinusoidal input caused full-scale input signal. by the presence of another sinusoidal input at a different frequency. Full-Power and Full-Linear Bandwidth If two pure sine waves of frequencies f and f are applied The full-power bandwidth is that input frequency at which a b to the ADC input, nonlinearities in the ADC transfer function the amplitude of reconstructed fundamental is reduced by can create distortion products at the sum and difference 3dB for full-scale input signal. frequencies of mf ± nf , where m and n = 0, 1, 2, 3, etc. a b The full-linear bandwidth is the input frequency at which the For example, the 2nd order IMD terms include (f ± f ). a b SINAD has dropped to 68dB (11 effective bits). The LTC2362 If the two input sine waves are equal in magnitude, the has been designed to optimize input bandwidth, allowing the value (in decibels) of the 2nd order IMD products can be ADC to undersample input signals with frequencies above expressed by the following formula: the converter’s Nyquist frequency. The noise fl oor stays ( ) ( ) Amplitude at f ±f very low at high frequencies; SINAD becomes dominated IMD f ±f =20log a b by distortion at frequencies far beyond Nyquist. a b Amplitude at f a 0 VDD = 3.6V –20 fSMPL = 500ksps fa = 99kHz fb = 101kHz B)–40 IMD = –76.5dB d E ( D U–60 T NI G A M–80 –100 –120 0 50 100 150 200 250 INPUT FREQUENCY (kHz) 236012 F09 Figure 9. LTC2362 Intermodulation Distortion Plot 236012fa 13

LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION OVERVIEW Data Transfer The LTC2360/LTC2361/LTC2362 use a successive ap- A rising CONV edge starts a conversion and disables SDO. proximation algorithm and internal sample-and-hold circuit After the conversion, the ADC automatically goes into sleep to convert an analog signal to a 12-bit serial output. All mode, drawing only leakage current. devices operate from a single 2.35V to 3.6V supply. The CONV going low enables SDO and clocks out the MSB bit, conversion time of the devices is controlled by an internal B11. SCK then synchronizes the data transfer with each oscillator, which allows the LTC2360/LTC2361/LTC2362 bit being transmitted on the falling SCK edge and can be to sample at a rate of 100ksps, 250ksps and 500ksps captured on the rising SCK edge. After completing the respectively. data transfer, if further SCK clocks are applied with CONV The LTC2360/LTC2361/LTC2362 contain a 12-bit, switched- low, SDO will output zeros indefi nitely (see Figure 10). For capacitor ADC, a sample-and-hold, a serial interface (see example, 16-clocks at SCK will produce the 12-bit data Block Diagram) and are available in tiny 6- or 8-lead and four trailing zeros on SDO. TSOT-23 packages. The S6 package of the LTC2360/LTC2361/LTC2362 uses SLEEP MODE V as the reference and has an analog input range of 0V DD The LTC2360/LTC2361/LTC2362 enter sleep mode to save to V . The ADC samples the analog input with respect to DD power after each conversion if CONV remains high. In sleep GND and outputs the result through the serial interface. mode, all bias currents are shut down and only leakage The TS8 package provides two additional pins: a reference currents remain (about 0.1μA). The sample-and-hold is pin, V , and an output supply pin, OV . The ADC can in hold mode while the ADC is in sleep mode. The ADC REF DD operate with reduced spans down to 1.4V and achieve returns to sample mode after the falling edge of CONV 342μV resolution. OV controls the output swing of the during power-up (see Figure 10). DD digital output pin, SDO, and allows the device to com- Exiting Sleep Mode and Power-Up Time municate with 1.8V, 2.5V or 3V digital systems. By taking CONV low, the ADC powers up and acquires an SERIAL INTERFACE input signal completely after the aquisition time (t ). ACQ After t , the ADC can perform a conversion as described The LTC2360/LTC2361/LTC2362 communicate with micro- ACQ in the Serial Interface section (see Figure 10). controllers, DSPs and other external circuitry via a 3-wire interface. Figure 10 shows the operating sequence of the serial interface. BY TAKING CONV LOW, THE DEVICE POWERS UP CONV AND ACQUIRES AN INPUT ACCURATELY AFTER tACQ tCONV SLEEP MODE t2 t6 SCK RECOMMENDED HIGH OR LOW 1 2 3 4 9 10 11 12 t3 t4 t5 t7 t8 Hi-Z STATE SDO B11 B10 B9 B3 B2 B1 B0* (MSB) 236012 F10 t1 tACQ tTHROUGHPUT *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY Figure 10. LTC2360/LTC2361/LTC2362 Serial Interface Timing Diagram 236012fa 14

LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION ACHIEVING MICROPOWER PERFORMANCE current. To obtain the lowest supply current, bring the CONV pin to GND when it is low and to V when it is high. With typical operating currents of 0.5mA, 0.75mA and DD 1.1mA for the LTC2360/LTC2361/LTC2362 and automati- After the conversion with CONV staying high, the converter cally entering sleep mode right after a conversion, these is in sleep mode and draws only leakage current. The status devices achieve extremely low power consumption over of the SCK input has no effect on supply current during a wide range of sample rates (see Figure 11). The sleep this time. For the best performance, hold SCK either high mode allows the supply current to drop with reduced or low while the ADC is converting. sample rate. Several things must be taken into account to achieve such low power consumption. Minimize the Device Active Time In systems that have signifi cant time between conversions, Minimize Power Consumption in Sleep Mode the ADC draws a minimal amount of power. Figures 12 The LTC2360/LTC2361/LTC2362 enter sleep mode after and 13 show two ways to minimize the amount of time each conversion if CONV remains high and draw only the ADC draws power. In Figure 12, the ADC draws power leakage current (see Figure 10). If the CONV input is not during t and t and is in sleep mode for the rest of ACQ CONV running rail-to-rail, the input logic buffer will draw current. the time. The conversion results are available at the next This current may be large compared to the typical supply CONV falling edge. In Figure 13, the ADC draws twice the power than that in Figure 12, but the conversion results are available during t . The user can use the fastest DATA 1200 VDD = OVDD = VREF = 3.6V SCK available in the system to shorten data transfer time, TA = 25°C 1000 tDATA as long as t4 and t7 are not violated. A) μ T ( 800 SDO Loading N E LTC2361 R UR 600 Capacitive loading on the digital output can increase power C LY LTC2362 consumption. A 100pF capacitor on the SDO pin can add P UP 400 more than 50μA to the supply current at a 200kHz clock S LTC2360 frequency. An extra 50μA or so of current goes into charg- 200 ing and discharging the load capacitor. The same goes for 0 1 10 100 1000 digital lines driven at a high frequency by any logic. The SAMPLE RATE (ksps) C • V • f currents must be evaluated with the troublesome 236012 TA01b ones minimized. Figure 11. Supply Current vs Sample Rate EXECUTING A CONVERSION AND PUTTING SAMPLING INPUT AND THE DEVICE INTO SLEEP MODE TRANSFERRING DATA CONV tACQ tCONV SLEEP MODE SCK RECOMMENDED HIGH OR LOW 1 2 3 4 9 10 11 12 Hi-Z STATE SDO B11 B10 B9 B3 B2 B1 B0 tTHROUGHPUT = tACQ + tCONV + tSLEEPMODE 236012 F12 Figure 12. Minimize the Time When the Device Draws Power, While the Conversion Results are Available After the Device Wakes Up 236012fa 15

LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION EXECUTE CONVERSION EXECUTING A DUMMY CONVERSION AND ACQUIRE DATA TRANSFER PUT THE DEVICE INTO SLEEP MODE INPUT CONV tACQ tCONV tDATA tCONV SLEEP MODE SCK RECOMMENDED HIGH OR LOW RECOMMENDED HIGH OR LOW 1 2 3 4 9 10 11 12 Hi-Z STATE SDO B11 B10 B9 B3 B2 B1 B0 tTHROUGHPUT = tACQ + 2 • tCONV + tDATA + tSLEEPMODE 236012 F13 Figure 13. Minimize the Time When the Device Draws Power, While the Conversion Results are Available Right After Conversion SINGLE-ENDED ANALOG INPUT used, more time for settling can be provided by increasing the time between conversions. The best choice for an op Driving the Analog Input amp to drive the LTC2360/LTC2361/LTC2362 will depend on the application. Generally, applications fall into two The analog input of the LTC2360/LTC2361/LTC2362 is categories: AC applications where dynamic specifi cations easy to drive. The input draws only one small current are most critical and time domain applications where DC spike while charging the sample-and-hold capacitor with accuracy and settling time are most critical. The follow- the ADC going into track mode. During the conversion, ing list is a summary of the op amps that are suitable for the analog input draws only a small leakage current. If driving the LTC2360/LTC2361/LTC2362. (More detailed the source impedance of the driving circuit is low, then information is available on the Linear Technology website at the input of the LTC2360/LTC2361/LTC2362 can be driven www.linear.com.) directly. As source impedance increases, so will acquisi- tion time. For minimum acquisition time with high source LTC1566-1: Low Noise 2.3MHz Continuous Time Low- impedance, a buffer amplifi er should be used. The main pass Filter. requirement is that the amplifi er driving the analog input LT®1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifi er. must settle after the small current spike before the next 2.7V to ±15V supplies. Very high A , 500μV offset and conversion starts (settling time must be less than t VOL ACQ 520ns settling to 0.5LSB for a 4V swing. THD and noise for full throughput rate). While choosing an input ampli- are –93dB to 40kHz and below 1LSB to 320kHz (A = fi er, also keep in mind the amount of noise and harmonic V 1, 2V into 1k, V = 5V), making the part excellent for distortion the amplifi er contributes. P-P S AC applications (to 1/3 Nyquist) where rail-to-rail perfor- mance is desired. Quad version is available as LT1631. Choosing an Input Amplifi er LTC6241: Dual 18MHz, Low Noise, Rail-to-Rail, CMOS Choosing an input amplifi er is easy if a few requirements Voltage FB Amplifi er. 2.8V to 6V supplies. Very high A are taken into consideration. First, to limit the magnitude VOL and 125μV offset. It is suitable for applications with a single of the voltage spike seen by the amplifi er from charging 5V supply. Quad version is available as LTC6242. the sampling capacitor, choose an amplifi er that has a low output impedance (<100Ω) at the closed-loop bandwidth LT1797: Unity-Gain Stable 10MHz, Rail-to-Rail Voltage frequency. For example, if an amplifi er is used in a gain Feedback Amplifi er. of 1 and has a unity-gain bandwidth of 10MHz, then the LT1801: 180MHz GBWP, –75dBc at 500kHz, 2mA/Ampli- output impedance at 10MHz must be less than 100Ω. The fi er, 8.5nV/√Hz. second requirement is that the closed-loop bandwidth must be greater than 8MHz to ensure adequate small-signal LT6203: 100MHz GBWP, –80dBc Distortion at 1MHz, Unity- settling for full throughput rate. If slower op amps are Gain Stable, R-R In and Out, 3mA/Amplifi er, 1.9nV/√Hz. 236012fa 16

LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION Input Filtering and Source Impedance Reference Input The noise and the distortion of the input amplifi er and On the TS8 package of the LTC2360/LTC2361/LTC2362, other circuitry must be considered since they will add to the voltage on the V pin defi nes the full-scale range REF the LTC2360/LTC2361/LTC2362 noise and distortion. The of the ADC. The reference voltage can range from V DD small-signal bandwidth of the sample-and-hold circuit is down to 1.4V. 10MHz. Any noise or distortion products that are pres- ent at the analog inputs will be summed over this entire Input Range bandwidth. Noisy input circuitry should be fi ltered prior The analog input of the LTC2360/LTC2361/LTC2362 is to the analog inputs to minimize noise. A simple 1-pole driven single-ended with respect to GND from a single RC fi lter is suffi cient for many applications. For example, supply. The input may swing up to V for the S6 package DD Figure 14 shows a 220pF capacitor from A to ground IN and to V for the TS8 package. The 0V to 2.5V range is and a 51Ω source resistor to limit the input bandwidth REF also ideally suited for single-ended input use with V or DD to 10MHz. The 220pF capacitor also acts as a charge V = 2.5V for single supply applications. If the difference REF reservoir for the input sample-and-hold and isolates the between the A input and GND exceeds V for the S6 IN DD ADC input from sampling-glitch sensitive circuitry. High package or V for the TS8 package, the output code will REF quality capacitors and resistors should be used since these stay fi xed at all ones, and if this difference goes below 0V, components can add distortion. NPO and silvermica type the output code will stay fi xed at all zeros. dielectric capacitors have excellent linearity. Carbon surface Figure 15 shows the ideal input/output characteristics for mount resistors can generate distortion from self heating the LTC2360/LTC2361/LTC2362. The code transitions oc- and from damage that may occur during soldering. Metal cur midway between successive integer LSB values (i.e., fi lm surface mount resistors are much less susceptible to 0.5LSB, 1.5LSB, 2.5LSB, …, FS – 1.5LSB). The output both problems. When high amplitude unwanted signals code is straight binary with 1LSB = V /4096 for the S6 are close in frequency to the desired signal frequency, DD package and 1LSB = V /4096 for the TS8 package. a multiple pole fi lter is required. High external source REF resistance, combined with the 20pF of input capacitance, will reduce the rated 10MHz bandwidth and increase acquisition time beyond 500ns. 111...111 111...110 E D O C LTC2362 T U 1 6 P VDD CONV UT 2.2μF O 2 5 R GND SDO A L 220pF 3 4 PO AIN SCK NI U 51Ω 236012 F14 000...001 000...000 Figure 14. RC Input Filter 0 1LSB INPUT VOLTAGE (V) FS – 1LSB 236012 F15 Figure 15. Transfer Characteristics 236012fa 17

LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION BOARD LAYOUT AND BYPASSING connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. Wire wrap boards are not recommended for high resolution and/or high speed A/D converters. To obtain the best per- Figure 16 shows the recommended system ground con- formance from the LTC2360/LTC2361/LTC2362, a printed nections. All analog circuitry grounds should be terminated circuit board with ground plane is required. Layout for the at the LTC2360/LTC2361/LTC2362. The ground return printed circuit board should ensure that digital and analog from the LTC2360/LTC2361/LTC2362 to the power supply signal lines are separated as much as possible. In particular, should be low impedance for noise free operation. Digital care should be taken not to run any digital track alongside circuitry grounds must be connected to the digital supply an analog signal track or underneath the ADC. The analog common. input should be screened by the ground plane. In applications where the ADC data outputs and control sig- High quality tantalum and ceramic bypass capacitors nals are connected to a continuously active microprocessor should be used at the V pin as shown in the Block bus, it is possible to get errors in the conversion results. DD Diagram on the fi rst page of this data sheet. For optimum These errors are due to feedthrough from the micropro- performance, a 2.2μF surface mount AVX capacitor with cessor to the successive approximation comparator. The a 0.1μF ceramic is recommended for the V and V problem can be eliminated by forcing the microprocessor DD REF pins. Alternatively, 2.2μF ceramic chip capacitors such as into a wait state during conversion or by using three-state Murata GRM235Y5V106Z016 may be used. The capacitors buffers to isolate the ADC data bus. must be located as close to the pins as possible. The traces CVDD + 2.2μF PIN 1 VDD CONV GND SDO CAIN AIN SCK VIAS TO GROUND PLANE 236012 F16 Figure 16. Power Supply Ground Practice 236012fa 18

LTC2360/LTC2361/LTC2362 PACKAGE DESCRIPTION S6 Package 6-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1636) 0.62 0.95 2.90 BSC MAX REF (NOTE 4) 1.22 REF 3.85 MAX2.62 REF 1.4 MIN 2.80 BSC 1(.5N0O T–E 1 4.7)5 PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT 0.30 – 0.45 0.95 BSC PER IPC CALCULATOR 6 PLCS (NOTE 3) 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 1.90 BSC (NOTE 3) S6 TSOT-23 0302 REV B NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 2. DRAWING NOT TO SCALE 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 3. DIMENSIONS ARE INCLUSIVE OF PLATING 6. JEDEC PACKAGE REFERENCE IS MO-193 TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637) 0.52 0.65 2.90 BSC MAX REF (NOTE 4) 1.22 REF 3.85 MAX2.62 REF 1.4 MIN 2.80 BSC 1(.5N0O T–E 1 4.7)5 PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT 0.22 – 0.36 0.65 BSC PER IPC CALCULATOR 8 PLCS (NOTE 3) 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 1.95 BSC (NOTE 3) TS8 TSOT-23 0802 NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 2. DRAWING NOT TO SCALE 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 3. DIMENSIONS ARE INCLUSIVE OF PLATING 6. JEDEC PACKAGE REFERENCE IS MO-193 236012fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 19 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC2360/LTC2361/LTC2362 TYPICAL APPLICATION Recommended AC Test Circuitry for the LTC2362 3V + + 4.7μF 2.2μF 1k 1% VDD ±1.5V AC INPUT 4.7μF 50(cid:31) CONV 5% TO AIN LTC2362 SCK MCU 220pF SDO 1k GND 2200pF 1% 236012 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS ADCs LTC1403/LTC1403A 12-/14-Bit, 2.8Msps Serial Sampling ADC 3V, Differential Input, 12mW, MSOP Package LTC1407/LTC1407A 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, 14mW, MSOP Package LTC1860 12-Bit, 250ksps Serial ADC 5V Supply, 1-Channel, 4.3mW, MSOP-8 Package LTC1860L 12-Bit, 150ksps Serial ADC 3V Supply, 1-Channel, 1.3mW, MSOP-8 Package LTC1861 12-Bit, 250ksps Serial ADC 5V Supply, 2-Channel, 4.3mW, MSOP-8 Package LTC1861L 12-Bit, 150ksps Serial ADC 3V Supply, 2-Channel, 1.3mW, MSOP-8 Package LTC1863 12-Bit, 200ksps Serial ADC 8-Channel ADC 5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible to LTC1863L, LTC1867 LTC1863L 12-Bit, 250ksps Serial ADC 8-Channel ADC 5V Supply, 2.2mW, SSOP-16 Package, Pin Compatible to LTC1863, LTC1867L LTC1864/LTC1865 16-Bit, 250ksps Serial ADC 5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package LTC1867 16-Bit, 200ksps Serial ADC 8-Channel ADC 5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible to LTC1863, LTC1867L LTC1867L 16-Bit, 175ksps Serial ADC 8-Channel ADC 3V Supply, 2.2mW, SSOP-16 Package, Pin Compatible to LTC1863L, LTC1867 LTC2355/LTC2356 12-/14-Bit, 3.5Msps Serial ADCs 3.3V Supply, Differential Input, 18mW, MSOP Package LTC2365/LTC2366 12-Bit, 1/3 Msps Serial ADCs in TSOT23 2.35V to 3.6V Supply, Pin and Software Compatible to LTC2360/LTC2361/LTC2362 DACs LTC1592 16-Bit, Serial SoftSpan™ I DAC ±1LSB INL/DNL, Software Selectable Spans OUT LTC1666/LTC1667/LTC1668 12-/14-/16-Bit, 50Msps DACs 87dB SFDR, 20ns Settling Time LTC2630 12-/10-/8-Bit Single V DACs SC70 6-Pin Package, Internal Reference, ±1LSB INL (12 Bits) OUT References LT1460-2.5 Micropower Series Voltage Reference 0.1% Initial Accuracy, 10ppm Drift LT1461-2.5 Precision Voltage Reference 0.05% Initial Accuracy, 3ppm Drift LT1790-2.5 Micropower Series Reference in SOT-23 0.05% Initial Accuracy, 10ppm Drift LT6660 Ultra-Tiny Micropower Series Reference 2mm × 2mm DFN Package, 0.2% Initial Accuracy, 10ppm Drift SoftSpan is a trademark of Linear Technology Corporation. 236012fa 20 Linear Technology Corporation LT 0809 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: LTC2362HS6#TRMPBF LTC2361HTS8#TRMPBF LTC2361CS6#PBF LTC2361HTS8#PBF LTC2360IS6#TRMPBF LTC2362IS6#PBF LTC2360ITS8#TRPBF LTC2360CTS8#TRMPBF LTC2361IS6#TRPBF LTC2360CTS8#PBF LTC2361ITS8#TRMPBF LTC2362CS6#PBF LTC2362HTS8#TRPBF LTC2360CS6#TRMPBF LTC2360IS6#TRPBF LTC2361HTS8#TRPBF LTC2361IS6#PBF LTC2362HS6#TRPBF LTC2361CTS8#TRPBF LTC2362CS6#TRPBF LTC2361CS6#TRMPBF LTC2360HTS8#PBF LTC2360HS6#TRMPBF LTC2360CS6#PBF LTC2361ITS8#PBF LTC2360CTS8#TRPBF LTC2361CS6#TRPBF LTC2362ITS8#TRPBF LTC2362CTS8#TRMPBF LTC2361CTS8#PBF LTC2360HTS8#TRPBF LTC2362IS6#TRPBF LTC2362HTS8#PBF LTC2362ITS8#PBF LTC2361ITS8#TRPBF LTC2361HS6#TRPBF LTC2362CS6#TRMPBF LTC2360HS6#TRPBF LTC2360ITS8#PBF LTC2362CTS8#TRPBF LTC2360IS6#PBF LTC2360ITS8#TRMPBF LTC2361HS6#PBF LTC2361IS6#TRMPBF LTC2362HTS8#TRMPBF LTC2362IS6#TRMPBF LTC2362CTS8#PBF LTC2362ITS8#TRMPBF LTC2361CTS8#TRMPBF LTC2360HTS8#TRMPBF LTC2360HS6#PBF LTC2362HS6#PBF LTC2361HS6#TRMPBF LTC2360CS6#TRPBF