LTC2314-14 14-Bit, 4.5Msps Serial Sampling ADC in TSOT FEATURES DESCRIPTION n 4.5Msps Throughput Rate The LTC®2314-14 is a 14-bit, 4.5Msps, serial sampling A/D n Guaranteed 14-Bit No Missing Codes converter that draws only 6.2mA from a wide range analog n Internal Reference: 2.048V/4.096V Span supply adjustable from 2.7V to 5.25V. The LTC2314-14 n Low Noise: 77.5dB SNR contains an integrated bandgap and reference buffer which n Low Power: 6.2mA at 4.5Msps and 5V provide a low cost, high performance (20ppm/°C max) n Dual Supply Range: 3V/5V operation and space saving applications solution. The LTC2314-14 n Sleep Mode with < 1µA Typical Supply Current achieves outstanding AC performance of 77dB SINAD and n Nap Mode with Quick Wake-up < 1 conversion –85dB THD while sampling a 500kHz input frequency. n Separate 1.8V to 5V Digital I/O Supply The extremely high sample rate-to-power ratio makes the n High Speed SPI-Compatible Serial I/O LTC2314-14 ideal for compact, low power, high speed n Guaranteed Operation from –40°C to 125°C systems. The LTC2314-14 also provides both nap and n 8-Lead TSOT-23 Package sleep modes for further optimization of the device power within a system. APPLICATIONS The LTC2314-14 has a high-speed SPI-compatible serial n Communication Systems interface that supports 1.8V, 2.5V, 3V and 5V logic. The n High Speed Data Acquisition fast 4.5Msps throughput makes the LTC2314-14 ideally n Handheld Terminal Interface suited for a wide variety of high speed applications. n Medical Imaging Complete 14-/12-Bit Pin-Compatible SAR ADC Family n Uninterrupted Power Supplies 500ksps 2.5Msps 4.5Msps 5Msps n Battery Operated Systems 14-Bit LTC2312-14 LTC2313-14 LTC2314-14 n Automotive 12-Bit LTC2312-12 LTC2313-12 LTC2315-12 L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Power 3V/5V 9mW/15mW 14mW/25mW 18mW/31mW 19mW/32mW Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 5V Supply, Internal Reference, 4.5Msps, 14-bit Sampling ADC 32k Point FFT, f = 4.5Msps, f = 500kHz S IN 5V 0 2.2µF LTC2314-14 –20 SNR = 7V7D.D5 d=B 5FVS VDD CS SINAD = 76.9dBFS –40 THD = 84.9dB 2.2µF SERIAL DATA LINK TO S) SFDR = 88.1dB REF SCK ASIC, PLD, MPU, DSP BF –60 d OR SHIFT REGISTERS E ( D –80 U GND SDO LIT ANALOG INPUT DIGITAL OUTPUT SUPPLY MP–100 0V TO 4.096V AIN OVDD 2.2µF1.8V TO 5V A–120 –160 231414 TA01 –140 0 250 500 750 100012501500175020002250 FREQUENCY (kHz) 231414 TA01a 231414fa 1 For more information www.linear.com/LTC2314-14

LTC2314-14 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) Supply Voltage (V , OV ) .......................................6V DD DD Reference (REF) and Analog Input (A ) Voltage IN TOP VIEW (Note 3) ......................................(–0.3V) to (V + 0.3V) DD VDD 1 8 CS Digital Input Voltage (Note 3) ..(–0.3V) to (OVDD + 0.3V) REF 2 7 SCK Digital Output Voltage .............(–0.3V) to (OV + 0.3V) GND 3 6 SDO DD Power Dissipation ...............................................100mW AIN 4 5 OVDD TS8 PACKAGE Operating Temperature Range 8-LEAD PLASTIC TSOT-23 LTC2314C ................................................0°C to 70°C TJMAX = 150°C, θJA = 195°C/W LTC2314I..............................................–40°C to 85°C LTC2314H ..........................................–40°C to 125°C Storage Temperature Range ..................–65°C to 150°C Lead Temperature Range (Soldering, 10 sec) ........300°C ORDER INFORMATION Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2314CTS8-14#TRMPBF LTC2314CTS8-14#TRPBF LTFZF 8-Lead Plastic TSOT-23 0°C to 70°C LTC2314ITS8-14#TRMPBF LTC2314ITS8-14#TRPBF LTFZF 8-Lead Plastic TSOT-23 –40˚C to 85˚C LTC2314HTS8-14#TRMPBF LTC2314HTS8-14#TRPBF LTFZF 8-Lead Plastic TSOT-23 –40˚C to 125˚C TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 231414fa 2 For more information www.linear.com/LTC2314-14

LTC2314-14 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Absolute Input Range l –0.05 V + 0.05 V AIN DD V Input Voltage Range (Note 11) 0 V V IN REF I Analog Input DC Leakage Current l –1 1 µA IN C Analog Input Capacitance Sample Mode 13 pF IN Hold Mode 3 pF CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution l 14 Bits No Missing Codes l 14 Bits Transition Noise (Note 6) 0.7 LSB RMS INL Integral Linearity Error V = 5V (Note 5) l –3.75 ±1 3.75 LSB DD V = 3V (Note 5) l –4.25 ±1.5 4.25 LSB DD DNL Differential Linearity Error V = 5V l –0.99 ±0.3 0.99 LSB DD V = 3V l –0.99 ±0.4 0.99 LSB DD Offset Error V = 5V l –9 ±2 9 LSB DD V = 3V l –22 ±4 22 LSB DD Full-Scale Error V = 5V l –18 ±5 18 LSB DD V = 3V l –26 ±7 26 LSB DD Total Unadjusted Error V = 5V l –22 ±6 22 LSB DD V = 3V l –30 ±8 30 LSB DD DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C and A = –1dBFS. (Note 4) A IN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SINAD Signal-to-(Noise + Distortion) Ratio f = 500kHz, V = 5V l 72 77 dB IN DD f = 500kHz, V = 3V l 69 72.6 dB IN DD SNR Signal-to-Noise Ratio f = 500kHz, V = 5V l 73 77.5 dB IN DD f = 500kHz, V = 3V l 69.5 73 dB IN DD THD Total Harmonic Distortion f = 500kHz, V = 5V l –85 –75 dB IN DD First 5 Harmonics f = 500kHz, V = 3V l –85 –74 dB IN DD SFDR Spurious Free Dynamic Range f = 500kHz, V = 5V l –87 –77 dB IN DD f = 500kHz, V = 3V l –87 –75 dB IN DD IMD Intermodulation Distortion 2nd Order Terms f = 461kHz, f = 541kHz –79.4 dBc IN1 IN2 3rd Order Terms A , A = –7dBFS –90.8 dBc IN1 IN2 Full Power Bandwidth At 3dB 130 MHz At 0.1dB 20 MHz –3dB Input Linear Bandwidth SINAD ≥ 74dB 5 MHz t Aperture Delay 1 ns AP t Aperture Jitter 10 ps JITTER RMS 231414fa 3 For more information www.linear.com/LTC2314-14

LTC2314-14 REFERENCE INPUT/OUTPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V V Output Voltage 2.7V ≤ V ≤ 3.6V l 2.040 2.048 2.056 V REF REF DD 4.75 ≤ V ≤ 5.25V l 4.080 4.096 4.112 V DD V Temperature Coefficient l 7 20 ppm/°C REF V Output Resistance Normal Operation 2 Ω REF Overdrive Condition 52 kΩ (V ≥ V + 50mV) REFIN REFOUT V Line Regulation 2.7V ≤ V ≤ 3.6V 0.4 mV/V REF DD 4.75 ≤ V ≤ 5.25V 0.2 mV/V DD V 2.048V/4.096V Supply Threshold 4.15 V REF V 2.048V/4.096V Supply Threshold Hysteresis 150 mV REF V Input Voltage Range 2.7V ≤ V ≤ 3.6V l V + 50mV V V REF DD REF DD (External Reference Input) 4.75 ≤ V ≤ 5.25V l V + 50mV 4.3 V DD REF DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V High Level Input Voltage l 0.8 • OV V IH DD V Low Level Input Voltage l 0.2 • OV V IL DD I Digital Input Current V = 0V to OV l –10 10 μA IN IN DD C Digital Input Capacitance 5 pF IN V High Level Output Voltage I = –500µA (Source) l OV –0.2 V OH O DD V Low Level Output Voltage I = 500µA (Sink) l 0.2 V OL O I High-Z Output Leakage Current V = 0V to OV , CS = High l –10 10 µA OZ OUT DD C High-Z Output Capacitance CS = High 4 pF OZ I Output Source Current V = 0V, OV = 1.8V –20 mA SOURCE OUT DD I Output Sink Current V = OV = 1.8V 20 mA SINK OUT DD POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Supply Voltage DD 3V Operational Range l 2.7 3 3.6 V 5V Operational Range l 4.75 5 5.25 V OV Digital Output Supply Voltage l 1.71 5.25 V DD I = Supply Current, Static Mode CS = 0V, SCK = 0V l 3.2 4 mA TOTAL I I Operational Mode l 6.2 7.2 mA VDD + OVDD Nap Mode 1.8 mA Sleep Mode l 0.8 5 µA P Power Dissipation, Static Mode CS = 0V, SCK = 0V l 16 20 mW D Operational Mode l 31 36 mW Nap Mode 9 mW Sleep Mode l 4 25 µW 231414fa 4 For more information www.linear.com/LTC2314-14

LTC2314-14 ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f Maximum Sampling Frequency (Notes 7, 8) l 4.5 MHz SAMPLE(MAX) f Shift Clock Frequency (Notes 7, 8) l 87.5 MHz SCK t Shift Clock Period l 11.4 ns SCK t Minimum Throughput Time, t + t l 222 ns THROUGHPUT ACQ CONV t Conversion Time l 182 ns CONV t Acquisition Time l 40 ns ACQ t Minimum CS Pulse Width (Note 7) l 10 ns 1 t2 SCK↔ Setup Time After CS↓ (Note 7) l 5 ns t3 SDO Enable Time After CS↓ (Notes 7, 8) l 10 ns t4 SDO Data Valid Access Time after SCK↓ (Notes 7, 8, 9) l 9.1 ns t SCLK Low Time l 4.5 ns 5 t SCLK High Time l 4.5 ns 6 t7 SDO Data Valid Hold Time After SCK↓ (Notes 7, 8, 9) l 1 ns t8 SDO into Hi-Z State Time After 16th SCK↓ (Notes 7, 8, 10) l 3 10 ns t9 SDO into Hi-Z State Time After CS↑ (Notes 7, 8, 10) l 3 10 ns t10 CS↑ Setup Time After 14th SCK↓ (Note 7) l 5 ns Latency l 1 Cycle Latency t _ Power-Up Time from Nap Mode See Nap Mode Section 50 ns WAKE NAP t _ Power-Up Time from Sleep Mode See Sleep Mode Section 1.1 ms WAKE SLEEP Note 1. Stresses beyond those listed under Absolute Maximum Ratings Note 6. Typical RMS noise at code transitions. may cause permanent damage to the device. Exposure to any Absolute Note 7. Parameter tested and guaranteed at OV = 2.5V. All input signals DD Maximum Rating condition for extended periods may affect device are specified with t = t = 1nS (10% to 90% of OV ) and timed from a r f DD reliability and lifetime. voltage level of OV /2. DD Note 2. All voltage values are with respect to ground. Note 8. All timing specifications given are with a 10pF capacitance load. Note 3. When these pin voltages are taken below ground or above V Load capacitances greater than this will require a digital buffer. DD (AIN, REF) or OVDD (SCK, CS, SDO) they will be clamped by internal Note 9. The time required for the output to cross the VIH or VIL voltage. diodes. This product can handle input currents up to 100mA below ground Note 10. Guaranteed by design, not subject to test. or above V or OV without latch-up. DD DD Note 11. Recommended operating conditions. Note 4. V = 5V, OV = 2.5V, f = 4.5MHz, f = 87.5MHz, A = DD DD SMPL SCK IN –1dBFS and internal reference unless otherwise noted. Note 5. Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 231414fa 5 For more information www.linear.com/LTC2314-14

LTC2314-14 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, V = 5V, OV = 2.5V, f = 4.5Msps, A DD DD SMPL unless otherwise noted. Integral Nonlinearity Differential Nonlinearity DC Histogram Near Mid-Scale vs Output Code vs Output Code (Code 8192) 2.0 1.00 7000 σ = 0.7 1.5 0.75 6000 1.0 0.50 5000 0.5 0.25 INL (LSB)–00..50 DNL (LSB)–00..2050 COUNTS 34000000 2000 –1.0 –0.50 –1.5 –0.75 1000 –2.0 –1.00 0 0 4096 8192 12288 16384 0 4096 8192 12288 16384 8194 8195 8196 8197 8198 8199 8200 OUTPUT CODE OUTPUT CODE CODE 231414 G03 231414 G01 231414 G02 32k Point FFT, f = 4.5Msps SNR, SINAD vs Input Frequency THD, Harmonics vs Input S f = 500kHz (100kHz to 2.2MHz) Frequency (100kHz to 2.2MHz) IN 0 78 –75 VDD = 5V SNR RIN/CIN = 50Ω/47pF –20 SISNNARD == 7776..59ddBBFFSS 77 VDD = 5V –80 VfSD =D 4=. 53MVsps AMPLITUDE (dBFS)––––146800000 STFHDDR == 8848..91ddBB SNR, SINAD (dBFS) 777546 SINAD HD, HARMONICS (dB)–––998055 THD 2ND 3RD –120 T SNR 73 –100 –160 VDD = 3V SINAD –140 72 –105 0 250 500 750 100012501500175020002250 0 250 500 750 100012501500175020002250 0 250 500 750 100012501500175020002250 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) 231414 G04 231414 G05 231414 G06 THD, Harmonics vs Input SNR, SINAD vs Temperature, THD, Harmonics vs Temperature, Frequency (100kHz to 2.2MHz) f = 500kHz f = 500kHz IN IN –75 79 –75 RIN/CIN = 50Ω/47pF VDD = 3V fS = 4.5Msps 78 SNR –80 VDD = 5V VDD = 5V –80 MONICS (dB)––9805 3TRHDD 2ND NAD (dBFS) 777567 SINAD MONICS (dB)–85 T2HNDD HD, HAR–95 SNR, SI 74 SNR HD, HAR–90 3RD T 73 VDD = 3V T –100 SINAD –95 72 –105 71 –100 0 250 500 750100012501500175020002250 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 INPUT FREQUENCY (kHz) TEMPERATURE (°C) TEMPERATURE (°C) 231414 G06a 231414 G07 231414 G08 231414fa 6 For more information www.linear.com/LTC2314-14

LTC2314-14 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, V = 5V, OV = 2.5V, f = 4.5Msps, A DD DD SMPL unless otherwise noted. THD, Harmonics vs Temperature, SNR, SINAD vs Reference Voltage Reference Current f = 500kHz f = 500kHz vs Reference Voltage IN IN –75 79 600 VDD = 5V SNR 78 fS = 5Msps 500 –80 THD, HARMONICS (dB)––9805 T32HRNDDD SNR, SINAD (dBFS) 77775476 VDD =S SN3I.RN6AVDOPERATVIODNDS I=N A5VD EFERENCE CURRENT (µA)234000000 fS =VfS D5 =DM 3=sMp 3ss.6pVs OPERAfTSVI O=D N3DM =s 5pVs –95 NOT ALLOWED R NOT ALLOWED 100 73 –100 72 0 –55 –35 –15 5 25 45 65 85 105 125 2 2.5 3 3.5 4 4.5 2 2.5 3 3.5 4 4.5 TEMPERATURE (°C) REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) 231414 G08a 231414 G10 231414 G11 Full-Scale Error vs Temperature Offset Error vs Temperature Supply Current vs Temperature 4 1 6.5 3 VDD = 5V 6.25 LSB) 2 B) 0.5 mA) LL-SCALE ERROR ( –101 OFFSET ERROR (LS 0 UPPLY CURRENT (5.57.556 VDD = 3V U –2 –0.5 S F 5.25 –3 –4 –1 5 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 231414 G12 231414 G13 231414 G14 Supply Current vs SCK Frequency Shutdown Current vs Temperature 7 1 IVDD + IOVDD OVDVDD D= =3 V1.8V 6 WN CURRENT (µA)00.7.55 LY CURRENT (mA) 453 IITVODTD O P TD UP 2 HU0.25 VDD = 3V S S 1 VDD = 5V IOVDD 0 0 10 20 30 40 50 60 70 80 90 –55 –35 –15 5 25 45 65 85 105 125 SCK FREQUENCY (MHz) TEMPERATURE (°C) 231414 G16 231414 G15 231414fa 7 For more information www.linear.com/LTC2314-14

LTC2314-14 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, V = 5V, OV = 2.5V, f = 4.5Msps, A DD DD SMPL unless otherwise noted. Supply Current (I ) Output Supply Current (I ) VDD OVDD vs Supply Voltage (V ) vs Output Supply Voltage (OV ) DD DD 6.50 2.5 5Msps 6.25 mA) 2.0 A)6.00 5Msps T ( m N NT (5.75 fSCK = 87.5MHz RRE 1.5 5Msps URRE5.50 NOOTP EARLALTOIWONED LY CU fSCK = 87.5MHz C P PLY 5.25 3Msps SUP 1.0 UP 3Msps UT S5.00 fSCK = 52.5MHz OUTP 0.5 3fSMCKs p=s 52.5MHz 4.75 4.50 0 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 1.7 2.3 2.9 3.5 4.1 4.7 5.3 SUPPLY VOLTAGE (V) OUTPUT SUPPLY VOLTAGE (V) 231414 G17 231414 G18 PIN FUNCTIONS V (Pin 1): Power Supply. The ranges of V are 2.7V SDO (Pin 6): Serial Data Output. The A/D conversion result DD DD to 3.6V and 4.75V to 5.25V. Bypass V to GND with a is shifted out on SDO as a serial data stream with the MSB DD 2.2µF ceramic chip capacitor. first through the LSB last. There is 1 cycle of conversion latency. Logic levels are determined by OV . REF (Pin 2): Reference Input/Output. The REF pin volt- DD age defines the input span of the ADC, 0V to V . By SCK (Pin 7): Serial Data Clock Input. The SCK serial clock REF default, REF is an output pin and produces a reference falling edge advances the conversion process and outputs voltage V of either 2.048V or 4.096V depending on a bit of the serialized conversion result, MSB first to LSB REF V (see Table 2). Bypass to GND with a 2.2µF, low ESR, last. SDO data transitions on the falling edge of SCK. A DD high quality ceramic chip capacitor. The REF pin may be continuous or burst clock may be used. Logic levels are overdriven with a voltage at least 50mV higher than the determined by OV . DD internal reference voltage output. CS (Pin 8): Chip Select Input. This active low signal starts GND (Pin 3): Ground. The GND pin must be tied directly a conversion on the falling edge and frames the serial data to a solid ground plane. transfer. Bringing CS high places the sample-and-hold into sample mode and also forces the SDO pin into high A (Pin 4): Analog Input. A is a single-ended input with IN IN impedance. Logic levels are determined by OV . respect to GND with a range from 0V to V . DD REF OV (Pin 5): I/O Interface Digital Power. The OV range DD DD is 1.71V to 5.25V. This supply is nominally set to the same supply as the host interface (1.8V, 2.5V, 3.3V or 5V). Bypass to GND with a 2.2µF ceramic chip capacitor. 231414fa 8 For more information www.linear.com/LTC2314-14

LTC2314-14 BLOCK DIAGRAM 2.2µF 2.2µF ANALOG SUPPLY DIGITAL SUPPLY RANGE 2.7V TO 5.25V RANGE 1.71V TO 5.25V 1 5 VDD OVDD 2.5V LDO ANALOG AIN INPUT RANGE 4 + THREE-STATE SDO 0V TO VREF SERIAL S/H 14-BIT SAR ADC 6 OUTPUT – PORT REF SCK 2 7 TIMING 2.2µF GND 1.024V LOGIC CS 3 2×/4× BANDGAP 8 TS8 PACKAGE 231414 BD ALL CAPACITORS UNLESS NOTED ARE HIGH QUALITY, CERAMIC CHIP TYPE TIMING DIAGRAMS 16TH EDGE t8 t9 SCK CS OVDD/2 OVDD/2 Hi-Z Hi-Z SDO SDO Figure 1. SDO Into Hi-Z after 16TH SCK↓ Figure 2. SDO Into Hi-Z after CS↑ 231414 TD01 231414 TD02 t7 t4 SCK SCK OVDD/2 OVDD/2 SDOVVOOHL SDO VVOOHL Figure 3. SDO Data Valid Hold after SCK↓ Figure 4. SDO Data Valid Access after SCK↓ 231414 TD03 231414 TD04 231414fa 9 For more information www.linear.com/LTC2314-14

LTC2314-14 APPLICATIONS INFORMATION Overview Leading zeros allow the 14-bit data result to be framed with both leading and trailing zeros for timing and data The LTC2314-14 is a low noise, high speed, 14-bit succes- verification. Since the rising edge of SCK will be coincident sive approximation register (SAR) ADC. The LTC2314-14 with the falling edge of CS, delay t is the delay to the first operates over a wide supply range (2.7V to 5.25V) and 2 falling edge of SCK, which is simply 0.5 • t . Delays t provides a low drift (20ppm/°C maximum), internal refer- SCK 2 (CS falling edge to SCK leading edge) and t (16th falling ence and reference buffer. The internal reference buffer is 10 SCK edge to CS rising edge) must be observed for Figures automatically configured to a 2.048V span in low supply 5, 6 and 7 and any timing implementation in order for the range (2.7V to 3.6V) and to a 4.096V span in the high conversion process and data readout to occur correctly. supply range (4.75V to 5.25V). The LTC2314-14 samples at a 4.5Msps rate and supports an 87.5MHz data clock. The user can bring CS high after the 16th falling SCK edge The LTC2314-14 achieves excellent dynamic performance provided that timing delay t is observed. Prematurely 10 (77dB SINAD, 85dB THD) while dissipating only 31mW terminating the conversion by bringing CS high before the from a 5V supply at the 4.5Msps conversion rate. 16th falling SCK edge plus delay t will cause a loss of 10 conversion data for that sample. The sample-and-hold is The LTC2314-14 outputs the conversion data with one placed in sample mode when CS is brought high. As shown cycle of conversion latency on the SDO pin. The SDO pin in Figure 6, a sample rate of 4.5Msps can be achieved on output logic levels are supplied by the dedicated OV DD the LTC2314-14 by using an 87.5MHz SCK data clock supply pin which has a wide supply range (1.71V to 5.25V) and a minimum acquisition time of 40ns which results in allowing the LTC2314-14 to communicate with 1.8V, 2.5V, the minimum throughput time (t ) of 222ns. 3V or 5V systems. THROUGHPUT Note that the maximum throughput of 4.5Msps can only The LTC2314-14 provides both nap and sleep power-down be achieved with the timing implementation of SCK held modes through serial interface control to reduce power high during acquisition as shown in Figure 6. dissipation during inactive periods. The LTC2314-14 also supports a continuous data clock as shown in Figure 7. With a continuous data clock the Serial Interface acquisition time period and conversion time period must The LT2314-14 communicates with microcontrollers, DSPs be designed as an exact integer number of data clock and other external circuitry via a 3-wire interface. A falling periods. Because the minimum acquisition time is not an CS edge starts a conversion and frames the serial data exact multiple of the minimum SCK period, the maximum transfer. SCK provides the conversion clock for the current sample rate for the continuous SCK timing is less than sample and controls the data readout on the SDO pin of 4.5Msps. For example, a 4.375Msps throughput is achieved the previous sample. CS transitioning low clocks out the using exactly 20 data clock periods with the maximum first leading zero and subsequent SCK falling edges clock data clock frequency of 87.5MHz. For this particular case, out the remaining data as shown in Figures 5, 6 and 7 for the acquisition time period and conversion clock period three different timing schemes. Data is serially output MSB are designed as 4 data clock periods (T = 45.7ns) and ACQ first through LSB last, followed by trailing zeros if further 16data clock periods (T = 182.9ns) respectively, CONV SCK falling edges are applied. Figure 5 illustrates that dur- yielding a throughput time of 228.6ns. ing the case where SCK is held low during the acquisition The following table illustrates the maximum throughput phase, only one leading zero is output. Figures 6 and 7 achievable for each of the three timing patterns. Note illustrate that for the SCK held high during acquisition or that in order to achieve the maximum throughput rate of continuous clocking mode two leading zeros are output. 231414fa 10 For more information www.linear.com/LTC2314-14

LTC2314-14 APPLICATIONS INFORMATION t10 CS tCONV = 15.5 • tSCK + t2 + t10 tACQ-MIN = 40ns tCONV tACQ-MIN t2 t6 SCK 1 2 3 4 14 15 16 t5 t3 t4 t7 t9 SDO 0 B13* B12 B11 B0 0 HI-Z STATE (MSB) tTHROUGHPUT *NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION 231414 F05 Figure 5: LTC2314-14 Serial Interface Timing Diagram (SCK Low During t ) ACQ t10 CS tCONV(MIN) = 15 • tSCK + t2 + t10 tACQ-MIN = 40ns tCONV tACQ-MIN t2 t6 SCK 1 2 3 4 5 15 16 t5 t3 t4 t7 t9 SDO 0 0 B13* B12 B11 B1 B0 0 HI-Z STATE (MSB) tTHROUGHPUT *NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION 231414 TD06 Figure 6: LTC2314-14 Serial Interface Timing Diagram (SCK High During t ) ACQ CS tCONV = 16 • tSCK tACQ = 4 • tSCK tCONV tACQ t2 t6 t10 SCK 20 1 2 3 4 5 15 16 17 18 19 20 t5 t3 t4 t7 t9 SDO 0 0 B13* B12 B11 B1 B0 0 HI-Z STATE (MSB) tTHROUGHPUT = 20 • tSCK *NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION 231414 TD07 Figure 7: LTC2314-14 Serial Interface Timing Diagram (SCK Continuous) 231414fa 11 For more information www.linear.com/LTC2314-14

LTC2314-14 APPLICATIONS INFORMATION 4.5Msps, the timing pattern where SCK is held high during Entering Nap/Sleep Mode the acquisition time must be used. Pulsing CS two times and holding SCK static places the Table 1: Maximum Throughput vs Timing Pattern LTC2314-14 into nap mode. Pulsing CS four times and TIMING PATTERN MAXIMUM holding SCK static places the LTC2314-14 into sleep mode. THROUGHPUT In sleep mode, all bias circuitry is shut down, including the SCK high during T 4.5Msps ACQ internal bandgap and reference buffer, and only leakage SCK low during T 4.375Msps ACQ currents remain (0.8µA typical). Because the reference SCK continuous (tTHROUGHPUT = 20 periods) 4.375Msps buffer is externally bypassed with a large capacitor (2.2µF), the LTC2314-14 requires a significant wait time (1.1ms) to Serial Data Output (SDO) recharge this capacitance before an accurate conversion The SDO output is always forced into the high impedance can be made. In contrast, nap mode does not power down state while CS is high. The falling edge of CS starts the the internal bandgap or reference buffer allowing for a fast conversion and enables SDO. The A/D conversion result wake-up and accurate conversion within one conversion clock is shifted out on the SDO pin as a serial data stream with cycle. Supply current during nap mode is nominally 1.8mA. the MSB first. The data stream consists of either one leading zero (SCK held low during acquisition, Fig. 5) or Exiting Nap/Sleep Mode two leading zeros (SCK held high during acquisition, Fig. Waking up the LTC2314-14 from either nap or sleep mode, 6) followed by 14 bits of conversion data. There is 1 cycle as shown in Figures 8 and 9, requires SCK to be pulsed of conversion latency. Subsequent falling SCK edges after one time. A conversion may be started immediately fol- the LSB is output will output zeros on the SDO pin. The lowing nap mode as shown in Figure 8. A period of time SDO output returns to the high impedance state after the allowing the reference voltage to recover must follow 16th falling edge of SCK. waking up from sleep mode as shown in Figure 9. The The output swing on the SDO pin is controlled by the wait period required before initiating a conversion for the OVDD pin voltage and supports a wide operating range recommended value of CREF of 2.2µF is 1.1ms. from 1.71V to 5.25V independent of the V pin voltage. DD Power Supply Sequencing Power Considerations The LTC2314-14 does not have any specific power sup- The LTC2314-14 provides two sets of power supply pins: ply sequencing requirements. Care should be taken to the analog 5V power supply (V ) and the digital input/ observe the maximum voltage relationships described in DD output interface power supply (OV ). The flexible OV the Absolute Maximum Ratings section. DD DD supply allows the LTC2314-14 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. 231414fa 12 For more information www.linear.com/LTC2314-14

LTC2314-14 APPLICATIONS INFORMATION 1 2 CS NAP MODE START tACQ SCK HOLD STATIC HIGH or LOW HOLD STATIC HIGH or LOW Z Z HI-Z STATE SDO 0 0 231414 F08 Figure 8: LTC2314-14 Entering/Exiting Nap Mode 1 2 3 4 CS VREF RECOVERY START tACQ NAP MODE SLEEP MODE tWAIT SCK HOLD STATIC HIGH or LOW Z Z HI-Z STATE SDO 0 0 231414 F09 Figure 9: LTC2314-14 Entering/Exiting Sleep Mode Single-Ended Analog Input Drive Choosing an Input Amplifier The analog input of the LTC2314-14 is easy to drive. The Choosing an input amplifier is easy if a few requirements input draws only one small current spike while charging are taken into consideration. First, to limit the magnitude the sample-and-hold capacitor at the end of conversion. of the voltage spike seen by the amplifier from charging During the conversion, the analog input draws only a small the sampling capacitor, choose an amplifier that has a low leakage current. If the source impedance of the driving output impedance (<50Ω) at the closed-loop bandwidth circuit is low, then the input of the LTC2314-14 can be frequency. For example, if an amplifier is used in a gain driven directly. As the source impedance increases, so of 1 and has a unity-gain bandwidth of 100MHz, then the will the acquisition time. For minimum acquisition time output impedance at 100MHz must be less than 50Ω. The with high source impedance, a buffer amplifier should be second requirement is that the closed-loop bandwidth used. The main requirement is that the amplifier driving must be greater than 100MHz to ensure adequate small the analog input must settle after the small current spike signal settling for full throughput rate. If slower op amps before the next conversion starts. Settling time must be less are used, more time for settling can be provided by in- than t (40ns) for full performance at the maximum creasing the time between conversions. The best choice ACQ-MIN throughput rate. While choosing an input amplifier, also for an op amp to drive the LTC2314-14 will depend on the keep in mind the amount of noise and harmonic distortion application. Generally, applications fall into two categories: the amplifier contributes. AC applications where dynamic specifications are most 231414fa 13 For more information www.linear.com/LTC2314-14

LTC2314-14 APPLICATIONS INFORMATION critical and time domain applications where DC accuracy A simple 1-pole RC filter is sufficient for many applications. and settling time are most critical. The following list is a For example, Figure 10 shows a recommended single- summary of the op amps that are suitable for driving the ended buffered drive circuit using the LT1818 in unity gain LTC2314-14. (More detailed information is available on mode. The 47pF capacitor from A to ground and 50Ω IN the Linear Technology website at www.linear.com.) source resistor limits the input bandwidth to 68MHz. The 47pF capacitor also acts as a charge reservoir for the input LT6230: 215MHz GBWP, –80dBc Distortion at 1MHz, sample-and-hold and isolates the LT1818 from sampling Unity-Gain Stable, Rail-to-Rail Input and Output, 3.5mA/ glitch kick-back. The 50Ω source resistor is used to help Amplifier, 1.1nV/√Hz. stabilize the settling response of the drive amplifier. When LT6200: 165MHz GBWP, –85dBc Distortion at 1MHz, Unity- choosing values of source resistance and shunt capaci- Gain Stable, R-R In and Out, 15mA/Amplifier, 0.95nV/√Hz. tance, the drive amplifier data sheet should be consulted and followed for optimum settling response. If lower input LT1818/1819: 400MHz GBWP, –85dBc Distortion at 5MHz, bandwidths are desired, care should be taken to optimize Unity-Gain Stable, 9mA/Amplifier, Single/Dual Voltage the settling response of the driver amplifier with higher Mode Operational Amplifier. values of shunt capacitance or series resistance. High Input Drive Circuits quality capacitors and resistors should be used in the RC filter since these components can add distortion. NP0/C0G The analog input of the LTC2314-14 is designed to be driven and silver mica type dielectric capacitors have excellent single-ended with respect to GND. A low impedance source linearity. Carbon surface mount resistors can generate can directly drive the high impedance analog input of the distortion from self heating and from damage that may LTC2314-14 without gain error. A high impedance source occur during soldering. Metal film surface mount resistors should be buffered to minimize settling time during acquisi- are much less susceptible to both problems. When high tion and to optimize the distortion performance of the ADC. amplitude unwanted signals are close in frequency to the For best performance, a buffer amplifier should be used desired signal frequency, a multiple pole filter is required. to drive the analog input of the LTC2314-14. The amplifier High external source resistance, combined with external provides low output impedance to allow for fast settling shunt capacitance at Pin 4 and 13pF of input capacitance on of the analog signal during the acquisition phase. It also the LTC2314-14 in sample mode, will significantly reduce provides isolation between the signal source and the ADC the internal 130MHz input bandwidth and may increase the inputs which draw a small current spike during acquisition. required acquisition time beyond the minimum acquisition time (t ) of 40ns. ACQ-MIN Input Filtering The noise and distortion of the buffer amplifier and other circuitry must be considered since they add to the ADC + 50Ω LTC2314-14 noise and distortion. Noisy input circuitry should be filtered ANALOG IN – AIN 47pF prior to the analog inputs to minimize noise. A simple LT1818 GND 1-pole RC filter is sufficient for many applications. 231414 F10 Large filter RC time constants slow down the settling at Figure 10. RC Input Filter the analog inputs. It is important that the overall RC time constants be short enough to allow the analog inputs to completely settle to >12-bit resolution within the minimum acquisition time (t ) of 40ns. ACQ-MIN 231414fa 14 For more information www.linear.com/LTC2314-14

LTC2314-14 APPLICATIONS INFORMATION ADC Reference the internal reference voltage (see Table 2) and must be less than or equal to the supply voltage (or 4.3V for the 5V A low noise, low temperature drift reference is critical to supply range). For example, a 3.3V external reference may achieving the full data sheet performance of the ADC. The be used with a 3.3V V supply voltage to provide a 3.3V LTC2314-14 provides an excellent internal reference with DD analog input voltage span (i.e. 3.3V > 2.048V + 50mV). a guaranteed 20ppm/°C maximum temperature coefficient. Or alternatively, a 2.5V reference may be used with a 3V For added flexibility, an external reference may also be used. supply voltage to provide a 2.5V input voltage range (i.e. The high speed, low noise internal reference buffer is used 2.5V > 2.048V + 50mV). The LTC6655-3.3, LTC6655-2.5, only in the internal reference configuration. The reference available from Linear Technology, may be suitable for buffer must be overdriven in the external reference con- many applications requiring a high performance external figuration with a voltage 50mV higher than the nominal reference for either 3.3V or 2.5V input spans respectively. reference output voltage in the internal configuration. Transfer Function Using the Internal Reference Figure 11 depicts the transfer function of the LTC2314-14. The internal bandgap and reference buffer are active by The code transitions occur midway between successive default when the LTC2314-14 is not in sleep mode. The integer LSB values (i.e. 0.5LSB, 1.5LSB, 2.5LSB… FS- reference voltage at the REF pin scales automatically with 0.5LSB). The output code is straight binary with 1LSB = the supply voltage at the VDD pin. The scaling of the refer- VREF/16,384. ence voltage with supply is shown in Table 2. Table 2: Reference Voltage vs Supply Range 111...111 SUPPLY VOLTAGE (V ) REF VOLTAGE (V ) DD REF 111...110 2.7V –> 3.6V 2.048V 4.75V –> 5.25V 4.096V E D O C T U The reference voltage also determines the full-scale analog P T U input range of the LTC2314-14. For example, a 2.048V O reference voltage will accommodate an analog input range from 0V to 2.048V. An analog input voltage that goes below 000...001 0V will be coded as all zeros and an analog input voltage 000...000 that exceeds 2.048V will be coded as all ones. 0 1LSB FS – 1LSB INPUT VOLTAGE (V) It is recommended that the REF pin be bypassed to ground 231414 F11 with a low ESR, 2.2µF ceramic chip capacitor for optimum Figure 11. LTC2314-14 Transfer Function performance. External Reference DC Performance An external reference can be used with the LTC2314-14 The noise of an ADC can be evaluated in two ways: if better performance is required or to accommodate a signal-to-noise ratio (SNR) in the frequency domain and larger input voltage span. The only constraints are that histogram in the time domain. The LTC2314-14 excels the external reference voltage must be 50mV higher than in both. The noise in the time domain histogram is the 231414fa 15 For more information www.linear.com/LTC2314-14

LTC2314-14 APPLICATIONS INFORMATION transition noise associated with a 14-bit resolution ADC Effective Number of Bits (ENOB) which can be measured with a fixed DC signal applied The effective number of bits (ENOB) is a measurement of to the input of the ADC. The resulting output codes are the resolution of an ADC and is directly related to SINAD collected over a large number of conversions. The shape by the equation where ENOB is the effective number of of the distribution of codes will give an indication of the bits of resolution and SINAD is expressed in dB: magnitude of the transition noise. In Figure 12, the distri- bution of output codes is shown for a DC input that has ENOB = (SINAD – 1.76)/6.02 been digitized 16,384 times. The distribution is Gaussian At the maximum sampling rate of 5MHz, the LTC2314-14 and the RMS code transition noise is 0.7LSB. This cor- maintains an ENOB above 12 bits up to the Nyquist input responds to a noise level of 77.5dB relative to a full scale frequency of 2.25MHz. (Figure 14) voltage of 4.096V. Signal-to-Noise Ratio (SNR) 7000 σ = 0.7 The signal-to-noise ratio (SNR) is the ratio between the 6000 RMS amplitude of the fundamental input frequency and 5000 the RMS amplitude of all other frequency components S 4000 except the first five harmonics and DC. Figure 13 shows T N U that the LTC2314-14 achieves a typical SNR of 77.5dB at CO 3000 a 4.5MHz sampling rate with a 500kHz input frequency. 2000 Total Harmonic Distortion (THD) 1000 0 Total Harmonic Distortion (THD) is the ratio of the RMS sum 8194 8195 8196 8197 8198 8199 8200 of all harmonics of the input signal to the fundamental itself. CODE 231414 F12 The out-of-band harmonics alias into the frequency band Figure 12. Histogram for 16384 Conversions between DC and half the sampling frequency (f /2). SMPL THD is expressed as: Dynamic Performance The LTC2314-14 has excellent high speed sampling V22+V32+V42+V2 N capability. Fast Fourier Transform (FFT) techniques are THD=20log V1 used to test the ADC’s frequency response, distortion and where V1 is the RMS amplitude of the fundamental fre- noise at the rated throughput. By applying a low distortion quency and V2 through V are the amplitudes of the second sine wave and analyzing the digital output using an FFT N through Nth harmonics. THD versus Input Frequency is algorithm, the ADC’s spectral content can be examined shown in the Typical Performance Characteristics section. for frequencies outside the applied fundamental. The The LTC2314-14 has excellent distortion performance up LTC2314-14 provides guaranteed tested limits for both to the Nyquist frequency. AC distortion and noise measurements. Intermodulation Distortion (IMD) Signal-to-Noise and Distortion Ratio (SINAD) If the ADC input signal consists of more than one spectral The signal-to-noise and distortion ratio (SINAD) is the ratio be- component, the ADC transfer function nonlinearity can tween the RMS amplitude of the fundamental input frequency produce intermodulation distortion (IMD) in addition to and the RMS amplitude of all other frequency components THD. IMD is the change in one sinusoidal input caused at the A/D output. The output is band-limited to frequencies by the presence of another sinusoidal input at a different from above DC and below half the sampling frequency. Figure frequency. 14 shows the LTC2314-14 maintains a SINAD above 74dB up to the Nyquist input frequency of 2.25MHz. 231414fa 16 For more information www.linear.com/LTC2314-14

LTC2314-14 APPLICATIONS INFORMATION If two pure sine waves of frequencies f and f are ap- 0 a b VDD = 5V plied to the ADC input, nonlinearities in the ADC transfer –20 SNR = 77.5dBFS SINAD = 76.9dBFS function can create distortion products at the sum and –40 THD = 84.9dB S) SFDR = 88.1dB difference frequencies m • fa ± n • fb, where m and n = 0, dBF –60 1, 2, 3, etc. For example, the 2nd order IMD terms include E ( TUD –80 (fa ± fb). If the two input sine waves are equal in magnitude, PLI–100 the value (in decibels) of the 2nd order IMD products can M A be expressed by the following formula: –120 –160 IMD(f ± f ) = 20 • log[V (f ± f )/V (f )] a b A a b A a –140 The LTC2314-14 has excellent IMD as shown in Figure 15. 0 250 500 750 100012501500175020002250 FREQUENCY (kHz) 231414 F13 Spurious Free Dynamic Range (SFDR) Figure 13. 32k Point FFT of the LTC2314-14 at f = 500 kHz IN The spurious free dynamic range is the largest spectral component excluding DC, the input signal and the harmon- 78 ics included in the THD. This value is expressed in decibels 77 12.50 relative to the RMS value of a full-scale input signal. VDD = 5V 76 12.33 Full-Power and Full-Linear Bandwidth S) NAD (dBF 7754 1122..0107ENOB tThhee a fmulpl-lpitouwdee ro fb tahned rwecidotnhs itsru thctee idn fpuuntd faremqeunetnacl iys aret dwuhcicedh SI 73 VDD = 3V 11.83 by 3dB for a full-scale input signal. 72 11.67 The full-linear bandwidth is the input frequency at which the SINAD has dropped to 74dB (12 effective bits). The 71 11.50 0 250 500 750 100012501500175020002250 LTC2314-14 has been designed to optimize the input INPUT FREQUENCY (kHz) 231414 F14 bandwidth, allowing the ADC to under-sample input signals with frequencies above the converter’s Nyquist frequency. Figure 14. LTC2314-14 ENOB/SINAD vs f IN The noise floor stays very low at high frequencies and SINAD becomes dominated by distortion at frequencies 0 VDD = 5V beyond Nyquist. –20 fS = 4.5Msps fa = 471.421kHz –40 fb = 531.421kHz Recommended Layout IMD2 (fb + fa) = –79.4dBc E (dB)–60 IMD3 (2fb –fa) = –90.8dBc To obtain the best performance from the LTC2314-14 a D U–80 printed circuit board is required. Layout for the printed T NI AG–100 circuit board (PCB) should ensure the digital and analog M signal lines are separated as much as possible. In particu- –120 lar, care should be taken not to run any digital clocks or –140 signals alongside analog signals or underneath the ADC. –160 0 500 1000 1500 2000 2500 The following is an example of a recommended PCB layout. INPUT FREQUENCY (kHz) A single solid ground plane is used. Bypass capacitors to 231414 F15 the supplies are placed as close as possible to the supply Figure 15. LTC2314-14 IMD Plot pins. Low impedance common returns for these bypass 231414fa 17 For more information www.linear.com/LTC2314-14

LTC2314-14 APPLICATIONS INFORMATION capacitors are essential to the low noise operation of the results. These errors are due to feed-through from the ADC. The analog input traces are screened by ground. microprocessor to the successive approximation com- For more details and information refer to DC1563, the parator. The problem can be eliminated by forcing the evaluation kit for the LTC2314-14. microprocessor into a “Wait” state during conversion or by using three-state buffers to isolate the ADC data bus. Bypassing Considerations High quality tantalum and ceramic bypass capacitors should be used at the V , OV and REF pins. For opti- DD DD mum performance, a 2.2µF ceramic chip capacitor should be used for the V and OV pins. The recommended DD DD bypassing for the REF pin is also a low ESR, 2.2µF ceramic capacitor. The traces connecting the pins and the bypass capacitors must be kept as short as possible and should be made as wide as possible avoiding the use of vias. The following is an example of a recommended PCB layout. All analog circuitry grounds should be terminated at the LTC2314-14. The ground return from the LTC2314-14 to the power supply should be low impedance for noise free operation. Digital circuitry grounds must be connected to the digital supply common. In applications where the ADC data outputs and control signals are connected to a continuously active micropro- cessor bus, it is possible to get errors in the conversion Figure 17. Layer 1 Top Layer Figure 16. Top Silkscreen Figure 18. Layer 2 GND Plane 231414fa 18 For more information www.linear.com/LTC2314-14

LTC2314-14 APPLICATIONS INFORMATION Figure 19. Layer 3 PWR Plane Figure 20. Layer 4 Bottom Layer REF + C6 C7 4.7µF OPT U5 9V TO 10V LT1790ACS6-2.048 VDD VCCIO 4 6 VCM VI VO GND GND C8 R9 1 2 10µF 1k C9 C10 C11 C12 4.7µF OPT OPT 4.7µF AC DC JP1 HD1X3-100 COUPLING U1 1 2 5 J4 R14 1 2 3 R15 * VDD REF OVDD CSL 8 CSL 0V TOA I4N.096V 0k 49.9Ω 4 AIN SCK 7 SCK C18 C17 C19 SDO 6 SDO OPT 1µF JP2 47pF GND R16 VCM NPO 231414 F21 33Ω 3 3 1.024V 2 1 2.048V HD1X3-100 R18 1k Figure 21. Partial 1563 Demo Board Schematic 231414fa 19 For more information www.linear.com/LTC2314-14

LTC2314-14 LTC2314-14 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637 Rev A) 2.90 BSC 0.40 0.65 (NOTE 4) MAX REF 1.22 REF 1.50 – 1.75 3.85 MAX2.62 REF 1.4 MIN 2.80 BSC (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT 0.22 – 0.36 0.65 BSC PER IPC CALCULATOR 8 PLCS (NOTE 3) 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 1.95 BSC 0.09 – 0.20 TS8 TSOT-23 0710 REV A (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 231414fa 20 For more information www.linear.com/LTC2314-14

LTC2314-14 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 10/13 Added pin-compatible family table 1 Changed T to 150°C 2 JMAX Changed SINAD condition for –3dB Input Linear Bandwidth to ≥74dB 3 Reordered/Renumbered Notes 3, 4, 5 231414fa 21 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnFeocrt imono orfe it sin cfiorcrumitsa atiso dne swcwribwed.l ihneeraeirn.c woimll n/oLTt iCnf2ri3n1ge4 o-1n 4existing patent rights.

LTC2314-14 TYPICAL APPLICATION Low-Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Re-Timing Flip-Flop VCC 0.1µF 1k NC7SVU04P5X MASTER CLOCK VCC 50Ω 1k PRE D > Q CONV CLR CONTROL NL17SZ74 CONV ENABLE LOGIC (FPGA, CPLD, DSP, ETC.) CS SCK LTC2314-14 NC7SVUO4P5X SDO 33Ω 231414 TA03 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS ADCs LTC2313-14 14-Bit, 2.5Msps Serial ADC 3V/5V, 14mW/25mW, 20ppm/°C Max Internal Reference, Single-Ended Input, 8-Lead TSOT-23 Package LTC2312-14 14-Bit, 500ksps Serial ADC 3V/5V, 9mW/15mW, 20ppm/°C Max Internal Reference, Single-Ended Input, 8-Lead TSOT-23 Package LTC1403A/LTC1403A-1 14-Bit, 2.8Msps Serial ADC 3V, 14mW, Unipolar/Bipolar Inputs, MSOP Package LTC1407A/LTC1407A-1 14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, Unipolar/Bipolar Inputs, 14mW, MSOP Package LTC2355/LTC2356 12-/14-Bit, 3.5Msps Serial ADC 3.3V Supply, Differential Input, 18mW, MSOP Package LTC2365/LTC2366 12-Bit, 1Msps/3Msps Serial Sampling ADC 3.3V Supply, 8mW, TSOT-23 Package Amplifiers LT6200/LT6201 Single/Dual Operational Amplifiers 165MHz, 0.95nV/√Hz LT6230/LT6231 Single/Dual Operational Amplifiers 215MHz, 3.5mA/Amplifier, 1.1nV/√Hz LT6236/LT6237 Single/Dual Operational Amplifier with 215MHz, 3.5mA/Amplifier, 1.1nV/√Hz Low Wideband Noise LT1818/LT1819 Single/Dual Operational Amplifiers 400MHz, 9mA/Amplifier, 6nV/√Hz References LTC6655-2.5/LTC6655-3.3 Precision Low Drift Low Noise Buffered Reference 2.5V/3.3V, 5ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package LT1461-3/LT1461-3.3V Precision Series Voltage Family 0.05% Initial Accuracy, 3ppm Drift 231414f 22 Linear Technology Corporation LT 1013 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2314-14 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2314-14  LINEAR TECHNOLOGY CORPORATION 2013

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: LTC2314ITS8-14#TRMPBF LTC2314HTS8-14#TRMPBF LTC2314CTS8-14#TRMPBF LTC2314ITS8-14#TRPBF LTC2314HTS8-14#TRPBF LTC2314ITS8-14#PBF LTC2314HTS8-14#PBF LTC2314CTS8-14#TRPBF LTC2314CTS8-14#PBF