LTC2312-14 14-Bit, 500ksps Serial Sampling ADC in TSOT FEATURES DESCRIPTION n 500ksps Throughput Rate The LTC®2312-14 is a 14-bit, 500ksps, serial sampling n No Cycle Latency A/D converter that draws only 3.2mA from a single 3V n Guaranteed 14-Bit No Missing Codes or 5V supply. The LTC2312-14 contains an integrated n Single 3V or 5V Supply low drift reference and reference buffer providing a low n Low Noise: 77.5dB SNR cost, high performance (20ppm/°C maximum) and space n Low Power: 9mW at 500ksps and 3V Supply saving solution. The LTC2312-14 achieves outstanding n Low Drift (20ppm/°C Maximum) 2.048V or 4.096V AC performance of 77dB SINAD and –85dB THD while Internal Reference sampling at 500ksps. The extremely high sample rate-to- n Sleep Mode with < 1µA Typical Supply Current power ratio makes the LTC2312-14 ideal for compact, low n Nap Mode with Quick Wake-Up < 1 Conversion power, high speed systems. The supply current decreases n Separate 1.8V to 5V Digital I/O Supply at lower sampling rates as the device automatically enters n High Speed SPI-Compatible Serial I/O nap mode after conversions. n Guaranteed Operation from –40°C to 125°C The LTC2312-14 has a high speed SPI-compatible serial n 8-Lead TSOT-23 Package interface that supports 1.8V, 2.5V, 3V and 5V logic. The fast 500ksps throughput with no-cycle latency makes APPLICATIONS the LTC2312-14 ideally suited for a wide variety of high n Communication Systems speed applications. n High Speed Data Acquisition Complete 14-/12-Bit Pin-Compatible SAR ADC Family n Handheld Terminal Interface 500ksps 2.5Msps 4.5Msps 5Msps n Medical Imaging 14-Bit LTC2312-14 LTC2313-14 LTC2314-14 n Uninterrupted Power Supplies 12-Bit LTC2312-12 LTC2313-12 LTC2315-12 n Battery Operated Systems Power 3V/5V 9mW/15mW 14mW/25mW 18mW/31mW 19mW/32mW n Automotive L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 16k Point FFT, f = 500ksps, f = 259kHz S IN 5V Supply, Internal Reference, 500ksps, 14-Bit Sampling ADC 0 VDD = 5V 5V –20 SNR = 77.5dBFS SINAD = 77dBFS 2.2µF LTC2312-14 –40 THD = –85dB VDD CONV S) SFDR = 88dB BF –60 2.2µF d SERIAL DATA LINK TO E ( REF SCK ASIC, PLD, MPU, DSP UD –80 OR SHIFT REGISTERS LIT P–100 M GND SDO A ANALOG INPUT DIGITAL OUTPUT SUPPLY –120 0V TO 4.096V AIN OVDD 2.2µF1.8V TO 5V –140 –160 231214 TA01 0 50 100 150 200 250 INPUT FREQUENCY (kHz) 231214 TA01b 231214fa 1 For more information www.linear.com/LTC2312-14

LTC2312-14 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) Supply Voltage (V , OV ) .......................................6V DD DD Reference (REF) and Analog Input (A ) Voltage IN TOP VIEW (Note 3) ......................................(–0.3V) to (V + 0.3V) DD VDD 1 8 CONV Digital Input Voltage (Note 3) ...(–0.3V) to (OVDD + 0.3V) REF 2 7 SCK Digital Output Voltage .............(–0.3V) to (OV + 0.3V) GND 3 6 SDO DD Power Dissipation ...............................................100mW AIN 4 5 OVDD TS8 PACKAGE Operating Temperature Range 8-LEAD PLASTIC TSOT-23 LTC2312C ................................................0°C to 70°C TJMAX = 150°C, θJA = 195°C/W LTC2312I ..............................................–40°C to 85°C LTC2312H ..........................................–40°C to 125°C Storage Temperature Range ..................–65°C to 150°C Lead Temperature Range (Soldering, 10 sec) ........300°C ORDER INFORMATION Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2312CTS8-14#TRMPBF LTC2312CTS8-14#TRPBF LTFZK 8-Lead Plastic TSOT-23 0°C to 70°C LTC2312ITS8-14#TRMPBF LTC2312ITS8-14#TRPBF LTFZK 8-Lead Plastic TSOT-23 –40˚C to 85˚C LTC2312HTS8-14#TRMPBF LTC2312HTS8-14#TRPBF LTFZK 8-Lead Plastic TSOT-23 –40˚C to 125˚C TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 231214fa 2 For more information www.linear.com/LTC2312-14

LTC2312-14 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Absolute Input Range l –0.05 V + 0.05 V AIN DD V Input Voltage Range (Note 11) l 0 V V IN REF I Analog Input DC Leakage Current l –1 1 µA IN C Analog Input Capacitance Sample Mode 13 pF IN Hold Mode 3 pF CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution l 14 Bits No Missing Codes l 14 Bits Transition Noise (Note 6) 0.7 LSB RMS INL Integral Linearity Error V = 5V (Note 5) l –3.75 ±1 3.75 LSB DD V = 3V (Note 5) l –4 ±1.5 4 LSB DD DNL Differential Linearity Error V = 5V l –0.99 ±0.3 0.99 LSB DD V = 3V l –0.99 ±0.4 0.99 LSB DD Offset Error V = 5V l –9 ±2 9 LSB DD V = 3V l –18 ±4 18 LSB DD Full-Scale Error V = 5V l –18 ±5 18 LSB DD V = 3V l –34 ±7 34 LSB DD Total Unadjusted Error V = 5V l –22 ±6 22 LSB DD V = 3V l –38 ±8 38 LSB DD DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C and A = –1dBFS. (Note 4) A IN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SINAD Signal-to-(Noise + Distortion) Ratio f = 20kHz, V = 5V l 72.5 77 dB IN DD f = 20kHz, V = 3V l 69 72.6 dB IN DD SNR Signal-to-Noise Ratio f = 20kHz, V = 5V l 73.5 77.5 dB IN DD f = 20kHz, V = 3V l 69.5 73 dB IN DD THD Total Harmonic Distortion f = 20kHz, V = 5V l –85 –76 dB IN DD First 5 Harmonics f = 20kHz, V = 3V l –85 –76 dB IN DD SFDR Spurious Free Dynamic Range f = 20kHz, V = 5V l 78 88 dB IN DD f = 20kHz, V = 3V l 76 88 dB IN DD IMD Intermodulation Distortion 2nd Order Terms f = 53kHz, f = 58kHz, –80 dBc IN1 IN2 3rd Order Terms A , A = –7dBFS –92 dBc IN1 IN2 Full Power Bandwidth At 3dB 130 MHz At 0.1dB 20 MHz –3dB Input Linear Bandwidth SINAD ≥ 74dB 5 MHz t Aperture Delay 1 ns AP t Aperture Jitter 10 ps JITTER RMS 231214fa 3 For more information www.linear.com/LTC2312-14

LTC2312-14 REFERENCE INPUT/OUTPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V V Output Voltage 2.7V ≤ V ≤ 3.6V l 2.040 2.048 2.056 V REF REF DD 4.75 ≤ V ≤ 5.25V l 4.080 4.096 4.112 V DD V Temperature Coefficient l 7 20 ppm/°C REF V Output Resistance Normal Operation, I = 0mA to 5mA 1 Ω REF LOAD Overdrive Condition 52 kΩ (V ≥ V + 50mV) REFIN REFOUT V Line Regulation 2.7V ≤ V ≤ 3.6V 0.4 mV/V REF DD 4.75 ≤ V ≤ 5.25V 0.2 mV/V DD V 2.048V/4.096V Supply Threshold 4.15 V REF V 2.048V/4.096V Supply Threshold Hysteresis 150 mV REF V Input Voltage Range 2.7V ≤ V ≤ 3.6V l V + 50mV V V REF DD REF DD (External Reference Input) 4.75 ≤ V ≤ 5.25V l V + 50mV 4.3 V DD REF DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V High Level Input Voltage l 0.8 • OV V IH DD V Low Level Input Voltage l 0.2 • OV V IL DD I Digital Input Current V = 0V to OV l –10 10 μA IN IN DD C Digital Input Capacitance 5 pF IN V High Level Output Voltage I = –500µA (Source) l OV –0.2 V OH O DD V Low Level Output Voltage I = 500µA (Sink) l 0.2 V OL O I Hi-Z Output Leakage Current V = 0V to OV , CONV = High l –10 10 µA OZ OUT DD C Hi-Z Output Capacitance CONV = High 4 pF OZ I Output Source Current V = 0V, OV = 1.8V –20 mA SOURCE OUT DD I Output Sink Current V = OV = 1.8V 20 mA SINK OUT DD POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Supply Voltage DD 3V Operational Range l 2.7 3 3.6 V 5V Operational Range l 4.75 5 5.25 V OV Digital Output Supply Voltage l 1.71 5.25 V DD I = Supply Current, Static Mode CONV = 0V, SCK = 0V l 3.4 4.3 mA TOTAL I I Operational Mode l 3.2 4 mA VDD + OVDD Nap Mode 2 mA Sleep Mode l 0.2 5 µA P Power Dissipation, Static Mode CONV = 0V, SCK = 0V l 17 21.5 mW D Operational Mode l 16 20 mW Nap Mode 10 mW Sleep Mode l 1 25 µW 231214fa 4 For more information www.linear.com/LTC2312-14

LTC2312-14 ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f Maximum Sampling Frequency (Notes 7, 8) l 500 kHz SAMPLE(MAX) f Shift Clock Frequency (Notes 7, 8) l 20 MHz SCK t Shift Clock Period l 50 ns SCK t Minimum Throughput Time, t + t l 2000 ns THROUGHPUT ACQ CONV t Conversion Time l 1300 ns CONV t Acquisition Time l 700 ns ACQ t Minimum CONV Pulse Width (Note 7), Valid for Nap and Sleep Modes Only l 10 ns 1 t SCK↑ Setup Time After CONV↓ (Note 7) l 10 ns 2 t SDO Enable Time After CONV↓ (Notes 7, 8) l 10 ns 3 t SDO Data Valid Access Time after SCK↓ (Notes 7, 8, 9) l 11 ns 4 t SCK Low Time l 10 ns 5 t SCK High Time l 10 ns 6 t SDO Data Valid Hold Time After SCK↓ (Notes 7, 8, 9) l 1 ns 7 t SDO into Hi-Z State Time After CONV↑ (Notes 7, 8, 10) l 3 10 ns 8 t CONV↑ Quiet Time After 14th SCK↓ (Note 7) l 15 ns 9 t _ Power-Up Time from Nap Mode See Nap Mode Section 50 ns WAKE NAP t _ Power-Up Time from Sleep Mode See Sleep Mode Section 1.1 ms WAKE SLEEP Note 1. Stresses beyond those listed under Absolute Maximum Ratings Note 6. Typical RMS noise at code transitions. may cause permanent damage to the device. Exposure to any Absolute Note 7. Parameter tested and guaranteed at OV = 2.5V. All input signals DD Maximum Rating condition for extended periods may affect device are specified with t = t = 1ns (10% to 90% of OV ) and timed from a r f DD reliability and lifetime. voltage level of OV /2. DD Note 2. All voltage values are with respect to ground. Note 8. All timing specifications given are with a 10pF capacitance load. Note 3. When these pin voltages are taken below ground or above V Load capacitances greater than this will require a digital buffer. DD (AIN, REF) or OVDD (SCK, CONV, SDO) they will be clamped by internal Note 9. The time required for the output to cross the VOH or VOL voltage. diodes. This product can handle input currents up to 100mA below ground Note 10. Guaranteed by design, not subject to test. or above V or OV without latch-up. DD DD Note 11. Recommended operating conditions. Note 4. V = 5V, OV = 2.5V, f = 500kHz, f = 20MHz, A = DD DD SMPL SCK IN –1dBFS and internal reference unless otherwise noted. Note 5. Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 231214fa 5 For more information www.linear.com/LTC2312-14

LTC2312-14 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, V = 5V, OV = 2.5V, f = 500ksps, A DD DD SMPL unless otherwise noted. Integral Nonlinearity Differential Nonlinearity DC Histogram Near Mid-Scale vs Output Code vs Output Code (Code 8192) 2.0 1.00 7000 σ = 0.7 1.5 0.75 6000 1.0 0.50 5000 0.5 0.25 NL (LSB) 0.0 NL (LSB) 0.00 COUNTS 34000000 I–0.5 D–0.25 2000 –1.0 –0.50 –1.5 –0.75 1000 –2.0 –1.00 0 0 4096 8192 12288 16384 0 4096 8192 12288 16384 8194 8195 8196 8197 8198 8199 8200 OUTPUT CODE OUTPUT CODE CODE 231214 G01 231214 G02 231214 G03 16k Point FFT, f = 500ksps SNR, SINAD vs Input Frequency THD, Harmonics vs Input S f = 259kHz (100kHz to 1.2MHz) Frequency (100kHz to 1.2MHz) IN 0 78 –75 VDD = 5V SNR RIN/CIN = 50Ω/47pF –20 SNR = 77.5dBFS fS = 500ksps AMPLITUDE (dBFS)––––146800000 STSHIFNDDAR =D = –= 88 7587dddBBBFS SNR, SINAD (dBFS) 77775467 SINAD VDD = 5V HD, HARMONICS (dB)––––99880550 VDD = 52VND THD 3RD –120 SNR T 73 –100 –140 VDD = 3V SINAD –160 72 –105 0 50 100 150 200 250 0 250 500 750 1000 1250 0 250 500 750 1000 1250 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) 231214 G04 231214 G05 231214 G06 THD, Harmonics vs Input SNR, SINAD vs Temperature, THD, Harmonics vs Temperature, Frequency (100kHz to 1.2MHz) f = 259kHz f = 259kHz IN IN –75 79 –75 RIN/CIN = 50Ω/47pF VDD = 3V fS = 500ksps 78 SNR –80 VDD = 3V THD VDD = 5V –80 HD, HARMONICS (dB)–––998055 2ND 3RD SNR, SINAD (dBFS) 77774567 SINADSNR HD, HARMONICS (dB)––9805 T32HRNDDD T 73 VDD = 3V T –95 –100 SINAD 72 –105 71 –100 0 250 500 750 1000 1250 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 INPUT FREQUENCY (kHz) TEMPERATURE (°C) TEMPERATURE (°C) 231214 G07 231214 G08 231214 G09 231214fa 6 For more information www.linear.com/LTC2312-14

LTC2312-14 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, V = 5V, OV = 2.5V, f = 500ksps, A DD DD SMPL unless otherwise noted. THD, Harmonics vs Temperature, SNR, SINAD vs Reference Voltage Reference Current f = 259kHz f = 259kHz vs Reference Voltage IN IN –75 79 200 VDD = 5V SNR –80 78 VDD = 5V THD, HARMONICS (dB)–1–––09980505 2NDTHD SNR, SINAD (dBFS) 77775476 VDD =S N3S.RI6NVADOPERATVIODNDS I=N A5VD EFERENCE CURRENT (µA)150 VDD = 3.6V NOOTP EARLALTOIWONED 3RD NOT ALLOWED R –105 73 –110 72 100 –55 –35 –15 5 25 45 65 85 105 125 2 2.5 3 3.5 4 4.5 2 2.5 3 3.5 4 4.5 TEMPERATURE (°C) REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) 231214 G10 231214 G11 231314 G12 Full-Scale Error vs Temperature Offset Error vs Temperature Supply Current vs Temperature 4 1 3.5 3.4 3 LSB) 2 B) 0.5 mA) 33..32 VDD = 5V LL-SCALE ERROR ( –101 OFFSET ERROR (LS 0 UPPLY CURRENT ( 2323....9180 VDD = 3V U –2 –0.5 S F 2.7 –3 2.6 –4 –1 2.5 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 231214 G13 231214 G14 231214 G15 Shutdown Current vs Temperature Supply Current vs Sample Rate 1 3.5 IVDD + IOVDD VDD = 5V ITOT OVDD = 2.5V 3.0 IVDD T (µA)0.75 mA) 2.5 EN T ( RR EN 2.0 CU 0.5 RR OWN LY CU 1.5 D P HUT0.25 VDD = 3V SUP 1.0 S 0.5 VDD = 5V IOVDD 0 0 –55 –35 –15 5 25 45 65 85 105 125 0 100 200 300 400 500 TEMPERATURE (°C) SAMPLE RATE (kHz) 231214 G16 231214 G17 231214fa 7 For more information www.linear.com/LTC2312-14

LTC2312-14 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, V = 5V, OV = 2.5V, f = 500ksps, A DD DD SMPL unless otherwise noted. Supply Current (I ) Output Supply Current (I ) VDD OVDD vs Supply Voltage (V ) vs Output Supply Voltage (OV ) DD DD 3.50 0.5 mA) 0.4 A) 3.25 T ( m N NT ( RRE 0.3 E U URR 3.00 NOOTP EARLALTOIWONED LY C C P PLY SUP 0.2 UP UT S 2.75 P UT 0.1 O 2.50 0 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 SUPPLY VOLTAGE (V) OUTPUT SUPPLY VOLTAGE (V) 231214 G18 231214 G19 PIN FUNCTIONS V (Pin 1): Power Supply. The ranges of V are 2.7V SDO (Pin 6): Serial Data Output. The A/D conversion result DD DD to 3.6V and 4.75V to 5.25V. Bypass V to GND with a is shifted out on SDO as a serial data stream with the MSB DD 2.2µF ceramic chip capacitor. first through the LSB last. The data stream consists of 14 bits of conversion data followed by trailing zeros. There REF (Pin 2): Reference Input/Output. The REF pin volt- is no cycle latency. Logic levels are determined by OV . age defines the input span of the ADC, 0V to V . By DD REF default, REF is an output pin and produces a reference SCK (Pin 7): Serial Data Clock Input. The SCK serial clock voltage V of either 2.048V or 4.096V depending on synchronizes the serial data transfer. SDO data transitions REF V (see Table 2). Bypass to GND with a 2.2µF, low ESR, on the falling edge of SCK. Logic levels are determined DD high quality ceramic chip capacitor. The REF pin may be by OV . DD overdriven with a voltage at least 50mV higher than the CONV (Pin 8): Convert Input. This active high signal starts internal reference voltage output. a conversion on the rising edge. The conversion is timed GND (Pin 3): Ground. The GND pin must be tied directly via an internal oscillator. The device automatically powers to a solid ground plane. down following the conversion process. The SDO pin is in high impedance when CONV is a logic high. Bringing A (Pin 4): Analog Input. A is a single-ended input with IN IN CONV low enables the SDO pin and outputs the MSB. respect to GND with a range from 0V to V . REF Subsequent bits of the conversion data are read out seri- OVDD (Pin 5): I/O Interface Digital Power. The OVDD range ally on the falling edge of SCK. A logic low on CONV also is 1.71V to 5.25V. This supply is nominally set to the places the sample-and-hold into sample mode. Logic levels same supply as the host interface (1.8V, 2.5V, 3.3V or are determined by OV . DD 5V). Bypass to GND with a 2.2µF ceramic chip capacitor. 231214fa 8 For more information www.linear.com/LTC2312-14

LTC2312-14 BLOCK DIAGRAM 2.2µF 2.2µF ANALOG SUPPLY I/O INTERFACE SUPPLY 3V OR 5V RANGE 1.8V TO 5V 1 5 VDD OVDD 2.5V LDO ANALOG AIN INPUT RANGE 4 + THREE-STATE SDO 0V TO VREF SERIAL S/H 14-BIT SAR ADC 6 OUTPUT – PORT REF SCK 2 7 TIMING 2.2µF GND 1.024V LOGIC CONV 3 2×/4× BANDGAP 8 TS8 PACKAGE 231214 BD ALL CAPACITORS UNLESS NOTED ARE HIGH QUALITY, CERAMIC CHIP TYPE TIMING DIAGRAMS t3 t8 CONV CONV OVDD/2 OVDD/2 Hi-Z VOH Hi-Z SDO MSB SDO VOL Figure 1. SDO Enabled After CONV↓ Figure 2. SDO Into Hi-Z After CONV↑ 231214 TD01 231214 TD02 t7 t4 SCK SCK OVDD/2 OVDD/2 SDOVVOOHL SDO VVOOHL Figure 3. SDO Data Valid Hold After SCK↓ Figure 4. SDO Data Valid Access After SCK↓ 231214 TD03 231214 TD04 231214fa 9 For more information www.linear.com/LTC2312-14

LTC2312-14 APPLICATIONS INFORMATION Overview Serial Data Output (SDO) The LTC2312-14 is a low noise, high speed, 14-bit succes- The SDO output is always forced into the high imped- sive approximation register (SAR) ADC. The LTC2312-14 ance state while CONV is high. The falling edge of CONV operates from a single 3V or 5V supply and provides a low enables SDO and also places the sample and hold into drift (20ppm/°C maximum), internal reference and refer- sample mode. The A/D conversion result is shifted out ence buffer. The internal reference buffer is automatically on the SDO pin as a serial data stream with the MSB first. configured with a 2.048V span in low supply range (2.7V The MSB is output on SDO on the falling edge of CONV. to 3.6V) and with a 4.096V span in the high supply range Delay t is the data valid access time for the MSB. The 3 (4.75V to 5.25V). The LTC2312-14 samples at a 500ksps following 13 bits of conversion data are shifted out on rate and supports a 20MHz serial data read clock. The SDO on the falling edge of SCK. Delay t is the data valid 4 LTC2312-14 achieves excellent dynamic performance access time for output data shifted out on the falling edge (77dB SINAD, 85dB THD) while dissipating only 15mW of SCK. There is no data latency. Subsequent falling SCK from a 5V supply up to the 500ksps conversion rate. The edges applied after the LSB is output will output zeros LTC2312-14 outputs the conversion data with no cycle indefinitely on the SDO pin. latency onto the SDO pin. The SDO pin output logic lev- The output swing on the SDO pin is controlled by the els are supplied by the dedicated OV supply pin which DD OV pin voltage and supports a wide operating range DD has a wide supply range (1.71V to 5.25V) allowing the from 1.71V to 5.25V independent of the V pin voltage. DD LTC2312-14 to communicate with 1.8V, 2.5V, 3V or 5V systems. The LTC2312-14 automatically switches to nap Power Considerations mode following the conversion process to save power. The The LTC2312-14 provides two sets of power supply pins: device also provides a sleep power-down mode through the analog power supply (V ) and the digital input/output serial interface control to reduce power dissipation during DD interface power supply (OV ). The flexible OV supply long inactive periods. DD DD allows the LTC2312-14 to communicate with any digital Serial Interface logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. The LTC2312-14 communicates with microcontrollers, DSPs and other external circuitry via a 3-wire interface. Entering Nap/Sleep Mode A rising CONV edge starts the conversion process which Pulsing CONV two times and holding SCK static places the is timed via an internal oscillator. Following the conver- LTC2312-14 into nap mode. Pulsing CONV four times and sion process the device automatically switches to nap holding SCK static places the LTC2312-14 into sleep mode. mode to save power as shown in Figure 7. This feature In sleep mode, all bias circuitry is shut down, including the saves considerable power for the LTC2312-14 operating internal bandgap and reference buffer, and only leakage at lower sampling rates. As shown in Figures 5 and 6, it currents remain (0.2µA typical). Because the reference is recommended to hold SCK static low or high during buffer is externally bypassed with a large capacitor (2.2µF), t . Note that CONV must be held high for the entire CONV the LTC2312-14 requires a significant wait time (1.1ms) to minimum conversion time (t ). A falling CONV edge CONV recharge this capacitance before an accurate conversion enables SDO and outputs the MSB. Subsequent SCK can be made. In contrast, nap mode does not power down falling edges clock out the remaining data as shown in the internal bandgap or reference buffer allowing for a fast Figures 5 and 6. Data is serially output MSB first through wake-up and accurate conversion within one conversion clock LSB last, followed by trailing zeros if further SCK falling cycle. Supply current during nap mode is nominally 2mA. edges are applied. 231214fa 10 For more information www.linear.com/LTC2312-14

LTC2312-14 APPLICATIONS INFORMATION t9 CONV tACQ-MIN = 13.5 • tSCK + t2 + t9 tCONV-MIN tACQ t2 t6 SCK 1 2 3 4 12 13 14 t5 t8 t3 t4 t7 HI-Z STATE SDO B13 B12 B11 B10 B1 B0 0 (MSB) tTHROUGHPUT 231214 F05 Figure 5. LTC2312-14 Serial Interface Timing Diagram (SCK Low During t ) CONV t9 CONV tACQ-MIN = 13.5 • tSCK + t2 + t9 tCONV-MIN t2 t6 tACQ SCK 1 2 3 4 13 14 t8 t3 t5 t4 t7 HI-Z STATE SDO B13 B12 B11 B10 B1 B0 0 (MSB) tTHROUGHPUT 231214 F06 Figure 6. LTC2312-14 Serial Interface Timing Diagram (SCK High During t ) CONV t9 t2 CONV CONVERT POWER-DOWN tCONV-MIN NAP MODE tACQ SCK t8 t3 HI-Z STATE SDO B13 B12 tCONV > tCONV-MIN (MSB) 231214 F07 Figure 7. LTC2312-14 Nap Mode Power-Down Following Conversion for t > t CONV CONV-MIN 231214fa 11 For more information www.linear.com/LTC2312-14

LTC2312-14 APPLICATIONS INFORMATION Exiting Nap/Sleep Mode with high source impedance, a buffer amplifier should be used. The main requirement is that the amplifier driving Waking up the LTC2312-14 from either nap or sleep the analog input must settle after the small current spike mode, as shown in Figures 8 and 9, requires SCK to be before the next conversion starts. Settling time must be pulsed one time. A conversion cycle (t ) may be started ACQ less than t (700ns) for full performance at the immediately following nap mode as shown in Figure 8. A ACQ-MIN maximum throughput rate. While choosing an input ampli- period of time allowing the reference voltage to recover fier, also keep in mind the amount of noise and harmonic must follow waking up from sleep mode as shown in Figure distortion the amplifier contributes. 9. The wait period required before initiating a conversion for the recommended value of C of 2.2µF is 1.1ms. REF Choosing an Input Amplifier Power Supply Sequencing Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude The LTC2312-14 does not have any specific power sup- of the voltage spike seen by the amplifier from charging ply sequencing requirements. Care should be taken to the sampling capacitor, choose an amplifier that has a low observe the maximum voltage relationships described in output impedance (<50Ω) at the closed-loop bandwidth the Absolute Maximum Ratings section. frequency. For example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 50MHz, then the Single-Ended Analog Input Drive output impedance at 50MHz must be less than 50Ω. The The analog input of the LTC2312-14 is easy to drive. The second requirement is that the closed-loop bandwidth input draws only one small current spike while charging must be greater than 50MHz to ensure adequate small the sample-and-hold capacitor following the falling edge signal settling for full throughput rate. If slower op amps of CONV. During the conversion, the analog input draws are used, more time for settling can be provided by in- only a small leakage current. If the source impedance of creasing the time between conversions. The best choice the driving circuit is low, then the input of the LTC2312-14 for an op amp to drive the LTC2312-14 will depend on the can be driven directly. As the source impedance increases, application. Generally, applications fall into two categories: so will the acquisition time. For minimum acquisition time AC applications where dynamic specifications are most tACQ(MIN) 1 2 CONV START tCONV NAP MODE START tACQ SCK HOLD STATIC HIGH OR LOW Z Z HI-Z STATE Z SDO 231214 F08 Figure 8. LTC2312-14 Entering/Exiting Nap Mode 1 2 3 4 CONV VREF RECOVERY START tCONV NAP MODE SLEEP MODE tWAIT SCK HOLD STATIC HIGH OR LOW Z Z HI-Z STATE Z SDO 231214 F09 Figure 9. LTC2312-14 Entering/Exiting Sleep Mode 231214fa 12 For more information www.linear.com/LTC2312-14

LTC2312-14 APPLICATIONS INFORMATION critical and time domain applications where DC accuracy gain mode. The 470pF capacitor from A to ground and IN and settling time are most critical. The following list is a 50Ω source resistor limits the input bandwidth to 7MHz. summary of the op amps that are suitable for driving the The 470pF capacitor also acts as a charge reservoir for LTC2312-14. (More detailed information is available on the input sample-and-hold and isolates the LT1818 from the Linear Technology website at www.linear.com.) sampling glitch kick-back. The 50Ω source resistor is used to help stabilize the settling response of the drive LT6230: 215MHz GBWP, –80dBc Distortion at 1MHz, amplifier. When choosing values of source resistance and Unity-Gain Stable, Rail-to-Rail Input and Output, 3.5mA/ shunt capacitance, the drive amplifier data sheet should be Amplifier, 1.1nV/√Hz. consulted and followed for optimum settling response. If LT6200: 165MHz GBWP, –85dBc Distortion at 1MHz, Unity- lower input bandwidths are desired, care should be taken Gain Stable, R-R In and Out, 15mA/Amplifier, 0.95nV/√Hz. to optimize the settling response of the driver amplifier with LT1818/1819: 400MHz GBWP, –85dBc Distortion at 5MHz, higher values of shunt capacitance or series resistance. Unity-Gain Stable, 9mA/Amplifier, Single/Dual Voltage High quality capacitors and resistors should be used in the Mode Operational Amplifier. RC filter since these components can add distortion. NP0/ C0G and silver mica type dielectric capacitors have excel- Input Drive Circuits lent linearity. Carbon surface mount resistors can generate The analog input of the LTC2312-14 is designed to be driven distortion from self heating and from damage that may single-ended with respect to GND. A low impedance source occur during soldering. Metal film surface mount resistors can directly drive the high impedance analog input of the are much less susceptible to both problems. When high LTC2312-14 without gain error. A high impedance source amplitude unwanted signals are close in frequency to the should be buffered to minimize settling time during acquisi- desired signal frequency, a multiple pole filter is required. tion and to optimize the distortion performance of the ADC. High external source resistance, combined with external shunt capacitance at Pin 4 will significantly reduce the For best performance, a buffer amplifier should be used input bandwidth and may increase the required acquisi- to drive the analog input of the LTC2312-14. The amplifier tion time beyond the minimum acquisition time (t ) provides low output impedance to allow for fast settling ACQ-MIN of 700ns. of the analog signal during the acquisition phase. It also provides isolation between the signal source and the ADC inputs which draw a small current spike during acquisition. LTC2312-14 ANALOG IN + 50Ω AIN – Input Filtering 470pF LT1818 GND The noise and distortion of the buffer amplifier and other circuitry must be considered since they add to the ADC 231214 F10 noise and distortion. Noisy input circuitry should be filtered Figure 10. RC Input Filter prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. ADC Reference Large filter RC time constants slow down the settling at A low noise, low temperature drift reference is critical to the analog inputs. It is important that the overall RC time achieving the full data sheet performance of the ADC. The constants be short enough to allow the analog inputs to completely settle to >14-bit resolution within the minimum LTC2312-14 provides an excellent internal reference with acquisition time (t ) of 700ns. a guaranteed 20ppm/°C maximum temperature coefficient. ACQ-MIN For added flexibility, an external reference may also be used. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 10 shows a recommended single- The high speed, low noise internal reference buffer is used ended buffered drive circuit using the LT1818 in unity only in the internal reference configuration. The reference 231214fa 13 For more information www.linear.com/LTC2312-14

LTC2312-14 APPLICATIONS INFORMATION buffer must be overdriven in the external reference con- the internal reference voltage (see Table 2) and must be figuration with a voltage 50mV higher than the nominal less than or equal to the supply voltage (or 4.3V for the 5V reference output voltage in the internal configuration. supply range). For example, a 3.3V external reference may be used with a 3.3V V supply voltage to provide a 3.3V DD Using the Internal Reference analog input voltage span (i.e. 3.3V > 2.048V + 50mV). Or alternatively, a 2.5V reference may be used with a 3V The internal bandgap and reference buffer are active by supply voltage to provide a 2.5V input voltage range (i.e. default when the LTC2312-14 is not in sleep mode. The 2.5V > 2.048V + 50mV). The LTC6655-3.3, LTC6655-2.5, reference voltage at the REF pin scales automatically with available from Linear Technology, may be suitable for the supply voltage at the V pin. The scaling of the refer- DD many applications requiring a high performance external ence voltage with supply is shown in Table 2. reference for either 3.3V or 2.5V input spans respectively. Table 2. Reference Voltage vs Supply Range SUPPLY VOLTAGE (VDD) REF VOLTAGE (VREF) Transfer Function 2.7V < V < 3.6V 2.048V DD Figure 11 depicts the transfer function of the LTC2312-14. 4.75V < V < 5.25V 4.096V DD The code transitions occur midway between successive integer LSB values (i.e. 0.5LSB, 1.5LSB, 2.5LSB… FS- The reference voltage also determines the full-scale analog 0.5LSB). The output code is straight binary with 1LSB = input range of the LTC2312-14. For example, a 2.048V V /16,384. reference voltage will accommodate an analog input range REF from 0V to 2.048V. An analog input voltage that goes below DC Performance 0V will be coded as all zeros and an analog input voltage that exceeds 2.048V will be coded as all ones. The noise of an ADC can be evaluated in two ways: signal-to-noise ratio (SNR) in the frequency domain and It is recommended that the REF pin be bypassed to ground histogram in the time domain. The LTC2312-14 excels with a low ESR, 2.2µF ceramic chip capacitor for optimum in both. The noise in the time domain histogram is the performance. transition noise associated with a 14-bit resolution ADC which can be measured with a fixed DC signal applied External Reference to the input of the ADC. The resulting output codes are An external reference can be used with the LTC2312-14 collected over a large number of conversions. The shape if better performance is required or to accommodate a of the distribution of codes will give an indication of the larger input voltage span. The only constraints are that magnitude of the transition noise. In Figure 12, the distri- the external reference voltage must be 50mV higher than bution of output codes is shown for a DC input that has 7000 σ = 0.7 111...111 6000 111...110 5000 E D O S 4000 C T UT UN TP CO 3000 U O 2000 1000 000...001 000...000 0 0 1LSB FS – 1LSB 8194 8195 8196 8197 8198 8199 8200 INPUT VOLTAGE (V) CODE 231214 F11 231214 F12 Figure 11. LTC2312-14 Transfer Function Figure 12. Histogram for 16384 Conversions 231214fa 14 For more information www.linear.com/LTC2312-14

LTC2312-14 APPLICATIONS INFORMATION been digitized 16,384 times. The distribution is Gaussian At the maximum sampling rate of 500kHz, the LTC2312-14 and the RMS code transition noise is 0.7LSB. This cor- maintains an ENOB above 12 bits up to an input frequency responds to a noise level of 77.5dB relative to a full scale of 1.25MHz. (Figure 14) voltage of 4.096V. Signal-to-Noise Ratio (SNR) Dynamic Performance The signal-to-noise ratio (SNR) is the ratio between The LTC2312-14 has excellent high speed sampling the RMS amplitude of the fundamental input frequency capability. Fast Fourier Transform (FFT) techniques are and the RMS amplitude of all other frequency compon- used to test the ADC’s frequency response, distortion and ents except the first five harmonics and DC. Figure 13 noise at the rated throughput. By applying a low distortion shows that the LTC2312-14 achieves a typical SNR of sine wave and analyzing the digital output using an FFT 77.5dB at a 500kHz sampling rate with a 259kHz input algorithm, the ADC’s spectral content can be examined frequency. for frequencies outside the applied fundamental. The LTC2312-14 provides guaranteed tested limits for both Total Harmonic Distortion (THD) AC distortion and noise measurements. Total Harmonic Distortion (THD) is the ratio of the RMS sum Signal-to-Noise and Distortion Ratio (SINAD) of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band The signal-to-noise and distortion ratio (SINAD) is the between DC and half the sampling frequency (f /2). ratio between the RMS amplitude of the fundamental input SMPL THD is expressed as: frequency and the RMS amplitude of all other frequency components at the A/D output. The output is band-limited to frequencies from above DC and below half the sampling V22+V32+V42+V2 N THD=20log frequency. Figure 14 shows the LTC2312-14 maintains a V1 SINAD above 76dB up to an input frequency of 1.25MHz. where V1 is the RMS amplitude of the fundamental fre- Effective Number of Bits (ENOB) quency and V2 through V are the amplitudes of the second N through Nth harmonics. THD versus Input Frequency is The effective number of bits (ENOB) is a measurement of shown in the Typical Performance Characteristics section. the resolution of an ADC and is directly related to SINAD The LTC2312-14 has excellent distortion performance well by the equation where ENOB is the effective number of beyond the Nyquist frequency. bits of resolution and SINAD is expressed in dB: ENOB = (SINAD – 1.76)/6.02 0 78 VDD = 5V –20 SNR = 77.5dBFS 77 VDD = 5V 12.50 SINAD = 77dBFS –40 THD = –85dB S) SFDR = 88dB 76 12.33 BF –60 S) AMPLITUDE (d––18000 SINAD (dBF 7754 VDD = 3V 1122..1070ENOB 73 11.83 –120 –140 72 11.67 –160 71 11.50 0 50 100 150 200 250 0 250 500 750 1000 1250 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) 231214 F13 231214 F14 Figure 13. 16k Point FFT of the LTC2312-14 at f = 259kHz Figure 14. LTC2312-14 ENOB/SINAD vs f IN IN 231214fa 15 For more information www.linear.com/LTC2312-14

LTC2312-14 APPLICATIONS INFORMATION Intermodulation Distortion (IMD) Full-Power and –3dB Input Linear Bandwidth If the ADC input signal consists of more than one spectral The full-power bandwidth is the input frequency at which component, the ADC transfer function nonlinearity can the amplitude of the reconstructed fundamental is reduced produce intermodulation distortion (IMD) in addition to by 3dB for a full-scale input signal. THD. IMD is the change in one sinusoidal input caused The –3dB linear bandwidth is the input frequency at which by the presence of another sinusoidal input at a different the SINAD has dropped to 74dB (12 effective bits). The frequency. LTC2312-14 has been designed to optimize the input If two pure sine waves of frequencies f and f are ap- bandwidth, allowing the ADC to under-sample input signals a b plied to the ADC input, nonlinearities in the ADC transfer with frequencies above the converter’s Nyquist frequency. function can create distortion products at the sum and The noise floor stays very low at high frequencies and difference frequencies m • f ± n • f , where m and n = 0, SINAD becomes dominated by distortion at frequencies a b 1, 2, 3, etc. For example, the 2nd order IMD terms include beyond Nyquist. (f ± f ). If the two input sine waves are equal in magnitude, a b the value (in decibels) of the 2nd order IMD products can Recommended Layout be expressed by the following formula: To obtain the best performance from the LTC2312-14 a IMD(f ± f ) = 20 • log[V (f ± f )/V (f )] printed circuit board is required. Layout for the printed a b A a b A a circuit board (PCB) should ensure the digital and analog The LTC2312-14 has excellent IMD, as shown in Figure 15. signal lines are separated as much as possible. In particu- lar, care should be taken not to run any digital clocks or 0 signals alongside analog signals or underneath the ADC. fa fb VDD = 5V –20 fs = 500ksps Figure 16 through Figure 20 is an example of a recom- fa = 53.421kHz mended PCB layout. A single solid ground plane is used. –40 fb = 58.421kHz dB) –60 IIMMDD23 ( (f2b f–b f–a )f a=) –=8 –09.42ddBBcc Bypass capacitors to the supplies are placed as close as E ( possible to the supply pins. Low impedance common NITUD –80 fb –2 ffaa – fb 2fb – fafb + fa returns for these bypass capacitors are essential to the AG–100 low noise operation of the ADC. The analog input traces M –120 are screened by ground. For more details and information refer to DC1563, the evaluation kit for the LTC2312-14. –140 –160 0 50 100 150 200 250 Bypassing Considerations INPUT FREQUENCY (kHz) 231214 F15 High quality tantalum and ceramic bypass capacitors Figure 15. LTC2312-14 IMD Plot should be used at the V , OV and REF pins. For opti- DD DD mum performance, a 2.2µF ceramic chip capacitor should Spurious Free Dynamic Range (SFDR) be used for the V and OV pins. The recommended DD DD bypassing for the REF pin is also a low ESR, 2.2µF ceramic The spurious free dynamic range is the largest spectral capacitor. The traces connecting the pins and the bypass component excluding DC and the input signal. This value capacitors must be kept as short as possible and should is expressed in decibels relative to the RMS value of a be made as wide as possible avoiding the use of vias. full-scale input signal. All analog circuitry grounds should be terminated at the LTC2312-14. The ground return from the LTC2312-14 to the power supply should be low impedance for noise free operation. Digital circuitry grounds must be connected to the digital supply common. 231214fa 16 For more information www.linear.com/LTC2312-14

LTC2312-14 APPLICATIONS INFORMATION In applications where the ADC data outputs and control microprocessor to the successive approximation com- signals are connected to a continuously active micropro- parator. The problem can be eliminated by forcing the cessor bus, it is possible to get errors in the conversion microprocessor into a “Wait” state during conversion or results. These errors are due to feed-through from the by using three-state buffers to isolate the ADC data bus. Figure 16. Top Silkscreen Figure 17. Layer 1 Top Layer Figure 18. Layer 2 GND Plane 231214fa 17 For more information www.linear.com/LTC2312-14

LTC2312-14 APPLICATIONS INFORMATION Figure 19. Layer 3 PWR Plane Figure 20. Layer 4 Bottom Layer 231214fa 18 For more information www.linear.com/LTC2312-14

LTC2312-14 APPLICATIONS INFORMATION REF + C6 C7 4.7µF OPT U5 9V TO 10V LT1790ACS6-2.048 VDD VCCIO 4 6 VCM VI VO GND GND C8 R9 1 2 10µF 1k C9 C10 C11 C12 4.7µF OPT OPT 4.7µF AC DC JP1 HD1X3-100 COUPLING U1 1 2 5 J4 R14 1 2 3 R15 * VDD REF OVDD CSL 8 CSL* 0V TOA I4N.096V 0k 49.9Ω 4 AIN SCK 7 SCK C18 C17 C19 SDO 6 SDO OPT 1µF JP2 47pF GND R16 VCM NP0 231214 F21 33Ω 3 3 1.024V 2 1 2.048V *NOTE: CSL = CONV HD1X3-100 R18 1k Figure 21. Partial 1563 Demo Board Schematic 231214fa 19 For more information www.linear.com/LTC2312-14

LTC2312-14 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637 Rev A) 2.90 BSC 0.40 0.65 (NOTE 4) MAX REF 1.22 REF 1.50 – 1.75 3.85 MAX2.62 REF 1.4 MIN 2.80 BSC (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT 0.22 – 0.36 0.65 BSC PER IPC CALCULATOR 8 PLCS (NOTE 3) 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 1.95 BSC 0.09 – 0.20 TS8 TSOT-23 0710 REV A (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 231214fa 20 For more information www.linear.com/LTC2312-14

LTC2312-14 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 11/14 Modification to Figure 8 and Figure 9 12 231214fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 21 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnFeocrt imono orfe it sin cfiorcrumitsa atiso dne swcrwibwed.l ihneeraeirn.c woimll n/oLtT iCnf2ri3n1ge2 o-1n 4existing patent rights.

LTC2312-14 TYPICAL APPLICATION Low Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Re-Timing Flip-Flop VCC 0.1µF 1k NC7SVU04P5X MASTER CLOCK VCC 50Ω 1k PRE D > Q CONV CLR CONTROL NL17SZ74 SDO ENABLE LOGIC (FPGA, CPLD, DSP, ETC.) CONV SCK LTC2312-14 NC7SVUO4P5X SDO 33Ω 231214 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS ADCs LTC2314-14 14-Bit, 4.5Msps Serial ADC 3V/5V, 18mW/31mW, 20ppm/°C Max Internal Reference, Single- Ended, 8-Lead TSOT-23 Package LTC2313-14 14-Bit, 2.5Msps Serial ADC 3V/5V, 14mW/25mW, 20ppm/°C Max Internal Reference, Single-Ended Input, 8-Lead TSOT-23 Package LTC1403A/LTC1403A-1 14-Bit, 2.8Msps Serial ADC 3V, 14mW, Unipolar/Bipolar Inputs, MSOP Package LTC1407A/LTC1407A-1 14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, Unipolar/Bipolar Inputs, 14mW, MSOP Package LTC2355/LTC2356 12-/14-Bit, 3.5Msps Serial ADC 3.3V Supply, Differential Inputs, 18mW, MSOP Package LTC2365/LTC2366 12-Bit, 1Msps/3Msps Serial Sampling ADC 3.3V Supply, Single-Ended, 8mW, TSOT-23 Package Amplifiers LT6200/LT6201 Single/Dual Operational Amplifiers 165MHz, 0.95nV/√Hz LT6230/LT6231 Single/Dual Operational Amplifiers 215MHz, 3.5mA/Amplifier, 1.1nV/√Hz LT6236/LT6237 Single/Dual Operational Amplifier with 215MHz, 3.5mA/Amplifier, 1.1nV/√Hz Low Wideband Noise LT1818/LT1819 Single/Dual Operational Amplifiers 400MHz, 9mA/Amplifier, 6nV/√Hz References LTC6655-2.5/LTC6655-3.3 Precision Low Drift Low Noise Buffered Reference 2.5V/3.3V, 5ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package LT1461-3/LT1461-3.3V Precision Series Voltage Family 0.05% Initial Accuracy, 3ppm Drift 231214fa 22 Linear Technology Corporation LT 1114 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2312-14 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2312-14  LINEAR TECHNOLOGY CORPORATION 2013

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: LTC2312CTS8-14#TRMPBF LTC2312HTS8-14#TRMPBF LTC2312CTS8-14#PBF LTC2312ITS8-14#TRMPBF LTC2312HTS8-14#TRPBF LTC2312CTS8-14#TRPBF LTC2312ITS8-14#PBF LTC2312ITS8-14#TRPBF LTC2312HTS8-14#PBF