LTC2309 8-Channel, 12-Bit SAR ADC 2 with I C Interface FeAtuRes DesCRIptIOn n 12-Bit Resolution The LTC®2309 is a low noise, low power, 8-channel, 12-bit n Low Power: 1.5mW at 1ksps, 35µW Sleep Mode successive approximation ADC with an I2C compatible n 14ksps Throughput Rate serial interface. This ADC includes an internal reference n Low Noise: SNR = 73.4dB and a fully differential sample-and-hold circuit to reduce n Guaranteed No Missing Codes common mode noise. The LTC2309 operates from an n Single 5V Supply internal clock to achieve a fast 1.3µs conversion time. n 2-Wire I2C Compatible Serial Interface with Nine The LTC2309 operates from a single 5V supply and Addresses Plus One Global for Synchronization draws just 300µA at a throughput rate of 1ksps. The n Fast Conversion Time: 1.3µs ADC enters nap mode when not converting, reducing n Internal Reference the power dissipation. n Internal 8-Channel Multiplexer n Internal Conversion Clock The LTC2309 is available in both a small 24-pin 4mm × n Unipolar or Bipolar Input Ranges (Software Selectable) 4mm QFN and a 20-pin TSSOP package. The internal 2.5V n Guaranteed Operation from –40°C to 125°C reference and 8-channel multiplexer further reduce PCB (TSSOP Package) board space requirements. n 24-Pin 4mm × 4mm QFN and 20-Pin TSSOP Packages The low power consumption and small size make the LTC2309 ideal for battery-operated and portable applica- AppLICAtIOns tions, while the 2-wire I2C compatible serial interface makes n Industrial Process Control this ADC a good match for space-constrained systems. n Motor Control L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Easy Drive is a trademark of Linear Technology Corporation. All other trademarks are the n Accelerometer Measurements property of their respective owners. n Battery-Operated Instruments n Isolated and/or Remote Data Acquisition n Power Supply Monitoring BLOCK DIAGRAM 5V Integral Nonlinearity vs Output Code 0.1µF 10µF 1.00 CH0 VDD AD1 0.75 CH1 LTC2309 AD0 0.50 CH2 0.25 0V T±AO2N. 04A4.L08O9V6G VB I INUPPNOUILPTAOSRLAR CCHH34 AINNMAPULUXOTG +– S1A2R- BAIDTC PIO2RCT SSDCLA INL (LSB)–0.205 CH5 CH6 –0.50 VREF CH7 INTERNAL 2.2µF –0.75 COM 2.5V REF –1.00 0 1024 2048 3072 4096 OUTPUT CODE REFCOMP 2309 G01 GND 0.1µF 10µF 2309 TA01 2309fd 

LTC2309 ABsOLute MAxIMuM RAtInGs (Notes 1, 2) Supply Voltage Power Dissipation ..............................................500mW V ..........................................................–0.3V to 6V Operating Temperature Range DD Analog Input Voltage (Note 3) LTC2309C ................................................0°C to 70°C CH0-CH7, COM, V , LTC2309I .............................................–40°C to 85°C REF REFCOMP ....................(GND – 0.3V) to (V + 0.3V) LTC2309H ..........................................–40°C to 125°C DD Digital Input Voltage Storage Temperature Range ..................–65°C to 150°C (Note 3) ............................(GND – 0.3V) to (V + 0.3V) Lead Temperature (Soldering, 10 sec) DD Digital Output Voltage ......(GND – 0.3V) to (V + 0.3V) TSSOP ..............................................................300°C DD pIn COnFIGuRAtIOn TOP VIEW H2 H1 H0 DD ND ND TOP VIEW C C C V G G 24 23 22 21 20 19 REFCOMP 1 20 VREF GND 2 19 COM CH3 1 18 GND CH4 2 17 SDA VDD 3 18 CH7 AD0 4 17 CH6 CH5 3 16 SCL 25 CH6 4 15 AD1 AD1 5 16 CH5 CH7 5 14 AD0 SCL 6 15 CH4 COM 6 13 VDD SDA 7 14 CH3 GND 8 13 CH2 7 8 9 10 11 12 VREF COMP GND GND GND VDD GVNDDD 190 1121 CCHH10 F E R F PACKAGE UF PACKAGE 20-LEAD PLASTIC TSSOP 24-LEAD (4mm (cid:115) 4mm) PLASTIC QFN TJMAX = 150°C, θJA = 37°C/W TJMAX = 150°C, θJA = 90°C/W, θJC = 20°C/W EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB ORDeR InFORMAtIOn LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2309CUF#PBF LTC2309CUF#TRPBF 2309 24-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C LTC2309IUF#PBF LTC2309IUF#TRPBF 2309 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C LTC2309CF#PBF LTC2309CF#TRPBF LTC2309F 20-Lead Plastic TSSOP 0°C to 70°C LTC2309IF#PBF LTC2309IF#TRPBF LTC2309F 20-Lead Plastic TSSOP –40°C to 85°C LTC2309HF#PBF LTC2309HF#TRPBF LTC2309F 20-Lead Plastic TSSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2309fd 

LTC2309 COnVeRteR AnD MuLtIpLexeR CHARACteRIstICs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Notes 4, 5) A PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) l 12 Bits Integral Linearity Error (Note 6) l ±0.45 ±1 LSB Differential Linearity Error l ±0.35 ±1 LSB Bipolar Zero Error (Note 7) l ±1 ±8 LSB Bipolar Zero Error Drift 0.002 LSB/°C Bipolar Zero Error Match ±0.1 ±3 LSB Unipolar Zero Error (Note 7) l ±0.4 ±6 LSB Unipolar Zero Error Drift 0.002 LSB/°C Unipolar Zero Error Match ±0.2 ±1 LSB Bipolar Full-Scale Error External Reference (Note 8) l ±0.5 ±10 LSB REFCOMP = 4.096V l ±0.4 ±9 LSB Bipolar Full-Scale Error Drift External Reference 0.05 LSB/°C Bipolar Full-Scale Error Match ±0.4 ±3 LSB Unipolar Full-Scale Error QFN External Reference (Note 8) l ±0.4 ±10 LSB TSSOP External Reference (Note 8) l ±0.5 ±12 LSB REFCOMP = 4.096V l ±0.3 ±6 LSB Unipolar Full-Scale Error Drift External Reference 0.05 LSB/°C Unipolar Full-Scale Error Match ±0.3 ±2 LSB AnALOG Input The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V + Absolute Input Range (CH0 to CH7) (Note 9) l –0.05 REFCOMP V IN V – Absolute Input Range (CH0 to CH7, COM) Unipolar (Note 9) l –0.05 0.25 • REFCOMP V IN Bipolar (Note 9) l –0.05 0.75 • REFCOMP V V + – V – Input Differential Voltage Range V = V + – V – (Unipolar) l 0 to REFCOMP V IN IN IN IN IN V = V + – V – (Bipolar) l ±REFCOMP/2 V IN IN IN I Analog Input Leakage Current l ±1 µA IN C Analog Input Capacitance Sample Mode 55 pF IN Hold Mode 5 pF CMRR Input Common Mode Rejection Ratio 70 dB DYnAMIC ACCuRACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. A = –1dBFS. (Notes 4, 10) A IN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SINAD Signal-to-(Noise + Distortion) Ratio f = 1kHz l 71 73.3 dB IN SNR Signal-to-Noise Ratio f = 1kHz l 71 73.4 dB IN THD Total Harmonic Distortion f = 1kHz, First 5 Harmonics l –88 –77 dB IN SFDR Spurious Free Dynamic Range f = 1kHz l 79 90 dB IN Channel-to-Channel Isolation f = 1kHz –109 dB IN Full Linear Bandwidth (Note 11) 700 kHz –3dB Input Linear Bandwidth 25 MHz Aperture Delay 13 ns Transient Response Full-Scale Step 240 ns 2309fd 

LTC2309 InteRnAL ReFeRenCe CHARACteRIstICs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4) A PARAMETER CONDITIONS MIN TYP MAX UNITS V Output Voltage I = 0 (QFN) l 2.47 2.50 2.53 V REF OUT I = 0 (TSSOP) l 2.46 2.50 2.54 V OUT V Output Tempco I = 0 ±25 ppm/°C REF OUT V Output Impedance –0.1mA ≤ I ≤ 0.1mA 8 kΩ REF OUT V Output Voltage I = 0 4.096 V REFCOMP OUT V Line Regulation V = 4.75V to 5.25V 0.8 mV/V REF DD 2 I C Inputs AnD DIGItAL Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V High Level Input Voltage l 2.85 V IH V Low Level Input Voltage l 1.5 V IL V High Level Input Voltage for Address Pins A1, A0 l 4.75 V IHA V Low Level Input Voltage for Address Pins A1, A0 l 0.25 V ILA R Resistance from A1, A0, to V to Set Chip l 10 kΩ INH DD Address Bit to 1 R Resistance from A1, A0 to GND to Set Chip l 10 kΩ INL Address Bit to 0 R Resistance from A1, A0 to GND or V to Set l 2 MΩ INF DD Chip Address Bit to Float I Digital Input Current V = V l –10 10 µA I IN DD V Hysteresis of Schmitt Trigger Inputs (Note 9) l 0.25 V HYS V Low Level Output Voltage (SDA) I = 3mA l 0.4 V OL t Output Fall Time V to V (Note 12) l 20 + 0.1C 250 ns OF H IL(MAX) B t Input Spike Suppression l 50 ns SP C External Capacitance Load On-Chip Address Pins l 10 pF CAX (A1, A0) for Valid Float pOWeR ReQuIReMents The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Supply Voltage l 4.75 5 5.25 V DD I Supply Current 14ksps Sample Rate l 2.3 3 mA DD Nap Mode SLP Bit = 0, Conversion Done l 210 350 µA Sleep Mode SLP Bit = 1, Conversion Done l 7 15 µA P Power Dissipation 14ksps Sample Rate l 11.5 15 mW D Nap Mode SLP Bit = 0, Conversion Done l 1.05 1.75 mW Sleep Mode SLP Bit = 1, Conversion Done l 35 75 µW 2309fd 

LTC2309 2 I C tIMInG CHARACteRIstICs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f SCL Clock Frequency l 400 kHz SCL t Hold Time (Repeated) START Condition l 0.6 µs HD(SDA) t LOW Period of the SCL Pin l 1.3 µs LOW t HIGH Period of the SCL Pin l 0.6 µs HIGH t Set-Up Time for a Repeated START Condition l 0.6 µs SU(STA) t Data Hold Time l 0 0.9 µs HD(DAT) t Data Set-Up Time l 100 ns SU(DAT) t Rise Time for SDA/SCL Signals (Note 12) l 20 + 0.1C 300 ns r B t Fall Time for SDA/SCL Signals (Note 12) l 20 + 0.1C 300 ns f B t Set-Up Time for STOP Condition l 0.6 µs SU(STO) t Bus Free Time Between a STOP and START Condition l 1.3 µs BUF ADC tIMInG CHARACteRIstICs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 4) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f Throughput Rate (Successive Reads) l 14 ksps SMPL t Conversion Time (Note 9) l 1.3 1.8 µs CONV t Acquisition Time (Note 9) l 240 ns ACQ t REFCOMP Wake-Up Time (Note 13) C = 10µF, C = 2.2µF 200 ms REFWAKE REFCOMP REF Note 1: Stresses beyond those listed under Absolute Maximum Ratings 1111. Unipolar zero error is the offset voltage measured from +0.5LSB may cause permanent damage to the device. Exposure to any Absolute when the output code flickers between 0000 0000 0000 and 0000 0000 Maximum Rating condition for extended periods may affect device 0001. reliability and lifetime. Note 8: Full-scale bipolar error is the worst-case of –FS or +FS untrimmed Note 2: All voltage values are with respect to ground. deviation from ideal first and last code transitions and includes the effect Note 3: When these pin voltages are taken below ground or above V , of offset error. Unipolar full-scale error is the deviation of the last code DD they will be clamped by internal diodes. These products can handle input transition from ideal and includes the effect of offset error. currents greater than 100mA below ground or above V without latchup. Note 9: Guaranteed by design, not subject to test. DD Note 4: V = 5V, f = 14ksps internal reference unless otherwise Note 10: All specifications in dB are referred to a full-scale ±2.048V input DD SMPL noted. with a 2.5V reference voltage. Note 5: Linearity, offset and full-scale specifications apply for a Note 11: Full linear bandwidth is defined as the full-scale input frequency single-ended analog input with respect to COM. at which the SINAD degrades to 60dB or 10 bits of accuracy. Note 6: Integral nonlinearity is defined as the deviation of a code from a Note 12: CB = capacitance of one bus line in pF (10pF ≤ CB ≤ 400pF). straight line passing through the actual endpoints of the transfer curve. Note 13: REFCOMP wake-up time is the time required for the REFCOMP The deviation is measured from the center of the quantization band. pin to settle within 0.5LSB at 12-bit resolution of its final value after Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB waking up from SLEEP mode. when the output code flickers between 0000 0000 0000 and 1111 1111 2309fd 

LTC2309 tYpICAL peRFORMAnCe CHARACteRIstICs T = 25°C, V = 5V, f = 14ksps, unless otherwise noted. A DD SMPL Integral Nonlinearity Differential Nonlinearity 1kHz Sine Wave vs Output Code vs Output Code 8192 Point FFT Plot 1.00 1.00 0 SNR = 73.4dB 0.75 0.75 –20 SINAD = 73.3dB THD = –88dB 0.50 0.50 –40 B) 0.25 0.25 d NL (LSB) 0 NL (LSB) 0 NITUDE ( ––8600 I D G –0.25 –0.25 A M –100 –0.50 –0.50 –0.75 –0.75 –120 –1.00 –1.00 –140 0 1024 2048 3072 4096 0 1024 2048 3072 4096 0 1 2 3 4 5 6 7 OUTPUT CODE OUTPUT CODE FREQUENCY (kHz) 2309 G01 2309 G02 2309 G03 Supply Current vs Sampling Frequency Offset Error vs Temperature Full-Scale Error vs Temperature 2.5 2.0 4 1.5 2.0 2 PPLY CURRENT (mA) 11..50 FFSET ERROR (LSB)–100...0055 UNIPOLAR L-SCALE ERROR (LSB) –02 UBNIPIPOOLLAARR U O L S –1.0 BIPOLAR U 0.5 F –4 –0.5 0 –2.0 –6 0.1 1 10 100 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 SAMPLING FREQUENCY (ksps) TEMPERATURE (°C) TEMPERATURE (°C) 3209 G04 2309 G05 2309 G06 Analog Input Leakage Current Supply Current vs Temperature Sleep Current vs Temperature vs Temperature 3.0 10 1000 2.8 900 2.6 8 800 mA) 2.4 A) nA)700 SUPPLY CURRENT ( 1122....6802 SLEEP CURRENT (µ 64 LEAKAGE CURRENT (345600000000 CH (ON) 1.4 2 200 CH (OFF) 1.2 100 1.0 0 0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 2309 G07 2309 G08 2309 G09 2309fd 

LTC2309 pIn FunCtIOns (QFN) CH3-CH7 (Pins 1-5): Channel 3 to Channel 7 Analog AD1 (Pin 15): Chip Address Control Pin. This pin is Inputs. CH3-CH7 can be configured as single-ended configured as a three-state (LOW, HIGH, floating) or differential input channels. See the Analog Input address control bit for the device I2C address. See Multiplexer section. Table 2 for address selection. COM (Pin 6): Common Input. This is the reference SCL (Pin 16): Serial Clock Pin of the I2C Interface. The point for all single-ended inputs. It must be free of LTC2309 can only act as a slave and the SCL pin only noise and should be connected to ground for unipolar accepts an external serial clock. Data is shifted into conversions and midway between GND and REFCOMP the SDA pin on the rising edges of the SCL clock and for bipolar conversions. output through the SDA pin on the falling edges of the SCL clock. V (Pin 7): 2.5V Reference Output. Bypass to GND REF with a minimum 2.2µF ceramic capacitor. The internal SDA (Pin 17): Bidirectional Serial Data Line of the I2C reference may be overdriven by an external 2.5V refer- Interface. In transmitter mode (read), the conversion ence at this pin. result is output at the SDA pin, while in receiver mode (write), the D word is input at the SDA pin to con- REFCOMP (Pin 8): Reference Buffer Output. Bypass IN figure the ADC. The pin is high impedance during the to GND with 10µF and 0.1µF ceramic capacitors in data input mode and is an open-drain output (requires parallel. Nominal output voltage is 4.096V. The internal an appropriate pull-up device to V ) during the data reference buffer driving this pin is disabled by ground- DD output mode. ing V , allowing REFCOMP to be overdriven by an REF external source. CH0-CH2 (Pins 22-24): Channel 0 to Channel 2 Analog Inputs. CH0-CH2 can be configured as single-ended GND (Pins 9-11, 18-20): Ground. All GND pins must or differential input channels. See the Analog Input be connected to a solid ground plane. Multiplexer section. V (Pins 12, 13, 21): 5V Supply. The range of V is DD DD Exposed Pad (Pin 25): Ground. Must be soldered 4.75V to 5.25V. Bypass V to GND with a 10µF ceramic DD directly to ground plane. capacitor in parallel with three 0.1µF ceramic capacitors, one located as close as possible to each pin. AD0 (Pin 14): Chip Address Control Pin. This pin is configured as a three-state (LOW, HIGH, floating) ad- dress control bit for the device I2C address. See Table 2 for address selection. 2309fd 

LTC2309 pIn FunCtIOns (TSSOP) REFCOMP (Pin 1): Reference Buffer Output. Bypass SDA (Pin 7): Bidirectional Serial Data Line of the I2C to GND with 10µF and 0.1µF ceramic capacitors in Interface. In transmitter mode (read), the conversion parallel. Nominal output voltage is 4.096V. The internal result is output at the SDA pin, while in receiver mode reference buffer driving this pin is disabled by ground- (write), the D word is input at the SDA pin to con- IN ing V , allowing REFCOMP to be overdriven by an figure the ADC. The pin is high impedance during the REF external source. data input mode and is an open-drain output (requires an appropriate pull-up device to V ) during the data GND (Pins 2, 8 , 9): Ground. All GND pins must be DD output mode. connected to a solid ground plane. CH0-CH7 (Pins 11-18): Channel 0 to Channel 7 Analog V (Pins 3, 10): 5V Supply. The range of V is 4.75V DD DD Inputs. CH0-CH7 can be configured as single-ended to 5.25V. Bypass V to GND with a 10µF ceramic ca- DD or differential input channels. See the Analog Input pacitor in parallel with two 0.1µF ceramic capacitors, Multiplexer section. one located as close as possible to each pin. COM (Pin 19): Common Input. This is the reference AD0 (Pin 4): Chip Address Control Pin. This pin is con- point for all single-ended inputs. It must be free of figured as a three-state (LOW, HIGH, floating) address noise and should be connected to ground for unipolar control bit for the device I2C address. See Table 2 for conversions and midway between GND and REFCOMP address selection. for bipolar conversions. AD1 (Pin 5): Chip Address Control Pin. This pin is V (Pin 20): 2.5V Reference Output. Bypass to GND configured as a three-state (LOW, HIGH, floating) REF with a minimum 2.2µF ceramic capacitor. The internal address control bit for the device I2C address. See reference may be overdriven by an external 2.5V refer- Table 2 for address selection. ence at this pin. SCL (Pin 6): Serial Clock Pin of the I2C Interface. The LTC2309 can only act as a slave and the SCL pin only accepts an external serial clock. Data is shifted into the SDA pin on the rising edges of the SCL clock and output through the SDA pin on the falling edges of the SCL clock. 2309fd 

LTC2309 FunCtIOnAL BLOCK DIAGRAM VDD CH0 LTC2309 AD1 CH1 AD0 CH2 CH3 AINNAPLUOTG + 12-BIT I2C SCL CH4 MUX – SAR ADC PORT SDA CH5 CH6 VREF CH7 INTERNAL 8k COM 2.5V REF GAIN = 1.6384x REFCOMP 2308 BD GND tIMInG DIAGRAM Definition of Timing for Fast/Standard Mode Devices on the I2C Bus SDA tLOW tSU(DAT) tHD(SDA) tBUF tf tr tf tSP tr SCL tHD(SDA) tSU(STA) tSU(STO) S tHD(DAT) tHIGH Sr P S 2309 TD S = START, Sr = REPEATED START, P = STOP 2309fd 

LTC2309 AppLICAtIOns InFORMAtIOn Overview Programming the LTC2309 The LTC2309 is a low noise, 8-channel, 12-bit succes- The various modes of operation of the LTC2309 are sive approximation register (SAR) A/D converter with an programmed by a 6-bit D word. The SDI input data IN I2C compatible serial interface. The LTC2309 includes a bits are loaded on the rising edge of SCL during a write precision internal reference and a configurable 8-chan- operation, with the S/D bit loaded on the first rising edge nel analog input multiplexer (MUX). The ADC may be and the SLP bit on the sixth rising edge (see Figure 8b configured to accept single-ended or differential signals in the I2C Interface section). The input data word is and can operate in either unipolar or bipolar mode. A defined as follows: sleep mode option is also provided to further reduce S/D O/S S1 S0 UNI SLP power during inactive periods. The LTC2309 communicates through a 2-wire I2C S/D = SINGLE-ENDED/DIFFERENTIAL BIT compatible serial interface. Conversions are initiated O/S = ODD/SIGN BIT by signaling a STOP condition after the part has been S1 = CHANNEL SELECT BIT 1 successfully addressed for a read/write operation. The device will not acknowledge (NACK) an external request S0 = CHANNEL SELECT BIT 0 until the conversion is finished. After a conversion is UNI = UNIPOLAR/BIPOLAR BIT finished, the device is ready to accept a read/write request. Once the LTC2309 is addressed for a read SLP = SLEEP MODE BIT operation, the device begins outputting the conver- sion result under the control of the serial clock (SCL). Analog Input Multiplexer There is no latency in the conversion result. There are The analog input MUX is programmed by the S/D, 12 bits of output data followed by 4 trailing zeros. Data O/S, S1 and S0 bits of the D word. Table 1 lists the IN is updated on the falling edges of SCL, allowing the MUX configurations for all combinations of the con- user to reliably latch data on the rising edge of SCL. A figuration bits. Figure 1a shows several possible MUX write operation may follow the read operation by using configurations and Figure 1b shows how the MUX can a repeat START or a STOP condition may be given to be reconfigured from one conversion to the next. start a new conversion. By selecting a write operation, the ADC can be programmed with a 6-bit DIN word. The Driving the Analog Inputs D word configures the MUX and programs various IN The analog inputs of the LTC2309 are easy to drive. modes of operation of the ADC. Each of the analog inputs can be used as a single-ended During a conversion, the internal 12-bit capacitive input relative to the COM pin (CH0-COM, CH1-COM, charge redistribution DAC output is sequenced through etc.) or in differential input pairs (CH0 and CH1, CH2 a successive approximation algorithm by the SAR start- and CH3, CH4 and CH5, CH6 and CH7). Figure 2 shows ing from the most significant bit (MSB) to the least how to drive COM for single-ended inputs in unipolar significant bit (LSB). The sampled input is successively and bipolar modes. Regardless of the MUX configura- compared with binary weighted charges supplied by tion, the “+” and “–” inputs are sampled at the same the capacitive DAC using a differential comparator. At instant. Any unwanted signal that is common to both the end of a conversion, the DAC output balances the inputs will be reduced by the common mode rejection analog input. The SAR contents (a 12-bit data word) of the sample-and-hold circuit. The inputs draw only that represent the sampled analog input are loaded into one small current spike while charging the sample-and- 12 output latches that allow the data to be shifted out hold capacitors during the acquire mode. In conversion via the I2C interface. 2309fd 0

LTC2309 AppLICAtIOns InFORMAtIOn 4 Differential 8 Single-Ended 1st Conversion 2nd Conversion +(–){ CH0 + CH0 –(+) CH1 + CH1 + CH2 + { CH2 – { CH2 +(–){ CH2 + CH3 – CH3 + CH3 +––(((–++))){ CCCHHH345 ++++ CCCCHHHH4567 +–{ CCCHHO45M ++ { CCCOHHM45 (–) +(–){ CH6 (UNUSED) –(+) CH7 COM (–) 2328 F01b Figure 1b. Changing the MUX Assignments “On the Fly” Combinations of Differential and Single-Ended +{ CH0 – CH1 Unipolar Mode Bipolar Mode –{ CH2 + CH3 + CH4 COM COM + CH5 REFCOMP/2 +– + CH6 2328 F02 + CH7 COM (–) Figure 2. Driving COM in Unipolar and Bipolar Modes 2309 F01a Figure 1a. Example of MUX Configurations mode, the analog inputs draw only a small leakage cur- Table 1. Channel Configuration rent. If the source impedance of the driving circuit is S/D O/S S1 S0 0 1 2 3 4 5 6 7 COM low, the ADC inputs can be driven directly. Otherwise, 0 0 0 0 + – more acquisition time should be allowed for a source 0 0 0 1 + – with higher impedance. 0 0 1 0 + – 0 0 1 1 + – Input Filtering 0 1 0 0 – + The noise and distortion of the input amplifier and 0 1 0 1 – + other circuitry must be considered since they will add 0 1 1 0 – + to the ADC noise and distortion. Therefore, noisy input 0 1 1 1 – + circuitry should be filtered prior to the analog inputs to 1 0 0 0 + – minimize noise. A simple 1-pole RC filter is sufficient for many applications. 1 0 0 1 + – 1 0 1 0 + – The analog inputs of the LTC2309 can be modeled as 1 0 1 1 + – a 55pF capacitor (CIN) in series with a 100Ω resistor (R ), as shown in Figure 3a. C gets switched to the 1 1 0 0 + – ON IN selected input once during each conversion. Large filter 1 1 0 1 + – RC time constants will slow the settling of the inputs. 1 1 1 0 + – It is important that the overall RC time constants be 1 1 1 1 + – short enough to allow the analog inputs to completely settle to 12-bit resolution within the acquisition time (t ) if DC accuracy is important. ACQ 2309fd 

LTC2309 AppLICAtIOns InFORMAtIOn When using a filter with a large C value (e.g. 1µF), FILTER 50Ω ANALOG the inputs do not completely settle and the capacitive INPUT CH0 input switching currents are averaged into a net DC 2000pF LTC2309 current (I ). In this case, the analog input can be mod- COM DC eled by an equivalent resistance (R = 1/(f • C )) EQ SMPL IN in series with an ideal voltage source (VREFCOMP/2), as REFCOMP 0.1µF 10µF shown in Figure 3b. The magnitude of the DC current 2309 F04a is then approximately I = (V – V /2)/R , DC IN REFCOMP EQ which is roughly proportional to V . To prevent large Figure 4a. Optional RC Input Filtering for Single-Ended Input IN DC drops across the resistor R , a filter with a small FILTER resistor and large capacitor should be chosen. When running at the maximum throughput rate of 14ksps, 1000pF 50Ω the input current equals 1.5µA at V = 4.096V, which CH0 IN DIFFERENTIAL amounts to a full-scale error of 0.5LSB when using a ANALOG 1000pF LTC2309 INPUTS 50Ω filter resistor (R ) of 333Ω. Applications requiring CH1 FILTER 1000pF lower sample rates can tolerate a larger filter resistor for the same amount of full-scale error. REFCOMP 0.1µF 10µF 2309 F04b INPUT RSOURCE CH0-CH7 1R0O0NΩ LTC2309 Figure 4b. Optional RC Input Filtering for Differential Inputs VIN CIN CFILTER 55pF self heating and from damage that may occur during soldering. Metal film surface mount resistors are much 2309 F03a less susceptible to both problems. Figure 3a. Analog Input Equivalent Circuit Dynamic Performance INPUT RFILTER IDC CH0-CH7 Fast Fourier Transform (FFT) test techniques are used to VIN LTC2309 test the ADC’s frequency response, distortion and noise REQ CFILTER 1/(fSMPL • CIN) at the rated throughput. By applying a low distortion + – VREFCOMP/2 sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined 2309 F03b for frequencies outside the fundamental. Figure 3b. Analog Input Equivalent Circuit for Large Filter Capacitances Signal-to-Noise and Distortion Ratio (SINAD) Figures 4a and 4b show examples of input filtering for The signal-to-noise and distortion ratio (SINAD) is the single-ended and differential inputs. For the single- ratio between the RMS amplitude of the fundamental ended case in Figure 4a, a 50Ω source resistor and a input frequency to the RMS amplitude of all other fre- 2000pF capacitor to ground on the input will limit the quency components at the A/D output. The output is input bandwidth to 1.6MHz. High quality capacitors and band-limited to frequencies from above DC and below resistors should be used in the RC filter since these half the sampling frequency. Figure 5 shows a typical components can add distortion. NPO and silver mica SINAD of 73.3dB with a 14kHz sampling rate and a type dielectric capacitors have excellent linearity. Carbon 1kHz input. An SNR of 73.4dB can be achieved with surface mount resistors can generate distortion from the LTC2309. 2309fd 

LTC2309 AppLICAtIOns InFORMAtIOn 0 internal reference buffer can also be overdriven from SNR = 73.4dB 1V to V , as shown in Figure 6c. To do so, V must –20 SINAD = 73.3dB DD REF THD = –88dB be grounded to disable the reference buffer. –40 B) d E ( –60 D U R1 T NI –80 VREF 8k BANDGAP G 2.5V A REFERENCE M 2.2µF –100 –120 4.096V REFCOMP REFERENCE AMP –140 0 1 2 3 4 5 6 7 10µF FREQUENCY (kHz) 0.1µF R2 2309 G03 Figure 5. 1kHz Sine Wave 8192 Point FFT Plot GND R3 LTC2309 2309 F06a Total Harmonic Distortion (THD) Figure 6a. LTC2309 Reference Circuit Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into 5V the frequency band between DC and half the sampling frequency (fSMPL/2). THD is expressed as: 0.1µF VIN LT1790A-2.5 V2+V2+V 2...+V 2 VOUT VREF 2 3 4 N THD=20log 2.2µF LTC2309 V 1 REFCOMP where V1 is the RMS amplitude of the fundamental 10µF 0.1µF frequency and V2 through VN are the amplitudes of the GND second through Nth harmonics. 2309 F06b Internal Reference Figure 6b. Using the LT®1790A-2.5 as an External Reference The LTC2309 has an on-chip, temperature compen- sated bandgap reference that is factory trimmed to 2.5V (Refer to Figure 6a). It is internally connected to a 5V reference amplifier and is available at V . V should be bypassed to GND with a 2.2μF ceraRmEiFc caRpEaFcitor to 0.1µF VIN VREF LTC2309 minimize noise. An 8k resistor is in series with the output LT1790A-4.096 VOUT REFCOMP so that it can be easily overdriven by an external refer- 10µF 0.1µF ence if more accuracy and/or lower drift are required, GND as shown in Figure 6b. The reference amplifier gains the V voltage by 1.638 to 4.096V at REFCOMP. To 2309 F06c REF compensate the reference amplifier, bypass REFCOMP Figure 6c. Overdriving REFCOMP Using the LT1790A-4.096 with a 10μF ceramic capacitor in parallel with a 0.1μF ceramic capacitor for best noise performance. The 2309fd 

LTC2309 AppLICAtIOns InFORMAtIOn Internal Conversion Clock The START and STOP Conditions The internal conversion clock is factory trimmed to Referring to Figure 7, a START (S) condition is gener- achieve a typical conversion time (t ) of 1.3μs and ated by transitioning SDA from HIGH to LOW while CONV a maximum conversion time of 1.8μs over the full SCL is HIGH. The bus is considered to be busy after the operating temperature range. START condition. When the data transfer is finished, a STOP (P) condition is generated by transitioning SDA I2C Interface from LOW to HIGH while SCL is HIGH. The bus is free The LTC2309 communicates through an I2C interface. after a STOP condition is generated. START and STOP The I2C interface is a 2-wire open-drain interface sup- conditions are always generated by the master. porting multiple devices and multiple masters on a When the bus is in use, it stays busy if a repeated single bus. The connected devices can only pull the START (Sr) is generated instead of a STOP condition. serial data line (SDA) LOW and can never drive it HIGH. The repeated START timing is functionally identical to SDA is required to be externally connected to the sup- the START and is used for writing and reading from the ply through a pull-up resistor. When the data line is not device before the initiation of a new conversion. being driven LOW, it is HIGH. Data on the I2C bus can be transferred at rates up to 100kbits/s in the standard START Condition STOP Condition mode and up to 400kbits/s in the fast mode. The V DD power should not be removed from the LTC2309 when SDA the I2C bus is active to avoid loading the I2C bus lines SDA S P through the internal ESD protection diodes. Each device on the I2C bus is recognized by a unique SCL SCL 2309 F07 address stored in the device and can only operate either Figure 7. Timing Diagrams of START and STOP Conditions as a transmitter or receiver, depending on the function of the device. A device can also be considered as a master or a slave when performing data transfers. A Data Transferring master is the device which initiates a data transfer on After the START condition, the I2C bus is busy and the bus and generates the clock signals to permit the data transfer can begin between the master and the transfer. Devices addressed by the master are consid- addressed slave. Data is transferred over the bus in ered slaves. groups of nine bits, one byte followed by one ac- The LTC2309 can only be addressed as a slave (see knowledge (ACK) bit. The master releases the SDA Table 2). Once addressed, it can receive configuration line during the ninth SCL clock cycle. The slave device bits (DIN word) or transmit the last conversion result. The can issue an ACK by pulling SDA LOW or issue a Not serial clock line (SCL) is always an input to the LTC2309 Acknowledge (NACK) by leaving the SDA line high and the serial data line (SDA) is bidirectional. The device impedance (the external pull-up resistor will hold the supports the standard mode and the fast mode for data line high). Change of data only occurs while the SCL transfer speeds up to 400kbits/s (see the Timing Diagram line is LOW. section for definition of the I2C timing). Data Format After a START condition, the master sends a 7-bit address followed by a read/write (R/W) bit. The R/W bit is 1 for a read request and 0 for a write request. If the 7-bit address matches one of the LTC2309’s 9 pin-selectable addresses, the ADC is selected. When 2309fd 

LTC2309 AppLICAtIOns InFORMAtIOn the ADC is addressed during a conversion, it will not a read operation, it acknowledges by pulling SDA acknowledge R/W requests and will issue a NACK by LOW and acts as a transmitter. The master/receiver leaving the SDA line HIGH. If the conversion is com- can read up to two bytes from the LTC2309. After a plete, the LTC2309 issues an ACK by pulling the SDA complete read operation of 2 bytes, a STOP condition line LOW. The LTC2309 has two registers. The 12-bit is needed to initiate a new conversion. The device will wide output register contains the last conversion result. NACK subsequent read operations while a conversion The 6-bit wide input register configures the input MUX is being performed. and the operating mode of the ADC. The data output stream is 16 bits long and is shifted out on the falling edges of SCL (see Figure 8a). The Output Data Format first bit is the MSB and the 12th bit is the LSB of the The output register contains the last conversion result. conversion result. The remaining four bits are zero. After each conversion is completed, the device auto- Figures 14 and 15 are the transfer characteristics for matically enters either nap or sleep mode depending the bipolar and unipolar modes. Data is output on the on the setting of the SLP bit (see Nap Mode and Sleep SDA line in 2’s complement format for bipolar readings Mode sections). When the LTC2309 is addressed for or in straight binary for unipolar readings. 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL • • • SDA A6 A5 A4 A3 A2 A1 A0 R/W B11 B10 B9 B8 B7 B6 B5 B4 • • • START BY ACK BY ACK BY MASTER ADC MOST SIGNIFICANT DATA BYTE MASTER ADDRESS FRAME READ 1 BYTE 1 2 3 4 5 6 7 8 9 SCL • • • (CONTINUED) CONVERSION INITIATED SDA • • • B3 B2 B1 B0 STOP (CONTINUED) BY MASTER NACK BY LEAST SIGNIFICANT DATA BYTE MASTER READ 1 BYTE 2309 F08a Figure 8a. Timing Diagram for Reading from the LTC2309 2309fd 

LTC2309 AppLICAtIOns InFORMAtIOn Input Data Format read/write operation will also initiate new conversion, but the output result may not be valid due to lack of When the LTC2309 is addressed for a write operation, adequate acquisition time (see Acquisition section). it acknowledges by pulling SDA LOW during the LOW period before the 9th cycle and acts as a receiver. The LTC2309 Address master/transmitter can then send 1 byte to program the device. The input byte consists of the 6-bit D word The LTC2309 has two address pins (AD0 and AD1) that IN followed by two bits that are ignored by the ADC and may be tied HIGH, LOW, or left floating to enable one are considered don’t cares (X) (see Figure 8b). The of 9 possible addresses (see Table 2). input bits are latched on the rising edge of SCL during In addition to the configurable addresses listed in the write operation. Table 2, the LTC2309 also contains a global address After power-up, the ADC initiates an internal reset (1101011) which may be used for synchronizing mul- cycle which sets the D word to all 0s (S/D = O/S = tiple LTC2309s or other I2C LTC230X SAR ADCs (see IN S0 = S1 = UNI = SLP = 0). A write operation may be Synchronizing Multiple LTC2309s with Global Address performed if the default state of the ADC’s configuration Call section). is not desired. Otherwise, the ADC must be properly Table 2. Address Assignment addressed and followed by a STOP condition to initiate AD1 AD0 ADDRESS a conversion. LOW LOW 0001000 Initiating a New Conversion LOW Float 0001001 LOW HIGH 0001010 The LTC2309 awakens from either nap or sleep when Float HIGH 0001011 properly addressed for a read/write operation. A STOP Float Float 0011000 command may then be issued after performing the Float LOW 0011001 read/write operation to trigger a new conversion. HIGH LOW 0011010 Issuing a STOP command after the 8th SCL clock pulse HIGH Float 0011011 of the address frame and before the completion of a HIGH HIGH 0101000 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL CONVERSION INITIATED SDA A6 A5 A4 A3 A2 A1 A0 R/W S/D O/S S1 S0 UNI SLP X X STOP BY MASTER START BY ACK BY ACK BY MASTER ADC DIN WORD ADC ADDRESS FRAME WRITE 1 BYTE 2309 F08b Figure 8b. Timing Diagram for Writing to the LTC2309 2309fd 

LTC2309 AppLICAtIOns InFORMAtIOn Continuous Read ates a NACK signal indicating the conversion cycle is in progress. In applications where the same input channel is sampled each cycle, conversions can be continuously performed Continuous Read/Write and read without a write cycle (see Figure 9). The D IN word remains unchanged from the last value written Once the conversion cycle is complete, the LTC2309 into the device. If the device has not been written to can be written to and then read from using the repeated since power-up, the D word defaults to all 0s (S/D = START (Sr) command. Figure 10 shows a cycle which IN O/S = S0 = S1 = UNI = SLP = 0). At the end of a read begins with a data write, a repeated START, followed operation, a STOP condition may be given to start a new by a read and concluded with a STOP command. After conversion. At the conclusion of the conversion cycle, all 16 bits are read out, a conversion may be initiated the next result may be read using the method described by issuing a STOP command. The following conver- above. If the conversion cycle is not concluded and a sion will be performed using the newly programmed valid address selects the device, the LTC2309 gener- data. S 7-BIT ADDRESS R ACK READ P S 7-BIT ADDRESS R ACK READ P CONVERSION NAP DATA OUTPUT CONVERSION NAP DATA CONVERSION OUTPUT 2309 F09 Figure 9. Consecutive Reading with the Same Configuration S 7-BIT ADDRESS W ACK WRITE Sr 7-BIT ADDRESS R ACK READ P CONVERSION NAP DATA INPUT ADDRESS DATA CONVERSION OUTPUT 2309 F10 Figure 10. Write, Read, START Conversion 2309fd 

LTC2309 AppLICAtIOns InFORMAtIOn Synchronizing Multiple LTC2309s with a Global Nap Mode Address Call The ADC enters nap mode after a conversion is com- In applications where several LTC2309s or other I2C SAR plete (t ) if the SLP bit is set to a logic 0. The sup- CONV ADCs from Linear Technology Corporation are used on ply current decreases to 210μA in nap mode between the same I2C bus, all converters can be synchronized conversions, thereby reducing the average power through the use of a global address call. Prior to issu- dissipation as the sample rate decreases. For example, ing the global address call, all converters must have the LTC2309 draws an average of 300µA at a 1ksps completed a conversion cycle. The master then issues sampling rate. The LTC2309 keeps only the reference a START, followed by the global address 1101011, and (V ) and reference buffer (REFCOMP) circuitry active REF a write request. All converters will be selected and ac- when in nap mode. knowledge the request. The master then sends a write byte (optional) followed by the STOP command. This will Sleep Mode update the channel selection (optional) and simultane- The ADC enters sleep mode after a conversion is com- ously initiate a conversion for all ADCs on the bus (see plete (t ) if the SLP bit is set to a logic 1. The ADC CONV Figure 11). In order to synchronize multiple converters draws only 7µA in sleep mode, provided that none of without changing the channel, a STOP command may the digital inputs are switching. When the LTC2309 is be issued after acknowledgement of the global write properly addressed, the ADC is released from sleep mode command. Global read commands are not allowed and and requires 200ms (t ) to wake up and charge REFWAKE the converters will NACK a global read request. the respective 2.2μF and 10μF bypass capacitors on the V and REFCOMP pins. A new conversion should not REF be initiated before this time, as shown in Figure 12. SCL SDA LTC2309 LTC2309 LTC2309 S GLOBAL ADDRESS W ACK WRITE (OPTIONAL) P CONVERSION NAP DATA OUTPUT CONVERSION OF ALL LTC2309s 2309 F11 Figure 11. Synchronous Multiple LTC2309s with a Global Address Call S 7-BIT ADDRESS R/W ACK P CONVERSION SLEEP tREFWAKE CONVERSION 2309 F12 Figure 12. Exiting Sleep Mode and Starting a New Conversion 2309fd 

LTC2309 AppLICAtIOns InFORMAtIOn Acquisition If a write operation is being performed, acquisition of the input signal begins on the falling edge of the sixth The LTC2309 begins acquiring the input signal at dif- clock cycle after the D word has been shifted in, as ferent instances depending on whether a read or write IN shown in Figure 13b. The LTC2309 will acquire the operation is being performed. If a read operation is signal from the input channel that was most recently being performed, acquisition of the input signal begins programmed by the D word. A minimum of 240ns is on the rising edge of the 9th clock pulse following the IN required to acquire the input signal before initiating a address frame, as shown in Figure 13a. new conversion. 1 2 3 4 5 6 7 8 9 1 2 SCL ACQUISITION BEGINS SDA A6 A5 A4 A3 A2 A1 A0 R/W B11 B10 2309 F13a tACQ Figure 13a. Timing Diagram Showing Acquisition During a Read Operation 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SCL ACQUISITION BEGINS SDA A2 A1 A0 R/W S/D O/S S1 S0 UNI SLP X X tACQ 2309 F13b Figure 13b. Timing Diagram Showing Acquisition During a Write Operation T) 011...111 111...111 EN 011...110 BIPOLAR 111...110 M E ZERO L P OM 000...001 DE 100...001 C O DE (TWO’S 011011011.........011011001 OUTPUT C 100011011.........011011001 UNZIPEORLOAR O C T OUTPU 110000......000001 F11SLL SS=BB 4 ==.0 F19Sm6/V2V12 000000......000001 F11SLL SS=BB 4 ==.0 F19Sm6/V2V12 –FS/2 –1 0V 1 FS/2 – 1LSB 0V FS – 1LSB LSB LSB INPUT VOLTAGE (V) INPUT VOLTAGE (V) 2309 F14 2309 F15 Figure 14. Bipolar Transfer Characteristics (2’s Complement) Figure 15. Unipolar Transfer Characteristics (Straight Binary) 2309fd 

LTC2309 AppLICAtIOns InFORMAtIOn Board Layout and Bypassing and V should be bypassed to the ground plane as close DD to the pin as possible. Maintaining a low impedance path To obtain the best performance, a printed circuit board with for the common return of these bypass capacitors is a solid ground plane is required. Layout for the printed essential to the low noise operation of the ADC. These board should ensure digital and analog signal lines are traces should be as wide as possible. See Figures 16a-e separated as much as possible. Care should be taken not for a suggested layout. to run any digital signals alongside an analog signal. All analog inputs should be shielded by GND. V , REFCOMP REF 2309 F16a Figure 16a. Top Silkscreen 2309fd 0

LTC2309 AppLICAtIOns InFORMAtIOn 2309 F16b Figure 16b. Layer 1 Component Side 2309 F16c Figure 16c. Layer 2 Ground Plane 2309fd 

LTC2309 AppLICAtIOns InFORMAtIOn 2309 F16d Figure 16d. Layer 3 Power Plane 2309 F16e Figure 16e. Layer Back Solder Side 2309fd 

LTC2309 pACKAGe DesCRIptIOn UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 0.70 ±0.05 4.50 ± 0.05 2.45 ± 0.05 3.10 ± 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.20 TYP OR 4.00 ± 0.10 0.75 ± 0.05 R = 0.115 0.35(cid:115) 45° CHAMFER TYP (4 SIDES) 23 24 PIN 1 0.40 ± 0.10 TOP MARK (NOTE 6) 1 2 2.45 ± 0.10 (4-SIDES) (UF24) QFN 0105 0.200 REF 0.25 ± 0.05 0.00 – 0.05 0.50 BSC NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2309fd 

LTC2309 pACKAGe DesCRIptIOn F Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1650) 6.40 – 6.60* (.252 – .260) 1.05 ±0.10 2019181716151413 1211 6.60 ±0.10 4.50 ±0.10 6.40 (.252) BSC 0.45±0.05 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10 1.10 4.30 – 4.50** (.0433) (.169 – .177) 0.25 MAX REF 0° – 8° 0.65 0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15 (.0035 – .0079) (.020 – .030) BSC (.002 – .006) 0.19 – 0.30 NOTE: (.0075 – .0118) F20 TSSOP 0204 1. CONTROLLING DIMENSION: MILLIMETERS TYP MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 2309fd 

LTC2309 ReVIsIOn HIstORY (Revision history begins at Rev D) REV DATE DESCRIPTION PAGE NUMBER D 7/10 Revised Block Diagram 1 Changed AV and DV pins to V only 2, 4-9, 20 DD DD DD Revised Note 2 5 Consolidated AV and DV into V and revised V and REFCOMP pin descriptions in Pin Functions section 7, 8 DD DD DD REF Revised Figures 6b and 6c and Internal Reference paragraph, and added text to I2C Interface in Applications 13, 14 Information section Changed NAK to NACK in Figure 8a 15 Revised Typical Application 26 2309fd Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC2309 tYpICAL AppLICAtIOn Driving the LTC2309 with ±10V Input Signals Using a Precision Attenuator 5V IN OUT 0.1µF LT1790-2.5 1µF GND 10V 5V 7 8 50k 450k 9 150k 10µF 0.1µF 10 – 4pF 450k LT1991 6 100Ω CH0 VDD AD1 AD0 1.7k 1.7k 1 450k + 450k 47pF CH1 LTC2309 2 150k CH2 SI±NIG1PN0UVATL 3 50k 4pF CCHH34 AINNMAPULUXOTG +– S1A2R- BAIDTC PIO2RCT SSDCLA (FCPOGLNAO,TG CRICPOLLD, 4 5 CH5 DSP, ETC) CH6 –10V CH7 IN2.T5EVR RNEAFL VREF COM 2.2µF REFCOMP GND 0.1µF 10µF 2309 TA02 ReLAteD pARts PART NUMBER DESCRIPTION COMMENTS LTC1417 14-Bit, 400ksps Serial ADC 20mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package LTC1468/LTC1469 Single/Dual 90MHz, 22V/µs, 16-Bit Accurate Low Input Offset: 75µV/125µV Op Amps LTC1609 16-Bit, 200ksps Serial ADC 65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply LTC1790 Micropower Low Dropout Reference 60µA Supply Current, 10ppm/°C, SOT-23 Package LTC1850/LTC1851 10-Bit/12-Bit, 8-Channel, 1.25Msps ADCs Parallel Output, Programmable MUX and Sequencer, 5V Supply LTC1852/LTC1853 10-Bit/12-Bit, 8-Channel, 400ksps ADCs Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply LTC1860/LTC1861 12-Bit, 1-/2-Channel 250ksps ADCs in MSOP 850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages LTC1860L/LTC1861L 3V, 12-bit, 1-/2-Channel 150ksps ADCs 450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages LTC1863/LTC1867 12-/16-Bit, 8-Channel 200ksps ADCs 6.5mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package LTC1863L/LTC1867L 3V, 12-/16-bit, 8-Channel 175ksps ADCs 2mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package LTC1864/LTC1865 16-Bit, 1-/2-Channel 250ksps ADCs in MSOP 850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel 150ksps ADCs in MSOP 450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages LTC2302/LTC2306 12-Bit, 1-/2-Channel 500ksps SPI ADCs in 14mW at 500ksps, Single 5V Supply, Software Compatible with LTC2308 3mm × 3mm DFN LTC2308 12-Bit, 8-Channel 500ksps SPI ADC 5V, Internal Reference, 4mm × 4mm QFN Package, Software Compatible with LTC2302/LTC2306 LTC2453 Easy-to-Use, Ultratiny 16-Bit I2C Delta Sigma ADC 2LSB INL, 50nA Sleep Current, 60Hz Output Rate, 3mm × 2mm DFN Package LTC2487/LTC2489/ 2-/4-Channel Easy Drive™ I2C Delta Sigma ADCs 16-/24 Bits, PGA and Temperature Sensor, 15Hz Output Rate, 4mm × 3mm LTC2493 DFN Packages LTC2495/LTC2497/ 8-/16-Channel Easy Drive I2C Delta Sigma ADCs 16-/24-Bits, PGA and Temperature Sensor, 15Hz Output Rate, 5mm × 7mm LTC2499 QFN Packages 2309fd  Linear Technology Corporation LT 0710 REV D • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2008

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: LTC2309HF#PBF LTC2309CF#PBF LTC2309IUF#PBF LTC2309CF#TRPBF LTC2309IUF#TRPBF LTC2309HF#TRPBF LTC2309CUF#TRPBF LTC2309IF#PBF LTC2309IF#TRPBF LTC2309CUF#PBF