LTC2145-14/ LTC2144-14/LTC2143-14 14-Bit, 125Msps/105Msps/ 80Msps Low Power Dual ADCs FEATURES DESCRIPTION n Two-Channel Simultaneously Sampling ADC The LTC®2145-14/LTC2144-14/LTC2143-14 are 2-channel n 73.1dB SNR simultaneous sampling 14-bit A/D converters designed n 90dB SFDR for digitizing high frequency, wide dynamic range signals. n Low Power: 189mW/149mW/113mW Total They are perfect for demanding communications applica- 95mW/75mW/57mW per Channel tions with AC performance that includes 73.1dB SNR and n Single 1.8V Supply 90dB spurious free dynamic range (SFDR). Ultralow jitter n CMOS, DDR CMOS, or DDR LVDS Outputs of 0.08ps allows undersampling of IF frequencies with RMS n Selectable Input Ranges: 1V to 2V excellent noise performance. P-P P-P n 750MHz Full Power Bandwidth S/H DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) n Optional Data Output Randomizer and no missing codes over temperature. The transition n Optional Clock Duty Cycle Stabilizer noise is 1.2LSB . RMS n Shutdown and Nap Modes n Serial SPI Port for Configuration The digital outputs can be either full rate CMOS, double n 64-Pin (9mm × 9mm) QFN Package data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to APPLICATIONS range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differentially n Communications or single-ended with a sine wave, PECL, LVDS, TTL, or n Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- n Software Defined Radios lows high performance at full speed for a wide range of n Portable Medical Imaging clock duty cycles. n Multi-Channel Data Acquisition L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Nondestructive Testing Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 64k Point 2-Tone FFT, f = 69MHz, IN 1.8V 1.8V 70MHz, –1dBFS, 125Msps VDD OVDD 0 –10 CH 1 –20 14-BIT D1_13 ANALOG S/H ADC CORE (cid:116) –30 ANINACLPHOU GT2 S/H AD1C4 -CBOITRE DORUITVPEURTS DDD122___(cid:116)(cid:116)(cid:116)(cid:116)(cid:116)0103 CDOOMDRUR TODP SCDU,MRT SOLVSDS AMPLITUDE (dBFS)–––––5768400000 INPUT –90 –100 –110 125MHz CLOCK –120 0 10 20 30 40 50 60 CLOCK CONTROL FREQUENCY (MHz) 21454314 TA03b 21454314 TA01a GND OGND 21454314fa 1

LTC2145-14/ LTC2144-14/LTC2143-14 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltages (V , OV ) .......................–0.3V to 2V Digital Output Voltage ................–0.3V to (OV + 0.3V) DD DD DD Analog Input Voltage (A +, A –, Operating Temperature Range IN IN PAR/SER, SENSE) (Note 3) ..........–0.3V to (V + 0.2V) LTC2145C, LTC2144C, LTC2143C.............0°C to 70°C DD Digital Input Voltage (ENC+, ENC–, CS, LTC2145I, LTC2144I, LTC2143I ............–40°C to 85°C SDI, SCK) (Note 4) ....................................–0.3V to 3.9V Storage Temperature Range ...................–65°C to 150°C SDO (Note 4) ............................................–0.3V to 3.9V PIN CONFIGURATIONS FULL RATE CMOS OUTPUT MODE DOUBLE DATA RATE CMOS OUTPUT MODE TOP VIEW TOP VIEW 3 1 1 1 DDENSE REFDOF1F21_131_121_111_101_91_81_71_61_51_4 DDENSE REFDOF2_1NC1_12_NC1_10_NC1_8_9NC1_6_7NC1_4_5NC VSVSOODDDDDDDDDD VSVSODDDDDDDDDDD 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 6666655555555554 6666655555555554 VDD 1 48 D1_3 VDD 1 48 D1_2_3 VCM1 2 47 D1_2 VCM1 2 47 DNC GND 3 46 D1_1 GND 3 46 D1_0_1 AIN1+ 4 45 D1_0 AIN1+ 4 45 DNC AIN1– 5 44 DNC AIN1– 5 44 DNC GND 6 43 DNC GND 6 43 DNC REFH 7 42 OVDD REFH 7 42 OVDD REFL 8 65 41 OGND REFL 8 65 41 OGND REFH 9 GND 40 CLKOUT+ REFH 9 GND 40 CLKOUT+ REFL 10 39 CLKOUT– REFL 10 39 CLKOUT– PAR/SER 11 38 D2_13 PAR/SER 11 38 D2_12_13 AIN2+ 12 37 D2_12 AIN2+ 12 37 DNC AIN2– 13 36 D2_11 AIN2– 13 36 D2_10_11 GND 14 35 D2_10 GND 14 35 DNC VCM2 15 34 D2_9 VCM2 15 34 D2_8_9 VDD 16 33 D2_8 VDD 16 33 DNC 7890123456789012 7890123456789012 1112222222222333 1112222222222333 V DD+ENC –ENC CS SCK SDI DNC DNC D2_0 D2_1 D2_2 D2_3 D2_4 D2_5 D2_6 D2_7 V DD+ENC –ENC CS SCK SDI DNC DNC DNC 2_0_1 DNC 2_2_3 DNC 2_4_5 DNC 2_6_7 D D D D UP PACKAGE UP PACKAGE 64-LEAD (9mm (cid:115) 9mm) PLASTIC QFN 64-LEAD (9mm (cid:115) 9mm) PLASTIC QFN TJMAX = 150°C, θJA = 20°C/W TJMAX = 150°C, θJA = 20°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB 21454314fa 2

LTC2145-14/ LTC2144-14/LTC2143-14 PIN CONFIGURATIONS DOUBLE DATA RATE LVDS OUTPUT MODE TOP VIEW +3–3+1–1 DDENSE REFDO+F2_1–F2_11_12_11_12_11_10_11_10_1+1_8_9–1_8_9+1_6_7–1_6_7+1_4_5–1_4_5 VSVSOODDDDDDDDDD 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 6666655555555554 VDD 1 48 D1_2_3+ VCM1 2 47 D1_2_3– GND 3 46 D1_0_1+ AIN1+ 4 45 D1_0_1– AIN1– 5 44 DNC GND 6 43 DNC REFH 7 42 OVDD REFL 8 65 41 OGND REFH 9 GND 40 CLKOUT+ REFL 10 39 CLKOUT– PAR/SER 11 38 D2_12_13+ AIN2+ 12 37 D2_12_13– AIN2– 13 36 D2_10_11+ GND 14 35 D2_10_11– VCM2 15 34 D2_8_9+ VDD 16 33 D2_8_9– 7890123456789012 1112222222222333 V DD+ENC –ENC CS SCK SDI DNC DNC –_0_1 +_0_1 –_2_3 +_2_3 –_4_5 +_4_5 –_6_7 +_6_7 22222222 DDDDDDDD UP PACKAGE 64-LEAD (9mm (cid:115) 9mm) PLASTIC QFN TJMAX = 150°C, θJA = 20°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2145CUP-14#PBF LTC2145CUP-14#TRPBF LTC2145UP-14 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C LTC2145IUP-14#PBF LTC2145IUP-14#TRPBF LTC2145UP-14 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C LTC2144CUP-14#PBF LTC2144CUP-14#TRPBF LTC2144UP-14 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C LTC2144IUP-14#PBF LTC2144IUP-14#TRPBF LTC2144UP-14 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C LTC2143CUP-14#PBF LTC2143CUP-14#TRPBF LTC2143UP-14 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C LTC2143IUP-14#PBF LTC2143IUP-14#TRPBF LTC2143UP-14 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 21454314fa 3

LTC2145-14/ LTC2144-14/LTC2143-14 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 5) A LTC2145-14 LTC2144-14 LTC2143-14 PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Resolution (No Missing Codes) l 14 14 14 Bits Integral Linearity Error Differential Analog Input (Note 6) l –2.6 ±1 2.6 –2.6 ±1 2.6 –2.6 ±1 2.6 LSB Differential Linearity Error Differential Analog Input l –0.9 ±0.3 0.9 –0.9 ±0.3 0.9 –0.8 ±0.3 0.8 LSB Offset Error (Note 7) l –9 ±1.5 9 –9 ±1.5 9 –9 ±1.5 9 mV Gain Error Internal Reference ±1.5 ±1.5 ±1.5 %FS External Reference l –1.8 –0.4 0.9 –1.5 –0.3 1.1 –1.5 –0.3 1.1 %FS Offset Drift ±10 ±10 ±10 μV/°C Full-Scale Drift Internal Reference ±30 ±30 ±30 ppm/°C External Reference ±10 ±10 ±10 ppm/°C Gain Matching ±0.2 ±0.2 ±0.2 %FS Offset Matching ±1.5 ±1.5 ±1.5 mV Transition Noise 1.25 1.28 1.20 LSB RMS ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 5) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Analog Input Range (A + – A –) 1.7V < V < 1.9V l 1 to 2 V IN IN IN DD P-P V Analog Input Common Mode (A + + A –)/2 Differential Analog Input (Note 8) l 0.7 V 1.25 V IN(CM) IN IN CM V External Voltage Reference Applied to SENSE External Reference Mode l 0.625 1.250 1.300 V SENSE I Analog Input Common Mode Current Per Pin, 125Msps 155 μA INCM Per Pin, 105Msps 130 μA Per Pin, 80Msps 100 μA I Analog Input Leakage Current (No Encode) 0 < A +, A – < V l –1.5 1.5 μA IN1 IN IN DD I PAR/SER Input Leakage Current 0 < PAR/SER < V l –3 3 μA IN2 DD I SENSE Input Leakage Current 0.625 < SENSE < 1.3V l –3 3 μA IN3 t Sample-and-Hold Acquisition Delay Time 0 ns AP t Sample-and-Hold Acquisition Delay Jitter Single-Ended Encode 0.08 ps JITTER RMS Differential Encode 0.10 ps RMS CMRR Analog Input Common Mode Rejection Ratio 80 dB BW-3B Full-Power Bandwidth Figure 6 Test Circuit 750 MHz 21454314fa 4

LTC2145-14/ LTC2144-14/LTC2143-14 DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. A = –1dBFS. (Note 5) A IN LTC2145-14 LTC2144-14 LTC2143-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS SNR Signal-to-Noise Ratio 5MHz Input 73.1 72.9 73.4 dBFS 70MHz Input l 71.4 73 71.2 72.8 71.7 73.3 dBFS 140MHz Input 72.6 72.4 72.9 dBFS SFDR Spurious Free Dynamic Range 5MHz Input 90 90 90 dBFS 2nd Harmonic 70MHz Input l 76 89 77 89 78 89 dBFS 140MHz Input 84 84 84 dBFS Spurious Free Dynamic Range 5MHz Input 90 90 90 dBFS 3rd Harmonic 70MHz Input l 79 89 79 89 81 89 dBFS 140MHz Input 84 84 84 dBFS Spurious Free Dynamic Range 5MHz Input 95 95 95 dBFS 4th Harmonic or Higher 70MHz Input l 86 95 86 95 86 95 dBFS 140MHz Input 95 95 95 dBFS S/(N+D) Signal-to-Noise Plus 5MHz Input 73 72.8 73.2 dBFS Distortion Ratio 70MHz Input l 70.8 72.8 70.8 72.6 71.4 73.1 dBFS 140MHz Input 72.2 72 72.4 dBFS Crosstalk 10MHz Input –110 –110 –110 dBc INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 5) A PARAMETER CONDITIONS MIN TYP MAX UNITS V Output Voltage I = 0 0.5 • V – 25mV 0.5 • V 0.5 • V + 25mV V CM OUT DD DD DD V Output Temperature Drift ±25 ppm/°C CM V Output Resistance –600μA < I < 1mA 4 Ω CM OUT V Output Voltage I = 0 1.225 1.250 1.275 V REF OUT V Output Temperature Drift ±25 ppm/°C REF V Output Resistance –400μA < I < 1mA 7 Ω REF OUT V Line Regulation 1.7V < V < 1.9V 0.6 mV/V REF DD 21454314fa 5

LTC2145-14/ LTC2144-14/LTC2143-14 DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 5) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC– ) Differential Encode Mode (ENC– Not Tied to GND) V Differential Input Voltage (Note 8) l 0.2 V ID V Common Mode Input Voltage Internally Set 1.2 V ICM Externally Set (Note 8) l 1.1 1.6 V V Input Voltage Range ENC+, ENC– to GND l 0.2 3.6 V IN R Input Resistance (See Figure 10) 10 kΩ IN C Input Capacitance (Note 8) 3.5 pF IN Single-Ended Encode Mode (ENC– Tied to GND) V High Level Input Voltage V = 1.8V l 1.2 V IH DD V Low Level Input Voltage V = 1.8V l 0.6 V IL DD V Input Voltage Range ENC+ to GND l 0 3.6 V IN R Input Resistance (See Figure 11) 30 kΩ IN C Input Capacitance (Note 8) 3.5 pF IN DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) V High Level Input Voltage V = 1.8V l 1.3 V IH DD V Low Level Input Voltage V = 1.8V l 0.6 V IL DD I Input Current V = 0V to 3.6V l –10 10 μA IN IN C Input Capacitance (Note 8) 3 pF IN SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used) R Logic Low Output Resistance to GND V = 1.8V, SDO = 0V 200 Ω OL DD I Logic High Output Leakage Current SDO = 0V to 3.6V l –10 10 μA OH C Output Capacitance (Note 8) 3 pF OUT DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE) OV = 1.8V DD V High Level Output Voltage I = –500μA l 1.750 1.790 V OH O V Low Level Output Voltage I = 500μA l 0.010 0.050 V OL O OV = 1.5V DD V High Level Output Voltage I = –500μA 1.488 V OH O V Low Level Output Voltage I = 500μA 0.010 V OL O OV = 1.2V DD V High Level Output Voltage I = –500μA 1.185 V OH O V Low Level Output Voltage I = 500μA 0.010 V OL O DIGITAL DATA OUTPUTS (LVDS MODE) V Differential Output Voltage 100Ω Differential Load, 3.5mA Mode l 247 350 454 mV OD 100Ω Differential Load, 1.75mA Mode 175 mV V Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode l 1.125 1.250 1.375 V OS 100Ω Differential Load, 1.75mA Mode 1.250 V R On-Chip Termination Resistance Termination Enabled, OV = 1.8V 100 Ω TERM DD 21454314fa 6

LTC2145-14/ LTC2144-14/LTC2143-14 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 9) A LTC2145-14 LTC2144-14 LTC2143-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS CMOS Output Modes: Full Data Rate and Double Data Rate V Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DD OV Output Supply Voltage (Note 10) l 1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9 V DD I Analog Supply Current DC Input l 105.2 116 82.8 92 62.8 70 mA VDD Sine Wave Input 105.9 83.3 63.2 mA I Digital Supply Current Sine Wave Input, OV = 1.2V 8.5 7.1 5.4 mA OVDD DD P Power Dissipation DC Input l 189 209 149 166 113 126 mW DISS Sine Wave Input, OV = 1.2V 201 159 120 mW DD LVDS Output Mode V Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DD OV Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V DD I Analog Supply Current Sine Input, 1.75mA Mode 107.3 84.7 64.6 mA VDD Sine Input, 3.5mA Mode l 108.7 123 86.1 97 66.1 75 mA I Digital Supply Current Sine Input, 1.75mA Mode 35.1 34.8 34.5 mA OVDD (0V = 1.8V) Sine Input, 3.5mA Mode l 66.3 77 66 76 65.7 76 mA DD P Power Dissipation Sine Input, 1.75mA Mode 256 215 178 mW DISS Sine Input, 3.5mA Mode l 315 360 274 312 237 272 mW All Output Modes P Sleep Mode Power 1 1 1 mW SLEEP P Nap Mode Power 16 16 16 mW NAP P Power Increase with Differential Encode Mode Enabled 20 20 20 mW DIFFCLK (No increase for Nap or Sleep Modes) TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 5) A LTC2145-14 LTC2144-14 LTC2143-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS f Sampling Frequency (Note 10) l 1 125 1 105 1 80 MHz S t ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 500 4.52 4.76 500 5.93 6.25 500 ns L Duty Cycle Stabilizer On l 2 4 500 2 4.76 500 2 6.25 500 ns t ENC High Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 500 4.52 4.76 500 5.93 6.25 500 ns H Duty Cycle Stabilizer On l 2 4 500 2 4.76 500 2 6.25 500 ns t Sample-and-Hold 0 0 0 ns AP Acquisition Delay Time SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate) t ENC to Data Delay C = 5pF (Note 8) l 1.1 1.7 3.1 ns D L t ENC to CLKOUT Delay C = 5pF (Note 8) l 1 1.4 2.6 ns C L t DATA to CLKOUT Skew t – t (Note 8) l 0 0.3 0.6 ns SKEW D C Pipeline Latency Full Data Rate Mode 6 Cycles Double Data Rate Mode 6.5 Cycles 21454314fa 7

LTC2145-14/ LTC2144-14/LTC2143-14 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 5) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (LVDS Mode) t ENC to Data Delay C = 5pF (Note 8) l 1.1 1.8 3.2 ns D L t ENC to CLKOUT Delay C = 5pF (Note 8) l 1 1.5 2.7 ns C L t DATA to CLKOUT Skew t – t (Note 8) l 0 0.3 0.6 ns SKEW D C Pipeline Latency 6.5 Cycles SPI Port Timing (Note 8) t SCK Period Write Mode l 40 ns SCK Readback Mode, C = 20pF, R = 2k l 250 ns SDO PULLUP t CS to SCK Setup Time l 5 ns S t SCK to CS Setup Time l 5 ns H t SDI Setup Time l 5 ns DS t SDI Hold Time l 5 ns DH t SCK Falling to SDO Valid Readback Mode, C = 20pF, R = 2k l 125 ns DO SDO PULLUP Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 6: Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute best fit straight line to the transfer curve. The deviation is measured from Maximum Rating condition for extended periods may affect device the center of the quantization band. reliability and lifetime. Note 7: Offset error is the offset voltage measured from –0.5 LSB when Note 2: All voltage values are with respect to GND with GND and OGND the output code flickers between 00 0000 0000 0000 and 11 1111 1111 shorted (unless otherwise noted). 1111 in 2’s complement output mode. Note 3: When these pin voltages are taken below GND or above V , they Note 8: Guaranteed by design, not subject to test. DD will be clamped by internal diodes. This product can handle input currents Note 9: V = 1.8V, f = 125MHz (LTC2145), 105MHz (LTC2144), DD SAMPLE of greater than 100mA below GND or above VDD without latchup. or 80MHz (LTC2143), CMOS outputs, ENC+ = single-ended 1.8V square Note 4: When these pin voltages are taken below GND they will be wave, ENC– = 0V, input range = 2V with differential drive, 5pF load on P-P clamped by internal diodes. When these pin voltages are taken above V each digital output unless otherwise noted. The supply current and power DD they will not be clamped by internal diodes. This product can handle input dissipation specifications are totals for the entire IC, not per channel. currents of greater than 100mA below GND without latchup. Note 10: Recommended operating conditions. Note 5: V = OV = 1.8V, f = 125MHz (LTC2145), 105MHz DD DD SAMPLE (LTC2144), or 80MHz (LTC2143), LVDS outputs, differential ENC+/ENC– = 2V sine wave, input range = 2V with differential drive, unless P-P P-P otherwise noted. 21454314fa 8

LTC2145-14/ LTC2144-14/LTC2143-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2145-14: Integral LTC2145-14: Differential LTC2145-14: 64k Point FFT, Nonlinearity (INL) Nonlinearity (DNL) f = 5MHz, –1dBFS, 125Msps IN 2.0 1.0 0 –10 0.8 1.5 –20 0.6 1.0 –30 INL ERROR (LSB)–00..550 DNL ERROR (LSB)––0000....42042 AMPLITUDE (dBFS)–––––5768400000 –1.0 –90 –0.6 –100 –1.5 –0.8 –110 –2.0 –1.0 –120 0 4096 8192 12288 16384 0 4096 8192 12288 16384 0 10 20 30 40 50 60 OUTPUT CODE OUTPUT CODE FREQUENCY (MHz) 21454314 G01 21454314 G02 21454314 G03 LTC2145-14: 64k Point FFT, LTC2145-14: 64k Point FFT, LTC2145-14: 64k Point FFT, f = 30MHz, –1dBFS, 125Msps f = 70MHz, –1dBFS, 125Msps f = 140MHz, –1dBFS, 125Msps IN IN IN 0 0 0 –10 –10 –10 –20 –20 –20 –30 –30 –30 FS)–40 FS)–40 FS)–40 B B B E (d–50 E (d–50 E (d–50 UD–60 UD–60 UD–60 T T T LI–70 LI–70 LI–70 P P P AM–80 AM–80 AM–80 –90 –90 –90 –100 –100 –100 –110 –110 –110 –120 –120 –120 0 10 20 30 40 50 60 0 10 20 30 40 50 60 0 10 20 30 40 50 60 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) 21454314 G04 21454314 G05 21454314 G06 LTC2145-14: 64k Point 2-Tone LTC2145-14: SNR vs Input FFT, f = 69MHz, 70MHz, LTC2145-14: Shorted Input Frequency, –1dBFS, 125Msps, IN –1dBFS, 125Msps Histogram 2V Range 0 6000 74 –10 –20 5000 –30 73 SINGLE-ENDED FS)–40 4000 ENCODE PLITUDE (dB–––576000 COUNT3000 SNR (dBFS) 72 DIFEFNERCEONDTEIAL AM–80 2000 –90 71 –100 1000 –110 –120 0 70 0 10 20 30 40 50 60 8183 8185 8187 8189 8191 0 50 100 150 200 250 300 FREQUENCY (MHz) OUTPUT CODE INPUT FREQUENCY (MHz) 21454314 G07 21454314 G08 21454314 G09 21454314fa 9

LTC2145-14/ LTC2144-14/LTC2143-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2145-14: 2nd, 3rd Harmonic LTC2145-14: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, vs Input Frequency, –1dBFS, LTC2145-14: SFDR vs Input Level, 125Msps, 2V Range 125Msps, 1V Range f = 70MHz, 125Msps, 2V Range IN 100 100 120 dBFS 110 S) 95 S) 95 BF BF 100 D HARMONIC (d 988050 2ND3RD D HARMONIC (d 988050 2ND 3RD dBc AND dBFS) 798000 dBc AND 3R 75 AND 3R 75 SFDR ( 60 D D 50 N N 2 70 2 70 40 65 65 30 0 50 100 150 200 250 300 0 50 100 150 200 250 300 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) INPUT LEVEL (dBFS) 21454314 G10 218543 G11 21454314 G12 LTC2145-14: I vs Sample LTC2145-14: IO vs Sample VDD VDD Rate, 5MHz, –1dBFS, Sine Wave Rate, 5MHz, –1dBFS, Sine Wave LTC2145-14: SNR vs SENSE, Input on Each Channel on Each Input f = 5MHz, –1dBFS IN 110 70 74 105 60 3.5mA LVDS 73 72 100 50 LVDS OUTPUTS I (mA)VDD 9950 CMOS OUTPUTS IO (mA)VDD 3400 1.75mA LVDS SNR (dBFS) 767190 85 20 68 80 10 1.8V CMOS 67 75 0 66 0 25 50 75 100 125 0 25 50 75 100 125 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 SAMPLE RATE (Msps) SAMPLE RATE (Msps) SENSE PIN (V) 21454314 G13 21454314 G14 21454314 G15 LTC2144-14: Integral LTC2144-14: Differential LTC2144-14: 64k Point FFT, Nonlinearity (INL) Nonlinearity (DNL) f = 5MHz, –1dBFS, 105Msps IN 2.0 1.0 0 1.5 0.8 –10 –20 0.6 1.0 –30 R (LSB) 0.5 R (LSB) 00..42 E (dBFS)––5400 RO 0 RO 0 UD–60 R R T L E–0.5 L E–0.2 PLI–70 IN DN–0.4 AM–80 –1.0 –90 –0.6 –100 –1.5 –0.8 –110 –2.0 –1.0 –120 0 4096 8192 12288 16384 0 4096 8192 12288 16384 0 10 20 30 40 50 OUTPUT CODE OUTPUT CODE FREQUENCY (MHz) 21454314 G16 21454314 G17 21454314 G1 21454314fa 10

LTC2145-14/ LTC2144-14/LTC2143-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2144-14: 64k Point FFT, LTC2144-14: 64k Point FFT, LTC2144-14: 64k Point FFT, f = 30MHz, –1dBFS, 105Msps f = 70MHz, –1dBFS, 105Msps f = 140MHz, –1dBFS, 105Msps IN IN IN 0 0 0 –10 –10 –10 –20 –20 –20 –30 –30 –30 BFS)–40 BFS)–40 BFS)–40 E (d–50 E (d–50 E (d–50 UD–60 UD–60 UD–60 T T T LI–70 LI–70 LI–70 P P P AM–80 AM–80 AM–80 –90 –90 –90 –100 –100 –100 –110 –110 –110 –120 –120 –120 0 10 20 30 40 50 0 10 20 30 40 50 0 10 20 30 40 50 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) 21454314 G19 21454314 G20 21454314 G21 LTC2144-14: 64k Point 2-Tone LTC2144-14: SNR vs Input FFT, f = 69MHz, 70MHz, LTC2144-14: Shorted Input Frequency, –1dBFS, 105Msps, IN –1dBFS, 105Msps Histogram 2V Range 0 6000 74 –10 –20 5000 –30 73 AMPLITUDE (dBFS)–––––7685400000 COUNT432000000000 SNR (dBFS) 72 DIFEFNESRCIEONNDEGTENLIACE-LOEDNEDED –90 71 –100 1000 –110 –120 0 70 0 10 20 30 40 50 8190 8192 8194 8196 8198 0 50 100 150 200 250 300 FREQUENCY (MHz) OUTPUT CODE INPUT FREQUENCY (MHz) 21454314 G22 21454314 G23 21454314 G24 LTC2144-14: 2nd, 3rd Harmonic LTC2144-14: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, vs Input Frequency, –1dBFS, LTC2144-14: SFDR vs Input Level, 105Msps, 2V Range 105Msps, 1V Range f = 70MHz, 105Msps, 2V Range IN 100 100 120 S) 95 S) 95 110 dBFS BF BF 100 d d NIC ( 90 3RD NIC ( 90 3RD BFS) 90 RMO 85 RMO 85 2ND ND d 80 HA 2ND HA c A dBc D 3RD 80 D 3RD 80 DR (dB 7600 AN 75 AN 75 SF D D 50 N N 2 70 2 70 40 65 65 30 0 50 100 150 200 250 300 0 50 100 150 200 250 300 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) INPUT LEVEL (dBFS) 21454314 G25 218543 G26 21454314 G27 21454314fa 11

LTC2145-14/ LTC2144-14/LTC2143-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2144-14: I vs Sample LTC2144-14: IO vs Sample VDD VDD Rate, 5MHz, –1dBFS, Sine Wave Rate, 5MHz, –1dBFS, Sine Wave LTC2144-14: SNR vs SENSE, Input on Each Channel on Each Input f = 5MHz, –1dBFS IN 90 70 74 85 60 3.5mA LVDS 73 72 80 50 LVDS OUTPUTS I (mA)VDD 7750 CMOS OUTPUTS IO (mA)VDD 3400 1.75mA LVDS SNR (dBFS) 767190 65 20 68 60 10 1.8V CMOS 67 55 0 66 0 25 50 75 100 0 25 50 75 100 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 SAMPLE RATE (Msps) SAMPLE RATE (Msps) SENSE PIN (V) 21454314 G28 21454314 G29 21454314 G30 LTC2143-14: Integral LTC2143-14: Differential LTC2143-14: 64k Point FFT, Nonlinearity (INL) Nonlinearity (DNL) f = 5MHz, –1dBFS, 80Msps IN 2.0 1.0 0 1.5 0.8 –10 –20 0.6 1.0 –30 R (LSB) 0.5 R (LSB) 00..42 E (dBFS)––5400 RO 0 RO 0 UD–60 INL ER–0.5 DNL ER––00..42 AMPLIT––7800 –1.0 –90 –0.6 –100 –1.5 –0.8 –110 –2.0 –1.0 –120 0 4096 8192 12288 16384 0 4096 8192 12288 16384 0 10 20 30 40 OUTPUT CODE OUTPUT CODE FREQUENCY (MHz) 21454314 G31 21454314 G32 21454314 G33 LTC2143-14: 64k Point FFT, LTC2143-14: 64k Point FFT, LTC2143-14: 64k Point FFT, f = 30MHz, –1dBFS, 80Msps f = 70MHz, –1dBFS, 80Msps f = 140MHz, –1dBFS, 80Msps IN IN IN 0 0 0 –10 –10 –10 –20 –20 –20 –30 –30 –30 BFS)–40 BFS)–40 BFS)–40 E (d–50 E (d–50 E (d–50 UD–60 UD–60 UD–60 T T T LI–70 LI–70 LI–70 P P P AM–80 AM–80 AM–80 –90 –90 –90 –100 –100 –100 –110 –110 –110 –120 –120 –120 0 10 20 30 40 0 10 20 30 40 0 10 20 30 40 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) 21454314 G34 21454314 G35 21454314 G36 21454314fa 12

LTC2145-14/ LTC2144-14/LTC2143-14 TYPICAL PERFORMANCE CHARACTERISTICS LTC2143-14: 64k Point 2-Tone FFT, LTC2143-14: SNR vs Input f = 69MHz, 70MHz, –1dBFS, LTC2143-14: Shorted Input Frequency, –1dBFS, 80Msps, IN 80Msps Histogram 2V Range 0 6000 74 –10 –20 5000 –30 73 SINGLE-ENDED FS)–40 4000 ENCODE AMPLITUDE (dB––––76850000 COUNT32000000 SNR (dBFS) 72 DIFEFNERCEONDTEIAL –90 71 –100 1000 –110 –120 0 70 0 10 20 30 40 8183 8185 8187 8189 8191 0 50 100 150 200 250 300 FREQUENCY (MHz) OUTPUT CODE INPUT FREQUENCY (MHz) 21454314 G37 21454314 G38 21454314 G39 LTC2143-14: 2nd, 3rd Harmonic vs LTC2143-14: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 80Msps, Input Frequency, –1dBFS, 80Msps, LTC2143-14: SFDR vs Input Level, 2V Range 1V Range f = 70MHz, 80Msps, 2V Range IN 100 100 120 dBFS 110 S) 95 S) 95 BF BF 100 D HARMONIC (d 988050 2ND3RD D HARMONIC (d 988050 2ND 3RD dBc AND dBFS) 798000 dBc 3R 3R R ( D D D 60 AN 75 AN 75 SF D D 50 N N 2 70 2 70 40 65 65 30 0 50 100 150 200 250 300 0 50 100 150 200 250 300 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) INPUT LEVEL (dBFS) 21454314 G40 218543 G41 21454314 G42 LTC2143-14: I vs Sample LTC2143-14: IO vs Sample VDD VDD Rate, 5MHz, –1dBFS, Sine Wave Rate, 5MHz, –1dBFS, Sine Wave LTC2143-14: SNR vs SENSE, Input on Each Channel on Each Input f = 5MHz, –1dBFS IN 70 70 74 60 3.5mA LVDS 73 65 72 50 60 I (mA)VDD 55 LVDS OUTPUCTMSOS OUTPUTS IO (mA)VDD 3400 1.75mA LVDS SNR (dBFS) 767190 50 20 68 45 10 1.8V CMOS 67 40 0 66 0 20 40 60 80 0 20 40 60 80 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 SAMPLE RATE (Msps) SAMPLE RATE (Msps) SENSE PIN (V) 21454314 G43 21454314 G44 21454314 G45 21454314fa 13

LTC2145-14/ LTC2144-14/LTC2143-14 PIN FUNCTIONS PINS THAT ARE THE SAME FOR ALL DIGITAL CS (Pin 20): In Serial Programming Mode, (PAR/SER = OUTPUT MODES 0V), CS Is the Serial Interface Chip Select Input. When CS is low, SCK is enabled for shifting data on SDI into the V (Pins 1, 16, 17, 64): Analog Power Supply, 1.7V to DD mode control registers. In the parallel programming mode 1.9V. Bypass to ground with 0.1μF ceramic capacitors. (PAR/SER = V ), CS controls the clock duty cycle stabilizer Adjacent pins can share a bypass capacitor. DD (See Table 2). CS can be driven with 1.8V to 3.3V logic. V (Pin 2): Common Mode Bias Output, Nominally Equal CM1 SCK (Pin 21): In Serial Programming Mode, (PAR/SER = to V /2. V should be used to bias the common mode DD CM1 0V), SCK Is the Serial Interface Clock Input. In the parallel of the analog inputs to channel 1. Bypass to ground with programming mode (PAR/SER = V ), SCK controls the a 0.1μF ceramic capacitor. DD digital output mode (see Table 2). SCK can be driven with GND (Pins 3, 6, 14): ADC Power Ground. 1.8V to 3.3V logic. AIN1+ (Pin 4): Channel 1 Positive Differential Analog Input. SDI (Pin 22): In Serial Programming Mode, (PAR/SER = A – (Pin 5): Channel 1 Negative Differential Analog Input. 0V), SDI Is the Serial Interface Data Input. Data on SDI IN1 is clocked into the mode control registers on the rising REFH (Pins 7, 9): ADC High Reference. See the Applica- edge of SCK. In the parallel programming mode (PAR/ tions Information section for recommended bypassing SER = V ), SDI can be used together with SDO to power DD circuits for REFH and REFL. down the part (see Table 2). SDI can be driven with 1.8V REFL (Pins 8, 10): ADC Low Reference. See the Applica- to 3.3V logic. tions Information section for recommended bypassing OGND (Pin 41): Output Driver Ground. Must be shorted circuits for REFH and REFL. to the ground plane by a very low inductance path. Use PAR/SER (Pin 11): Programming Mode Selection Pin. multiple vias close to the pin. Connect to ground to enable the serial programming mode. OV (Pin 42): Output Driver Supply. Bypass to ground DD CS, SCK, SDI, SDO become a serial interface that control with a 0.1μF ceramic capacitor. the A/D operating modes. Connect to V to enable the DD SDO (Pin 61): In Serial Programming Mode, (PAR/SER parallel programming mode where CS, SCK, SDI, SDO = 0V), SDO Is the Optional Serial Interface Data Output. become parallel logic inputs that control a reduced set of Data on SDO is read back from the mode control regis- the A/D operating modes. PAR/SER should be connected ters and can be latched on the falling edge of SCK. SDO directly to ground or V and not be driven by a logic signal. DD is an open-drain NMOS output that requires an external A + (Pin 12): Channel 2 Positive Differential Analog Input. IN2 2k pull-up resistor to 1.8V – 3.3V. If read back from the A – (Pin 13): Channel 2 Negative Differential Analog Input. mode control registers is not needed, the pull-up resistor IN2 is not necessary and SDO can be left unconnected. In the V (Pin 15): Common Mode Bias Output, Nominally CM2 parallel programming mode (PAR/SER = V ), SDO can DD Equal to V /2. V should be used to bias the common DD CM2 be used together with SDI to power down the part (see mode of the analog inputs to channel 2. Bypass to ground Table 2). When used as an input, SDO can be driven with with a 0.1μF ceramic capacitor. 1.8V to 3.3V logic through a 1k series resistor. ENC+ (Pin 18): Encode Input. Conversion starts on the V (Pin 62): Reference Voltage Output. Bypass to REF rising edge. ground with a 2.2μF ceramic capacitor. The output voltage ENC– (Pin 19): Encode Complement Input. Conversion is nominally 1.25V. starts on the falling edge. Tie to GND for single-ended encode mode. 21454314fa 14

LTC2145-14/ LTC2144-14/LTC2143-14 PIN FUNCTIONS SENSE (Pin 63): Reference Programming Pin. Connecting is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13) SENSE to V selects the internal reference and a ±1V input appear when CLKOUT+ is high. DD range. Connecting SENSE to ground selects the internal DNC (Pins 23, 24, 25, 27, 29, 31, 33, 35, 37, 43, 44, 45, reference and a ±0.5V input range. An external reference 47, 49, 51, 53, 55, 57, 59): Do not connect these pins. between 0.625V and 1.3V applied to SENSE selects an input range of ±0.8 • V . CLKOUT– (Pin 39): Inverted Version of CLKOUT+. SENSE Ground (Exposed Pad Pin 65): The exposed pad must be CLKOUT+ (Pin 40): Data Output Clock. The Digital Outputs soldered to the PCB ground. normally transition at the same time as the falling and ris- ing edges of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the Digital Outputs by programming FULL RATE CMOS OUTPUT MODE the mode control registers. All Pins Below Have CMOS Output Levels D1_0_1 to D1_12_13 (Pins 46, 48, 50, 52, 54, 56, 58): (OGND to OV ) DD Channel 1 Double Data Rate Digital Outputs. Two data bits D2_0 to D2_13 (Pins 25, 26, 27, 28, 29, 30, 31, 32, 33, are multiplexed onto each output pin. The even data bits 34, 35, 36, 37, 38): Channel 2 Digital Outputs. D2_13 is (D0, D2, D4, D6, D8, D10, D12) appear when CLKOUT+ the MSB. is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13) appear when CLKOUT+ is high. DNC (Pins 23, 24, 43, 44): Do not connect these pins. OF2_1 (Pin 60): Over/Underflow Digital Output. OF2_1 is CLKOUT– (Pin 39): Inverted Version of CLKOUT+. high when an overflow or underflow has occurred. The CLKOUT+ (Pin 40): Data Output Clock. The digital outputs over/under flow for both channels are multiplexed onto normally transition at the same time as the falling edge this pin. Channel 2 appears when CLKOUT+ is low, and of CLKOUT+. The phase of CLKOUT+ can also be delayed Channel 1 appears when CLKOUT+ is high. relative to the Digital Outputs by programming the mode control registers. DOUBLE DATA RATE LVDS OUTPUT MODE D1_0 to D1_13 (Pins 45, 46, 47, 48, 49, 50, 51, 52, 53, All Pins Below Have LVDS Output Levels. The Output 54, 55, 56, 57, 58): Channel 1 Digital Outputs. D1_13 is Current Level Is Programmable. There Is an Optional the MSB. Internal 100Ω Termination Resistor Between the Pins OF2 (Pin 59): Channel 2 Over/Underflow Digital Output. of Each LVDS Output Pair. OF2 is high when an overflow or underflow has occurred. D2_0_1–/D2_0_1+ to D2_12_13–/D2_12_13+ (Pins 25/26, OF1 (Pin 60): Channel 1 Over/Underflow Digital Output. 27/28, 29/30, 31/32, 33/34, 35/36, 37/38): Channel OF1 is high when an overflow or underflow has occurred. 2 Double Data Rate Digital Outputs. Two data bits are multiplexed onto each differential output pair. The even DOUBLE DATA RATE CMOS OUTPUT MODE data bits (D0, D2, D4, D6, D8, D10, D12) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, All Pins Below Have CMOS Output Levels D11, D13) appear when CLKOUT+ is high. (OGND to OV ) DD CLKOUT–/CLKOUT+ (Pins 39/40): Data Output Clock. D2_0_1 to D2_12_13 (Pins 26, 28, 30, 32, 34, 36, 38): The digital outputs normally transition at the same time Channel 2 Double Data Rate Digital Outputs. Two data bits as the falling and rising edges of CLKOUT+. The phase of are multiplexed onto each output pin. The even data bits CLKOUT+ can also be delayed relative to the digital outputs (D0, D2, D4, D6, D8, D10, D12) appear when CLKOUT+ by programming the mode control registers. 21454314fa 15

LTC2145-14/ LTC2144-14/LTC2143-14 PIN FUNCTIONS DNC (Pins 23, 24, 43, 44): Do not connect these pins. OF2_1–/OF2_1+ (Pins 59/60): Over/Underflow Digital Output. OF2_1+ is high when an overflow or underflow D1_0_1–/D1_0_1+ to D1_12_13–/D1_12_13+ (Pins has occurred. The over/under flow for both channels 45/46, 47/48, 49/50, 51/52, 53/54, 55/56, 57/58): are multiplexed onto this pin. Channel 2 appears when Channel 1 Double Data Rate Digital Outputs. Two data CLKOUT+ is low, and Channel 1 appears when CLKOUT+ bits are multiplexed onto each differential output pair. is high. The even data bits (D0, D2, D4, D6, D8, D10, D12) ap- pear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13) appear when CLKOUT+ is high. FUNCTIONAL BLOCK DIAGRAM OVDD CH 1 OF1 14-BIT ANALOG S/H ADC CORE INPUT OF2 CORRECTION D1_13 LOGIC (cid:116) (cid:116) (cid:116) CH 2 14-BIT D1_0 ANALOG S/H ADC CORE OUTPUT INPUT DRIVERS CLKOUT+ CLKOUT– VREF 1.25V D2_13 REFERENCE (cid:116) 2.2μF (cid:116) (cid:116) D2_0 RANGE SELECT OGND REFH REFL INTERNAL CLOCK SIGNALS REF BUF SENSE VDD VCM1 VDD/2 ADRMIEFFPF CLCOOCCNYKCT/RLDEOULTY RCEOGMNIOSTDTREEORLS 0.1μF VCM2 0.1μF GND REFH REFL ENC+ ENC– PAR/SER CS SCK SDI SDO 2.2μF 21454314 F01 0.1μF 0.1μF Figure 1. Functional Block Diagram 21454314fa 16

LTC2145-14/ LTC2144-14/LTC2143-14 TIMING DIAGRAMS Full Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels tAP CH 1 A A + 2 A + 4 ANALOG INPUT A + 3 tAP A + 1 CH 2 B B + 2 B + 4 ANALOG INPUT B + 3 tH B + 1 tL ENC– ENC+ tD D1_0 - D1_13, OF1 A – 6 A – 5 A – 4 A – 3 A – 2 D2_0 - D2_13, OF2 B – 6 B – 5 B – 4 B – 3 B – 2 tC CLKOUT+ CLKOUT– 21454314 TD01 21454314fa 17

LTC2145-14/ LTC2144-14/LTC2143-14 TIMING DIAGRAMS Double Data Rate CMOS Output Mode Timing All Outputs Are Single-Ended and Have CMOS Levels tAP CH 1 A A + 2 A + 4 ANALOG INPUT A + 3 tAP A + 1 CH 2 B B + 2 B + 4 ANALOG INPUT B + 3 tH B + 1 tL ENC– ENC+ tD tD BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 D1_0_1 A-6 A-6 A-5 A-5 A-4 A-4 A-3 A-3 A-2 (cid:116) (cid:116) (cid:116) BIT 12 BIT 13 BIT 12 BIT 13 BIT 12 BIT 13 BIT 12 BIT 13 BIT 12 D1_12_13 A-6 A-6 A-5 A-5 A-4 A-4 A-3 A-3 A-2 BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 D2_0_1 B-6 B-6 B-5 B-5 B-4 B-4 B-3 B-3 B-2 (cid:116) (cid:116) (cid:116) BIT 12 BIT 13 BIT 12 BIT 13 BIT 12 BIT 13 BIT 12 BIT 13 BIT 12 D2_12_13 B-6 B-6 B-5 B-5 B-4 B-4 B-3 B-3 B-2 OF OF OF OF OF OF OF OF OF OF2_1 B-6 A-6 B-5 A-5 B-4 A-4 B-3 A-3 B-2 tC tC CLKOUT+ CLKOUT– 21454314 TD02 21454314fa 18

LTC2145-14/ LTC2144-14/LTC2143-14 TIMING DIAGRAMS Double Data Rate LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels tAP CH 1 ANALOG A A + 2 A + 4 INPUT A + 3 tAP A + 1 CH 2 ANALOG B B + 2 B + 4 INPUT B + 3 tH B + 1 tL ENC– ENC+ tD tD D1_0_1+ BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 D1_0_1– A-6 A-6 A-5 A-5 A-4 A-4 A-3 A-3 A-2 (cid:116) (cid:116) D1_12_1(cid:116)3+ BIT 12 BIT 13 BIT 12 BIT 13 BIT 12 BIT 13 BIT 12 BIT 13 BIT 12 D1_12_13– A-6 A-6 A-5 A-5 A-4 A-4 A-3 A-3 A-2 D2_0_1+ BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 BIT 1 BIT 0 D2_0_1– B-6 B-6 B-5 B-5 B-4 B-4 B-3 B-3 B-2 (cid:116) (cid:116) D2_12_1(cid:116)3+ BIT 12 BIT 13 BIT 12 BIT 13 BIT 12 BIT 13 BIT 12 BIT 13 BIT 12 D2_12_13– B-6 B-6 B-5 B-5 B-4 B-4 B-3 B-3 B-2 OF2_1+ OF OF OF OF OF OF OF OF OF OF2_1– B-6 A-6 B-5 A-5 B-4 A-4 B-3 A-3 B-2 tC tC CLKOUT+ CLKOUT– 21454314 TD03 SPI Port Timing (Readback Mode) tS tDS tDH tSCK tH CS SCK tDO SDI R/W A6 A5 A4 A3 A2 A1 A0 XX XX XX XX XX XX XX XX SDO D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE SPI Port Timing (Write Mode) CS SCK SDI R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDO HIGH IMPEDANCE 21454314 TD04 21454314fa 19

LTC2145-14/ LTC2144-14/LTC2143-14 APPLICATIONS INFORMATION CONVERTER OPERATION to V + 0.5V. There should be 180° phase difference CM between the inputs. The LTC2145-14/LTC2144-14/LTC2143-14 are low power, two-channel, 14-bit, 125Msps/105Msps/80Msps A/D The two channels are simultaneously sampled by a shared converters that are powered by a single 1.8V supply. The encode circuit (Figure 2). analog inputs should be driven differentially. The encode Single-Ended Input input can be driven differentially, or single ended for lower power consumption. The digital outputs can be CMOS, For applications less sensitive to harmonic distortion, the double data rate CMOS (to halve the number of output A + input can be driven single-ended with a 1V signal IN P-P lines), or double data rate LVDS (to reduce digital noise centered around V . The A – input should be connected CM IN in the system.) Many additional features can be chosen to V and the V bypass capacitor should be increased CM CM by programming the mode control registers through a to 2.2μF. With a single-ended input, the harmonic distortion serial SPI port. and INL will degrade, but the noise and DNL will remain unchanged. ANALOG INPUT INPUT DRIVE CIRCUITS The analog inputs are differential CMOS sample-and-hold circuits (Figure 2). The inputs should be driven differen- Input Filtering tially around a common mode voltage set by the V or CM1 If possible, there should be an RC lowpass filter right at V output pins, which are nominally V /2. For the 2V CM2 DD the analog inputs. This lowpass filter isolates the drive input range, the inputs should swing from V – 0.5V CM circuitry from the A/D sample-and-hold switching, and also limits wideband noise from the drive circuitry. Figure 3 LTC2145-14 shows an example of an input RC filter. The RC component VDD CSAMPLE values should be chosen based on the application’s input RON 5pF 10Ω 15Ω frequency. AIN+ CPARASITIC VDD 1.8pF Transformer Coupled Circuits CSAMPLE 10Ω 1R5OΩN 5pF Figure 3 shows the analog input being driven by an RF AIN– transformer with a center-tapped secondary. The center CPARASITIC 1.8pF tap is biased with V , setting the A/D input at its optimal CM VDD DC level. At higher input frequencies a transmission line balun transformer (Figure 4 to Figure 6) has better balance, resulting in lower A/D distortion. 1.2V 10k 50Ω VCM ENC+ 0.1μF ENC– ANALOG 0.1μF 1T:11 25Ω AIN+ 10k INPUT LTC2145-14 25Ω 0.1μF 1.2V 12pF 21454314 F02 25Ω Figure 2. Equivalent Input Circuit. Only One of the Two 25Ω AIN– Analog Channels Is Shown T1: MA/COM MABAES0060 RESISTORS, CAPACITORS 21454314 F03 ARE 0402 PACKAGE SIZE Figure 3. Analog Input Circuit Using a Transformer. Recommended for Input Frequencies from 5MHz to 70MHz 21454314fa 20

LTC2145-14/ LTC2144-14/LTC2143-14 APPLICATIONS INFORMATION Amplifier Circuits Reference Figure 7 shows the analog input being driven by a high The LTC2145-14/LTC2144-14/LTC2143-14 has an internal speed differential amplifier. The output of the amplifier is 1.25V voltage reference. For a 2V input range using the AC-coupled to the A/D so the amplifier’s output common internal reference, connect SENSE to V . For a 1V input DD mode voltage can be optimally set to minimize distortion. range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, At very high frequencies an RF gain block will often have apply a 1.25V reference voltage to SENSE (Figure 9). lower distortion than a differential amplifier. If the gain block is single-ended, then a transformer circuit (Figure 4 The input range can be adjusted by applying a voltage to to Figure 6) should convert the signal to differential before SENSE that is between 0.625V and 1.30V. The input range driving the A/D. will then be 1.6 • V . SENSE The V , REFH and REFL pins should be bypassed as REF 50Ω VCM shown in Figure 8. A low inductance 2.2μF interdigitated 0.1μF capacitor is recommended for the bypass between REFH 0.1μF ANALOG T2 12Ω AIN+ and REFL. This type of capacitor is available at a low cost INPUT T1 25Ω 0.1μF LTC2145-14 from multiple suppliers. 8.2pF 0.1μF 25Ω 12Ω AIN– 50Ω VCM 0.1μF 21454314 F04 0.1μF T1: MA/COM MABA-007159-000000 ANALOG 4.7nH AIN+ T2: COILCRAFT WBC1-1TL INPUT LTC2145-14 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE T1 25Ω 0.1μF Figure 4. Recommended Front-End Circuit for Input 0.1μF 25Ω 4.7nH AIN– Frequencies from 5MHz to 150MHz T1: MA/COM ETC1-1-13 21454314 F06 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE 50Ω VCM Figure 6. Recommended Front-End Circuit for Input 0.1μF Frequencies Above 250MHz 0.1μF ANALOG T2 AIN+ INPUT T1 LTC2145-14 25Ω 0.1μF 1.8pF VCM 0.1μF 25Ω AIN– DHIFIGFEHR SEPNETEIADL 200Ω 200Ω 0.1μF 0.1μF AMPLIFIER 25Ω AIN+ 21454314 F05 T1: MA/COM MABA-007159-000000 ANIANLPOUGT + + 12pF LTC2145-14 T2: COILCRAFT WBC1-1TL RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE – – 0.1μF 25Ω AIN– Figure 5. Recommended Front-End Circuit for Input 12pF Frequencies from 150MHz to 250MHz 21454314 F07 Figure 7. Front-End Circuit Using a High Speed Differential Amplifier 21454314fa 21

LTC2145-14/ LTC2144-14/LTC2143-14 APPLICATIONS INFORMATION in some vendors’ capacitors. In Figure 8d the REFH and LTC2145-14 REFL pins are connected by short jumpers in an internal VREF 5Ω 1.25V BANDGAP 1.25V layer. To minimize the inductance of these jumpers they REFERENCE 2.2μF can be placed in a small hole in the GND plane on the 0.625V second board layer. RANGE DETECT AND CONTROL TIE TO VDD FOR 2V RANGE; TIE TO GND FOR 1V RANGE; SENSE (cid:51)(cid:34)(cid:47)(cid:40)(cid:38)(cid:1)(cid:30)(cid:1)(cid:18)(cid:15)(cid:23)(cid:1)(cid:116)(cid:1)(cid:55)SENSE FOR 0.625V < VSENSE < 1.300V BUFFER INTERNAL ADC HIGH REFERENCE REFH C2 – + 0.1μF Figure 8c. Recommended Layout for the REFH/REFL REFL + – Bypass Circuit in Figure 8a 0.8x C1 DIFF AMP REFH – + C3 REFL + – 0.1μF INTERNAL ADC LOW REFERENCE C1: 2.2μF LOW INDUCTANCE INTERDIGITATED CAPACITOR 21454314 F08a TDK CLLE1AX7S0G225M MURATA LLA219C70G225M AVX W2L14Z225M Figure 8d. Recommended Layout for the REFH/REFL OR EQUIVALENT Bypass Circuit in Figure 8b Figure 8a. Reference Circuit VREF Alternatively, C1 can be replaced by a standard 2.2μF 2.2μF capacitor between REFH and REFL (see Figure 8b). The LTC2145-14 capacitors should be as close to the pins as possible (not 1.25V SENSE EXTERNAL on the back side of the circuit board). REFERENCE 1μF 21454314 F09 Figure 8c and Figure 8d show the recommended circuit board layout for the REFH/REFL bypass capacitors. Note Figure 9. Using an External 1.25V Reference that in Figure 8c, every pin of the interdigitated capacitor (C1) is connected since the pins are not internally connected Encode Input The signal quality of the encode inputs strongly affects LTC2145-14 REFH the A/D noise performance. The encode inputs should C3 0.1μF be treated as analog signals – do not route them next to REFL digital traces on the circuit board. There are two modes C1 2.2μF of operation for the encode inputs: the differential encode REFH mode (Figure 10), and the single-ended encode mode C2 REFL (Figure 11). 0.1μF CAPACITORS ARE 0402 PACKAGE SIZE 21454314 F08b The differential encode mode is recommended for si- nusoidal, PECL, or LVDS encode inputs (Figure 12 and Figure 8b. Alternative REFH/REFL Bypass Circuit Figure 13). The encode inputs are internally biased to 1.2V 21454314fa 22

LTC2145-14/ LTC2144-14/LTC2143-14 APPLICATIONS INFORMATION through 10kΩ equivalent resistance. The encode inputs LTC2145-14 VDD can be taken above V (up to 3.6V), and the common DD DIFFERENTIAL mode range is from 1.1V to 1.6V. In the differential encode COMPARATOR VDD mode, ENC– should stay at least 200mV above ground to avoid falsely triggering the single ended encode mode. 15k For good jitter performance ENC+ and ENC– should have ENC+ fast rise and fall times. ENC– The single-ended encode mode should be used with CMOS 30k encode inputs. To select this mode, ENC– is connected to ground and ENC+ is driven with a square wave encode input. 21454314 F10 ENC+ can be taken above V (up to 3.6V) so 1.8V to 3.3V DD Figure 10. Equivalent Encode Input Circuit CMOS logic levels can be used. The ENC+ threshold is 0.9V. for Differential Encode Mode For good jitter performance ENC+ should have fast rise and fall times. If the encode signal is turned off or drops LTC2145-14 below approximately 500kHz, the A/D enters nap mode. 1.8V TO 3.3V ENC+ Clock Duty Cycle Stabilizer 0V ENC– 30k CMOS LOGIC For good performance the encode signal should have a BUFFER 50% (±5%) duty cycle. If the optional clock duty cycle 21454314 F11 stabilizer circuit is enabled, the encode duty cycle can Figure 11. Equivalent Encode Input Circuit vary from 30% to 70% and the duty cycle stabilizer will for Single-Ended Encode Mode maintain a constant 50% internal duty cycle. If the encode signal changes frequency, the duty cycle stabilizer circuit requires one hundred clock cycles to lock onto the input 0.1μF ENC+ clock. The duty cycle stabilizer is enabled by mode control register A2 (serial programming mode), or by CS (parallel T1 50Ω 100Ω LTC2145-14 programming mode). 0.1μF 50Ω For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If – ENC the duty cycle stabilizer is disabled, care should be taken 0.1μF to make the sampling clock have a 50% (±5%) duty cycle. T1 = MA/COM ETC1-1-13 21454314 F12 The duty cycle stabilizer should not be used below 5Msps. RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE Figure 12. Sinusoidal Encode Drive DIGITAL OUTPUTS Digital Output Modes 0.1μF ENC+ The LTC2145-14/LTC2144-14/LTC2143-14 can operate in three digital output modes: full rate CMOS, double data PECL OR LVDS LTC2145-14 rate CMOS (to halve the number of output lines), or double CLOCK 0.1μF ENC– data rate LVDS (to reduce digital noise in the system.) The output mode is set by mode control register A3 (serial 21454314 F13 programming mode), or by SCK (parallel programming Figure 13. PECL or LVDS Encode Drive 21454314fa 23

LTC2145-14/ LTC2144-14/LTC2143-14 APPLICATIONS INFORMATION mode). Note that double data rate CMOS cannot be selected D1_0_1– through D1_12_13+/D1_12_13– and D2_0_1+/ in the parallel programming mode. D2_0_1– through D2_12_13+/D2_12_13–) for the digital output data. Overflow (OF2_1+/OF2_1–) and the data Full Rate CMOS Mode output clock (CLKOUT+/CLKOUT–) each have an LVDS output pair. Note that the overflow for both ADC channels In full rate CMOS mode the data outputs (D1_0 to D1_13 is multiplexed onto the OF2_1+/OF2_1– output pair. and D2_0 to D2_13), overflow (OF2, OF1), and the data output clocks (CLKOUT+, CLKOUT–) have CMOS output By default the outputs are standard LVDS levels: 3.5mA levels. The outputs are powered by OVDD and OGND which output current and a 1.25V output common mode volt- are isolated from the A/D core power and ground. OVDD age. An external 100Ω differential termination resistor can range from 1.1V to 1.9V, allowing 1.2V through 1.8V is required for each LVDS output pair. The termination CMOS logic outputs. resistors should be located as close as possible to the LVDS receiver. For good performance the digital outputs should drive minimal capacitive loads. If the load capacitance is larger The outputs are powered by OV and OGND which are DD than 10pF a digital buffer should be used. isolated from the A/D core power and ground. In LVDS mode, OV must be 1.8V. DD Double Data Rate CMOS Mode Programmable LVDS Output Current In double data rate CMOS mode, two data bits are multiplexed and output on each data pin. This reduces In LVDS mode, the default output driver current is 3.5mA. the number of digital lines by fifteen, simplifying board This current can be adjusted by serially programming mode routing and reducing the number of input pins needed control register A3. Available current levels are 1.75mA, to receive the data. The data outputs (D1_0_1, D1_2_3, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. D1_4_5, D1_6_7, D1_8_9, D1_10_11, D1_12_13, D2_0_1, D2_2_3, D2_4_5, D2_6_7, D2_8_9, D2_10_11, Optional LVDS Driver Internal Termination D2_12_13), overflow (OF2_1), and the data output clocks In most cases using just an external 100Ω termination (CLKOUT+, CLKOUT–) have CMOS output levels. The out- resistor will give excellent LVDS signal integrity. In addi- puts are powered by OV and OGND which are isolated DD tion, an optional internal 100Ω termination resistor can from the A/D core power and ground. OV can range DD be enabled by serially programming mode control register from 1.1V to 1.9V, allowing 1.2V through 1.8V CMOS logic A3. The internal termination helps absorb any reflections outputs. Note that the overflow for both ADC channels is caused by imperfect termination at the receiver. When the multiplexed onto the OF2_1 pin. internal termination is enabled, the output driver current For good performance the digital outputs should drive is doubled to maintain the same output voltage swing. minimal capacitive loads. If the load capacitance is larger than 10pF a digital buffer should be used. Overflow Bit When using double data rate CMOS at sample rates above The overflow output bit outputs a logic high when the analog 100Msps the SNR may degrade slightly, about 0.1dB to input is either overranged or underranged. The overflow 0.3dB depending on load capacitance and board layout. bit has the same pipeline latency as the data bits. In full rate CMOS mode each ADC channel has its own overflow Double Data Rate LVDS Mode pin (OF1 for channel 1, OF2 for channel 2). In DDR CMOS or DDR LVDS mode the overflow for both ADC channels In double data rate LVDS mode, two data bits are multi- is multiplexed onto the OF2_1 output. plexed and output on each differential output pair. There are seven LVDS output pairs per ADC channel (D1_0_1+/ 21454314fa 24

LTC2145-14/ LTC2144-14/LTC2143-14 APPLICATIONS INFORMATION Phase Shifting the Output Clock DATA FORMAT In full rate CMOS mode the data output bits normally Table 1 shows the relationship between the analog input change at the same time as the falling edge of CLKOUT+, voltage, the digital data output bits and the overflow bit. so the rising edge of CLKOUT+ can be used to latch the By default the output data format is offset binary. The 2’s output data. In double data rate CMOS and LVDS modes complement format can be selected by serially program- the data output bits normally change at the same time as ming mode control register A4. the falling and rising edges of CLKOUT+. To allow adequate set-up and hold time when latching the data, the CLKOUT+ Table 1. Output Codes vs Input Voltage A + – A – D13-D0 D13-D0 signal may need to be phase shifted relative to the data IN IN (2V Range) OF (OFFSET BINARY) (2’s COMPLEMENT) output bits. Most FPGAs have this feature; this is generally >1.000000V 1 11 1111 1111 1111 01 1111 1111 1111 the best place to adjust the timing. +0.999878V 0 11 1111 1111 1111 01 1111 1111 1111 The LTC2145-14/LTC2144-14/LTC2143-14 can also phase +0.999756V 0 11 1111 1111 1110 01 1111 1111 1110 shift the CLKOUT+/CLKOUT– signals by serially program- +0.000122V 0 10 0000 0000 0001 00 0000 0000 0001 ming mode control register A2. The output clock can be +0.000000V 0 10 0000 0000 0000 00 0000 0000 0000 shifted by 0°, 45°, 90°, or 135°. To use the phase shift- –0.000122V 0 01 1111 1111 1111 11 1111 1111 1111 ing feature the clock duty cycle stabilizer must be turned –0.000244V 0 01 1111 1111 1110 11 1111 1111 1110 on. Another control register bit can invert the polarity of –0.999878V 0 00 0000 0000 0001 10 0000 0000 0001 CLKOUT+ and CLKOUT–, independently of the phase shift. –1.000000V 0 00 0000 0000 0000 10 0000 0000 0000 The combination of these two features enables phase shifts ≤–1.000000V 1 00 0000 0000 0000 10 0000 0000 0000 of 45° up to 315° (Figure 14). ENC+ D0-D13, OF MODE CONTROL BITS PHASE SHIFT CLKINV CLKPHASE1 CLKPHASE0 0° 0 0 0 45° 0 0 1 90° 0 1 0 135° 0 1 1 CLKOUT+ 180° 1 0 0 225° 1 0 1 270° 1 1 0 315° 1 1 1 21454314 F14 Figure 14. Phase Shifting CLKOUT 21454314fa 25

LTC2145-14/ LTC2144-14/LTC2143-14 APPLICATIONS INFORMATION Digital Output Randomizer Interference from the A/D digital outputs is sometimes CLKOUT CLKOUT unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. OF OF Even a tiny coupling factor can cause unwanted tones D13 in the ADC output spectrum. By randomizing the digital D13/D0 output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted D12 D12/D0 (cid:116) tone amplitude. (cid:116) (cid:116) D2 The digital output is randomized by applying an exclusive- D2/D0 OR logic operation between the LSB and all other data RANDOMIZER output bits. To decode, the reverse operation is applied; ON D1 D1/D0 an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT outputs are not affected. The output randomizer is enabled by serially D0 D0 programming mode control register A4. 21454314 F15 Alternate Bit Polarity Figure 15. Functional Equivalent of Digital Output Randomizer Another feature that reduces digital feedback on the circuit board is the alternate bit polarity mode. When this mode is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11, PC BOARD D13) are inverted before the output buffers. The even bits CLKOUT FPGA (D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are not affected. This can reduce digital currents in the circuit OF board ground plane and reduce digital noise, particularly D13/D0 for very small analog input signals. D13 When there is a very small signal at the input of the A/D D12/D0 that is centered around mid-scale, the digital outputs toggle LTC2145-14 D12 (cid:116) between mostly 1’s and mostly 0’s. This simultaneous (cid:116) switching of most of the bits will cause large currents in the D2/D0 (cid:116) D2 ground plane. By inverting every other bit, the alternate bit D1/D0 polarity mode makes half of the bits transition high while D1 half of the bits transition low. This cancels current flow in the ground plane, reducing the digital noise. D0 D0 The digital output is decoded at the receiver by inverting 21454314 F16 the odd bits (D1, D3, D5, D7, D9, D11, D13). The alternate bit polarity mode is independent of the digital output ran- Figure 16. Unrandomizing a Randomized Digital domizer – either, both or neither function can be on at the Output Signal same time. The alternate bit polarity mode is enabled by serially programming mode control register A4. 21454314fa 26

LTC2145-14/ LTC2144-14/LTC2143-14 APPLICATIONS INFORMATION Digital Output Test Patterns allowed so the on-chip references can settle from the slight temperature shift caused by the change in supply current To allow in-circuit testing of the digital interface to the as the A/D leaves nap mode. Either channel 2 or both chan- A/D, there are several test modes that force the A/D data nels can be placed in nap mode; it is not possible to have outputs (OF, D13-D0) to known values: channel 1 in nap mode and channel 2 operating normally. All 1s: All outputs are 1 Sleep mode and nap mode are enabled by mode control All 0s: All outputs are 0 register A1 (serial programming mode), or by SDI and Alternating: Outputs change from all 1s to all 0s on SDO (parallel programming mode). alternating samples. DEVICE PROGRAMMING MODES Checkerboard: Outputs change from 101010101010101 to 010101010101010 on alternat- The operating modes of the LTC2145-14/LTC2144-14/ ing samples. LTC2143-14 can be programmed by either a parallel in- terface or a simple serial interface. The serial interface has The digital output test patterns are enabled by serially more flexibility and can program all available modes. The programming mode control register A4. When enabled, parallel interface is more limited and can only program the Test Patterns override all other formatting modes: 2’s some of the more commonly used modes. complement, randomizer, alternate bit polarity. Parallel Programming Mode Output Disable To use the parallel programming mode, PAR/SER should The digital outputs may be disabled by serially program- be tied to V . The CS, SCK, SDI and SDO pins are binary ming mode control register A3. All digital outputs including DD logic inputs that set certain operating modes. These pins OF and CLKOUT are disabled. The high-impedance disabled can be tied to V or ground, or driven by 1.8V, 2.5V, or state is intended for in-circuit testing or long periods of DD 3.3V CMOS logic. When used as an input, SDO should inactivity – it is too slow to multiplex a data bus between be driven through a 1k series resistor. Table 2 shows the multiple converters at full speed. When the outputs are modes set by CS, SCK, SDI and SDO. disabled both channels should be put into either sleep or nap mode. Table 2. Parallel Programming Mode Control Bits (PAR/SER = V ) DD PIN DESCRIPTION Sleep and Nap Modes CS Clock Duty Cycle Stabilizer Control Bit The A/D may be placed in sleep or nap modes to conserve 0 = Clock Duty Cycle Stabilizer Off power. In sleep mode the entire device is powered down, 1 = Clock Duty Cycle Stabilizer On resulting in 1mW power consumption. The amount of time SCK Digital Output Mode Control Bit required to recover from sleep mode depends on the size 0 = Full Rate CMOS Output Mode of the bypass capacitors on V , REFH, and REFL. For the 1 = Double Data Rate LVDS Output Mode REF (3.5mA LVDS Current, Internal Termination Off) suggested values in Fig. 8, the A/D will stabilize after 2ms. SDI/SDO Power Down Control Bit In nap mode the A/D core is powered down while the internal 00 = Normal Operation reference circuits stay active, allowing faster wakeup than 01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode from sleep mode. Recovering from nap mode requires at 10 = Channel 1 and Channel 2 in Nap Mode least 100 clock cycles. If the application demands very 11 = Sleep Mode (Entire Device Powered Down) accurate DC settling then an additional 50μs should be 21454314fa 27

LTC2145-14/ LTC2144-14/LTC2143-14 APPLICATIONS INFORMATION Serial Programming Mode GROUNDING AND BYPASSING To use the serial programming mode, PAR/SER should be The LTC2145-14/LTC2144-14/LTC2143-14 requires a tied to ground. The CS, SCK, SDI and SDO pins become a printed circuit board with a clean unbroken ground plane. serial interface that program the A/D mode control registers. A multilayer board with an internal ground plane in the Data is written to a register with a 16-bit serial word. Data first layer beneath the ADC is recommended. Layout for can also be read back from a register to verify its contents. the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In Serial data transfer starts when CS is taken low. The data particular, care should be taken not to run any digital track on the SDI pin is latched at the first 16 rising edges of alongside an analog signal track or underneath the ADC. SCK. Any SCK rising edges after the first 16 are ignored. The data transfer ends when CS is taken high again. High quality ceramic bypass capacitors should be used at the V , OV , V , V , REFH and REFL pins. Bypass The first bit of the 16-bit input word is the R/W bit. The DD DD CM REF capacitors must be located as close to the pins as pos- next seven bits are the address of the register (A6:A0). sible. Size 0402 ceramic capacitors are recommended. The The final eight bits are the register data (D7:D0). traces connecting the pins and bypass capacitors must If the R/W bit is low, the serial data (D7:D0) will be writ- be kept short and should be made as wide as possible. ten to the register set by the address bits (A6:A0). If the Of particular importance is the capacitor between REFH R/W bit is high, data in the register set by the address bits and REFL. This capacitor should be on the same side of (A6:A0) will be read back on the SDO pin (see the timing the circuit board as the A/D, and as close to the device diagrams). During a read back command the register is as possible. not updated and data on SDI is ignored. The analog inputs, encode signals, and digital outputs The SDO pin is an open drain output that pulls to ground should not be routed next to each other. Ground fill and with a 200Ω impedance. If register data is read back grounded vias should be used as barriers to isolate these through SDO, an external 2k pull-up resistor is required. If signals from each other. serial data is only written and read back is not needed, then SDO can be left floating and no pull-up resistor is needed. HEAT TRANSFER Table 3 shows a map of the mode control registers. Most of the heat generated by the LTC2145-14/LTC2144- Software Reset 14/LTC2143-14 is transferred from the die through the bottom-side exposed pad and package leads onto the If serial programming is used, the mode control registers printed circuit board. For good electrical and thermal should be programmed as soon as possible after the power performance, the exposed pad must be soldered to a large supplies turn on and are stable. The first serial command grounded pad on the PC board. This pad should be con- must be a software reset which will reset all register data nected to the internal ground planes by an array of vias. bits to logic 0. To perform a software reset, bit D7 in the reset register is written with a logic 1. After the reset SPI write command is complete, bit D7 is automatically set back to zero. 21454314fa 28

LTC2145-14/ LTC2144-14/LTC2143-14 APPLICATIONS INFORMATION Table 3. Serial Programming Mode Register Map (PAR/SER = GND) REGISTER A0: RESET REGISTER (ADDRESS 00h) D7 D6 D5 D4 D3 D2 D1 D0 RESET X X X X X X X Bit 7 RESET Software Reset Bit 0 = Not Used 1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC is momentarily placed in SLEEP mode. This bit is automatically set back to zero at the end of the SPI write command. The reset register is write only. Data read back from the reset register will be random. Bits 6-0 Unused, Don’t Care Bits. REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h) D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X PWROFF1 PWROFF0 Bits 7-2 Unused, Don’t Care Bits. Bits 1-0 PWROFF1:PWROFF0 Power Down Control Bits 00 = Normal Operation 01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode 10 = Channel 1 and Channel 2 in Nap Mode 11 = Sleep Mode REGISTER A2: TIMING REGISTER (ADDRESS 02h) D7 D6 D5 D4 D3 D2 D1 D0 X X X X CLKINV CLKPHASE1 CLKPHASE0 DCS Bits 7-4 Unused, Don’t Care Bits. Bit 3 CLKINV Output Clock Invert Bit 0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams) 1 = Inverted CLKOUT Polarity Bits 2-1 CLKPHASE1:CLKPHASE0 Output Clock Phase Delay Bits 00 = No CLKOUT Delay (As Shown in the Timing Diagrams) 01 = CLKOUT+/CLKOUT– Delayed by 45° (Clock Period • 1/8) 10 = CLKOUT+/CLKOUT– Delayed by 90° (Clock Period • 1/4) 11 = CLKOUT+/CLKOUT– Delayed by 135° (Clock Period • 3/8) Note: If the CLKOUT Phase Delay Feature Is Used, the Clock Duty Cycle Stabilizer Must Also Be Turned On Bit 0 DCS Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer Off 1 = Clock Duty Cycle Stabilizer On 21454314fa 29

LTC2145-14/ LTC2144-14/LTC2143-14 APPLICATIONS INFORMATION REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h) D7 D6 D5 D4 D3 D2 D1 D0 X ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE1 OUTMODE0 Bit 7 Unused, Don’t Care Bit. Bits 6-4 ILVDS2:ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current 111 = 1.75mA LVDS Output Driver Current Bit 3 TERMON LVDS Internal Termination Bit 0 = Internal Termination Off 1 = Internal Termination On. LVDS Output Driver Current is 2× the Current Set by ILVDS2:ILVDS0 Bit 2 OUTOFF Output Disable Bit 0 = Digital Outputs Are Enabled 1 = Digital Outputs Are Disabled and Have High Output Impedance Note: If the Digital Outputs Are Disabled the Part Should Also Be Put in Sleep or Nap Mode (Both Channels). Bits 1-0 OUTMODE1:OUTMODE0 Digital Output Mode Control Bits 00 = Full Rate CMOS Output Mode 01 = Double Data Rate LVDS Output Mode 10 = Double Data Rate CMOS Output Mode 11 = Not Used REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h) D7 D6 D5 D4 D3 D2 D1 D0 X X OUTTEST2 OUTTEST1 OUTTEST0 ABP RAND TWOSCOMP Bit 7-6 Unused, Don’t Care Bits. Bits 5-3 OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits 000 = Digital Output Test Patterns Off 001 = All Digital Outputs = 0 011 = All Digital Outputs = 1 101 = Checkerboard Output Pattern. OF, D13-D0 Alternate Between 1 01 0101 0101 0101 and 0 10 1010 1010 1010 111 = Alternating Output Pattern. OF, D13-D0 Alternate Between 0 00 0000 0000 0000 and 1 11 1111 1111 1111 Note: Other Bit Combinations Are not Used Bit 2 ABP Alternate Bit Polarity Mode Control Bit 0 = Alternate Bit Polarity Mode Off 1 = Alternate Bit Polarity Mode On. Forces the Output Format to Be Offset Binary Bit 1 RAND Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On Bit 0 TWOSCOMP Two’s Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two’s Complement Data Format 21454314fa 30

LTC2145-14/ LTC2144-14/LTC2143-14 TYPICAL APPLICATIONS Silkscreen Top Top Side 21454314fa 31

LTC2145-14/ LTC2144-14/LTC2143-14 TYPICAL APPLICATIONS Inner Layer 2 GND Inner Layer 3 21454314fa 32

LTC2145-14/ LTC2144-14/LTC2143-14 TYPICAL APPLICATIONS Inner Layer 4 Inner Layer 5 Power 21454314fa 33

LTC2145-14/ LTC2144-14/LTC2143-14 TYPICAL APPLICATIONS Bottom Side 21454314fa 34

LTC2145-14/ LTC2144-14/LTC2143-14 TYPICAL APPLICATIONS LTC2145-14 Schematic SDO C23 2.2μF SENSE C17 1μF VDD C19 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 C20 0.1μF 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 0.1μF VDD SENSE VREF SDO+OF2_1–OF2_1+12_13–12_13+10_11–10_11+1_8_9–1_8_9+1_6_7–1_6_7+1_4_5–1_4_5 DIGITAL _ _ _ _ D D D D D D 1 VDD D1 D1 D1 D1 D1_2_3+ 48 OUTPUTS 2 VCM1 D1_2_3– 47 3 GND D1_0_1+ 46 AIN1+ 4 AIN1+ D1_0_1– 45 AIN1– 5 AIN1– DNC 44 6 43 C15 GND DNC 0.1μF – + 7 REFH OVDD 42 OVDD + – 8 REFL OGND 41 C37 CN1 9 REFH LTC2145-14 CLKOUT+ 40 0.1μF – + 10 REFL CLKOUT– 39 C21 + – 11 PAR/SER D2_12_13+ 38 0.1μF 12 AIN2+ D2_12_13– 37 13 AIN2– D2_10_11+ 36 14 GND D2_10_11– 35 15 VCM2 D2_8_9+ 34 DOIUGTIPTAULTS 16 VDD D2_8_9– 33 PAR/SER – + – + – + – + AIN2+ DD+NC–NC S CK DI NC NC 2_0_1 2_0_1 2_2_3 2_2_3 2_4_5 2_4_5 2_6_7 2_6_7 PAD 65 AIN2– V E E C S S D D D D D D D D D D 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 VDD C67 C18 0.1μF 0.1μF C78 0.1μF C79 0.1μF R51 100Ω ENCODE SPI BUS CLOCK 21454314 TA02 21454314fa 35

LTC2145-14/ LTC2144-14/LTC2143-14 PACKAGE DESCRIPTION UP Package 64-Lead Plastic QFN (9mm (cid:119) 9mm) (Reference LTC DWG # 05-08-1705 Rev C) 0.70 ±0.05 7.15 ±0.05 7.50 REF 8.10 ±0.05 9.50 ±0.05 (4 SIDES) 7.15 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 9 .00 ±0.10 0.75 ±0.05 R = 0.115 (4 SIDES) R = 0.10 TYP TYP 6364 0.40 ±0.10 PIN 1 TOP MARK (SEE NOTE 5) 1 2 PIN 1 CHAMFER C = 0.35 7.15 ±0.10 7.50 REF (4-SIDES) 7.15 ±0.10 (UP64) QFN 0406 REV C 0.200 REF 0.25 ±0.05 0.00 – 0.05 0.50 BSC NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 BOTTOM VIEW—EXPOSED PAD 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4. EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE 21454314fa 36

LTC2145-14/ LTC2144-14/LTC2143-14 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 07/12 Corrected Channel 1 Data Bus (D1_*) Pin Description to state “Channel 1” 16 21454314fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 37 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC2145-14/ LTC2144-14/LTC2143-14 TYPICAL APPLICATIONS 64k Point 2-Tone FFT, f = 69MHz, 1.8V 1.8V IN 70MHz, –1dBFS, 125Msps VDD OVDD 0 CH 1 –10 14-BIT D1_13 ANALOG S/H ADC CORE (cid:116) –20 INPUT (cid:116) (cid:116) CMOS, –30 D1_0 DDR CMOS FS)–40 B D2_13 OORU TDPDURT SLVDS E (d–50 ANIANCLPHOU G2T S/H AD1C4 -CBOITRE DORUITVPEURTS D2_(cid:116)(cid:116)(cid:116)0 AMPLITUD–––768000 –90 –100 125MHz CLOCK –110 CLOCK CONTROL –120 0 10 20 30 40 50 60 21454314 TA03a FREQUENCY (MHz) 21454314 TA03b GND OGND RELATED PARTS PART NUMBER DESCRIPTION COMMENTS ADCs LTC2259-14/LTC2260-14/ 14-Bit, 80Msps/105Msps/125Msps 89mW/106mW/127mW, 73.4dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/CMOS LTC2261-14 1.8V ADCs, Ultralow Power Outputs, 6mm × 6mm QFN-40 LTC2262-14 14-Bit, 150Msps 1.8V ADC, Ultralow 149mW, 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs, Power 6mm × 6mm QFN-40 LTC2266-14/LTC2267-14/ 14-Bit, 80Msps/105Msps/125Msps 216mW/250mW/293mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, LTC2268-14 1.8V Dual ADCs, Ultralow Power 6mm × 6mm QFN-40 LTC2266-12/LTC2267-12/ 12-Bit, 80Msps/105Msps/125Msps 216mW/250mW/293mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs, LTC2268-12 1.8V Dual ADCs, Ultralow Power 6mm × 6mm QFN-40 LTC2183/LTC2184/ 16-Bit, 80Msps/105Msps/125Msps 370mW/308mW/200mW, 76.8dB SNR, 90dV SFDR, DDR LVDS/DDR CMOS/ LTC2185 1.8V Dual ADCs, Ultralow Power CMOS Outputs, Pin Compatible with LTC2145 Family, 9mm × 9mm QFN-64 RF Mixers/Demodulators LTC5517 40MHz to 900MHz Direct Conversion High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator Quadrature Demodulator LTC5557 400MHz to 3.8GHz High Linearity 23.7dBm IIP3 at 2.6GHz, 23.5dBm IIP3 at 3.5GHz, NF = 13.2dB, 3.3V Supply Downconverting Mixer Operation, Integrated Transformer LTC5575 800MHz to 2.7GHz Direct Conversion High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF Quadrature Demodulator and LO Transformer Amplifiers/Filters LTC6412 800MHz, 31dB Range, Analog-Controlled Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure, Variable Gain Amplifier 4mm × 4mm QFN-24 LTC6605-7/LTC6605-10/ Dual Matched 7MHz/10MHz/14MHz Dual Matched 2nd Order Lowpass Filters with Differential Drivers, LTC6605-14 Filters with ADC Drivers Pin-Programmable Gain, 6mm × 3mm DFN-22 Signal Chain Receivers LTM9002 14-Bit Dual Channel IF/Baseband Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers Receiver Subsystem 21454314fa 38 Linear Technology Corporation LT 0712 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2011