LTC1878 High Efficiency Monolithic Synchronous Step-Down Regulator FEATURES DESCRIPTIOU n High Efficiency: Up to 95% The LTC®1878 is a high efficiency monolithic synchro- m n Very Low Quiescent Current: Only 10 A nous buck regulator using a constant frequency, current During Operation mode architecture. Supply current during operation is n 600mA Output Current at V = 3.3V only 10m A and drops to < 1m A in shutdown. The 2.65V to IN n 2.65V to 6V Input Voltage Range 6V input voltage range makes the LTC1878 ideally suited n 550kHz Constant Frequency Operation for single Li-Ion battery-powered applications. 100% duty n Synchronizable from 400kHz to 700kHz cycle provides low dropout operation, extending battery n Selectable Burst ModeTM Operation or life in portable systems. Pulse Skipping Mode Switching frequency is internally set at 550kHz, allowing n No Schottky Diode Required the use of small surface mount inductors and capacitors. n Low Dropout Operation: 100% Duty Cycle For noise sensitive applications the LTC1878 can be n 0.8V Reference Allows Low Output Voltages externally synchronized from 400kHz to 700kHz. Burst n Shutdown Mode Draws < 1m A Supply Current n – 2% Output Voltage Accuracy Mode operation is inhibited during synchronization or when the SYNC/MODE pin is pulled low, preventing low n Current Mode Control for Excellent Line and frequency ripple from interfering with audio circuitry. Load Transient Response n Overcurrent and Overtemperature Protected The internal synchronous switch increases efficiency and n Available in 8-Lead MSOP Package eliminates the need for an external Schottky diode. Low APPLICATIOUS output voltages are easily supported with the 0.8V feed- back reference voltage. The LTC1878 is available in a n Cellular Telephones space saving 8-lead MSOP package. n Wireless Modems For higher input voltage (11V abs max) applications, refer n Personal Information Appliances to the LTC1877 data sheet. n Portable Instruments , LTC and LT are registered trademarks of Linear Technology Corporation. n Distributed Power Systems Burst Mode is a trademark of Linear Technology Corporation. n Battery-Powered Equipment TYPICAL APPLICATIOU Efficiency vs Output Load Current 100 High Efficiency Step-Down Converter 95 VIN = 3.6V T2O.6V 56IVVN 22µCFE*R* 761 SVYINNCLTC1878SW 5 102µ0pHF* + 47µV3F.O*3U*VT*† CIENCY (%) 8950 VIN = 4.2V RUN FI VIN = 6V 2 3 887k EF 80 ITH GND VFB 220pF 4 280k 75 Burst Mode OPERATION VOUT = 3.3V 1878 TA01 L = 10µH *TOKO D62CB A920CY-100M 70 **TAIYO-YUDEN CERAMIC JMK325BJ226MM 0.1 1 10 100 1000 ***SANYO POSCAP 6TPA47M OUTPUT CURRENT (mA) †VOUT CONNECTED TO VIN FOR 2.65V < VIN < 3.3V 1878 TA02 1

LTC1878 ABSOLUTE W AXIW UW RATIU GS PACKAGE/ORDER IU FORW ATIOU (Note 1) Input Supply Voltage (V )...........................–0.3V to 7V IN ORDER PART ITH, PLL LPF Voltage ................................–0.3V to 2.7V TOP VIEW NUMBER RUN, V Voltages......................................–0.3V to V FB IN RUN1 8 PLL LPF SYNC/MODE Voltage..................................–0.3V to VIN ITH2 7 SYNC/MODE LTC1878EMS8 VFB3 6 VIN SW Voltage...................................–0.3V to (VIN + 0.3V) GND4 5 SW P-Channel MOSFET Source Current (DC)........... 800mA MS8 PACKAGE MS8 PART MARKING 8-LEAD PLASTIC MSOP N-Channel MOSFET Sink Current (DC)............... 800mA Peak SW Sink and Source Current ........................ 1.5A TJMAX = 125(cid:176)C, q JA = 150(cid:176)C/W LTNX Operating Ambient Temperature Range (Note 2).................................................. –40(cid:176) C to 85(cid:176) C Consult factory for Industrial and Military grade parts. Junction Temperature (Note 3)............................ 125(cid:176) C Storage Temperature Range................. –65(cid:176) C to 150(cid:176) C Lead Temperature (Soldering, 10 sec)..................300(cid:176) C ELECTRICAL CHARACTERISTICS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25(cid:176) C. V = 3.6V unless otherwise specified. IN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I Feedback Current (Note 4) l 4 30 nA VFB V Regulated Output Voltage (Note 4) 0(cid:176) C £ T £ 85(cid:176) C 0.784 0.8 0.816 V FB A (Note 4) –40(cid:176) C £ T £ 85(cid:176) C l 0.74 0.8 0.84 V A D V Output Overvoltage Lockout D V = V – V l 20 50 110 mV OVL OVL OVL FB D V Reference Voltage Line Regulation V = 2.65V to 6V (Note 4) 0.05 0.2 %/V FB IN V Output Voltage Load Regulation Measured in Servo Loop; V = 0.9V to 1.2V l 0.1 0.5 % LOADREG ITH Measured in Servo Loop; V = 1.6V to 1.2V l –0.1 –0.5 % ITH V Input Voltage Range l 2.65 6 V IN I Input DC Bias Current (Note 5) Q Pulse Skipping Mode 2.65V < V < 6V, V = 0V, I = 0A 230 350 m A IN SYNC/MODE OUT Burst Mode Operation V = V , I = 0A 10 15 m A SYNC/MODE IN OUT Shutdown V = 0V, V = 6V 0 1 m A RUN IN f Oscillator Frequency V = 0.8V 495 550 605 kHz OSC FB V = 0V 80 kHz FB f SYNC Capture Range 400 700 kHz SYNC I Phase Detector Output Current PLL LPF Sinking Capability f < f l 3 10 20 m A PLLIN OSC Sourcing Capability f > f l –3 –10 –20 m A PLLIN OSC R R of P-Channel MOSFET I = 100mA 0.5 0.7 W PFET DS(ON) SW R R of N-Channel MOSFET I = –100mA 0.6 0.8 W NFET DS(ON) SW 2

LTC1878 ELECTRICAL CHARACTERISTICS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25(cid:176) C. V = 3.6V unless otherwise specified. IN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I Peak Inductor Current V = 3.3V, V = 0.7V, Duty Cycle < 35% 0.8 1.0 1.25 A PK IN FB I SW Leakage V = 0V, V = 0V or 6V, V = 6V – 0.01 – 1 m A LSW RUN SW IN V SYNC/MODE Threshold V Rising l 0.3 1.0 1.5 V SYNC/MODE SYNC/MODE I SYNC/MODE Leakage Current – 0.01 – 1 m A SYNC/MODE V RUN Threshold V Rising l 0.3 0.7 1.5 V RUN RUN I RUN Input Current – 0.01 – 1 m A RUN Note 1: Absolute Maximum Ratings are those values beyond which the life Note 4: The LTC1878 is tested in a feedback loop which servos V to the FB of a device may be impaired. balance point for the error amplifier (V = 1.2V). ITH Note 2: The LTC1878E is guaranteed to meet performance specifications Note 5: Dynamic supply current is higher due to the gate charge being from 0(cid:176) C to 70(cid:176) C. Specifications over the –40(cid:176) C to 85(cid:176) C operating delivered at the switching frequency. temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: T is calculated from the ambient temperature T and power J A dissipation P according to the following formulas: D LTC1878EMS8: T = T + (P )(150(cid:176) C/W) J A D TYPICAL PERFORW AU CE CHARACTERISTICS Efficiency vs Input Voltage Efficiency vs Output Current Efficiency vs Output Current 100 100 95 95 ILOAD = 100mA ILOAD = 10mA 9800 VIN = V3.I6NV = 4.2V 8950 L = 15µH L = 10µH 90 70 %) 85 ILOAD = 300mA %) %) 80 NCY ( 80 ILOAD = 1mA NCY ( 5600 VIN = 3.6V NCY ( 75 EFFICIE 75 ILOAD = 0.1mA EFFICIE 40 VIN = 4.2V EFFICIE 7605 30 70 PULSE SKIPPING MODE 60 20 Burst Mode OPERATION Burst Mode OPERATION Burst Mode OPERATION 65 VOUT = 2.5V 10 VOUT = 1.8V 55 VIN = 6V L = 10µH L = 10µH VOUT = 2.5V 60 0 50 2 3 4 5 6 7 8 0.1 1 10 100 1000 0.1 1 10 100 1000 INPUT VOLTAGE (V) OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) 1878 G01 1878 G02 1878 G03 3

LTC1878 TYPICAL PERFORW AU CE CHARACTERISTICS RReeffeerreennccee VVoollttaaggee Oscillator Frequency Efficiency vs Output Current vvss TTeemmppeerraattuurree vs Temperature 95 0.814 605 VIN = 3.6V VIN = 3.6V 595 90 VIN = 3V 0.809 585 EFFICIENCY (%) 887505 VIN = 6VVINV I=N 4=. 23V.6V EFERENCE VOLTAGE (V)000...877099494 FREQUENCY (kHz) 555555765432555555 R 70 0.789 515 VOUT = 1.8V 505 L = 10µH 65 0.784 495 0.1 1 10 100 1000 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 OUTPUT CURRENT (mA) TEMPERATURE (°C) TEMPERATURE (°C) 1878 G04 1878 G05 1878 G06 Oscillator Frequency vs Supply Voltage Output Voltage vs Load Current R vs Input Voltage DS(ON) 605 1.83 0.9 595 0.8 1.82 Hz) 585 0.7 SYNCHRONOUS OR FREQUENCY (k 555546575555 UT VOLTAGE (V)11..8810 ΩR ()DS(ON) 000...645 SWMITACINHSWITCH LAT 535 UTP1.79 0.3 L 525 O OSCI 515 1.78 PULSE SKIPPING MODE 0.2 505 VIN = 3.6V 0.1 L = 10µH 495 1.77 0 0 2 4 6 8 0 100 200 300 400 500 600 700 800 900 0 1 2 3 4 5 6 7 8 SUPPLY VOLTAGE (V) LOAD CURRENT (mA) INPUT VOLTAGE (V) 1878 G07 1878 G08 1878 G09 DC Supply Current DC Supply Current R vs Temperature vs Input Voltage vs Temperature DS(ON) 1.2 250 300 SYNCHRONOUS SWITCH VOUT = 1.8V VIN = 3.6V 1.1 MAIN SWITCH PULSE SKIPPING 250 200 MODE 1.0 A) ΩR ()DS(ON) 0000....6789 VIN = V3IVN = 5V µC SUPPLY CURRENT (115000 µSUPPLY CURRENT (A) 211050000 PULSEM SOKDIEPPING 0.5 D 50 Burst Mode 50 Burst Mode 0.4 OPERATION OPERATION 0.3 0 0 –50 –25 0 25 50 75 100 125 0 1 2 3 4 5 6 7 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) INPUT VOLTAGE (V) TEMPERATURE (°C) 1878 G10 1878 G11 1878 G12 4

LTC1878 TYPICAL PERFORW AU CE CHARACTERISTICS Switch Leakage vs Temperature Switch Leakage vs Input Voltage Burst Mode Operation 2.5 1.2 VIN = 7V RUN = 0V RUN = 0V 1.0 SW 2.0 SYNCHRONOUS 5V/DIV A) A) SWITCH µAGE ( 1.5 AGE (n 0.8 VOUT K K 50mV/DIV A A 0.6 E E AC L L H 1.0 MAIN H COUPLED C C WIT SWITCH WIT 0.4 S SYNCHRONOUS S MAIN 0.5 SWITCH 0.2 SWITCH IL 200mA/DIV 0 0 –50 –25 0 25 50 75 100 125 0 1 2 3 4 5 6 7 8 10µs/DIV TEMPERATURE (°C) INPUT VOLTAGE (V) VIN = 4.2V CIN = 22µF 1878 G13 1878 G20 VL O=U 1T0 =µ 1H.5V CILOOUATD == 4570µmFA 1878 G14 Pulse Skipping Mode Operation Start-Up from Shutdown Load Step Response SW RUN VOUT 5V/DIV 2V/DIV 50mV/DIV AC COUPLED VOUT VOUT 1V/DIV 20mV/DIV AC IL 500mA/DIV COUPLED IL 500mA/DIV IL 200mA/DIV ITH 1V/DIV 1µs/DIV 40µs/DIV 40µs/DIV VIN = 4.2V CIN = 22µF VIN = 3.6V CIN = 22µF VIN = 3.6V CIN = 22µF VOUT = 1.5V COUT = 47µF VOUT = 1.5V COUT = 47µF VOUT = 1.5V COUT = 47µF L = 10µH ILOAD = 50mA 1878 G15 L = 10µH ILOAD = 500mA 1878 G16 L = 10µH ILOAD = 200mA TO 500mA 1878 G17 PULSE SKIPPING MODE Load Step Response Load Step Response VOUT VOUT 100mV/DIV 100mV/DIV AC AC COUPLED COUPLED IL IL 500mA/DIV 500mA/DIV ITH 1V/DITIVH 1V/DIV 40µs/DIV 40µs/DIV VIN = 3.6V CIN = 22µF VIN = 3.6V CIN = 22µF VOUT = 1.5V COUT = 47µF VOUT = 1.5V COUT = 47µF L = 10µH ILOAD = 50mA TO 500mA 1878 G18 L = 10µH ILOAD = 50mA TO 500mA 1878 G19 PULSE SKIPPING MODE Burst Mode OPERATION 5

LTC1878 PIU FUU CTIOU S RUN (Pin 1): Run Control Input. Forcing this pin below connects to the drains of the internal main and synchro- 0.4V shuts down the LTC1878. In shutdown all functions nous power MOSFET switches. are disabled drawing <1m A supply current. Forcing this V (Pin 6): Main Supply Pin. Must be closely decoupled IN pin above 1.2V enables the LTC1878. Do not leave RUN to GND, Pin 4. floating. SYNC/MODE (Pin 7): External Clock Synchronization and I (Pin 2): Error Amplifier Compensation Point. The TH Mode Select Input. To synchronize with an external clock, current comparator threshold increases with this control apply a clock with a frequency between 400kHz and voltage. Nominal voltage range for this pin is from 0.5V 700kHz. To select Burst Mode operation, tie to V . Ground- IN to 1.9V. ing this pin selects pulse skipping mode. Do not leave this V (Pin 3): Feedback Pin. Receives the feedback voltage pin floating. FB from an external resistive divider across the output. PLL LPF (Pin 8): Output of the Phase Detector and Control GND (Pin 4): Ground Pin. Input of Oscillator. Connect a series RC lowpass network from this pin to ground if externally synchronized. If SW (Pin 5): Switch Node Connection to Inductor. This pin unused, this pin may be left open. FUU CTIOU AL DIAGRAW VIN BURST Y = “0” ONLY WHEN X IS A CONSTANT “1” DEFEAT Y X PLL LPF 8 SYNC/MODE SLOPE COMP 7 0.8V VCO OSC 0.6V – FREQ 6 VIN 3 + SHIFT – VFB + – EN SLEEP V0R.8EVF +EA 0.55V + –ICOM+P 6Ω – VIN SLEEP BURST gm = 0.5mΩ VIN S Q R Q SWITCHING VIN 2 ITH RS LATCH LOGIC AND ANTI- BLANKING SHOOT- RUN CIRCUIT THRU 5 SW 1 0.8V REF – OVDET 0.85V + SHUTDOWN + IRCMP – 4 GND 1878 BD 6

LTC1878 OPERATIOU Main Control Loop BURST comparator trips, causing the internal sleep line to go high and forces off both power MOSFETs. The I pin The LTC1878 uses a constant frequency, current mode TH is then disconnected from the output of the EA amplifier step-down architecture. Both the main (P-channel and parked a diode voltage above ground. MOSFET) and synchronous (N-channel MOSFET) switches are internal. During normal operation, the internal top In sleep mode, both power MOSFETs are held off and a power MOSFET is turned on each cycle when the oscillator majority of the internal circuitry is partially turned off, sets the RS latch, and turned off when the current com- reducing the quiescent current to 10m A. The load current parator, I , resets the RS latch. The peak inductor is now being supplied solely from the output capacitor. COMP current at which ICOMP resets the RS latch is controlled by When the output voltage drops, the ITH pin reconnects to the voltage on the ITH pin, which is the output of error the output of the EA amplifier and the top MOSFET is again amplifier EA. The V pin, described in the Pin Functions turned on and this process repeats. FB section, allows EA to receive an output feedback voltage from an external resistive divider. When the load current Short-Circuit Protection increases, it causes a slight decrease in the feedback When the output is shorted to ground, the frequency of the voltage relative to the 0.8V reference, which in turn, oscillator is reduced to about 80kHz, 1/7 the nominal causes the I voltage to increase until the average induc- TH frequency. This frequency foldback ensures that the tor current matches the new load current. While the top inductor current has ample time to decay, thereby pre- MOSFET is off, the bottom MOSFET is turned on until venting runaway. The oscillator’s frequency will progres- either the inductor current starts to reverse as indicated by sively increase to 550kHz (or the synchronized frequency) the current reversal comparator I , or the beginning of RCMP when V rises above 0.3V. FB the next clock cycle. Comparator OVDET guards against transient overshoots Frequency Synchronization >6.25% by turning the main switch off and keeping it off A phase-locked loop (PLL) is available on the LTC1878 to until the fault is removed. allow the internal oscillator to be synchronized to an external source connected to the SYNC/MODE pin. The Burst Mode Operation output of the phase detector at the PLL LPF pin operates The LTC1878 is capable of Burst Mode operation in which over a 0V to 2.4V range corresponding to 400kHz to the internal power MOSFETs operate intermittently based 700kHz. When locked, the PLL aligns the turn-on of the top on load demand. To enable Burst Mode operation, simply MOSFET to the rising edge of the synchronizing signal. tie the SYNC/MODE pin to V or connect it to a logic high IN When the LTC1878 is clocked by an external source, Burst (V > 1.5V). To disable Burst Mode operation and SYNC/MODE Mode operation is disabled; the LTC1878 then operates in enable PWM pulse skipping mode, connect the SYNC/ PWM pulse skipping mode. In this mode, when the output MODE pin to GND. In this mode, the efficiency is lower at load is very low, current comparator I may remain COMP light loads, but becomes comparable to Burst Mode tripped for several cycles and force the main switch to stay operation when the output load exceeds 50mA. The ad- off for the same number of cycles. Increasing the output vantage of pulse skipping mode is lower output ripple and load slightly allows constant frequency PWM operation to less interference to audio circuitry. resume. This mode exhibits low output ripple as well as When the converter is in Burst Mode operation, the peak low audio noise and reduced RF interference while provid- current of the inductor is set to approximately 250mA, ing reasonable low current efficiency. even though the voltage at the I pin indicates a lower TH Frequency synchronization is inhibited when the feedback value. The voltage at the I pin drops when the inductor’s TH voltage V is below 0.6V. This prevents the external clock FB average current is greater than the load requirement. As from interfering with the frequency foldback for short- the I voltage drops below approximately 0.55V, the TH circuit protection. 7

LTC1878 OPERATIOU Dropout Operation Another important detail to remember is that at low input supply voltages, the R of the P-channel switch When the input supply voltage decreases toward the DS(ON) increases. Therefore, the user should calculate the power output voltage, the duty cycle increases toward the maxi- dissipation when the LTC1878 is used at 100% duty cycle mum on-time. Further reduction of the supply voltage with a low input voltage (see Thermal Considerations in forces the main switch to remain on for more than one the Applications Information section). cycle until it reaches 100% duty cycle. The output voltage will then be determined by the input voltage minus the Slope Compensation and Inductor Peak Current voltage drop across the internal P-channel MOSFET and the inductor. Slope compensation provides stability in constant fre- quency architectures by preventing subharmonic oscilla- Low Supply Operation tions at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current The LTC1878 is designed to operate down to an input signal at duty cycles in excess of 40%. As a result, the supply voltage of 2.65V although the maximum allowable maximum inductor peak current is reduced for duty cycles output current is reduced at this low voltage. Figure 1 >40%. This is shown in the decrease of the inductor peak shows the reduction in the maximum output current as a current as a function of duty cycle graph in Figure 2. function of input voltage for various output voltages. 1200 1100 L = 10µH A) VIN = 3.3V m 1000 T ( mA) VOUT = 1.5V REN1000 NT ( 800 CUR AX OUTPUT CURRE 460000 VOUT = 2.5V VOUT = 3.3V M INDUCTOR PEAK 980000 M200 MU 700 XI A M 0 600 2.5 3.5 4.5 5.5 6.5 7.5 0 20 40 60 80 100 INPUT VOLTAGE (V) DUTY CYCLE (%) 1878 F01 1878 F02 Figure 1. Maximum Output Current vs Input Voltage Figure 2. Maximum Inductor Peak Current vs Duty Cycle APPLICATIOU S IU FORW ATIOU The basic LTC1878 application circuit is shown on the first The operating frequency and inductor selection are inter- page. External component selection is driven by the load related in that higher operating frequencies allow the use requirement and begins with the selection of L followed by of smaller inductor and capacitor values. However, oper- C and C . ating at a higher frequency generally results in lower IN OUT efficiency because of increased internal gate charge losses. Inductor Value Calculation The inductor value has a direct effect on ripple current. The The inductor selection will depend on the operating fre- ripple current D I decreases with higher inductance or L quency of the LTC1878. The internal nominal frequency is frequency and increases with higher V or V . IN OUT 550kHz, but can be externally synchronized from 400kHz to 700kHz. 8

LTC1878 APPLICATIOU S IU FORW ATIOU 1 (cid:230) V (cid:246) New designs for surface mount inductors are available D IL= (f)(L)VOUTŁ(cid:231) 1- VOUTł(cid:247) (1) from Coiltronics, Coilcraft, Dale and Sumida. IN C and C Selection Accepting larger values of D I allows the use of low IN OUT L inductance, but results in higher output voltage ripple and In continuous mode, the source current of the top MOSFET greater core losses. A reasonable starting point for setting is a square wave of duty cycle VOUT/VIN. To prevent large ripple current is D I = 0.4(I ). voltage transients, a low ESR input capacitor sized for the L MAX maximum RMS current must be used. The maximum The inductor value also has an effect on Burst Mode RMS capacitor current is given by: operation. The transition to low current operation begins when the inductor current peaks fall to approximately [V (V - V )]1/2 250mA. Lower inductor values (higher D I ) will cause this C required I @ I OUT IN OUT L IN RMS OMAX V to occur at lower load currents, which can cause a dip in IN efficiency in the upper range of low current operation. In This formula has a maximum at V = 2V , where IN OUT Burst Mode operation, lower inductance values will cause I = I /2. This simple worst-case condition is com- RMS OUT the burst frequency to increase. monly used for design because even significant deviations do not offer much relief. Note the capacitor manufacturer’s Inductor Core Selection ripple current ratings are often based on 2000 hours of life. Once the value for L is known, the type of inductor must be This makes it advisable to further derate the capacitor, or selected. High efficiency converters generally cannot choose a capacitor rated at a higher temperature than afford the core loss found in low cost powdered iron cores, required. Several capacitors may also be paralleled to forcing the use of more expensive ferrite, molypermalloy, meet size or height requirements in the design. Always or Kool Mm ® cores. Actual core loss is independent of core consult the manufacturer if there is any question. size for a fixed inductor value, but it is very dependent on The selection of C is driven by the required effective inductance selected. As inductance increases, core losses OUT series resistance (ESR). Typically, once the ESR require- go down. Unfortunately, increased inductance requires ment is satisfied, the capacitance is adequate for filtering. more turns of wire and therefore copper losses will The output ripple D V is determined by: increase. OUT Ferrite designs have very low core losses and are pre- (cid:230) 1 (cid:246) ferred at high switching frequencies, so design goals can D VOUT@ D IL(cid:231) E+SR (cid:247) Ł 8fC ł OUT concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that where f = operating frequency, C = output capacitance OUT inductance collapses abruptly when the peak design cur- and D I = ripple current in the inductor. The output ripple L rent is exceeded. This results in an abrupt increase in is highest at maximum input voltage since D I increases L inductor ripple current and consequent output voltage with input voltage. For the LTC1878, the general rule for ripple. Do not allow the core to saturate! proper operation is: Kool Mm (from Magnetics, Inc.) is a very good, low loss C required ESR < 0.25W OUT core material for toroids with a “soft” saturation character- The choice of using a smaller output capacitance istic. Molypermalloy is slightly more efficient at high increases the output ripple voltage due to the frequency (>200kHz) switching frequencies but quite a bit more dependent term but can be compensated for by using expensive. Toroids are very space efficient, especially capacitor(s) of very low ESR to maintain low ripple when you can use several layers of wire, while inductors voltage. The I pin compensation components can be wound on bobbins are generally easier to surface mount. TH Kool Mm is a registered trademark of Magnetics, Inc. 9

LTC1878 APPLICATIOU S IU FORW ATIOU optimized to provide stable high performance transient external and internal oscillators. This type of phase detec- response regardless of the output capacitor selected. tor will not lock up on input frequencies close to the har- monics of the V center frequency. The PLL hold-in range ESR is a direct function of the volume of the capacitor. CO D f is equal to the capture range, D f = D f = – 150kHz. Manufacturers such as Taiyo-Yuden, AVX, Kemet, Sprague H H C and Sanyo should be considered for high performance The output of the phase detector is a pair of complemen- capacitors. The POSCAP solid electrolytic chip capacitor tary current sources charging or discharging the external available from Sanyo is an excellent choice for output bulk filter network on the PLL LPF pin. The relationship capacitors due to its low ESR/size ratio. Once the ESR between the voltage on the PLL LPF pin and operating requirement for C has been met, the RMS current frequency is shown in Figure 4. A simplified block diagram OUT rating generally far exceeds the I requirement. is shown in Figure 5. RIPPLE(P-P) When using tantalum capacitors, it is critical that they are 800 surge tested for use in switching power supplies. A good choice is the AVX TPS series of surface mount tantalum, Hz) 700 available in case heights ranging from 2mm to 4mm. Other Y (k C capacitor types include KEMET T510 and T495 series and N E 600 U Q Sprague 593D and 595D series. Consult the manufacturer E R F for other specific recommendations. OR 500 T A L L Output Voltage Programming SCI 400 O The output voltage is set by a resistive divider according 300 to the following formula: 0 0.4 0.8 1.2 1.6 2.0 V (V) PLL LPF (cid:230) R2(cid:246) 1878 F04 V =0.8V(cid:231) 1+ (cid:247) OUT Ł R1ł (2) Figure 4. Relationship Between Oscillator Frequency and Voltage at PLL LPF Pin The external resistive divider is connected to the output, allowing remote voltage sensing as shown in Figure 3. RLP PHASE 2.4V CLP 0.8V ≤ VOUT ≤ 6V DETECTOR PLL LPF R2 SYNC/ VFB MODE DIGITAL LTC1878 R1 FRPEHQAUSEEN/CY VCO DETECTOR GND 1878 F03 Figure 3. Setting the LTC1878 Output Voltage Phase-Locked Loop and Frequency Synchronization 1878 F05 The LTC1878 has an internal voltage-controlled oscillator Figure 5. Phase-Locked Loop Block Diagram and phase detector comprising a phase-locked loop. This allows the top MOSFET turn-on to be locked to the rising If the external frequency (V ) is greater than SYNC/MODE edge of an external frequency source. The frequency range 550kHz, the center frequency, current is sourced of the voltage-controlled oscillator is 400kHz to 700kHz. The continuously, pulling up the PLL LPF pin. When the phase detector used is an edge sensitive digital type that external frequency is less than 550kHz, current is sunk provides zero degrees phase shift between the continuously, pulling down the PLL LPF pin. If the 10

LTC1878 APPLICATIOU S IU FORW ATIOU external and internal frequencies are the same but exhibit 1 VIN = 4.2V a phase difference, the current sources turn on for an L = 10µH amount of time corresponding to the phase difference. 0.1 VVOOUUTT == 12..55VV Thus the voltage on the PLL LPF pin is adjusted until the W) Burst MVOoUdTe =O P3E.3RVATION phase and frequency of the external and internal oscilla- ST ( 0.01 O L tors are identical. At this stable operating point the phase R WE 0.001 comparator output is high impedance and the filter O P capacitor C holds the voltage. LP 0.0001 The loop filter components C and R smooth out the LP LP current pulses from the phase detector and provide a 0.00001 0.1 1 10 100 1000 stable input to the voltage controlled oscillator. The filter LOAD CURRENT (mA) component’s C and R determine how fast the loop 1878 F06 LP LP acquires lock. Typically R = 10k and C is 2200pF to Figure 6. Power Lost vs Load Current LP LP 0.01m F. When not synchronized to an external clock, the internal connection to the VCO is disconnected. This internal power MOSFET switches. Each time the gate is disallows setting the internal oscillator frequency by a DC switched from high to low to high again, a packet of voltage on the VPLL LPF pin. charge dQ moves from VIN to ground. The resulting dQ/dt is the current out of V that is typically larger than IN Efficiency Considerations the DC bias current. In continuous mode, I = GATECHG The efficiency of a switching regulator is equal to the f(QT + QB) where QT and QB are the gate charges of the output power divided by the input power times 100%. It is internal top and bottom switches. Both the DC bias and often useful to analyze individual losses to determine what gate charge losses are proportional to VIN and thus is limiting the efficiency and which change would produce their effects will be more pronounced at higher supply the most improvement. Efficiency can be expressed as: voltages. Efficiency = 100% – (L1 + L2 + L3 + ...) 2. I2R losses are calculated from the resistances of the internal switches, R , and external inductor R . In SW L where L1, L2, etc. are the individual losses as a percentage continuous mode the average output current flowing of input power. through inductor L is “chopped” between the main Although all dissipative elements in the circuit produce switch and the synchronous switch. Thus, the series losses, two main sources usually account for most of the resistance looking into the SW pin is a function of both losses in LTC1878 circuits: V quiescent current and I2R top and bottom MOSFET R and the duty cycle IN DS(ON) losses. The V quiescent current loss dominates the (DC) as follows: IN efficiency loss at very low load currents whereas the I2R R = (R )(DC) + (R )(1 – DC) loss dominates the efficiency loss at medium to high load SW DS(ON)TOP DS(ON)BOT currents. In a typical efficiency plot, the efficiency curve at The RDS(ON) for both the top and bottom MOSFETs can very low load currents can be misleading since the actual be obtained from the Typical Performance Charateristics power lost is of no consequence as illustrated in Figure 6. curves. Thus, to obtain I2R losses, simply add R to SW R and multiply the result by the square of the average L 1. The V quiescent current is due to two components: IN output current. the DC bias current as given in the electrical character- istics and the internal main switch and synchronous Other losses including C and C ESR dissipative IN OUT switch gate charge currents. The gate charge current losses and inductor core losses generally account for less results from switching the gate capacitance of the than 2% total additional loss. 11

LTC1878 APPLICATIOU S IU FORW ATIOU Thermal Considerations P-channel switch at 70(cid:176) C is approximately 0.7W . There- fore, power dissipated by the part is: In most applications the LTC1878 does not dissipate much heat due to its high efficiency. But, in applications P = I 2 • R = 0.175W D LOAD DS(ON) where the LTC1878 is running at high ambient tempera- For the MSOP package, the q is 150(cid:176) C/W. Thus, the JA ture with low supply voltage and high duty cycles, such junction temperature of the regulator is: as in dropout, the heat dissipated may exceed the maxi- mum junction temperature of the part. If the junction TJ = 70(cid:176) C + (0.175)(150) = 96(cid:176) C temperature reaches approximately 150(cid:176) C, both power which is below the maximum junction temperature of switches will be turned off and the SW node will become 125(cid:176) C. high impedance. Note that at higher supply voltages, the junction tempera- To avoid the LTC1878 from exceeding the maximum ture is lower due to reduced switch resistance (R ). DS(ON) junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to Checking Transient Response determine whether the power dissipated exceeds the The regulator loop response can be checked by looking at maximum junction temperature of the part. The tempera- the load transient response. Switching regulators take ture rise is given by: several cycles to respond to a step in load current. When TR = (PD)(q JA) a load step occurs, VOUT immediately shifts by an amount equal to (D I • ESR), where ESR is the effective series where P is the power dissipated by the regulator and q LOAD D JA resistance of C . D I also begins to charge or is the thermal resistance from the junction of the die to the OUT LOAD discharge C , which generates a feedback error signal. ambient temperature. OUT The regulator loop then acts to return V to its steady- OUT The junction temperature, T , is given by: J state value. During this recovery time V can be moni- OUT T = T + T tored for overshoot or ringing that would indicate a stabil- J A R ity problem. The internal compensation provides adequate where T is the ambient temperature. A compensation for most applications. But if additional As an example, consider the LTC1878 in dropout at an compensation is required, the I pin can be used for TH input voltage of 3V, a load current of 500mA, and an external compensation using R , C as shown in C C1 ambient temperature of 70(cid:176) C. From the typical perfor- Figure 7. (The 220pF capacitor, C , is typically needed for C2 mance graph of switch resistance, the R of the noise decoupling.) DS(ON) CC2 LTC1878 OPTIONAL 1 8 RUN PLL LPF RC CC1 2 7 ITH SYNC/MODE BOLD LINES INDICATE HIGH CURRENT PATHS 3 6 VFB VIN + 4 5 L1 GND SW R1 R2 + + CIN + VOUT VIN COUT – – 1878 F07 Figure 7. LTC1878 Layout Diagram 12

LTC1878 APPLICATIOU S IU FORW ATIOU A second, more severe transient is caused by switching in Design Example loads with large (>1m F) supply bypass capacitors. The As a design example, assume the LTC1878 is used in a discharged bypass capacitors are effectively put in parallel single lithium-ion battery-powered cellular phone applica- with C , causing a rapid drop in V . No regulator can OUT OUT tion. The input voltage will be operating from a maximum deliver enough current to prevent this problem if the load of 4.2V down to about 2.7V. The load current requirement switch resistance is low and it is driven quickly. The only is a maximum of 0.3A but most of the time it will be in solution is to limit the rise time of the switch drive so that standby mode, requiring only 2mA. Efficiency at both low the load rise time is limited to approximately (25 • C ). LOAD and high load currents is important. Output voltage is Thus, a 10m F capacitor charging to 3.3V would require a 2.5V. With this information we can calculate L using 250m s rise time, limiting the charging current to about equation (1), 130mA. 1 (cid:230) V (cid:246) PC Board Layout Checklist L= (f)(D I )VOUTŁ(cid:231) 1- VOUTł(cid:247) (3) L IN When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the Substituting VOUT = 2.5V, VIN = 4.2V, D IL=120mA and LTC1878. These items are also illustrated graphically in f = 550kHz in equation (3) gives: the layout diagram of Figure 7. Check the following in your (cid:230) (cid:246) layout: 2.5V 2.5V L= (cid:231) 1- (cid:247) =15.3m H 550kHz(120mA)Ł 4.2Vł 1. Are the signal and power grounds segregated? The LTC1878 signal ground consists of the resistive A 15m H inductor works well for this application. For best divider, the optional compensation network (R and C efficiency choose a 1A inductor with less than 0.25W C ) and C . The power ground consists of the (–) C1 C2 series resistance. plate of C , the (–) plate of C and Pin 4 of the IN OUT LTC1878. The power ground traces should be kept C will require an RMS current rating of at least 0.15A at IN short, direct and wide. The signal ground and power temperature and C will require an ESR of less than OUT ground should converge to a common node in a star- 0.25W . In most applications, the requirements for these ground configuration. capacitors are fairly similar. 2. Does the V pin connect directly to the feedback FB For the feedback resistors, choose R1 = 412k. R2 can resistors? The resistive divider R1/R2 must be con- then be calculated from equation (2) to be: nected between the (+) plate of C and signal ground. OUT (cid:230) (cid:246) V 3. Does the (+) plate of CIN connect to VIN as closely as R2=(cid:231) OUT - 1(cid:247) R1=875.5k; use 887k possible? This capacitor provides the AC current to the Ł 0.8 ł internal power MOSFETs. Figure 8 shows the complete circuit along with its effi- 4. Keep the switching node SW away from sensitive small ciency curve. signal nodes. 13

LTC1878 APPLICATIOU S IU FORW ATIOU 95 VIN = 3V VIN 2.65V 90 LTC1878 TO 4.2V VIN = 3.6V 220pF 1234 RIVGTFUNHBND SYNCP/LML OLSVDPWINEF 8765 15 µ H2C*2EµRF** VOUT EFFICIENCY (%) 8805 VIN = 4.2V + 2.5V 47µF*** 75 VOUT = 2.5V 887k L = 15µH 1878 F08a 70 412k 20pF *SUMIDA CD54-150 0.1 1 10 100 1000 **TAIYO-YUDEN CERAMIC JMK325BJ226MM OUTPUT CURRENT (mA) ***SANYO POSCAP 6TPA47M 1878 F08b Figure 8. Single Lithium-Ion to 2.5V/0.3A Regulator from Design Example TYPICAL APPLICATIOU S Single Li-Ion to 2.5V/0.6A Regulator Using All Ceramic Capacitors LTC1878 1 8 RUN PLL LPF 2 7 ITH SYNC/MODE 220pF 34 VFB VIN 65 10µH* VOUT CIN** V3VIN TO 4.2V GND SW 2.5V 22µF 20pF 887k COUT** 0.6A CER 22µF CER *TOKO D62CB A920CY-100M 412k **TAIYO-YUDEN CERAMIC JMK325BJ226MM 1878 TA03 3- to 4-Cell NiCd/NiMH to 1.8V/0.5A Regulator Using All Ceramic Capacitors LTC1878 1 8 RUN PLL LPF 2 7 ITH SYNC/MODE 220pF 34 VFB VIN 65 10µH* VOUT CIN** V2.I7NV TO 6V GND SW 1.8V 22µF COUT** 0.5A CER 20pF 887k 22µF CER *TOKO D62CB A920CY-100M 698k **TAIYO-YUDEN CERAMIC JMK325BJ226MM 1878 TA04 14

LTC1878 TYPICAL APPLICATIOU S Externally Synchronized 2.5V/0.6A Regulator Using All Ceramic Capacitors LTC1878 0.01µF 1 8 10k RUN PLL LPF 2 7 ITH SYNC/MODE EXT CLOCK 220pF 34 VFB VIN 65 71000µkHHz* VOUT CIN** V3VIN TO 6V GND SW 2.5V 22µF COUT** 0.6A CER 20pF 887k 22µF CER *TOKO D62CB A920CY-100M 412k **TAIYO-YUDEN CERAMIC JMK325BJ226MM 1878 TA04 Low Noise 2.5V/0.3A Regulator LTC1878 1 8 RUN PLL LPF 2 7 ITH SYNC/MODE 220pF 34 VFB VIN 65 15µH* VOUT CIN** V2.I6N5V TO 6V GND SW + COUT*** 20..53VA 2C2EµRF 20pF 887k 47µF 6.3V *SUMIDA CD54-150 412k **TAIYO-YUDEN CERAMIC JMK325BJ226MM ***SANYO POSCAP CTPA47M 1878 TA06 3- to 4-Cell NiCd/NiMH to 3.3V/0.5A Regulator Using All Ceramic Capacitors LTC1878 1 8 RUN PLL LPF 2 7 ITH SYNC/MODE 220pF 34 VFB VIN 65 10µH* VOUT† CIN** V2.I7NV TO 6V GND SW 3.3V 22µF COUT** 0.5A CER 20pF 887k 22µF CER *TOKO D62CB A920CY-100M 280k **TAIYO-YUDEN CERAMIC JMK325BJ226MM †VOUT CONNECTED TO VIN FOR 2.7V < VIN < 3.3V 1878 TA06 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 15 However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1878 TYPICAL APPLICATIOU Single Li-Ion to 2.5V/0.5A Regulator with Precision 2.7V Undervoltage Lockout 1.58M LTC1540 0.1µF 10k LTC1878 1% 1 8 1 8 GND OUT RUN PLL LPF 2 7 2 7 V– V+ ITH SYNC/MODE 11.%18M 34 IINN+– HRYESF 65 4124%.3.27kM 02.2001pµFF 34 VGFNBD SVWIN 65 10µH* 20pF 887k 2C2OµUFT** V20..O56UVAT C2C2IENµR*F* V2.I7NV TO 4.2V 1% CER *TOKO D62CB A920CY-100M 412k **TAIYO-YUDEN CERAMIC JMK325BJ226MM 1878 TA08 PACKAGE DESCRIPTIOU Dimensions in inches (millimeters) unless otherwise noted. MS8 Package 8-Lead Plastic MSOP (LTC DWG # 05-08-1660) 0.118 – 0.004* (3.00 – 0.102) 0.040 – 0.006 0.034 – 0.004 8 7 6 5 (1.02 – 0.15) (0.86 – 0.102) 0.007 0° – 6° TYP (0.18) SEATING 0.193 – 0.006 0.118 – 0.004** 0.021 – 0.006 PLANE 0.012 0.006 – 0.004 (4.90 – 0.15) (3.00 – 0.102) (0.53 – 0.015) (0.30) (0.15 – 0.102) 0.0256 REF (0.65) MSOP (MS8) 1098 BSC 1 2 3 4 *DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1174/LTC1174-3.3 High Efficiency Step-Down and Inverting DC/DC Converters Monolithic Switching Regulators, I to 450mA, OUT LTC1174-5 Burst Mode Operation LTC1265 1.2A, High Efficiency Step-Down DC/DC Converter Constant Off-Time, Monolithic, Burst Mode Operation LTC1474/LTC1475 Low Quiescent Current Step-Down DC/DC Converters Monolithic, I to 250mA, I = 10m A, 8-Pin MSOP OUT Q LTC1504A Monolithic Synchronous Step-Down Switching Regulator Low Cost, Voltage Mode I to 500mA, V from 4V to 10V OUT IN LTC1622 Low Input Voltage Current Mode Step-Down DC/DC Controller High Frequency, High Efficiency, 8-Pin MSOP LTC1626 Low Voltage, High Efficiency Step-Down DC/DC Converter Monolithic, Constant Off-Time, I to 600mA, OUT Low Supply Voltage Range: 2.5V to 6V LTC1627 Monolithic Synchronous Step-Down Switching Regulator Constant Frequency, I to 500mA, Secondary Winding OUT Regulation, V from 2.65V to 8.5V IN LTC1701 Monolithic Current Mode Step-Down Switching Regulator Constant Off-Time, I to 500mA, 1MHz Operation, OUT V from 2.5V to 5.5V IN LTC1707 Monolithic Synchronous Step-Down Switching Regulator 1.19V V Pin, Constant Frequency, I to 600mA, REF OUT V from 2.65V to 8.5V IN LTC1772 Low Input Voltage Current Mode Step-Down DC/DC Controller 550kHz, 6-Pin SOT-23, I Up to 5A, V from 2.2V to 10V OUT IN LTC1877 High Efficiency Monolithic Step-Down Regulator 550kHz, MS8, V Up to 10V, I = 10m A, I to 600mA IN Q OUT 16 Linear Technology Corporation 1878f LT/TP 1000 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l w ww.linear-tech.com ª LINEAR TECHNOLOGY CORPORATION 2000