LTC1864/LTC1865 µPower, 16-Bit, 250ksps 1- and 2-Channel ADCs in MSOP FEATURES DESCRIPTION n 16-Bit 250ksps ADCs in MSOP Package The LTC®1864/LTC1865 are 16-bit A/D converters that n Single 5V Supply are offered in MSOP and SO-8 packages and operate n Low Supply Current: 850μA (Typ) on a single 5V supply. At 250ksps, the supply current is n Auto Shutdown Reduces Supply Current only 850μA. The supply current drops at lower speeds to 2μA at 1ksps because the LTC1864/LTC1865 automatically power down n True Differential Inputs between conversions. These 16-bit switched capacitor n 1-Channel (LTC1864) or 2-Channel (LTC1865) successive approximation ADCs include sample-and- Versions holds. The LTC1864 has a differential analog input with an n SPI/MICROWIRE™ Compatible Serial I/O adjustable reference pin. The LTC1865 offers a software- n 16-Bit Upgrade to 12-Bit LTC1286/LTC1298 selectable 2-channel MUX and an adjustable reference pin n Pin Compatible with 12-Bit LTC1860/LTC1861 on the MSOP version. n Guaranteed Operation to +125°C (MSOP Package) The 3-wire, serial I/O, small MSOP or SO-8 package and extremely high sample rate-to-power ratio make these APPLICATIONS ADCs ideal choices for compact, low power, high speed systems. n High Speed Data Acquisition These ADCs can be used in ratiometric applications or with n Portable or Compact Instrumentation external references. The high impedance analog inputs n Low Power Battery-Operated Instrumentation and the ability to operate with reduced spans down to n Isolated and/or Remote Data Acquisition 1V full scale, allow direct connection to signal sources L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other in many applications, eliminating the need for external trademarks are the property of their respective owners. gain stages. TYPICAL APPLICATION Single 5V Supply, 250ksps, 16-Bit Sampling ADC Supply Current vs Sampling Frequency 1000 1μF 5V 100 A) μ LTC1864 NT ( 10 E 1 VREF VCC 8 URR ANALOG INPUT 2 IN+ SCK 7 SERIAL DATA LINK TO PLY C 1 0V TO 5V 3 IN– SDO 6 ASIC, PLD, MPU, DSP UP S 4 5 OR SHIFT REGISTERS 0.1 GND CONV 18645 TA01 0.01 0.01 0.1 1 10 100 1000 SAMPLING FREQUENCY (kHz) 18645 TA02 18645fb 1

LTC1864/LTC1865 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (V ) .................................................7V Operating Temperature Range CC Ground Voltage Difference LTC1864C/LTC1865C/ AGND, DGND LTC1865 MSOP Package ............±0.3V LTC1864AC/LTC1865AC ...........................0°C to 70°C Analog Input ................(GND – 0.3V) to (V + 0.3V) LTC1864I/LTC1865I/ CC Digital Input ................................(GND – 0.3V) to 7V LTC1864AI/LTC1865AI ...................... –40°C to 85°C Digital Output ..............(GND – 0.3V) to (V + 0.3V) LTC1864H/LTC1865H CC Power Dissipation ..............................................400mW LTC1864AH/LTC1865AH ................. –40°C to 125°C Storage Temperature Range ...................–65°C to 150°C Lead Temperature (Soldering, 10 sec) ..................300°C PIN CONFIGURATION LTC1864 LTC1865 TOP VIEW TOP VIEW VRINE+F 12 87VSCCCK COCNHV0 12 190 VVRCCEF CH1 3 8 SCK IN¯ 3 6SDO AGND 4 7 SDO GND 4 5CONV DGND 5 6 SDI MS8 PACKAGE MS PACKAGE 8-LEAD PLASTIC MSOP 10-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 210°C/W TJMAX = 150°C, θJA = 210°C/W LTC1864 LTC1865 TOP VIEW TOP VIEW VREF 1 8 VCC CONV 1 8 VCC IN+ 2 7 SCK CH0 2 7 SCK IN– 3 6 SDO CH1 3 6 SDO GND 4 5 CONV GND 4 5 SDI S8 PACKAGE S8 PACKAGE 8-LEAD PLASTIC SO 8-LEAD PLASTIC SO TJMAX = 150°C, θJA = 175°C/W TJMAX = 150°C, θJA = 175°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1864CMS8#PBF LTC1864CMS8#TRPBF LTHQ 8-Lead Plastic MSOP 0°C to 70°C LTC1864IMS8#PBF LTC1864IMS8#TRPBF LTHQ 8-Lead Plastic MSOP –40°C to 85°C LTC1864HMS8#PBF LTC1864HMS8#TRPBF LTHQ 8-Lead Plastic MSOP –40°C to 125°C LTC1864ACMS8#PBF LTC1864ACMS8#TRPBF LTHQ 8-Lead Plastic MSOP 0°C to 70°C LTC1864AIMS8#PBF LTC1864AIMS8#TRPBF LTHQ 8-Lead Plastic MSOP –40°C to 85°C LTC1864AHMS8#PBF LTC1864AHMS8#TRPBF LTHQ 8-Lead Plastic MSOP –40°C to 125°C LTC1864CS8#PBF LTC1864CS8#TRPBF 1864 8-Lead Plastic SO 0°C to 70°C LTC1864IS8#PBF LTC1864IS8#TRPBF 1864I 8-Lead Plastic SO –40°C to 85°C LTC1864ACS8#PBF LTC1864ACS8#TRPBF 1864A 8-Lead Plastic SO 0°C to 70°C LTC1684AIS8#PBF LTC1684AIS8#TRPBF 1864AI 8-Lead Plastic SO –40°C to 85°C LTC1865CMS#PBF LTC1865CMS#TRPBF LTHS 10-Lead Plastic MSOP 0°C to 70°C LTC1865IMS#PBF LTC1865IMS#TRPBF LTHS 10-Lead Plastic MSOP –40°C to 85°C 18645fb 2

LTC1864/LTC1865 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1865HMS#PBF LTC1865HMS#TRPBF LTHS 10-Lead Plastic MSOP –40°C to 125°C LTC1865ACMS#PBF LTC1865ACMS#TRPBF LTHS 10-Lead Plastic MSOP 0°C to 70°C LTC1865AIMS#PBF LTC1865AIMS#TRPBF LTHS 10-Lead Plastic MSOP –40°C to 85°C LTC1865AHMS#PBF LTC1865AHMS#TRPBF LTHS 10-Lead Plastic MSOP –40°C to 125°C LTC1865CS8#PBF LTC1865CS8#TRPBF 1865 8-Lead Plastic SO 0°C to 70°C LTC1865IS8#PBF LTC1865IS8#TRPBF 1865I 8-Lead Plastic SO –40°C to 85°C LTC1865ACS8#PBF LTC1865ACS8#TRPBF 1865A 8-Lead Plastic SO 0°C to 70°C LTC1865AIS8#PBF LTC1865AIS8#TRPBF 1865AI 8-Lead Plastic SO –40°C to 85°C LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1864CMS8 LTC1864CMS8#TR LTHQ 8-Lead Plastic MSOP 0°C to 70°C LTC1864IMS8 LTC1864IMS8#TR LTHQ 8-Lead Plastic MSOP –40°C to 85°C LTC1864HMS8 LTC1864HMS8#TR LTHQ 8-Lead Plastic MSOP –40°C to 125°C LTC1864ACMS8 LTC1864ACMS8#TR LTHQ 8-Lead Plastic MSOP 0°C to 70°C LTC1864AIMS8 LTC1864AIMS8#TR LTHQ 8-Lead Plastic MSOP –40°C to 85°C LTC1864AHMS8 LTC1864AHMS8#TR LTHQ 8-Lead Plastic MSOP –40°C to 125°C LTC1864CS8 LTC1864CS8#TR 1864 8-Lead Plastic SO 0°C to 70°C LTC1864IS8 LTC1864IS8#TR 1864I 8-Lead Plastic SO –40°C to 85°C LTC1864ACS8 LTC1864ACS8#TR 1864A 8-Lead Plastic SO 0°C to 70°C LTC1684AIS8 LTC1684AIS8#TR 1864AI 8-Lead Plastic SO –40°C to 85°C LTC1865CMS LTC1865CMS#TR LTHS 10-Lead Plastic MSOP 0°C to 70°C LTC1865IMS LTC1865IMS#TR LTHS 10-Lead Plastic MSOP –40°C to 85°C LTC1865HMS LTC1865HMS#TR LTHS 10-Lead Plastic MSOP –40°C to 125°C LTC1865ACMS LTC1865ACMS#TR LTHS 10-Lead Plastic MSOP 0°C to 70°C LTC1865AIMS LTC1865AIMS#TR LTHS 10-Lead Plastic MSOP –40°C to 85°C LTC1865AHMS LTC1865AHMS#TR LTHS 10-Lead Plastic MSOP –40°C to 125°C LTC1865CS8 LTC1865CS8#TR 1865 8-Lead Plastic SO 0°C to 70°C LTC1865IS8 LTC1865IS8#TR 1865I 8-Lead Plastic SO –40°C to 85°C LTC1865ACS8 LTC1865ACS8#TR 1865A 8-Lead Plastic SO 0°C to 70°C LTC1865AIS8 LTC1865AIS8#TR 1865AI 8-Lead Plastic SO –40°C to 85°C Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/ 18645fb 3

LTC1864/LTC1865 CONVERTER AND MULTIPILEXER CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. A V = 5V, V = 5V, f = f as defi ned in Recommended Operating Conditions, unless otherwise noted. CC REF SCK SCK(MAX) LTC1864/LTC1865 LTC1864A/LTC1865A PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Resolution l 16 16 Bits No Missing Codes Resolution l 14 15 Bits INL (Note 3) l ±8 ±6 LSB H-Grade (Note 3) l ±8.5 ±6.5 LSB Transition Noise 1.1 1.1 LSB RMS Gain Error l ±20 ±20 mV Offset Error LTC1864 SO-8 and MSOP, LTC1865 MSOP l ±2 ±5 ±2 ±5 mV LTC1865 SO-8 l ±3 ±7 ±3 ±7 mV Input Differential Voltage Range V = IN+ – IN– l 0 V 0 V V IN REF REF Absolute Input Range IN+ Input –0.05 V + 0.05 –0.05 V + 0.05 V CC CC IN– Input –0.05 V /2 –0.05 V /2 V CC CC V Input Range LTC1864 SO-8 and MSOP, 1 V 1 V V REF CC CC LTC1865 MSOP Analog Input Leakage Current (Note 4) l ±1 ±1 μA C Input Capacitance In Sample Mode 12 12 pF IN During Conversion 5 5 pF DYNAMIC ACCURACY T = 25°C. V = 5V, V = 5V, f = 250kHz, unless otherwise noted. A CC REF SAMPLE LTC1864/LTC1865 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SNR Signal-to-Noise Ratio 87 dB S/(N + D) Signal-to-Noise Plus Distortion Ratio 10kHz Input Signal 83 dB 100kHz Input Signal 76 dB THD Total Harmonic Distortion Up to 5th Harmonic 10kHz Input Signal 88 dB 100kHz Input Signal 77 dB Full Power Bandwidth 20 MHz Full Linear Bandwidth S/(N+D) ≥ 75dB 125 kHz 18645fb 4

LTC1864/LTC1865 DIGITAL AND DC ELECTRICAL CHARACTERISTICS The ● denotes specifi cations which apply over the full operating temperature range, otherwise specifi cations are T = 25°C. V = 5V, V = 5V, unless otherwise noted. A CC REF LTC1864/LTC1865 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V High Level Input Voltage V = 5.25V l 2.4 V IH CC V Low Level Input Voltage V = 4.75V l 0.8 V IL CC I High Level Input Current V = V l 2.5 μA IH IN CC I Low Level Input Current V = 0V l –2.5 μA IL IN V High Level Output Voltage V = 4.75V, I = 10μA l 4.5 4.74 V OH CC O V = 4.75V, I = 360μA l 2.4 4.72 V CC O V Low Level Output Voltage V = 4.75V, I = 1.6mA ● 0.4 V OL CC O I Hi-Z Output Leakage CONV = V ● ±3 μA OZ CC I Output Source Current V = 0V –25 mA SOURCE OUT I Output Sink Current V = V 20 mA SINK OUT CC I Reference Current (LTC1864 SO-8 and MSOP, CONV = VCC ● 0.001 3 μA REF LTC1865 MSOP) f = f ● 0.05 0.1 mA SMPL SMPL(MAX) I Supply Current CONV = V After Conversion ● 0.001 3 μA CC CC CONV = V After Conversion, H-Grade ● 0.001 5 μA CC fSMPL = fSMPL(MAX) ● 0.85 1.3 mA P Power Dissipation f = f 4.25 mW D SMPL SMPL(MAX) 18645fb 5

LTC1864/LTC1865 RECOMMENDED OPERATING CONDITIONS The ● denotes specifi cations which apply over the full operating temperature range, otherwise specifi cations are T = 25°C. A LTC1864/LTC1865 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Supply Voltage 4.75 5.25 V CC f Clock Frequency ● 20 MHz SCK H-Grade ● 16.7 MHz t Total Cycle Time 16 • SCK + t μs CYC CONV t Analog Input Sampling Time LTC1864 (Note 5) 16 SCK SMPL LTC1865 (Note 5) 14 SCK tsuCONV Setup Time CONV↓ Before First SCK↑ 60 30 ns (See Figure 1) H-Grade 65 30 ns thDI Hold Time SDI After SCK↑ LTC1865 15 ns tsuDI Setup Time SSDI Stable Before SCK↑ LTC1865 15 ns t SCK High Time f = f 40% 1/f WHCLK SCK SCK(MAX) SCK t SCK Low Time f = f 40% 1/f WLCLK SCK SCK(MAX) SCK t CONV High Time Between Data Transfer (Note 5) t μs WHCONV CONV Cycles t CONV Low Time During Data Transfer (Note 5) 16 SCK WLCONV thCONV Hold Time CONV Low After Last SCK↑ 13 ns 18645fb 6

LTC1864/LTC1865 TIMING CHARACTERISTICS The ● denotes specifi cations which apply over the full operating temperature range, otherwise specifi cations are T = 25°C. V = 5V, V = 5V, f = f as defi ned in Recommended Operating Conditions, A CC REF SCK SCK(MAX) unless otherwise noted. LTC1864/LTC1865 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t Conversion Time (See Figure 1) ● 2.75 3.2 μs CONV H-Grade ● 2.75 3.3 μs f Maximum Sampling Frequency ● 250 kHz SMPL(MAX) H-Grade ● 234 kHz tdDO Delay Time, SCK↓ to SDO Data Valid CLOAD = 20pF 15 20 ns C = 20pF ● 25 ns LOAD C = 20pF, H-Grade ● 30 ns LOAD tdis Delay Time, CONV↑ to SDO Hi-Z ● 30 60 ns H-Grade ● 30 65 ns ten Delay Time, CONV↓ to SDO Enabled CLOAD = 20pF ● 30 60 ns C = 20pF, H-Grade ● 30 65 ns LOAD thDO Time Output Data Remains Valid After SCK↓ CLOAD = 20pF ● 5 10 ns t SDO Rise Time C = 20pF 8 ns r LOAD t SDO Fall Time C = 20pF 4 ns f LOAD Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: Integral nonlinearity is defi ned as deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual endpoints of the transfer curve. Maximum Rating condition for extended periods may affect device The deviation is measured from the center of the quantization band. reliability and lifetime. Note 4: Channel leakage current is measured while the part is in sample Note 2: All voltage values are with respect to GND. mode. Note 5: Guaranteed by design, not subject to test. 18645fb 7

LTC1864/LTC1865 TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Sampling Frequency Supply Current vs Temperature Sleep Current vs Temperature 1000 1000 1000 VCC = 5V CONV = VCC= 5V TA = 25°C 900 CONV LOW = 800ns 100 800 800 SUPPLY CURRENT (A)μ 101 SUPPLY CURRENT (A)μ640000 SLEEP CURRENT (nA)765430000000000 0.1 200 VCC = 5V 200 VREF = 5V fSAMPLE = 250kHz 100 CONV HIGH = 3.2μS 0.01 0 0 0.01 0.1 1.0 10 100 1000 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 SAMPLING FREQUENCY (kHz) TEMPERATURE (°C) TEMPERATURE (°C) 18645 G01 18645 G02 18645 G03 Reference Current vs Reference Current vs Reference Current vs Sampling Rate Temperature Reference Voltage 60 55 60 VCC = 5V VCC= 5V VCC= 5V TA = 25°C 54 VREF= 5V TA = 25°C 50 VREF = 5V 53 fS = 250kHz 50 fS = 250kHz A) CONV LOW = 800ns A) A) μ μ μ T ( 40 T ( 52 T ( 40 N N N RE RE 51 RE R R R CU 30 CU 50 CU 30 E E E NC NC 49 NC RE 20 RE RE 20 E E 48 E EF EF EF R R 47 R 10 10 46 0 45 0 0 50 100 150 200 250 –50 –25 0 25 50 75 100 125 0 1 2 3 4 5 SAMPLE RATE (kHz) TEMPERATURE (°C) VREF (V) 18645 G04 18645 G05 18645 G06 Analog Input Leakage Current vs Typical INL Curve Typical DNL Curve Temperature 4 2 100 VCC = 5V VCC = 5V VCC = 5V TA = 25°C TA = 25°C VREF = 5V VREF = 5V VREF = 5V A) CONV = 0V Bs) 2 Bs) 1 AGE (n 75 S S K R (L R (L LEA RO 0 RO 0 UT 50 R R P NL E NL E G IN I D O –2 –1 AL 25 N A –4 –2 0 0 16384 32768 49152 65536 0 16384 32768 49152 65536 –50 –25 0 25 50 75 100 125 CODE CODE TEMPERATURE (°C) 18645 G07 18645 G08 18645 G09 18645fb 8

LTC1864/LTC1865 TYPICAL PERFORMANCE CHARACTERISTICS Change in Offset Error vs Change in Gain Error vs Reference Voltage Change in Offset vs Temperature Reference Voltage 75 5 20 VCC = 5V VCC = 5V VCC = 5V TA = 25°C 4 VREF = 5V 15 TA = 25°C SB) 3 B) OR (L 50 LSB) 2 R (LS 10 FFSET ERR 25 N OFFSET ( 10 GAIN ERRO 50 HANGE IN O 0 CHANGE I –––123 CHANGE IN ––150 C –15 –4 –25 –5 –20 0 1 2 3 4 5 –50 –25 0 25 50 75 100 125 0 1 2 3 4 5 REFERENCE VOLTAGE (V) TEMPERATURE (°C) REFERENCE VOLTAGE(V) 18645 G10 18645 G11 18645 G12 Change in Gain Error vs Histogram of 4096 Conversions of Temperature a DC Input Voltage 4096 Point FFT Nonaveraged 5 1800 0 VCC = 5V VCC = 5V fS = 203.125kHz LSB) 43 VREF = 5V 11640000 1534 TVAR E=F 2=5 5°CV –20 fVVINCRC E=F = 9= 59 5V.7V2763kHz OR ( 2 1200 1178 B)–40 TA = 25°C ERR 1 NCY 1000 E (d–60 NGE IN GAIN ––012 FREQUE 860000 729 516 AMPLITUD––18000 HA –3 400 C –120 –4 200 127 0 0 12 0 0 –5 0 –140 –50 –25 0 25 50 75 100 125 –4 –3 –2 –1 0 1 2 3 4 5 0 20 40 60 80 100 120 TEMPERATURE (°C) CODE FREQUENCY (kHz) 18645 G13 18645 G14 18645 G15 SINAD vs Frequency THD vs Frequency SFDR vs Frequency 100 0 100 90 SNR –10 90 80 –20 80 70 SINAD –30 70 SINAD (dB) 654000 THD (dB)–––456000 SFDR (dB) 654000 30 –70 30 20 VVCRCEF = = 5 5VV –80 VVCRCEF = = 5 5VV 20 VVCRCEF = = 5 5VV 10 TA = 25°C –90 TA = 25°C 10 TA = 25°C VIN = 0dB VIN = 0dB VIN = 0dB 0 –100 0 1 10 100 1000 1 10 100 1000 1 10 100 1000 FIN (kHz) FIN (kHz) FIN (kHz) 18645 G16 18645 G17 18645 G18 18645fb 9

LTC1864/LTC1865 PIN FUNCTIONS LTC1864 V (Pin 1): Reference Input. The reference input defi nes powers down. A logic low on this input enables the SDO REF the span of the A/D converter and must be kept free of pin, allowing the data to be shifted out. noise with respect to GND. SDO (Pin 6): Digital Data Output. The A/D conversion IN+, IN– (Pins 2, 3): Analog Inputs. These inputs must result is shifted out of this pin. be free of noise with respect to GND. SCK (Pin 7): Shift Clock Input. This clock synchronizes GND (Pin 4): Analog Ground. GND should be tied directly the serial data transfer. to an analog ground plane. V (Pin 8): Positive Supply. This supply must be kept CC CONV (Pin 5): Convert Input. A logic high on this input free of noise and ripple by bypassing directly to the starts the A/D conversion process. If the CONV input is analog ground plane. left high after the A/D conversion is fi nished, the part LTC1865 (MSOP Package) CONV (Pin 1): Convert Input. A logic high on this input SDO (Pin 7): Digital Data Output. The A/D conversion starts the A/D conversion process. If the CONV input is result is shifted out of this output. left high after the A/D conversion is fi nished, the part SCK (Pin 8): Shift Clock Input. This clock synchronizes powers down. A logic low on this input enables the SDO the serial data transfer. pin, allowing the data to be shifted out. V (Pin 9): Positive Supply. This supply must be kept CC CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must free of noise and ripple by bypassing directly to the be free of noise with respect to AGND. analog ground plane. AGND (Pin 4): Analog Ground. AGND should be tied directly V (Pin 10): Reference Input. The reference input defi nes REF to an analog ground plane. the span of the A/D converter and must be kept free of DGND (Pin 5): Digital Ground. DGND should be tied directly noise with respect to AGND. to an analog ground plane. SDI (Pin 6): Digital Data Input. The A/D confi guration word is shifted into this input. LTC1865 (SO-8 Package) CONV (Pin 1): Convert Input. A logic high on this input SDI (Pin 5): Digital Data Input. The A/D confi guration starts the A/D conversion process. If the CONV input is word is shifted into this input. left high after the A/D conversion is fi nished, the part SDO (Pin 6): Digital Data Output. The A/D conversion powers down. A logic low on this input enables the SDO result is shifted out of this output. pin, allowing the data to be shifted out. SCK (Pin 7): Shift Clock Input. This clock synchronizes CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must the serial data transfer. be free of noise with respect to GND. V (Pin 8): Positive Supply. This supply must be kept CC GND (Pin 4): Analog Ground. GND should be tied directly free of noise and ripple by bypassing directly to the analog to an analog ground plane. ground plane. V is tied internally to this pin. REF 18645fb 10

LTC1864/LTC1865 FUNCTIONAL BLOCK DIAGRAM VCC CONV(SDI) SCK PIN NAMES IN PARENTHESES REFER TO LTC1865 CONVERT BIAS AND SERIAL SDO CLK SHUTDOWN PORT DATA IN 16 BITS IN+ + (CH0) 16-BIT SAMPLING DATA OUT IN– – ADC (CH1) 18645 BD GND VREF 18645fb 11

LTC1864/LTC1865 TEST CIRCUITS Load Circuit for t , t, t, t and t Voltage Waveforms for SDO Rise and Fall Times, t, t dDO r f dis en r f TEST POINT VOH SDO VOL 3k VCC tdis WAVEFORM 2, ten SDO tdis WAVEFORM 1 tr tf 18645 TC04 20pF 18645 TC01 Voltage Waveforms for t Voltage Waveforms for t en dis CONV CONV VIH SDO 18645 TC03 SDO 90% WAVEFORM 1 ten (SEE NOTE 1) tdis SDO WAVEFORM 2 Voltage Waveforms for SDO Delay Times,t and t 10% dDO hDO (SEE NOTE 2) NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL SCK VIL NTHOATTE T2H: WE OAVUETFPOURTM IS 2 L IOSW FO URN ALNES OSU DTIPSUATB LWEIDT HB YIN TTHEER NOAULT PCUOTN CDOITNIOTRNOS LSUCH tdDO 18645 TC05 thDO VOH SDO VOL 18645 TC02 18645fb 12

LTC1864/LTC1865 APPLICATIONS INFORMATION LTC1864 OPERATION Analog Inputs The LTC1864 has a unipolar differential analog input. The Operating Sequence converter will measure the voltage between the “IN+” The LTC1864 conversion cycle begins with the rising edge and “IN–” inputs. A zero code will occur when IN+ minus of CONV. After a period equal to tCONV, the conversion is IN– equals zero. Full scale occurs when IN+ minus IN– fi nished. If CONV is left high after this time, the LTC1864 equals V minus 1LSB. See Figure 2. Both the “IN+” and REF goes into sleep mode drawing only leakage current. On the “IN–” inputs are sampled at the same time, so common falling edge of CONV, the LTC1864 goes into sample mode mode noise on the inputs is rejected by the ADC. If “IN–” and SDO is enabled. SCK synchronizes the data transfer is grounded and V is tied to V , a rail-to-rail input REF CC with each bit being transmitted from SDO on the falling span will result on “IN+” as shown in Figure 3. SCK edge. The receiving system should capture the data from SDO on the rising edge of SCK. After completing the Reference Input data transfer, if further SCK clocks are applied with CONV The voltage on the reference input of the LTC1864 defi nes low, SDO will output zeros indefi nitely. See Figure 1. the full-scale range of the A/D converter. The LTC1864 can operate with reference voltages from V to 1V. CC tsuCONV CONV tSMPL tCONV SLEEP MODE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK SDO B15B14B13B12B11B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 18645 F01 Figure 1. LTC1864 Operating Sequence 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1μF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 VCC • • • LTC1864 1 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VIN* VREF VCC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VIN = 0V TO VCC 2 IN+ SCK 7 0V 1LSB *VIN = IN+ – IN– REFV REFV REFV 3 IN– SDO 6 SAESRICIA, PL LDDA, TMAP LUIN, DK STPO – 2LSB – 1LSB 18645 F02 4 GND CONV 158645 F03 OR SHIFT REGISTERS Figure 2. LTC1864 Transfer Curve Figure 3. LTC1864 with Rail-to-Rail Input Span 18645fb 13

LTC1864/LTC1865 APPLICATIONS INFORMATION LTC1865 OPERATION single-ended mode, all input channels are measured with respect to GND. A zero code will occur when the Operating Sequence “+” input minus the “–” input equals zero. Full scale oc- curs when the “+” input minus the “–” input equals V The LTC1865 conversion cycle begins with the rising edge REF minus 1LSB. See Figure 5. Both the “+” and “–” inputs of CONV. After a period equal to t , the conversion is CONV are sampled at the same time so common mode noise fi nished. If CONV is left high after this time, the LTC1865 is rejected. The input span in the SO-8 package is fi xed goes into sleep mode drawing only leakage current. The at V = V . If the “–” input in differential mode is LTC1865’s 2-bit data word is clocked into the SDI input REF CC grounded, a rail-to-rail input span will result on the “+” on the rising edge of SCK after CONV goes low. Additional input. inputs on the SDI pin are then ignored until the next CONV cycle. The shift clock (SCK) synchronizes the data transfer Reference Input with each bit being transmitted on the falling SCK edge and captured on the rising SCK edge in both transmitting and The reference input of the LTC1865 SO-8 package is receiving systems. The data is transmitted and received internally tied to V . The span of the A/D converter is CC simultaneously (full duplex). After completing the data therefore equal to V . The voltage on the reference CC transfer, if further SCK clocks are applied with CONV low, input of the LTC1865 MSOP package defi nes the span SDO will output zeros indefi nitely. See Figure 4. of the A/D converter. The LTC1865 MSOP package can operate with reference voltages from 1V to V . Analog Inputs CC Table 1. Multiplexer Channel Selection The two bits of the input word (SDI) assign the MUX MUX ADDRESS CHANNEL # confi guration for the next requested conversion. For a SGL/DIFF ODD/SIGN 0 1 GND given channel selection, the converter will measure the SINGLE-ENDED 1 0 + – voltage between the two channels indicated by the “+” MUX MODE 1 1 + – and “–” signs in the selected row of the following table. In DIFFERENTIAL 0 0 + – MUX MODE 0 1 – + 18645 TBL1 CONV tSMPL tCONV SLEEP MODE SDI DON’T CARE S/DO/S DON’T CARE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK SDO B15B14B13B12B11B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 18645 F04 Figure 4. LTC1865 Operating Sequence 18645fb 14

LTC1864/LTC1865 APPLICATIONS INFORMATION GENERAL ANALOG CONSIDERATIONS induce errors or noise in the output code. Bypass the V CC and V pins directly to the analog ground plane with REF Grounding a minimum of 1μF tantalum. Keep the bypass capacitor leads as short as possible. The LTC1864/LTC1865 should be used with an analog ground plane and single point grounding techniques. Do not Analog Inputs use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance, use a Because of the capacitive redistribution A/D conversion printed circuit board. The ground pins (AGND and DGND techniques used, the analog inputs of the LTC1864/LTC1865 for the LTC1865 MSOP package and GND for the LTC1864 have capacitive switching input current spikes. These cur- and LTC1865 SO-8 package) should be tied directly to the rent spikes settle quickly and do not cause a problem if analog ground plane with minimum lead length. source resistances are less than 200Ω or high speed op amps are used (e.g., the LT®1211, LT1469, LT1807, LT1810, Bypassing LT1630, LT1226 or LT1215). But if large source resistances are used, or if slow settling op amps drive the inputs, take For good performance, the V and V pins must be free CC REF care to ensure the transients caused by the current spikes of noise and ripple. Any changes in the V /V voltage CC REF settle completely before the conversion begins. with respect to ground during the conversion cycle can 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 • • • 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VIN* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0V 1LS CCV CCV CCV B – – * V(SINE L=E (CSTEELDE C“–T”E DC H“A+”N CNHELA)NNEL) – 2LSB 1LSB 18645 F05 REFER TO TABLE 1 Figure 5. LTC1865 Transfer Curve 18645fb 15

LTC1864/LTC1865 APPLICATIONS INFORMATION 5V5VDIGDIG C13C140.1F0.1FμμJ43201S40G1 4039U45VDIG74HC595ADT38373635116QBVCC3433215QCQA3231143QDA3029134QEOENB2827125QFLCLK2625116QGSCLK2423107QHRESET222198GNDSQH2019181716151161413QBVCC2151211QCQA143109QDA13487QEOENB12565QFLCLK11643QGSCLK10721QHRESET98GNDSQHC155VDIGU50.1Fμ74HC595ADTU9D74AC00U9C74AC00 E2CONV E3ENABLEDATA2E7DGNDJP5U8EU8FE6174AC14DGND74AC14E4DOUT E5CLKOUTJ3 CLKINC19R95V0.1FμDIG51Ω U13AU13D74AC3274AC32 NOTES: UNLESS OTHERWISE SPECIFIEDINSTALL SHUNTS ON JP1, JP3-JP7 PIN 1 AND PIN2;ON JP8 AND JP9 PIN 2 AND PIN 4, PIN 3 AND PIN 5.18645 AI1 ematic 5V5VANDIGR42Ω3VOUTC26D10Fμ6.3V21206 R5402, 1%Ω U8AC2174AC1447pF R6402Ω1% U8BC2274AC1447pF C255V0.1FDIGμ U8D74AC14 1JP62JP73213 U8C74AC14 U13C74AC32 h N c G LTC1864 Evaluation Circuit S 15V 1VINC21FC1μ10V0.1Fμ5VAN0805 C3C410Fμ0.1Fμ6.3V1206RN133018VVREFCC2187+INSCK3276C8–INSDOC741000pF365GNDCONV390pFOPT45U3C9C10LTC1864CMS8180pF680pFOPT C12C111000pF390pFOPT ANALOG GROUND PLANE C23C245V5VDIGDIG0.1F0.1Fμμ U12BU12A1674AC10974AC10916261410VVCCCCJP4JQJQ2137139KQKQ412CLKCLK115CLRCLR58118PREGNDPREGND 5V5VDIGDIG C16C170.1F0.1Fμμ5VDIG U7C18R125V74HC163AD0.1FμDIG10k116RESETVCC215U10CLKRCO143LTC1799P0Q013451+P1Q1VOUT1252P2Q2GND11643P3Q3DIVSET107R10ENPENT9820kGNDLO CLKU13B74AC32 Ω Ω R32Ω6VVINOUTU1GNDLT1021-54 21 JP1C50.1Fμ R151021 JP2 C60.1FμR2510 2JP31 U9B74AC00 U9A74AC00 5VDIG U674HC163AD116RESETVCC152CLKRCO143P0Q0134P1Q1125P2Q2116P3Q3107ENPENT98GNDLO 2 C270.1Fμ 15V +U2OPT– –15V V +IN R751Ω0PT –IN R851Ω0PT 6 5 6 5 15 4 P8 3 4 P9 3 E115V J1+IN E8AGND E9 J2–IN VDIG 2 J 1 2 J 1 5 18645fb 16

LTC1864/LTC1865 APPLICATIONS INFORMATION Component Side Silk Screen for LTC1864 Evaluation Circuit Component Side Showing Traces Bottom Side Showing Traces (Note Sider Traces on Analog Side) (Note Almost No Analog Traces on Board Bottom) Ground Layer with Separate Analog and Digital Grounds Supply Layer with 5V Digital Supply and Analog Ground Repeated 18645fb 17

LTC1864/LTC1865 APPLICATIONS INFORMATION U11 15V LT1121CST-5 5VAN R4 5VDIG 1 VIN VOUT 3 2Ω C26 GND 10μF 2 6.3V 5VAN 1206 C3 10μF C4 6.3V 0.1μF 1206 5VDIG 5VDIG 15V RN1 LTC1485 1V t0oV 5 tVo RVERFEEF RINENPUCET 1234 VIIGNNRN+–EDF CSOSVDNCCOKVC 8765 1234330 8765 1234 RRDDOEEI GVNCDBAC 8765 120Ω U3 LTC1864CMS8 ANALOG GROUND PLANE 4 CONDUCTOR TELEPHONE WIRES C23 C24 TO RECEIVER 5VDIG 0.1μF 5VDIG 0.1μF 4 1 2 U12A U12B 5V 500Ω U9B 74AC109 16 74AC109 16 5 3 74AC00 2 J VCC Q 6 14 J VCC Q 10 3 7 13 9 K Q K Q MC74VHC1G66 4 12 1v CLK 15v CLK CLR CLR 5 8 11 8 PRE GND PRE GND U9A 5VDIG 5VDIG 74AC00 C16 C17 0.1μF 0.1μF 5VDIG 5VDIG 5VDIG 74AC74 74AC86 U6 U7 C18 74HC163AD 74HC163AD 5VDIG 0.1μF PRE Q 1 16 1 16 D 23 RCLEKSET RVCCOC 1154 23 RCLEKSET RVCCOC 1154 ULT1C01799 v C CLRLK Q P0 Q0 P0 Q0 4567 PPP123 QQQ123 11113210 4567 PPP123 QQQ123 11113210 100k 123 VGSE+NTD ODUIVT 54 5VDIG74AC74 8 ENP ENT 9 8 ENP ENT 9 PRE Q GND LO GND LO D U13C v CLK 74AC32 CLR Q CLK 18645 AI2 U13B 74AC32 Figure 6. LTC1864 Manchester Transmitter 18645fb 18

LTC1864/LTC1865 APPLICATIONS INFORMATION VCC VCC VCC IC3A IC2B IC4B 74AC74 DATA INVCC42 I7C4PD1ARACE74 Q 5 VCC I7C45ACC86 I7C46ADC32 I7C44AAC08 CLK 4231 vI7C4PD C2ARALCEK74 Q 56 CLK11110213 v74PD CCARLLCREK74 QQ 98 74AC08 CLK 4231 vPD CCRLLREK QQ 56 CLK 31 v C CLRLK Q 6 1102 PDRE Q 9 CLR Q CLK1113 v C CLRLK Q 8 DATA I7C46LCS32D DATA IC1B 74AC74 I7C44ADC08 IC4C VCC I7C43ABC74 74AC08 10 PRE Q 9 STROBE 12 D CLK 11 v CLK 13 CLR Q 8 RECEIVE CLOCK AT IC8 8 X TRANSMIT 74AC595 CLOCK FREQUENCY 14 SER QA 15D15 1 12ULTRR1COE1485 VCBC 87 VCC VCC 111102vSS RCCCKLK QQQQQQDGBCEF 23456 DDDDDD11111943210 34 DDEI GNDA 65 13 8 QHQIHN 79 D8 OPTIONAL SERIAL TO PARALLEL CONVERTER VCC IC9 15V SUPPLY TO 74AC595 TRANSMITTER 14 SER QA 15D7 1 STROBE 11 SCK QQBC 2 DD65 3 TETLOE 4TP RHCAOONNNSEDM UWICTITRTOEERRS R1210Ω DATA 11111423 vI7CPJ K4C7RALBECK109 Q 10 111023vS 8RCCLK QHQQQQQIDGHEFN 45679 DDDDD43210 15 CLR Q 9 18645 AI3 Figure 7. LTC1864 Manchester Receiver 18645fb 19

LTC1864/LTC1865 APPLICATIONS INFORMATION Transmit LTC1864 Data Over Modular Telephone Wire zeros, a start bit, followed by the 16 data bits (one sample Using Simple Transmitter/Receiver every 48 clock cycles) at a clock frequency of 1MHz set by the LTC1799 oscillator. Sending at least 18 zeros before Figure 6 shows a simple Manchester encoder and dif- each start bit ensures that if synchronization is lost, the ferential transmitter suitable for use with the LTC1864. receiver can resynchronize to a start bit under all condi- This circuit allows transmission of data over inexpensive tions. The serial to parallel converter shown in Figure 7 telephone wire. This is useful for measuring a remote requires 18 zeros to avoid triggering on data bits. sensor, particularly when the cost of preserving the analog signal over a long distance is high. The Manchester receiver shown in Figure 7 was adopted from Xilinx application note 17-30 and would typically be Manchester encoding is a clock signal that is modulated implemented in an FPGA. The decoder clock frequency is by exclusive ORing with the data signal. The resulting nominally 8 times the transmit clock frequency and is very signal contains both clock and data information and has tolerant of frequency errors. The outputs of the decoder an average duty cycle of 50%, that also allows transformer are data and a strobe that indicates a valid data bit. The coupling. In practice, generating a Manchester encoded data can be deserialized using shift registers as shown. signal with an XOR gate will often produce glitches due The start bit resets the J-K/fl ip-fl op on its way into the to the skew between data and clock transitions. The D fi rst shift register. When it appears at the QH output of fl ip-fl ops in this encoder retime the clock and data such IN the second shift register, it sets the fl ip-fl op that loads the that the respective edges are closely aligned, effectively parallel data into the output register. suppressing glitches. The retimed data and clock are then XORed to produce the Manchester encoded data, which With AC family CMOS logic at 5V the receiver clock fre- is interfaced to telephone wire with an LTC1485 RS485 quency is limited to 20MHz; the corresponding transmitter transceiver. clock frequency is 2.5MHz. If the receiver is implemented in an FPGA that can be clocked at 160MHz, the LTC1864 In order to synchronize to incoming data, the receiver can be clocked at its rated clock frequency of 20MHz. needs a sequence to indicate the start of a data word. The transmitter schematic shows logic that will produce 31 18645fb 20

LTC1864/LTC1865 PACKAGE DESCRIPTION MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) 3.00 ± 0.102 0.889 ± 0.127 (.118 ± .004) 0.52 (.035 ± .005) (NOTE 3) 8 7 6 5 (.206) REF 5.23 (.206) 3.2 – 3.45 4.88 ± 0.1 3.00 ± 0.102 MIN (.126 – .136) 0.254 DETAIL “A” (.192 ± .004) (.118 ± .004) NOTE 4 (.010) 0° – 6° TYP GAUGE PLANE 0.42 ± 0.04 0.65 (.0165 ± .0015) (.0256) 1 2 3 4 TYP BSC 0.53 ± 0.015 RECOMMENDED SOLDER PAD LAYOUT (.021 ± .006) (1.0.1403) (0.0.8364) DETAIL “A” MAX REF 0.18 (.077) SEATING PLANE 0.22 – 0.38 0.13 ± 0.05 (.009 – .015) (.005 ± .002) 0.65 MSOP (MS8) 1001 (.0256) NOTE: BCS 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 18645fb 21

LTC1864/LTC1865 PACKAGE DESCRIPTION MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 3.00 ± 0.102 0.889 ± 0.127 (.118 ± .004) 0.497 ± 0.076 (.035 ± .005) (NOTE 3) (.0196 ± .003) 10 9 8 76 REF 5.23 (.206) 3.2 – 3.45 4.88 ± 0.10 3.00 ± 0.102 MIN (.126 – .136) 0.254 DETAIL “A” (.192 ± .004) (.11N8O ±TE . 0404) (.010) 0° – 6° TYP 0.305 ± 0.038 0.50 GAUGE PLANE (.0120 ± .0015) (.0197) 1 2 3 4 5 TYP BSC 0.53 ± 0.01 RECOMMENDED SOLDER PAD LAYOUT (.021 ± .006) 1.10 0.86 (.043) (.034) DETAIL “A” MAX REF 0.18 (.007) SEATING NOTE: PLANE 0.17 – 0.27 0.13 ± 0.05 1. DIMENSIONS IN MILLIMETER/(INCH) (.007 – .011) (.005 ± .002) 0.50 2. DRAWING NOT TO SCALE (.0197) MSOP (MS) 1001 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. TYP MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 18645fb 22

LTC1864/LTC1865 PACKAGE DESCRIPTION S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.228 – 0.244 0.150 – 0.157** (5.791 – 6.197) (3.810 – 3.988) SO8 1298 1 2 3 4 0.010 – 0.020 × 45°(cid:31) 0.053 – 0.069 (0.254 – 0.508) (1.346 – 1.752) 0.004 – 0.010 0.008 – 0.010 (0.203 – 0.254) 0°– 8° TYP (0.101 – 0.254) 0.016 – 0.050 0.014 – 0.019 0.050 (0.406 – 1.270) (0.355 – 0.483) (1.270) TYP BSC *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 18645fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 23 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1864/LTC1865 TYPICAL APPLICATION Sample Two Channels Simultaneously with a Single Input ADC 4096 Point FFT of Output 0 5V 10 f1 = 7.507324kHz AT 530mVP-P 0.1μF f2 = 45.007324kHz AT 1.7VP-P f1 + 20 fS = 100kHz (0V TO 0.66V) LT11/4292 100Ω 4.R0E9F6V 0.1μF 1μF B) 3400 4.R0E9F6V 5k – 100pF 0.1μF 1μF UDE (d 5600 28.7k 20k 8 1 MPLIT 7800 10k 5pF 2 VCC REFSCK 7 A 90 IN+ 6 100 10k 1μF LTC1864 SDO 110 5k 5V IN– 5 120 3 CONV (0V TO 2Vf2) 0.1μF + 8 0.1μF GND4 1300 5 10 15FRE2Q0UE2N5CY 3(k0Hz3)5 40 45 50 1/2 100Ω 18645 TA03b LT1492 – 4 100pF 18645 TA03a RELATED PARTS PART NUMBER SAMPLE RATE POWER DISSIPATION DESCRIPTION 14-Bit Serial I/O ADCs LTC1417 400ksps 20mW 16-Pin SSOP, Unipolar or Bipolar, Reference, 5V or ±5V LTC1418 200ksps 15mW Serial/Parallel I/O, Internal Reference, 5V or ±5V 16-Bit Serial I/O ADCs LTC1609 200ksps 65mW Confi gurable Bipolar or Unipolar Input Ranges, 5V References LT1460 Micropower Precision Series Reference Bandgap, 130μA Supply Current, 10ppm/°C, Available in SOT-23 LT1790 Micropower Low Dropout Reference 60μA Supply Current, 10ppm/°C, SOT-23 Op Amps LT1468/LT1469 Single/Dual 90MHz, 16-Bit Accurate Op Amps 22V/μs Slew Rate, 75μV/125μV Offset LT1806/LT1807 Single/Dual 325MHz Low Noise Op Amps 140V/μs Slew Rate, 3.5nV/√Hz Noise, –80dBc Distortion LT1809/LT1810 Single/Dual 180MHz Low Distortion Op Amps 350V/μs Slew Rate, –90dBc Distortion at 5MHz 18645fb 24 Linear Technology Corporation LT 1207 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: LTC1865ACMS#TR LTC1864AHMS8#PBF LTC1864AIS8#TRPBF LTC1865IMS#TRPBF LTC1864ACS8#TR LTC1864IMS8#TR LTC1865IS8#TR LTC1865AIMS#TR LTC1865CS8#TR LTC1865AIS8#PBF LTC1864ACMS8#TR LTC1864CMS8#TR LTC1865ACS8#PBF LTC1864IMS8#TRPBF LTC1865ACMS#TRPBF LTC1864CMS8 LTC1865CS8 LTC1865AIMS#TRPBF LTC1864AIMS8#PBF LTC1865IS8#TRPBF LTC1865IS8 LTC1865AIS8#TR LTC1864IMS8 LTC1864AIMS8#TR LTC1864IS8#TR LTC1864ACMS8 LTC1864CS8#TR LTC1864CMS8#TRPBF LTC1865CMS#PBF LTC1864ACMS8#TRPBF LTC1864AIS8 LTC1865CS8#TRPBF LTC1865IMS LTC1865ACS8 LTC1864ACMS8#PBF LTC1864ACS8 LTC1864AIMS8#TRPBF LTC1864IS8 LTC1865AIS8 LTC1865ACS8#TRPBF LTC1865ACMS LTC1865AIS8#TRPBF LTC1864AIS8#PBF LTC1864CS8#TRPBF LTC1865IMS#PBF LTC1864IS8#TRPBF LTC1864ACS8#TRPBF LTC1864ACS8#PBF LTC1865AHMS#PBF LTC1864IS8#PBF LTC1865CMS LTC1865CMS#TR LTC1864CS8#PBF LTC1865AIMS LTC1864AIMS8 LTC1865IMS#TR LTC1865CMS#TRPBF LTC1864CMS8#PBF LTC1865IS8#PBF LTC1864HMS8#PBF LTC1864IMS8#PBF LTC1865CS8#PBF LTC1865AIMS#PBF LTC1865AHMS#TRPBF LTC1864AHMS8#TRPBF LTC1865ACS8#TR LTC1865HMS#PBF LTC1864HMS8#TRPBF LTC1864AIS8#TR LTC1865ACMS#PBF LTC1864CS8 LTC1865HMS#TRPBF