LTC1735-1 High Efficiency Synchronous Step-Down Switching Regulator FEATURES DESCRIPTIOU n Dual N-Channel MOSFET Synchronous Drive The LTC®1735-1 is a synchronous step-down switching n Programmable/Synchronizable Fixed Frequency regulator controller optimized for CPU power. OPTI-LOOP n V Range: 0.8V to 7V compensation allows the transient response to be opti- OUT n Wide V Range: 3.5V to 36V Operation mized over a wide range of output capacitance and ESR IN n Very Low Dropout Operation: 99% Duty Cycle values. n OPTI-LOOPTM Compensation Minimizes C OUT The operating frequency (synchronizable up to 500kHz) is – n 1% Output Voltage Accuracy set by an external capacitor allowing maximum flexibility n Power Good Output Voltage Monitor in optimizing efficiency. The output voltage is monitored n Internal Current Foldback by a power good window comparator that indicates when n Output Overvoltage Crowbar Protection the output is within 7.5% of its programmed value, con- n Latched Short-Circuit Shutdown Timer forming to Intel Mobile CPU Specifications. with Defeat Option n Optional Programmable Soft-Start Protection features include internal foldback current lim- n Remote Output Voltage Sense iting, output overvoltage crowbar and optional short- n Logic Controlled Micropower Shutdown: I < 25m A circuit shutdown. Soft-start is provided by an external Q n Available in 16-Lead Narrow SSOP and SO Packages capacitor that can be used to properly sequence supplies. The operating current level is user-programmable via an APPLICATIOU S external current sense resistor. Wide input supply range allows operation from 3.5V to 30V (36V maximum). n Notebook and Palmtop Computers, PDAs n Power Supply for Mobile Pentium® III Processor with Pin defeatable Burst ModeTM operation provides high SpeedStepTM Technology efficiency at low load currents while 99% duty cycle n Cellular Telephones and Wireless Modems provides low dropout operation. , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode and OPTI-LOOP are trademarks of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation. SpeedStep is a trademark of Intel Corporation. TYPICAL APPLICATIOU VIN PGOOD 4.5V TO 24V CIN CIN: MARCON THCR70E1H226ZT 22µF COUT: PANASONIC EEFUE06181R COSC 47pF 1 16 Q1 50V L1: PANASONIC ETQP6RZ1R20HFA CSS 0.1µF 2 COSC TG 15 CB 0.22µF FDS6680A C· E2RAMIC RSENSE: IRC CRF2010-01-R004J CC2 330pF RC1 33k 3 RITUHN/SLSTC1735-1BOOSSWT 14 1.L21µH 0R.S0E0N4SΩE VOUT CC1 47pF 4 13 D1 1.35V TO 1.60V PGOOD VIN CMDSH-3 12A 47pF 1000pF56 SSEENNSSEE–+ INTVBCGC 1121 + 4.7µF MQB2,R QS3340DT23 47pF R100.15k% + C18O0UµTF 78 VOSENSE PGND 190 F·D2S6680A 47pF R333.2k 4PVANASONIC SP SGND EXTVCC 5V 1% · 4 (OPTIONAL) Q4 10Ω R142.3k 2N7002 VVSSEELL == 10:: VVOOUUTT == 11..6305VV 10Ω 0.5% GND 1735-1 F01 Figure 1. CPU Core DC/DC Converter with Dynamic Voltage Selection from SpeedStep Enabled Processors 1

LTC1735-1 ABSOLUTE WAXIWUW RATIUGS PACKAGE/ORDER IUFORWATIOU (Note 1) Input Supply Voltage (VIN)........................ 36V to –0.3V TOP VIEW ORDER PART Topside Driver Supply Voltage (BOOST)... 42V to –0.3V COSC 1 16 TG NUMBER Switch Voltage (SW) ................................... 36V to –5V RUN/SS 2 15 BOOST LTC1735CGN-1 INTVCC, EXTVCC (BOOST, SW) Voltages..... 7V to –0.3V ITH 3 14 SW SENSE+, SENSE–, PGOOD 4 13 VIN LTC1735CS-1 LTC1735IGN-1 PGOOD Voltages................1.1(INTVCC + 0.3V) to –0.3V SENSE– 5 12 INTVCC I , V , C Voltages .....................2.7V to –0.3V SENSE+ 6 11 BG LTC1735IS-1 TH OSENSE OSC RUN/SS Voltage ....................(INTVCC + 0.3V) to –0.3V VOSENSE 7 10 PGND GN PART Peak Driver Output Current <10m s (TG, BG).............. 3A SGND 8 9 EXTVCC MARKING INTVCC Output Current ......................................... 50mA GN PACKAGE S PACKAGE 16-LEAD PLASTIC SSOP 16-LEAD PLASTIC SO 17351 Operating Ambient Temperature Range LTC1735C-1............................................0(cid:176) C to 85(cid:176) C TTJJMMAAXX == 112255(cid:176)(cid:176)CC,, qq JJAA == 111300(cid:176)(cid:176)CC//WW ((SG)N) 1735I1 LTC1735I-1 ........................................ –40(cid:176) C to 85(cid:176) C Consult factory for Military grade parts. Junction Temperature (Note 2).............................125(cid:176) C Storage Temperature Range................. –65(cid:176) C to 150(cid:176) C Lead Temperature (Soldering, 10 sec)..................300(cid:176) C ELECTRICAL CHARACTERISTICS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25(cid:176) C. V = 15V, V = 5V unless otherwise noted. A IN RUN/SS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loop I Feedback Current (Note 3) –4 –25 nA VOSENSE V Feedback Voltage (Note 3) l 0.792 0.8 0.808 V OSENSE D V Reference Voltage Line Regulation V = 3.6V to 30V (Note 3) 0.001 0.02 %/V LINEREG IN D V Output Voltage Load Regulation (Note 3) LOADREG Measured in Servo Loop; V = 0.7V l 0.1 0.3 % ITH Measured in Servo Loop; V = 2V l –0.1 –0.3 % ITH DF Max Maximum Duty Factor In Dropout 98 99.4 % g Transconductance Amplifier g 1.3 mmho m m V Feedback Overvoltage Lockout l 0.84 0.86 0.88 V OVL I Input DC Supply Current (Note 5) Q Normal Mode 3.6V < V < 30V 450 m A IN Shutdown V = 0V 15 25 m A RUN/SS V Run Pin Start Threshold V , Ramping Positive 1.0 1.5 1.9 V RUN/SS RUN/SS Run Pin Begin Latchoff Threshold V , Ramping Positive 4.1 4.5 V RUN/SS I Soft-Start Charge Current V = 0V –0.7 –1.2 m A RUN/SS RUN/SS I RUN/SS Discharge Current Soft Short Condition, V = 0.5V, 0.5 2 4 m A SCL OSENSE V = 4.5V RUN/SS UVLO Undervoltage Lockout Measured at V Pin (Ramping Negative) l 3.5 3.9 V IN D V Maximum Current Sense Threshold V = 0.7V l 60 75 85 mV SENSE(MAX) OSENSE I SENSE Pins Total Source Current V – = V + = 0V 60 80 m A SENSE SENSE SENSE t Minimum On-Time Tested with a Square Wave (Note 4) 160 200 ns ON(MIN) 2

LTC1735-1 ELECTRICAL CHARACTERISTICS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25(cid:176) C. V = 15V, V = 5V unless otherwise noted. A IN RUN/SS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS TG Transition Time: (Note 7) TG t Rise Time C = 3300pF 50 90 ns r LOAD TG t Fall Time C = 3300pF 50 90 ns f LOAD BG Transition Time: (Note 7) BG t Rise Time C = 3300pF 50 90 ns r LOAD BG t Fall Time C = 3300pF 40 80 ns f LOAD TG/BG T1D Top Gate Off to Synchronous C = 3300pF Each Driver 100 ns LOAD Gate-On Delay Time TG/BG T2D Synchronous Gate Off to Top C = 3300pF Each Driver 70 ns LOAD Gate-On Delay Time Internal V Regulator CC V Internal V Voltage 6V < V < 30V, V = 4V 5.0 5.2 5.4 V INTVCC CC IN EXTVCC V INTV Load Regulation I = 0mA to 20mA, V = 4V 0.2 1 % LDO(INT) CC CC EXTVCC V EXTV Drop Voltage I = 20mA, V = 5V 130 200 mV LDO(EXT) CC CC EXTVCC V EXTV Switchover Voltage I = 20mA, EXTV Ramping Positive l 4.5 4.7 V EXTVCC CC CC CC V EXTV Hysteresis 0.2 V EXTVCC(HYS) CC Oscillator f Oscillator Frequency (Note 6), C = 43pF 265 300 335 kHz OSC OSC f /f Maximum Sync Frequency Ratio 1.3 H OSC PGOOD Pin V PGOOD Threshold for Sync Ramping Negative 0.9 1.2 V PG(SYNC) V PGOOD Threshold for Force Cont. 0.76 0.8 0.84 V PG(FC) V PGOOD Voltage Low I = 2mA 110 200 mV PGL PGOOD I PGOOD Pull-Up Current V = 0.85V –0.17 m A PGOOD PGOOD V PGOOD Trip Level V With Respect to Set Output Voltage PG OSENSE V Ramping Negative –6.0 –7.5 –9.5 % OSENSE V Ramping Positive 6.0 7.5 9.5 % OSENSE Note 1: Absolute Maximum Ratings are those values beyond which the life Note 5: Dynamic supply current is higher due to the gate charge being of the device may be impaired. delivered at the switching frequency. See Applications Information. Note 2: T is calculated from the ambient temperature T and power Note 6: Oscillator frequency is tested by measuring the C charge J A OSC dissipation P according to the following formulas: current (I ) and applying the formula: D OSC LTC1735CS-1, LTC1735IS-1: T = T + (P • 110 (cid:176) C/W) LTC1735CGN-1, LTC1735IGN-1J: TJ A= TA +D (PD • 130(cid:176) C/W) fOSC(kHz)=(cid:230)Ł(cid:231) C8.47(p7(F1)0+81)1(cid:246)ł(cid:247) (cid:230)Ł(cid:231) I 1 +I1 (cid:246)ł(cid:247) –1 Note 3: The LTC1735-1 is tested in a feedback loop that servos V OSC CHG DIS OSENSE to the balance point for the error amplifier (VITH = 1.2V). Note 7: Rise and fall times are measured using 10% to 90% levels. Note 4: The minimum on-time condition corresponds to an inductor Delay times are measured using 50% levels. peak-to-peak ripple current >40% of I (see Minimum On-Time MAX Considerations in the Applications Information section). 3

LTC1735-1 TYPICAL PERFORW AU CE CHARACTERISTICS Efficiency vs Load Current (3 Operating Modes) Efficiency vs Load Current Efficiency vs Input Voltage 100 100 100 EXTVCC OPEN EXTVCC = 5V EXTVCC = 5V 90 VOUT = 1.6V VOUT = 1.6V 90 95 FIGURE 1 80 BURST VIN = 5V %) 70 SYNC %) 80 %) 90 NCY ( 60 CONT NCY ( 70 VIN = 24V VIN = 15V NCY ( 85 IOUT = 5A EFFICIE 50 EFFICIE 60 EFFICIE 80 IOUT = 0.5A 40 VIN = 10V VOUT = 3.3V 50 75 30 RS = 0.01Ω fO = 300kHz 20 40 70 0.001 0.01 0.1 1 10 10mA 100mA 1A 10A 0 5 10 15 20 25 30 LOAD CURRENT (A) LOAD CURRENT (A) INPUT VOLTAGE (V) 1735-1 G01 1735-1 G02 1735-1 G03 V – V Dropout Voltage IN OUT Efficiency vs Input Voltage Load Regulation vs Load Current 100 0 500 EXTVCC OPEN FCB = 0V RSENSE = 0.005Ω VOUT = 1.6V VIN = 15V VOUT = 5V – 5% DROP 95 FIGURE 1 FIGURE 1 400 %)–0.1 EFFICIENCY (%) 889050 IOUT = 0.5A IOUT = 5A RMALIZED V (OUT–0.2 V – V (mV)INOUT 320000 O N–0.3 100 75 70 –0.4 0 0 5 10 15 20 25 30 0 2 4 6 8 10 0 2 4 6 8 10 INPUT VOLTAGE (V) LOAD CURRENT (A) LOAD CURRENT (A) 1735-1 G04 1735-1 G05 1735-1 G06 Input and Shutdown Currents EXTV Switch Drop CC vs Input Voltage INTV Line Regulation vs INTV Load Current CC CC 500 100 6 500 1mA LOAD EXTVCC OPEN 5 400 80 S 400 H µINPUT CURRENT (A)320000 SHUTDOWN 6400 UTDOWN CURRENT (µ INTV VOLTAGE (V)CC 234 EXTV – INTV (mV)CCCC230000 A 100 20 ) 100 1 EXTVCC = 5V 0 0 0 0 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 0 10 20 30 40 50 INPUT VOLTAGE (V) INPUT VOLTAGE (V) INTVCC LOAD CURRENT (mA) 1735-1 G07 1735-1 G08 1735-1 G09 4

LTC1735-1 TYPICAL PERFORW AU CE CHARACTERISTICS Maximum Current Sense Threshold vs Normalized Output Voltage Maximum Current Sense Threshold Maximum Current Sense Threshold (Foldback) vs V vs Sense Common Mode Voltage RUN/SS mV) 80 mV) 80 VSENSE(CM) = 1.6V mV) 80 D ( 70 D ( D ( HOL HOL HOL 76 RES 60 RES 60 RES H H H NSE T 50 NSE T NSE T 72 NT SE 40 NT SE 40 NT SE 68 RE 30 RE RE R R R M CU 20 M CU 20 M CU 64 U U U M 10 M M MAXI 0 MAXI 0 MAXI 60 0 25 50 75 100 0 1 2 3 4 5 6 0 1 2 3 4 5 NORMALIZED OUTPUT VOLTAGE (%) VRUN/SS (V) COMMON MODE VOLTAGE (V) 1735-1 G10 1735-1 G11 1735-1 G12 Maximum Current Sense Voltage Maximum Current Sense Threshold vs I Voltage vs Temperature V vs V TH ITH RUN/SS LTAGE (V) 79680000 SHOLD (mV) 7850 VSENSE(CM) = 1.6V 22..50 VOSENSE = 0.7V O E RENT SENSE V 54320000 NT SENSE THR 70 V (V)ITH 11..05 M CUR 100 CURRE 65 XIMU –10 MUM 0.5 MA –20 XI A –30 M 60 0 0 0.5 1 1.5 2 2.5 –40 –15 10 35 60 85 110 135 0 1 2 3 4 5 6 VITH (V) TEMPERATURE (°C) VRUN/SS (V) 1735-1 G13 1735-1 G18 1735-1 G15 SENSE Pins Total Source Current I Voltage vs Load Current Output Current vs Duty Cycle TH 100 2.5 100 VIN = 10V %) IOUT/IMAX VOUT = 3.3V (X (SYNCHRONIZED) 50 2.0 RfOS =EN 3S0E0 =k H0z.01Ω /IUTMA 80 (FRIOEUET /RIMUANX) O V) T I µI (A)SENSE–500 I VOLTAGE (TH 11..05 CONTINMUOOUDBOSEuPrEsRt AMSToYIOdNeNCHRONIZED f = fO E OUTPUT CURREN 4600 0.5 G 20 A R AVE fSYNC = fO –100 0 0 0 2 4 6 0 1 2 3 4 5 6 0 20 40 60 80 100 VSENSE COMMON MODE VOLTAGE (V) LOAD CURRENT (A) DUTY CYCLE (%) 1735-1 G16 1735-1 G17 1735-1 G14 5

LTC1735-1 TYPICAL PERFORW AU CE CHARACTERISTICS Oscillator Frequency RUN/SS Pin Current PGOOD Pin Current vs Temperature vs Temperature vs Temperature 300 0 0 COSC = 47pF VRUN/SS = 0V VPGOOD = 0.85V 290 –1 –0.2 FREQUENCY (kHz)228700 µUN/SS CURRENT (A) ––23 µOOD PIN CURRENT (A)––00..46 R G 260 –4 P–0.8 250 –5 –1.0 –40 –15 10 35 60 85 110 135 –40 –15 10 35 60 85 110 135 –40 –15 10 35 60 85 110 135 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 1735-1 G19 1735-1 G20 1735-1 G21 V OUT(RIPPLE) Start-Up V (Synchronized) (Burst Mode Operation) OUT(RIPPLE) VOUT ILOAD = 10mA FIGURE 1 ILOAD = 50mA FIGURE 1 1V/DIV VOUT VOUT 10mV/DIV 20mV/DIV VRUN/SS 5V/DIV IL IL 5A/DIV 5A/DIV IL 5A/DIV VIN = 15V 5ms/DIV 1735-1 G22 EXT SYNC f = fO 10m s/DIV 1735-1 G23 VIN = 15V 50m s/DIV 1735-1 G24 VOUT = 1.6V VIN = 15V VOUT = 1.6V RLOAD = 0.16W VOUT = 1.6V V Load Step OUT(RIPPLE) (Burst Mode Operation) (Burst Mode Operation) Load Step (Continuous Mode) ILOAD = 1.5A FIGURE 1 FIGURE 1 FIGURE 1 20mVV/DOUIVT VOUT 50mVV/DOUIVT 50mV/DIV IL IL IL 5A/DIV 5A/DIV 5A/DIV VIN = 15V 5m s/DIV 1735-1 G25 10mA TO 10m s/DIV 1735-1 G26 0A TO 10m s/DIV 1735-1 G27 VOUT = 1.6V 11A LOAD STEP 11A LOAD STEP VIN = 15V PGOOD = 0V VOUT = 1.6V VIN = 15V VOUT = 1.6V 6

LTC1735-1 PIU FUUCTIOUS C (Pin 1): External capacitor C from this pin to SGND (Pin 8): Small-Signal Ground. All small-signal OSC OSC ground sets the operating frequency. components such as C , C , the feedback divider plus OSC SS the loop compensation resistors and capacitor(s) should RUN/SS (Pin 2): Combination of Soft-Start and Run single-point tie to this pin. This pin should, in turn, connect Control Inputs. A capacitor to ground at this pin sets the to PGND. ramp time to full current output. The time is approximately 1.25s/m F. Forcing this pin below 1.5V causes the device to EXTV (Pin 9): Input to the Internal Switch Connected to CC be shut down. In shutdown all functions are disabled. INTV . This switch closes and supplies V power when- CC CC Latchoff overcurrent protection is also invoked via this pin ever EXTV is higher than 4.7V. See EXTV connection CC CC as described in the Applications Information section. in Applications Information section. Do not exceed 7V on this pin and ensure EXTV is £ V . I (Pin 3): Error Amplifier Compensation Point. The CC IN TH current comparator threshold increases with this control PGND (Pin 10): Driver Power Ground. This pin connects voltage. Nominal voltage range for this pin is 0V to 2.4V. to the source of the bottom N-channel MOSFET, the anode of the Schottky diode and the (–) terminal of C . PGOOD (Pin 4): Open-Drain Logic Output and Forced IN Continuous/Synchronization Input. The PGOOD pin is BG (Pin 11): High Current Gate Drive for the Bottom pulled to ground when the voltage on the V pin is N-Channel MOSFET. Voltage swing at this pin is from OSENSE not within – 7.5% of its nominal set point. If power good ground to INTV . CC indication is not needed, this pin can be tied to ground to INTV (Pin 12): Output of the Internal 5.2V Low Dropout CC force continuous synchronous operation. Clocking this Regulator and EXTV Switch. The driver and control CC pin with a signal above 1.5V synchronizes the internal P-P circuits are powered from this voltage. Decouple to power oscillator to the external clock. Synchronization only ground with a 1m F ceramic capacitor placed directly adja- occurs while the main output is in regulation (PGOOD not cent to the IC together with a minimum of 4.7m F tantalum internally pulled low). When synchronized, Burst Mode or other low ESR capacitor. operation is disabled but cycle skipping is allowed at low load currents. This pin requires a pull-up resistor for VIN (Pin 13): Main Supply Pin. This pin must be closely power good indication. Do not connect this pin directly to decoupled to power ground. an external source (or INTV ). Do not exceed INTV on CC CC SW (Pin 14): Switch Node Connection to Inductor and this pin. Bootstrap Capacitor. Voltage swing at this pin is from a SENSE– (Pin 5): The (–) Input to the Current Comparator. Schottky diode (external) voltage drop below ground to V . SENSE+ (Pin 6): The (+) Input to the Current Comparator. IN Built-in offsets between SENSE+ and SENSE– pins in BOOST (Pin 15): Supply to Topside Floating Driver. The conjunction with R set the inductor current trip bootstrap capacitor is returned to this pin. Voltage swing SENSE threshold. at this pin is from a diode drop below INTVCC to VIN + INTV . CC V (Pin 7): Receives the feedback voltage from an OSENSE external resistive divider across the output. TG (Pin 16): High Current Gate Drive for Top N-Channel MOSFET. This is the output of a floating driver with a voltage swing equal to INTV superimposed on the CC switch node voltage SW. 7

LTC1735-1 FUUCTIOUAL DIAGRAW VIN + INTVCC 13 VIN CIN 100k COSC INTVCC 0.8V UVL REF PGOOD 4 COSC 1 SGND 8 0.17µA INTVCC SYNC C – – F FC BOOST DB OSC 15 + 1.2V 0.8V + CB TG FORCE BOT TOP 16 DROP OUT SW – DET BOT SWITCH 14 + 0.74V + OV S Q TOP ON LOGIC D1 L RSENSE 0.86V – R 0.55V + B + VOUT – COUT 2.4V SD 2k 45k 45k VOS7ENSE VFB –EAgm =1.3mΩ ICMP I1– – + + – –I2 IREV BOT 0.8V + + + INTVCC R1 R2 SD 0.86V BURST 3mV VIN 12 + DISABLE FC 5.2V CINTVCC 1.2µA SSRTOAUFRNTT- 4(VFB) A BUFFERED INTVCC LRDEOG + ITH 4.8V + BG 6V CUORVREREN-T SLOPE COMP 30k 30k – 11 LATCHOFF RC PGND RUN/SS 2 3 ITH SENSE+ 6 5 SENSE– EXTVCC 9 10 CSS CC 1735-1 FD OPERATIOU (Refer to Functional Diagram) Main Control Loop: the average inductor current matches the new load cur- rent. While the top MOSFET is off, the bottom MOSFET is The LTC1735-1 uses a constant frequency, current mode turned on until either the inductor current starts to reverse, step-down architecture. During normal operation, the top as indicated by current comparator I , or the beginning of 2 MOSFET is turned on each cycle when the oscillator sets the next cycle. the RS latch, and turned off when the main current comparator I resets the RS latch. The peak inductor The top MOSFET driver is powered from a floating boot- 1 current at which I resets the RS latch is controlled by the strap capacitor C . This capacitor is normally recharged 1 B voltage on Pin I , which is the output of error amplifier from INTV through an external Schottky diode when the TH CC EA. Pin V , described in the Pin Functions, allows EA top MOSFET is turned off. As V decreases towards V , OSENSE IN OUT to receive an output feedback voltage V from the external the converter will attempt to turn on the top MOSFET con- FB resistive divider. When the load current increases, it tinuously (“dropout’’). A dropout counter detects this con- causes a slight decrease in V relative to the 0.8V refer- dition and forces the top MOSFET to turn off for about 500ns FB ence, which in turn causes the I voltage to increase until every tenth cycle to recharge the bootstrap capacitor. TH 8

LTC1735-1 OPERATIOU (Refer to Functional Diagram) The main control loop is shut down by pulling Pin 2 (RUN/ continuous operation and assists in controlling voltage SS) low. Releasing RUN/SS allows an internal 1.2m A regulation. If the output voltage is not within 7.5% of its current source to charge soft-start capacitor C . When nominal value the PGOOD open-drain output will be SS CSS reaches 1.5V, the main control loop is enabled with the pulled low and Burst Mode operation will be disabled. I voltage clamped at approximately 30% of its maximum TH value. As C continues to charge, I is gradually re- Foldback Current, Short-Circuit Detection SS TH leased allowing normal operation to resume. If V has and Short-Circuit Latchoff OUT not reached 70% of its final value when C has charged SS The RUN/SS capacitor, C , is used initially to limit the SS to 4.1V, latchoff can be invoked as described in the inrush current of the switching regulator. After the con- Applications Information section. troller has been started and been given adequate time to The internal oscillator can be synchronized to an external charge up the output capacitors and provide full load clock applied though a series resistor to the PGOOD pin current, C is used as a short-circuit time-out circuit. If SS and can lock to a frequency between 90% and 130% of its the output voltage falls to less than 70% of its nominal nominal rate set by capacitor COSC. output voltage, CSS begins discharging on the assumption that the output is in an overcurrent and/or short-circuit An overvoltage comparator OV guards against transient condition. If the condition lasts for a long enough period overshoots (>7.5%) as well as other more serious as determined by the size of the C , the controller will be SS conditions that may overvoltage the output. In this case, shut down until the RUN/SS pin voltage is recycled. This the top MOSFET is turned off and the bottom MOSFET is built-in latchoff can be overridden by providing a current turned on until the overvoltage condition is cleared. >5m A at a compliance of 5V to the RUN/SS pin. This Foldback current limiting for an output shorted to ground current shortens the soft-start period but also prevents net is provided by amplifier A. As V drops below 0.6V, discharge of C during an overcurrent and/or short- OSENSE SS the buffered I input to the current comparator is gradually circuit condition. Foldback current limiting is activated TH pulled down to a 0.86V clamp. This reduces peak inductor when the output voltage falls below 70% of its nominal current to about 1/4 of its maximum value. level whether or not the short-circuit latchoff circuit is enabled. Low Current Operation INTV /EXTV Power CC CC The LTC1735-1 has three low current modes controlled by the PGOOD pin. Burst Mode operation is selected when Power for the top and bottom MOSFET drivers and most the PGOOD pin is above 0.8V (typically tied through a of the internal circuitry of the LTC1735-1 is derived from resistor to INTVCC). During Burst Mode operation, if the the INTVCC pin. When the EXTVCC pin is left open, an error amplifier drives the I voltage below 0.86V, the internal 5.2V low dropout regulator supplies the INTVCC TH power from V . If EXTV is raised above 4.7V, the buffered I input to the current comparator will be IN CC TH internal regulator is turned off and an internal switch clamped at 0.86V. The inductor current peak is then held connects EXTV to INTV . This allows a high efficiency at approximately 20mV/R (about 1/4 of maximum CC CC SENSE source, such as the primary or a secondary output of the output current). If I then drops below 0.5V, the Burst TH converter itself, to provide the INTV power. Voltages up Mode comparator B will turn off both MOSFETs to maxi- CC to 7V can be applied to EXTV for additional gate drive mize efficiency. The load current will be supplied solely by CC capability. the output capacitor until I rises above the 60mV TH hysteresis of the comparator and switching is resumed. To provide clean start-up and to protect the MOSFETs, Burst Mode operation is disabled by comparator F when undervoltage lockout is used to keep both MOSFETs off the PGOOD pin is brought below 0.8V. This forces until the input voltage is above 3.5V. 9

LTC1735-1 OPERATIOU (Refer to Functional Diagram) POWER GOOD over the widest possible output current range. This con- stant frequency operation is not quite as efficient as Burst A window comparator monitors the output voltage and its Mode operation, but does provide a lower noise, constant open-drain output is pulled low when the divided down frequency operation. When the power good window com- output voltage (appearing at the V pin) is not within OSENSE parator indicates the output is not in regulation, the – 7.5% of the reference voltage of 0.8V. PGOOD pin is pulled to ground and synchronization is During a programmed output voltage transition (i.e., a inhibited. Obviously when driving the PGOOD pin with an transition from 1.55V to 1.3V) the PGOOD open-drain external clock the power good indication is not available output will be pulled low and Burst Mode operation will be unless additional circuitry is added. disabled until the output voltage is within 7.5% of its newly If the PGOOD pin is tied to ground, continuous operation programmed value. is forced. This operation is the least efficient mode, but is When the PGOOD pin is driven by an external oscillator desirable in certain applications. The output can source through a series resistor, cycle-skipping operation is or sink current in this mode. When forcing continuous invoked and the internal oscillator is synchronized to the operation and sinking current, current will be forced back external clock by comparator C. In this mode, the 25% into the main power supply potentially boosting the input minimum inductor current clamp is removed, providing supply to dangerous voltage levels—BEWARE. low noise, constant frequency discontinuous operation APPLICATIOUS IUFORWATIOU The basic LTC1735-1 application circuit is shown in Allowing a margin for variations in the LTC1735-1 and Figure 1 on the first page of this data sheet. External external component values yields: component selection is driven by the load requirement and begins with the selection of RSENSE. Once RSENSE R = 50mV SENSE is known, C and L can be chosen. Next, the power I OSC MAX MOSFETs and D1 are selected. The operating frequency and the inductor are chosen based largely on the desired C Selection for Operating Frequency OSC amount of ripple current. Finally, CIN is selected for its and Synchronization ability to handle the large RMS current into the converter The choice of operating frequency and inductor value is and C is chosen with low enough ESR to meet the OUT a trade-off between efficiency and component size. Low output voltage ripple and transient specifications. The frequency operation improves efficiency by reducing circuit shown in Figure 1 can be configured for operation MOSFET switching losses, both gate charge loss and up to an input voltage of 28V (limited by the external transition loss. However, lower frequency operation MOSFETs). requires more inductance for a given amount of ripple current. R Selection For Output Current SENSE The LTC1735-1 uses a constant frequency architecture R is chosen based on the required output current. SENSE with the frequency determined by an external oscillator The LTC1735-1 current comparator has a maximum capacitor C . Each time the topside MOSFET turns on, threshold of 75mV/R and an input common mode OSC SENSE the voltage on C is reset to ground. During the on-time, range of SGND to 1.1(INTV ). The current comparator OSC CC C is charged by a fixed current. When the voltage on the threshold sets the peak of the inductor current, yielding a OSC capacitor reaches 1.19V, C is reset to ground. The maximum average output current I equal to the peak OSC MAX value less half the peak-to-peak ripple current, D I . process then repeats. L 10

LTC1735-1 APPLICATIOUS IUFORWATIOU The value of C is calculated from the desired operating clamp present in Burst Mode operation is removed, OSC frequency assuming no external clock input on the PGOOD providing constant frequency discontinuous operation pin: over the widest possible output current range. In this mode the synchronous MOSFET is forced on once every Ø 7 ø 1.61(10 ) C (pF)= Œ œ –11 10 clock cycles to recharge the bootstrap capacitor. This OSC ºŒ Frequencyßœ minimizes audible noise while maintaining reasonably high efficiency. A graph for selecting C versus frequency is given in OSC Figure 2. The maximum recommended switching fre- Inductor Value Calculation quency is 550kHz . The operating frequency and inductor selection are inter- The internal oscillator runs at its nominal frequency (f ) related in that higher operating frequencies allow the use O when the PGOOD pin is pulled high (to INTV ) though a of smaller inductor and capacitor values. So why would CC series resistor or connected to ground. Clocking the anyone ever choose to operate at lower frequencies with PGOOD pin above and below 1.2V will cause the internal larger components? The answer is efficiency. A higher oscillator to injection-lock to an external clock signal frequency generally results in lower efficiency because of applied to the PGOOD pin with a frequency between 0.9f MOSFET gate charge losses. In addition to this basic trade O and 1.3f . The clock high level must exceed 1.3V for at off, the effect of inductor value on ripple current and low O least 0.3m s, and the clock low level must be less than 0.3V current operation must also be considered. for at least 0.3m s. The top MOSFET turn-on will synchro- The inductor value has a direct effect on ripple current. The nize with the rising edge of the external clock. inductor ripple current D I decreases with higher induc- L Attempting to synchronize to too high of an external tance or frequency and increases with higher V or V : IN OUT frequency (above 1.3f ) can result in inadequate slope O compensation and possible loop instability at high duty 1 Ø V ø D I = V Œ 1– OUTœ cycles. If this condition exists, simply lower the value of L OUT (f)(L) º V ß IN C so (f = f ) according to Figure 2. OSC EXT O Accepting larger values of D I allows the use of low L 100.0 inductances, but results in higher output voltage ripple 87.5 and greater core losses. A reasonable starting point for setting ripple current is D I = 0.3 to 0.4(I ). Remember, 75.0 L MAX the maximum D I occurs at the maximum input voltage. pF) 62.5 L E ( U The inductor value also has an effect on low current L 50.0 A VSC 37.5 operation. The transition to low current operation begins O C when the inductor current reaches zero while the bottom 25.0 MOSFET is on. Burst Mode operation begins when the 12.5 average inductor current required results in a peak current 0 below 25% of the current limit determined by R . 0 100 200 300 400 500 600 SENSE OPERATING FREQUENCY (kHZ) Lower inductor values (higher D IL) will cause this to occur 1735-1 F02 at higher load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode Figure 2. Timing Capacitor Value operation, lower inductance values will cause the burst When synchronized to an external clock, Burst Mode frequency to decrease. operation is disabled but the inductor current is not allowed to reverse. The 25% minimum inductor current 11

LTC1735-1 APPLICATIOUS IUFORWATIOU Inductor Core Selection Selection criteria for the power MOSFETs include the “ON” resistance R , reverse transfer capacitance C , Once the value for L is known, the type of inductor must be DS(ON) RSS input voltage and maximum output current. When the selected. High efficiency converters generally cannot afford LTC1735-1 is operating in continuous mode the duty the core loss found in low cost powdered iron cores, cycles for the top and bottom MOSFETs are given by: forcing the use of more expensive ferrite, molypermalloy, or Kool Mm ® cores. Actual core loss is independent of core V size for a fixed inductor value, but it is very dependent on MainSwitchDutyCycle= OUT V inductance selected. As inductance increases, core losses IN go down. Unfortunately, increased inductance requires SynchronousSwitchDutyCycle= VIN–VOUT more turns of wire and therefore copper losses will increase. V IN Ferrite designs have very low core loss and are preferred The MOSFET power dissipations at maximum output at high switching frequencies, so design goals can current are given by: concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that P = VOUT (I )2(1+d )R + inductance collapses abruptly when the peak design current MAIN MAX DS(ON) V IN is exceeded. This results in an abrupt increase in inductor ( )2( )( )( ) ripple current and consequent output voltage ripple. Do k V I C f IN MAX RSS not allow the core to saturate! P = VIN –VOUT (I )2(1+d )R SYNC MAX DS(ON) Molypermalloy (from Magnetics, Inc.) is a very good, low V IN loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same where d is the temperature dependency of R and k DS(ON) manufacturer is Kool Mm . Toroids are very space efficient, is a constant inversely related to the gate drive current. especially when you can use several layers of wire. Because Both MOSFETs have I2R losses while the topside they generally lack a bobbin, mounting is more difficult. N-channel equation includes an additional term for transi- However, designs for surface mount are available that do tion losses, which are highest at high input voltages. For not increase the height significantly. V < 20V the high current efficiency generally improves IN Power MOSFET and D1 Selection with larger MOSFETs, while for V > 20V the transition IN losses rapidly increase to the point that the use of a higher Two external power MOSFETs must be selected for use R device with lower C actually provides higher with the LTC1735-1: an N-channel MOSFET for the top DS(ON) RSS efficiency. The synchronous MOSFET losses are greatest (main) switch, and an N-channel MOSFET for the bottom at high input voltage or during a short circuit when the duty (synchronous) switch. cycle in this switch is nearly 100%. The peak-to-peak gate drive levels are set by the INTV CC The term (1 + d ) is generally given for a MOSFET in the voltage. This voltage is typically 5.2V during start-up (see form of a normalized R vs Temperature curve, but EXTV Pin Connection). Consequently, logic-level DS(ON) CC d = 0.005/(cid:176) C can be used as an approximation for low threshold MOSFETs must be used in most LTC1735-1 voltage MOSFETs. C is usually specified in the applications. The only exception is when low input voltage RSS MOSFET characteristics. The constant k = 1.7 can be used is expected (V < 5V); then, sub-logic level threshold IN to estimate the contributions of the two terms in the main MOSFETs (V < 3V) should be used. Pay close GS(TH) switch dissipation equation. attention to the BV specification for the MOSFETs as DSS well; most of the logic level MOSFETs are limited to 30V or The Schottky diode D1 shown in Figure 1 conducts during less. the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom Kool Mm is a registered trademark of Magnetics, Inc. 12

LTC1735-1 APPLICATIOUS IUFORWATIOU MOSFET from turning on and storing charge during the the output ripple will be less than 50mV at max V IN dead-time, which could cost as much as 1% in efficiency. assuming: A 3A Schottky is generally a good size for 10A to 12A regu- C required ESR < 2.2 R OUT SENSE lators due to the relatively small average current. Larger C > 1/(8fR ) diodes result in additional transition losses due to their OUT SENSE larger junction capacitance. The diode may be omitted if the The first condition relates to the ripple current into the ESR efficiency loss can be tolerated. of the output capacitance while the second term guaran- tees that the output voltage does not significantly dis- C Selection IN charge during the operating frequency period due to ripple In continuous mode, the source current of the top current. The choice of using smaller output capacitance N-channel MOSFET is a square wave of duty cycle VOUT / increases the ripple voltage due to the discharging term VIN. To prevent large voltage transients, a low ESR input but can be compensated for by using capacitors of very capacitor sized for the maximum RMS current must be low ESR to maintain the ripple voltage at or below 50mV. used. The maximum RMS capacitor current is given by: The I pin OPTI-LOOP compensation components can be TH optimized to provide stable, high performance transient 1/2 V (cid:230) V (cid:246) I @ I OUT (cid:231) IN –1(cid:247) response regardless of the output capacitors selected. RMS O(MAX) V Ł V ł IN OUT The selection of output capacitors for CPU or other appli- This formula has a maximum at V = 2V , where I cations with large load current transients is primarily de- IN OUT RMS = I /2. This simple worst-case condition is commonly termined by the voltage tolerance specifications of the load. OUT used for design because even significant deviations do not The resistive component of the capacitor, ESR, multiplied offer much relief. Note that capacitor manufacturer’s ripple by the load current change plus any output voltage ripple current ratings are often based on only 2000 hours of life. must be within the voltage tolerance of the load (CPU). This makes it advisable to further derate the capacitor, or The required ESR due to a load current step is: to choose a capacitor rated at a higher temperature than R < D V/D I required. Several capacitors may also be paralleled to ESR meet size or height requirements in the design. Always where D I is the change in current from full load to zero load consult the manufacturer if there is any question. (or minimum load) and D V is the allowed voltage deviation (not including any droop due to finite capacitance). C Selection OUT The amount of capacitance needed is determined by the The selection of COUT is primarily determined by the maximum energy stored in the inductor. The capacitance effective series resistance (ESR) to minimize voltage ripple. must be sufficient to absorb the change in inductor current The output ripple (D VOUT) in continuous mode is deter- when a high current to low current transition occurs. The mined by: opposite load current transition is generally determined by the control loop OPTI-LOOP components, so make sure (cid:230) (cid:246) 1 D VOUT »D IL(cid:231) ESR+ (cid:247) not to over compensate and slow down the response. The Ł 8fCOUTł minimum capacitance to assure the inductors’ energy is adequately absorbed is: where f = operating frequency, C = output capacitance, OUT and D I = ripple current in the inductor. The output ripple ( )2 L L D I is highest at maximum input voltage since D IL increases C > ( ) OUT with input voltage. Typically, once the ESR requirement 2 D V V OUT for C has been met, the RMS current rating generally far eOxUcTeeds the I requirement. With D I = where D I is the change in load current. RIPPLE(P-P) L 0.3I and allowing for 2/3 of the ripple due to ESR, OUT(MAX) 13

LTC1735-1 APPLICATIOUS IUFORWATIOU Manufacturers such as Nichicon, United Chemicon and INTV and PGND IC pins is highly recommended. Good CC Sanyo can be considered for high performance through- bypassing is required to supply the high transient cur- hole capacitors. The OS-CON semiconductor dielectric rents required by the MOSFET gate drivers. capacitor available from Sanyo has the lowest (ESR)(size) Higher input voltage applications in which large MOSFETs product of any aluminum electrolytic at a somewhat are being driven at high frequencies may cause the maxi- higher price. An additional ceramic capacitor in parallel mum junction temperature rating for the LTC1735-1 to be with OS-CON capacitors is recommended to reduce the exceeded. The system supply current is normally domi- inductance effects. nated by the gate charge current. Additional loading of In surface mount applications, multiple capacitors may INTV also needs to be taken into account for the power CC need to be used in parallel to meet the ESR, RMS current dissipation calculations. The total INTV current can be CC handling and load step requirements of the application. supplied by either the 5.2V internal linear regulator or by Aluminum electrolytic, dry tantalum and special polymer the EXTV input pin. When the voltage applied to the CC capacitors are available in surface mount packages. Special EXTV pin is less than 4.7V, all of the INTV current is CC CC polymer surface mount capacitors offer very low ESR but supplied by the internal 5.2V linear regulator. Power have much lower capacitive density per unit volume than dissipation for the IC in this case is highest, (V )(I ), IN INTVCC other capacitor types. These capacitors offer a very cost- and overall efficiency is lowered. The gate charge current effective output capacitor solution and are an ideal choice is dependant on operating frequency as discussed in the when combined with a controller having high loop Efficiency Consideration section. The junction tempera- bandwidth. Tantalum capacitors offer the highest ture can be estimated by using the equations given in Note capacitance density and are often used as output capacitors 2 of the Electrical Characteristics. For example, the for switching regulators having controlled soft-start. LTC1735CS-1 is limited to less than 17mA from a 30V Several excellent surge-tested choices are the AVX TPS, supply when not using the EXTV pin as follows: CC AVX TPSV or the KEMET T510 series of surface mount T = 70(cid:176) C + (17mA)(30V)(110(cid:176) C/W) = 126(cid:176) C J tantalums, available in case heights ranging from 2mm to Use of the EXTV input pin reduces the junction tempera- 4mm. Aluminum electrolytic capacitors can be used in CC ture to: cost-driven applications providing that consideration is given to ripple current ratings, temperature and long-term T = 70(cid:176) C + (17mA)(5V)(110(cid:176) C/W) = 79(cid:176) C J reliability. A typical application will require several to many To prevent maximum junction temperature from being aluminum electrolytic capacitors in parallel. A combination exceeded, the input supply current must be checked of the above mentioned capacitors will often result in operating in continuous mode at maximum V . IN maximizing performance and minimizing overall cost. Other capacitor types include Sanyo OS-CON, Nichicon PL EXTVCC Connection series and Sprague 595D series. Consult manufacturers The LTC1735-1 contains an internal P-channel MOSFET for other specific recommendations. switch connected between the EXTV and INTV pins. CC CC INTVCC Regulator Whenever the EXTVCC pin is above 4.7V the internal 5.2V regulator shuts off, the switch closes and INTV power is CC An internal P-channel low dropout regulator produces the supplied via EXTV until EXTV drops below 4.5V. This CC CC 5.2V supply that powers the drivers and internal circuitry allows the MOSFET gate drive and control power to be within the LTC1735-1. The INTV pin can supply a CC derived from the output or other external source during maximum RMS current of 50mA and must be bypassed normal operation. When the output is out of regulation to ground with a minimum of 4.7m F tantalum, 10m F (start-up, short circuit) power is supplied from the internal special polymer or low ESR type electrolytic capacitor. A regulator. Do not apply greater than 7V to the EXTV pin 1m F ceramic capacitor placed directly adjacent to the CC and ensure that EXTV < V . CC IN 14

LTC1735-1 APPLICATIOUS IUFORWATIOU Significant efficiency gains can be realized by powering VOUT INTV from the output, since the V current resulting CC IN R2 from the driver and control currents will be scaled by a VOSENSE factor of (Duty Cycle)/(Efficiency). For 5V regulators this LTC1735-1 47pF R1 SGND simply means connecting the EXTV pin directly to V . CC OUT However, for dynamic (VID-like) programmed regulators 1735-1 F03 and other lower voltage regulators, additional circuitry is Figure 3. Setting the LTC1735-1 Output Voltage required to derive INTV power from the output. CC The resistive divider is connected to the output as shown The following list summarizes the four possible connec- in Figure 3 allowing remote voltage sensing. tions for EXTV CC: The output voltage can be digitally set to voltages between 1. EXTV Left Open (or Grounded). This will cause INTV CC CC any two levels with the addition of a resistor and small to be powered from the internal 5.2V regulator resulting signal N-channel MOSFET as shown in the circuit of in an efficiency penalty of up to 10% at high input Figure 1. Dynamic output voltage selection can be accom- voltages. plished with this technique. Output voltages of 1.30V and 2. EXTV connected directly to V . This is the normal 1.55V are set by the resistors R1 to R3. With the gate of CC OUT connection for a 5V to 7V output regulator and provides the MOSFET low, (VG = 0), the output voltage is set by the the highest efficiency. For output voltages >5V, EXTVCC ratio of R1 to R2. When the MOSFET is on (VG = high), the is required to connect to V so the SENSE pins output voltage is the ratio of R1 to the parallel combina- OUT absolute maximum ratings are not exceeded. tion of R2 and R3. With the available power good output (PGOOD), the circuit in Figure 1 creates a low cost Intel 3. EXTV Connected to an External Supply (This Option CC Pentium III mobile processor compliant supply. is the Most Likely Used). If an external supply is available in the 5V to 7V range, such as notebook main The LTC1735-1 has remote sense capability. The top of the 5V system power, it may be used to power EXTVCC internal resistive divider is connected to VOSENSE and is providing it is compatible with the MOSFET gate drive referenced to the SGND pin. This allows a kelvin connec- requirements. This is the typical case as the 5V power tion for remotely sensing the output voltage directly across is almost always present and is derived by another high the load, eliminating any PC board trace resistance errors. efficiency regulator. Topside MOSFET Driver Supply (C , D ) B B 4. EXTV Connected to an Output-Derived Boost Net- CC An external bootstrap capacitor C connected to the BOOST B work. For low output voltage regulators, efficiency pin supplies the gate drive voltage for the topside gains can still be realized by connecting EXTV to an CC MOSFET. Capacitor C in the Functional Diagram is charged B output-derived voltage that has been boosted to greater though external diode D from INTV when the SW pin is B CC than 4.7V. This can be done with either the inductive low. Note that the voltage across C is about a diode drop B boost winding or capacitive charge pump circuits. below INTV . When the topside MOSFET is to be turned CC Refer to the LTC1735 data sheet for details. The charge on, the driver places the C voltage across the gate-source B pump has the advantage of simple magnetics. of the MOSFET. This enhances the MOSFET and turns on Output Voltage Programming the topside switch. The switch node voltage SW rises to V and the BOOST pin rises to V + INTV . The value of IN IN CC The output voltage is set by an external resistive divider the boost capacitor C needs to be 100 times greater than B according to the following formula: the total input capacitance of the topside MOSFET. In most (cid:230) R2(cid:246) applications 0.1m F to 0.33m F is adequate. The reverse VOUT =0.8VŁ(cid:231) 1+ R1ł(cid:247) breakdown on DB must be greater than VIN(MAX) . 15

LTC1735-1 APPLICATIOUS IUFORWATIOU When adjusting the gate drive level, the final arbiter is the capacitor C If RUN/SS has been pulled all the way to SS. total input current for the regulator. If you make a change ground there is a delay before starting of approximately: and the input current decreases, then you improved the ( ) 1.5V efficiency. If there is no change in input current, then there T = C = 1.25s/m F C DELAY SS SS is no change in efficiency. 1.2m A SENSE+/SENSE– Pins When the voltage on RUN/SS reaches 1.5V the LTC1735-1 begins operating with a current limit at ap- The common mode input range of the current comparator proximately 25mV/R . As the voltage on RUN/SS SENSE is from 0V to 1.1(INTV ). Continuous linear operation is CC increases from 1.5V to 3V, the internal current limit is guaranteed throughout this range allowing output volt- increased from 25mV/R to 75mV/R . The out- SENSE SENSE ages anywhere from 0.8V to 7V. A differential NPN input put current limit ramps up slowly, taking an additional stage is used and is biased with internal resistors from an 1.25s/m F to reach full current. Ramping the output cur- internal 2.4V source as shown in the Functional Diagram. rent slowly reduces the starting surge current This causes current either to be sourced or sunk by these required from the input supply. pins depending on the output voltage. If the output voltage Diode D1 in Figure 4 and Figure 5 reduces the start delay is below 2.4V, current will flow out of both SENSE pins to while allowing C to charge up slowly for the soft-start the main output. This forces a minimum load current that SS function. This diode and C can be deleted if soft-start is can be fulfilled by the V resistive divider. The maxi- SS OUT not needed. The RUN/SS pin has an internal 6V zener mum current flowing out of the SENSE pins is: clamp (see Functional Diagram). I ++ I –= (2.4V – V )/24k SENSE SENSE OUT 3.3V OR 5V RUN/SS RUN/SS Since V is servoed to the 0.8V reference voltage, we OSENSE D1 can choose R1 in Figure 3 to have a maximum value to absorb this current: CSS CSS (cid:230) 0.8V (cid:246) 1735-1 F04 R1(Max)=24k(cid:231) (cid:247) Ł 2.4V–V ł Figure 4. RUN/SS Pin Interfacing OUT Regulating an output voltage of 1.8V, the maximum value VIN INTVCC 3.3V OR 5V RUN/SS of R1 should be 32k. Note that for output voltages above RSS RSS D1 2.4V no maximum value of R1 is necessary to absorb the RUN/SS D1 sense currents; however, R1 is still bounded by the CSS V feedback current. OSENSE CSS Soft-Start/Run Function The RUN/SS pin is a multipurpose pin that provides a soft- (a) (b) 1735-1 F05 start function and a means to shut down the LTC1735-1. Figure 5. RUN/SS Pin Interfacing with Latchoff Defeated Soft-start reduces surge currents from V by gradually IN increasing the controller’s current limit I . This pin Fault Conditions: Overcurrent Latchoff TH(MAX) can also be used for power supply sequencing. The RUN/SS pin also provides the ability to shut off the Pulling the RUN/SS pin below 1.5V puts the LTC1735-1 controller and latchoff when an overcurrent condition is into a low quiescent current shutdown (I < 25m A). This detected. The RUN/SS capacitor C is used initially to Q SS pin can be driven directly from logic as shown in Figures turn on and limit the inrush current of the controller. After 4 and 5. Releasing the RUN/SS pin allows an internal the controller has been started and given adequate time to 1.2m A current source to charge up the external soft-start charge up the output capacitor and provide full load 16

LTC1735-1 APPLICATIOUS IUFORWATIOU current, C is used as a short-circuit timer. If the output The LTC1735-1 includes current foldback to help further SS voltage falls to less than 70% of its nominal output voltage limit load current when the output is shorted to ground. If after C reaches 4.1V, the assumption is made that the the output falls by more than half, then the maximum SS output is in a severe overcurrent and/or short-circuit sense voltage is progressively lowered from 75mV to condition and C begins discharging. If the condition 30mV. Under short-circuit conditions with very low duty SS lasts for a long enough period as determined by the size of cycles, the LTC1735-1 will begin cycle skipping in order to C , the controller will be shut down until the RUN/SS pin limit the short-circuit current. In this situation the bottom SS voltage is recycled. MOSFET will be conducting the peak current. The short- circuit ripple current is determined by the minimum on- This built-in latchoff can be overridden by providing a time t of the LTC1735-1 (less than 200ns), the current >5m A at a compliance of 5V to the RUN/SS pin as ON(MIN) input voltage, and inductor value: shown in Figure 5a. This current shortens the soft-start period but also prevents net discharge of the RUN/SS D I = t (V /L) L(SC) ON(MIN) IN capacitor during a severe overcurrent and/or short-circuit The resulting short circuit-current is: conditions. When deriving the 5m A current from V as in IN Figure 5a, current latchoff is always defeated. The diode 30mV 1 I = + D I connecting this pull-up resistor to INTV , as in Figure 5b, SC L(SC) CC R 2 SENSE eliminates any extra supply current during shutdown The current foldback function is always active and is not while eliminating the INTV loading from preventing CC effected by the current latchoff function. controller start-up. If the voltage on C does not exceed SS 4.1V, the overcurrent latch is not armed and the function Fault Conditions: Output Overvoltage Protection is disabled. (Crowbar) Why should you defeat current latchoff? During the The output overvoltage crowbar is designed to blow a prototyping stage of a design, there may be a problem with system fuse in the input lead when the output of the noise pickup or poor layout causing the protection circuit regulator rises much higher than nominal levels. This to latch off. Defeating this feature will easily allow trouble- condition causes huge currents to flow, much greater than shooting of the circuit and PC layout. The internal short in normal operation. This feature is designed to protect circuit and foldback current limiting still remains active, against a shorted top MOSFET; it does not protect against thereby protecting the power supply system from failure. a failure of the controller itself. After the design is complete, a decision can be made whether to enable the latchoff feature. The comparator (OV in the Functional Diagram) detects overvoltage faults greater than 7.5% above the nominal The value of the soft-start capacitor C will need to be SS output voltage. When this condition is sensed the top scaled with output current, output capacitance and load MOSFET is turned off and the bottom MOSFET is forced current characteristics. The minimum soft-start capaci- on. The bottom MOSFET remains on continuously for as tance is given by: long as the OV condition persists; if V returns to a safe OUT C > (C )(V ) (10–4) (R ) level, normal operation automatically resumes. Note that SS OUT OUT SENSE dynamically changing the output voltage may cause over- The minimum recommended soft-start capacitor of voltage protection to be momentarily activated during C = 0.1m F will be sufficient for most applications. SS output voltage decreases. This will not cause permanent latchoff nor will it disrupt the desired voltage change. Fault Conditions: Current Limit and Current Foldback With soft-latch overvoltage protection, dynamically chang- The LTC1735-1 current comparator has a maximum sense ing the output voltage is allowed and the overvoltage voltage of 75mV resulting in a maximum MOSFET current protection tracks the newly programmed output voltage, of 75mV/R . SENSE always protecting the load (CPU). 17

LTC1735-1 APPLICATIOUS IUFORWATIOU Minimum On-Time Considerations PGOOD Pin Operation Minimum on-time t is the smallest amount of time The PGOOD pin is a multifunction pin intended primarily to ON(MIN) that the LTC1735-1 is capable of turning the top MOSFET indicate when the output voltage is within – 7.5% of its on and off again. It is determined by internal timing delays nominal set point. A window comparator monitors the and the gate charge required to turn on the top MOSFET. V pin and activates an open-drain internal MOSFET OSENSE Low duty cycle applications may approach this minimum that pulls down the PGOOD pin when the output voltage is on-time limit and care should be taken to ensure that: out of regulation. Normally a 10k to 100k pull-up resistor is connected to this pin from a voltage source such as t < VOUT INTVCC. Do not apply a voltage greater than INTVCC to this ON(MIN) V (f) pin. Dynamically changing the output voltage between two IN voltage levels greater that 7.5% apart from each other will If the duty cycle falls below what can be accommodated by invoke the power good indication, causing the PGOOD the minimum on-time, the LTC1735-1 will begin to skip output to go low until the new output voltage is reached. cycles. The output voltage will continue to be regulated, When the DC voltage on the PGOOD pin drops below its but the ripple voltage and current will increase. 0.8V threshold, continuous mode operation is forced. In The minimum on-time for the LTC1735-1 in a properly this case, the top and bottom MOSFETs continue to be configured application is less than 200ns. However, as the driven synchronously regardless of the load on the main peak sense voltage decreases, the minimum on-time output. Burst Mode operation is disabled and current gradually increases as shown in Figure 6. This is of reversal is allowed in the inductor. This mode is forced particular concern in forced continuous applications with whenever the output voltage is not within its 7.5% low ripple current at light loads. If the duty cycle drops window. below the minimum on-time limit in this situation, a In addition to providing a power good output, the PGOOD significant amount of cycle skipping can occur with corre- pin provides a logic input to force continuous synchro- spondingly larger current and voltage ripple. nous operation and allow synchronization to an external If an application can operate close to the minimum on- clock. time limit, an inductor must be chosen that is low enough The internal LTC1735-1 oscillator can be synchronized to to provide sufficient ripple amplitude to meet the mini- an external oscillator by applying a clock signal to the mum on-time requirement. As a general rule keep the PGOOD pin though a series resistor with a signal ampli- inductor ripple current equal or greater than 30% of tude above 1.5V . When synchronized to an external I at V . P-P OUT(MAX) IN(MAX) frequency, Burst Mode operation is disabled but cycle 250 skipping is allowed at low load currents since current reversal is inhibited. The bottom gate will come on every 200 10 clock cycles to assure the bootstrap capacitor is kept s) n E ( refreshed. The rising edge of an external clock applied to M 150 TI the PGOOD pin starts a new cycle. If the output voltage is N- M O not within the 7.5% window around its nominal set point, U 100 M the open-drain PGOOD output will pull low, disabling the NI MI external synchronization. 50 The following table summarizes the possible states avail- 0 able on the PGOOD pin. 0 10 20 30 40 ∆IL/IOUT(MAX) (%) 1736-1 F06 Figure 6. Minimum On-Time vs D I L 18

LTC1735-1 APPLICATIOUS IUFORWATIOU Table 1 and control currents. VIN current results in a small (<0.1%) loss that increases with V . PGOOD PIN CONDITION IN DC Voltage: 0V to 0.7V No Power Good Indication 2. INTV current is the sum of the MOSFET driver and CC Burst Mode Operation Disabled/Forced control currents. The MOSFET driver current results Continuous Current Reversal Enabled from switching the gate capacitance of the power Resistor Pull-Up to Power Good Indication INTVCC (or Other DC Burst Mode, No Current Reversal MOSFETs. Each time a MOSFET gate is switched from Voltage Less Than INTV ) When Power is Good CC low to high to low again, a packet of charge dQ moves Resistor to Ext Clock: No Power Good Indication from INTV to ground. The resulting dQ/dt is a current (0V to 1.5V) Burst Mode Operation Disabled CC No Current Reversal out of INTV that is typically much larger than the CC control circuit current. In continuous mode, I = GATECHG The circuit shown in Figure 7 provides a power good f(Q + Q ), where Q and Q are the gate charges of the T B T B output and forces continuous operation. Transistor Q1 topside and bottom-side MOSFETs. keeps the voltage at the PGOOD pin below 0.8V thus By powering EXTV from an output-derived source (or disabling Burst Mode operation. When the window com- CC other high efficiency source), the additional V current parator indicates the output voltage is not within its 7.5% IN resulting from the driver and control currents will be window, the base of Q1 is pulled to ground and the power scaled by a factor of (Duty Cycle)/(Efficiency). For good output appearing at the collector of Q2 goes low. example, in a 15V to 1.8V application, 10mA of INTV CC INTVCC current results in approximately 1.2mA of VIN current. This reduces the midcurrent loss from 10% or more (if 470k 100k 10k POWER the driver was powered directly from V ) to only a few IN GOOD percent. PGOOD Q2 PIN 4 Q1 3. I2R losses are predicted from the DC resistances of the 1735-1 F07 MOSFETs, inductor and current shunt. In continuous Figure 7. Forced Continuous Operation with Power Good Indication mode, the average output current flows through L and R , but is “chopped” between the topside main Efficiency Considerations SENSE MOSFET and the synchronous MOSFET. If the two The percent efficiency of a switching regulator is equal to MOSFETs have approximately the same R , then DS(ON) the output power divided by the input power times 100%. the resistance of one MOSFET can simply be summed It is often useful to analyze individual losses to determine with the resistances of L and R to obtain I2R SENSE what is limiting the efficiency and which change would losses. For example, if each R = 0.02W , R = DS(ON) L produce the most improvement. Percent efficiency can be 0.03W , and R = 0.01W , then the total resistance is SENSE expressed as: 0.06W . This results in losses ranging from 3% to 17% as the output current increases from 1A to 5A for a 1.8V %Efficiency = 100% – (L1 + L2 + L3 + ...) output, or 4% to 20% for a 1.5V output. Efficiency where L1, L2, etc., are the individual losses as a percent- varies as the inverse square of V for the same OUT age of input power. external components and power level. I2R losses cause Although all dissipative elements in the circuit produce the efficiency to drop at high output currents. losses, four main sources usually account for most of the 4. Transition losses apply only to the topside MOSFET(s), losses in LTC1735-1 circuits: 1) LTC1735-1 VIN current, and only become significant when operating at high 2) INTVCC current, 3) I2R losses, 4) Topside MOSFET input voltages (typically 12V or greater). Transition transition losses. losses can be estimated from: 1. The VIN current is the DC supply current given in the Transition Loss = (1.7) VIN2 IO(MAX) CRSS f electrical characteristics which excludes MOSFET driver 19

LTC1735-1 APPLICATIOUS IUFORWATIOU Other “hidden” losses such as copper trace and internal determined. The output capacitors need to be decided battery resistances can account for an additional 5% to upon because the various types and values determine the 10% efficiency degradation in portable systems. It is very loop feedback factor gain and phase. An output current important to include these “system” level losses in the pulse of 20% to 100% of full load current having a rise time design of a system. The internal battery and fuse resistance of 1m s to 10m s will produce output voltage and I pin TH losses can be minimized by making sure that C has waveforms that will give a sense of the overall loop IN adequate charge storage and a very low ESR at the stability without breaking the feedback loop. The initial switching frequency. A 25W supply will typically require output voltage step may not be within the bandwidth of the a minimum of 20m F to 40m F of capacitance having a feedback loop, so the standard second order overshoot/ maximum of 0.01W to 0.02W of ESR. Other losses DC ratio cannot be used to determine phase margin. The including Schottky conduction losses during dead-time gain of the loop will be increased by increasing R and the C and inductor core losses generally account for less than bandwidth of the loop will be increased by decreasing C . C 2% total additional loss. If R is increased by the same factor that C is decreased, C C the zero frequency will be kept the same, thereby keeping Checking Transient Response the phase shift the same in the most critical frequency The regulator loop response can be checked by looking at range of the feedback loop. The output voltage settling the load current transient response. Switching regulators behavior is related to the stability of the closed-loop take several cycles to respond to a step in DC (resistive) system and will demonstrate the actual overall supply load current. When a load step occurs, V shifts by an performance. For a detailed explanation of optimizing the OUT amount equal to D I (ESR), where ESR is the effective compensation components, including a review of control LOAD series resistance of C . D I also begins to charge or loop theory, refer to Application Note 76. OUT LOAD discharge C generating the feedback error signal that OUT Improve Transient Response and Reduce Output forces the regulator to adapt to the current change and Capacitance with Active Voltage Positioning return V to its steady-state value. During this recovery OUT time V can be monitored for excessive overshoot or Fast load transient response, limited board space and low OUT ringing, which would indicate a stability problem. cost are normal requirements of microprocessor power OPTI-LOOP compensation allows the transient response supplies. Active voltage positioning improves transient to be optimized over a wide range of output capacitance response and reduces the output capacitance required to and ESR values. The availability of the I pin not only power a microprocessor where a typical load step can be TH allows optimization of control loop behavior but also from 0.2A to 15A in 100ns or 15A to 0.2A in 100ns. The provides a DC coupled and AC filtered closed-loop response voltage at the microprocessor must be held to about test point. The DC step, rise time and settling at this test – 0.1V of nominal in spite of these load current steps. point truly reflects the closed loop response. Assuming a Since the control loop cannot respond this fast, the output predominantly second order system, phase margin and/or capacitors must supply the load current until the control damping factor can be estimated using the percentage of loop can respond. Capacitor ESR and ESL primarily deter- overshoot seen at this pin. The bandwidth can also be mine the amount of droop or overshoot in the output estimated by examining the rise time at the pin. The I voltage. Normally, several capacitors in parallel are re- TH external components shown in the Figure 1 circuit will quired to meet microprocessor transient requirements. provide an adequate starting point for most applications. Active voltage positioning is a form of deregulation. It The I series R -C filter sets the dominant pole-zero sets the output voltage high for light loads and low for TH C C loop compensation. The values can be modified slightly heavy loads. When load current suddenly increases, the (from 0.5 to 2 times their suggested values) to optimize output voltage starts from a level higher than nominal so transient response once the final PC layout is done and the the output voltage can droop more and stay within the particular output capacitor type and value have been specified voltage range. When load current suddenly 20

LTC1735-1 APPLICATIOUS IUFORWATIOU decreases the output voltage starts at a level lower than accuracy is – 1%. Using 1% tolerance resistors, the total nominal so the output voltage can have more overshoot feedback divider accuracy is about 1% because both and stay within the specified voltage range. Less output feedback resistors are close to the same value. The result- capacitance is required when voltage positioning is used ing setpoint accuracy is – 2% so the output transient because more voltage variation is allowed on the output voltage cannot exceed – 0.082V. For V = 1.5V, the OUT capacitors. maximum output voltage change controlled by the I pin TH would be: Active voltage positioning can be implemented using the OPTI-LOOP architecture of the LTC1735-1 and two resis- InputOffsetVoltage•V tors connected to the ITH pin. An input voltage offset is D VOSENSE= OUT introduced when the error amplifier has to drive a resistive VREF load. This offset voltage is limited to – 30mV at the input – 0.03V•1.5 = = – 56mV of the error amplifier. The resulting change in output 0.8V voltage is the product of input offset voltage and the feedback voltage divider ratio. With optimum resistor values at the I pin, the output TH voltage will swing from 1.55V at minimum load to 1.44V Figure 8 shows a CPU-core-voltage regulator with active at full load. At this output voltage, active voltage position- voltage positioning. Resistors R1 and R5 force the input ing provides an additional – 56mV to the allowable tran- voltage offset that adjusts the output voltage according to sient voltage on the output capacitors, a 68% improvement the load current level. To select values for R1 and R5, first over the – 82mV allowed without active voltage determine the amount of output deregulation allowed. The positioning. actual specification for a typical microprocessor allows the output to vary – 0.112V. The LTC1735-1 reference R3 680k VIN 7.5V TO R4 100k C7 C12 TO C14 24V R1 PGOOD 0.1µF 1305µVF 27k R5 100k GND C9, C19: TAIYO YUDEN JMK107BJ105 C1 C10: KEMET T494A475M010AS 39pF 1 16 Q1 C12 TO C14: TAIYO YUDEN GMK325F106 C2 COSC TG FDS6680A CD115: CTEON CT1R8A:L P SAENMASI COMNIDCS EHE-F3UE0G181R 0.1µF D2: MOTOROLA MBRS340 2 15 RUN/SS BOOST L1: PANASONIC ETQP6F1R0SA C3 C8 Q1 TO Q3: FAIRCHILD FDS6680A R2 100pF 0.22µF R5: IRC LRF2512-01-R003-J 100k 3 14 U1: LINEAR TECHNOLOGY LTC1735CS-1 C4 ITH U1 SW 100pF LTC1735-1 L1 R6 4 PGOOD VIN 13 DCM1DSH-3 1µH 0.003Ω V1.O5UVT C11 15A C5 5 SENSE– INTVCC 12 MBRS3D402 330Rp7F C1µ19F 4C76pF 1000pF 67 SENSE+ BG 1110 C1µ9F + 1C4.017V0µF QF· D22S, Q66380A 111.R05k8k + CC148V11058µ TFO VOSENSE PGND GND 8 9 SGND EXTVCC 5V (OPTIONAL) 1735-1 F08 Figure 8. CPU-Core-Voltage Regulator with Active Voltage Positioning 21

LTC1735-1 APPLICATIOUS IUFORWATIOU The next step is to calculate the I pin voltage, V , scale V from 0.40V at light load to 1.77V at full load, a 1.37V TH ITH ITH factor. The V scale factor reflects the I pin voltage change. During Burst Mode operation, the LTC1735-1 ITH TH required for a given load current in continuous inductor output voltage is controlled by a comparator, not the error current operation. V controls the peak sense resistor amplifier. Even though the error amplifier is not used in ITH voltage, which represents the DC output current plus one Burst Mode operation, it is necessary to assume linear half of the peak-to-peak inductor current. The no load to operation for all error amplifier gain calculations. full load V range is from 0.3V to 2.4V, which controls ITH To create the – 30mV input offset error, the voltage gain of the sense resistor voltage from 0V to the D V SENSE(MAX) the error amplifier must be limited. The desired gain is: voltage of 75mV. For the circuit shown in Figure 8, the calculated VITH scale factor is: D V 1.37V A = ITH = =22.8 V InputOffsetError 2(0.03V) V Range•SenseResistor Value V ScaleFactor = ITH ITH D V Connecting a resistor to the output of the transconductance SENSE(MAX) error amplifier will limit the voltage gain. The value of this (2.4V–0.3V)•0.003 = =0.084V/A resistor is: 0.075V A 22.8 Assuming continuous inductor current, V is: R = V = =17.54k ITH ITH Error Amplifierg 1.3ms m VITH = غŒ (cid:230)Ł(cid:231) IOUTDC+ D 2IL(cid:246)ł(cid:247) •VITHScaleFactorøßœ Tceon tceernetde rs ot hthea to nuotp Iut pvionl tcaugrer evnat rfilaotwiosn w, hVeITnH t hme uosutt pbuet TH +V Offset voltage is nominal. VITH(NOM) is the average voltage be- ITH tween V at maximum output current and minimum ITH At full load current: output current: Ø (cid:230) (cid:246) ø V –V VITH(MAX) = ºŒŒ Ł(cid:231) 15A+ 5A2P- Pł(cid:247) •0.084V/Aßœœ +0.3V VITH(NOM) = ITH(MAX)2 ITH(MIN) +VITH(MIN) 1.77V–0.40V =1.77V = +0.40V=1.085V 2 At minimum load current: The Thevenin equivalent of the gain limiting resistance value of 17.54k is made up of a resistor R5 that sources Ø (cid:230) (cid:246) ø VITH(MIN) = Œ (cid:231) 0.2A+ 2AP- P(cid:247) •0.084V/Aœ +0.3V current into the ITH pin and resistor R1 that sinks current ºŒ Ł 2 ł ßœ to SGND. =0.40V To calculate the resistor values, first determine the ratio between them: Notice that D I , the peak-to-peak inductor current, changes L from light load to full load. Increasing the DC inductor V –V 5.2V–1.085V current decreases the permeability of the inductor core k = INTVCC ITH(NOM) = =3.79 V 1.085V material, which decreases the inductance and increases ITH(NOM) D I . The amount of inductance change is a function of the L V is equal to V or 5.2V if EXTV is not used. INTVCC EXTVCC CC inductor design. Resistor R5 is: If the circuit shown in Figure 8 sustained continuous in- ductor current operation, the error amplifier would control R5=(k+1)•R =(3.79+1)•17.54k =84.0k ITH 22

LTC1735-1 APPLICATIOUS IUFORWATIOU Resistor R1 is: Automotive Considerations: Plugging Into the Cigarette Lighter (k+1)•R (3.79+1)•17.54k R1= ITH = =22.17k As battery-powered devices go mobile, there is a natural k 3.79 interest in plugging into the cigarette lighter in order to Unfortunately, PCB noise can add to the voltage developed conserve or even recharge battery packs during operation. across the sense resistor, R6, causing the ITH pin voltage But before you connect, be advised: you are plugging into to be slightly higher than calculated for a given output the supply from hell. The main power line in an auto is the current. The amount of noise is proportional to the output source of a number of nasty potential transients, including current level. This PCB noise does not present a serious load dump, reverse battery and double battery. problem but it does change the effective value of R6 so the Load dump is the result of a loose battery cable. When the calculated values of R1 and R5 may need to be adjusted to cable breaks connection, the field collapse in the alternator achieve the required results. Since PCB noise is a function can cause a positive spike as high as 60V which takes of the layout, it will be the same on all boards with the same several hundred milliseconds to decay. Reverse battery is layout. just what it says, while double battery is a consequence of Figures 9 and 10 show the transient response before and tow-truck operators finding that a 24V jump start cranks after active voltage positioning is implemented. Notice cold engines faster than 12V. that active voltage positioning reduced the transient re- sponse from almost 200mV to a little over 100mV . The network shown in Figure 11 is the most straight P-P P-P forward approach to protect a DC/DC converter from the Refer to Design Solutions 10 for more information about ravages of an automotive power line. The series diode active voltage positioning. prevents current from flowing during reverse battery, while the transient suppressor clamps the input voltage VIN = 12V FIGURE 8 CIRCUIT VOUT = 1.5V during load dump. Note that the transient suppressor 1.582V should not conduct during double-battery operation, but 100mV/DIV 1.50V OUTPUT VOLTAGE must still clamp the input voltage below breakdown of the 1.418V converter. Although the LTC1735-1 has a maximum input 15A voltage of 36V, most applications will be limited to 30V by LOAD CURRENT the MOSFET BV . DSS 0.2A 5A/DIV 0A 50A IPK RATING 50m s/DIV 1735-1 F09 VIN 12V Figure 9. Transient Response Without Active Voltage Positioning LTC1735-1 TRANSIENT VOLTAGE VIN = 12V FIGURE 8 CIRCUIT SUPPRESSOR VOUT = 1.5V GENERAL INSTRUMENT 1.5KA24A 1.582V OUTPUT 100mV/DIV 1.50V VOLTAGE 1.418V 1735-1 F11 15A LOAD Figure 11. Plugging Into the Cigarette Lighter CURRENT 0.2A 5A/DIV 0A 50m s/DIV 1735-1 F10 Figure 10. Transient Response with Active Voltage Positioning 23

LTC1735-1 APPLICATIOUS IUFORWATIOU Design Example P = 22V–1.5V(12A)2(1.1)(0.0065W ) SYNC As a design example, assume V = 12V (nominal), V = 22V IN IN 22V (max), V = 1.5V, I = 12A and f = 300kHz, =959mW OUT MAX R and C can immediately be calculated: SENSE OSC Thanks to current foldback, the bottom MOSFET dissipa- R = 50mV/12A = 0.042W tion in short circuit will be less than under full-load SENSE conditions. C = 1.61(107)/(300kHz) – 11pF = 43pF OSC C is chosen for an RMS current rating of at least 6A at Assume a 1.2m H inductor and check the actual value of the IN temperature. C is chosen with an ESR of 0.01W for low ripple current. The following equation is used : OUT output ripple. The output ripple in continuous mode will be V (cid:230) V (cid:246) highest at the maximum input voltage. The output voltage D I = OUT (cid:231) 1– OUT(cid:247) ripple due to ESR is approximately: L (f)(L)Ł V ł IN V = R (D I ) = 0.01W (3.9A) = 39mV ORIPPLE ESR L P-P The highest value of the ripple current occurs at the Since the output voltage is below 2.4V, the output resistive maximum input and output voltages: divider will need to be sized to not only set the output voltage but also to absorb the SENSE pins specified input 1.5V (cid:230) 1.5V(cid:246) D I = (cid:231) 1– (cid:247) =3.9A current. L 300kHz(1.2m H)Ł 22Vł (cid:230) (cid:246) 0.8V The maximum ripple current is 32% of maximum output R1(MAX)=24k(cid:231) (cid:247) =21.3k Ł 2.4V–1.5Vł current, which is about right. Next, verify the minimum on-time of 200ns is not violated. Choosing 1% resistors: R1 = 21k and R2 = 18.7k yields an The minimum on-time occurs at maximum V and mini- output voltage of 1.512V. IN mum V . OUT PC Board Layout Checklist V 1.5V t = OUT = =227ns ON(MIN) When laying out the printed circuit board, the following V f 22V(300kHz) IN(MAX) checklist should be used to ensure proper operation of the The power dissipation on the topside MOSFET can be LTC1735-1. These items are also illustrated graphically in easily estimated. Choosing a Fairchild FDS6612A results the layout diagram of Figure 12. Check the following in in; R = 0.03W , C = 80pF. At maximum input your layout: DS(ON) RSS voltage with T(estimated) = 50(cid:176) C: 1. Are the signal and power grounds segregated? The LTC1735-1 PGND pin should tie to the ground plane P = 1.5V(12)2[1+(0.005)(50(cid:176) C–25(cid:176) C)](0.03W ) close to the input capacitor(s). The SGND pin should MAIN 22V then connect to PGND and all components that connect +1.7(22V)2(12A)(80pF)(300kHz) to SGND should make a single-point tie to the SGND pin. The synchronous MOSFET source should connect =568mW to the input capacitor(s) ground. Because the duty cycle of the bottom MOSFET is much 2. Does the V pin connect directly to the feedback OSENSE greater than the top, two larger MOSFETs must be paral- resistors? The resistive divider R1, R2 must be con- leled. Choosing Fairchild FDS6680A MOSFETs yields a nected between the (+) plate of C and signal ground. OUT parallel RDS(ON) of 0.0065W . The total power dissipation The 47pF capacitor from VOSENSE to SGND should be for both bottom MOSFETs, again assuming T = 50(cid:176) C, is: as close as possible to the LTC1735-1. Be careful locating the feedback resistors too far away from the 24

LTC1735-1 APPLICATIOUS IUFORWATIOU LTC1735-1. The V line should not be routed 5. Is the INTV decoupling capacitor connected closely OSENSE CC close to any other nodes with high slew rates. betweenINTV and the power ground pin? This capaci- CC tor carries the MOSFET driver peak currents. An addi- 3. Are the SENSE+ and SENSE– leads routed together with tional 1m F ceramic placed immediately next to the INTV minimum PC trace spacing? The filter capacitor be- CC and PGND pins can help improve noise performance. tween SENSE+ and SENSE– should be as close as possible to the LTC1735-1. Ensure accurate current 6. Keep the switching node (SW), Top Gate node (TG), and sensing with kelvin connections to the SENSE resistors Boost node (BOOST) away from sensitive small-signal shown in Figure 13. Series resistance can be added to nodes, especially from the voltage and current sensing the SENSE lines to increase noise rejection. feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the 4. Does the (+) terminal of C connect to the drain of the IN “output side” (Pins 9 to 16) of the LTC1735-1 and topside MOSFET(s) as closely as possible? This capaci- occupy minimum PC trace area. tor provides the AC current to the MOSFET(s). INTVCC + COSC 1 16 COSC TG Q1 CSS 2 15 RUN/SS BOOST RC CC 3 ITH LTC1735-1 SW 14 + CIN CC2 4 PGOOD VIN 13 DB CB VIN 5 SENSE– INTVCC 12 D1 1000pF 6 SENSE+ BG 11 + 4.7µF 7 10 VOSENSE PGND 47pF 8 9 SGND EXTVCC Q2 – L1 – R1 COUT VOUT + R2 RSENSE + 1735-1 F12 Figure 12. LTC1735-1 Layout Diagram HIGH CURRENT PATH 1735-1 F13 CURRENT SENSE RESISTOR SENSE+ SENSE– (RSENSE) Figure 13. Kelvin Sensing R SENSE 25

LTC1735-1 TYPICAL APPLICATIONUS 1.8V/5A Converter with Power Good INTVCC 4.5V VTION 22V COSC 100k CIN 43pF 22µF 1 16 Q1 50V CSS COSC TG CB Si4412DY CER 0.1µF 0.1µF 2 15 RUN/SS BOOST RC 47C0CpF 33k 3 14 ITH SW CC2 220pF POGWOOERD 4 PGOOLDTC1735-1 VIN 13 DCMBDSH-3 3.L31µH R0S.0E1NΩSE V1.O8UVT R2 5A 5 12 SENSE– INTVCC + 312%.4k + C15O0UµTF 1000pF 4.7µF 6.3V 6 SENSE+ BG 11 Q2 R1 · 2 Si4410DY 25.5k PANASONIC SP 47pF MBRS140T3 1% 7 10 VOSENSE PGND SGND 8 9 OPTIONAL: SGND EXTVCC CONNECT TO 5V COUT: PANASONIC EEFUEOG151R CIN: MARCON THCR70LE1H226ZT L1: PANASONIC ETQP6F3R3HFA RSENSE: IRC LR 2010-01-R010F 1735-1 TA02 CPU Core Voltage Regulator for 2-Step Applications (V = 5V) with Burst Mode Operation Disabled IN VIN 5V 100k* CIN COSC 39pF 150µF 1 16 Q1 6.3V CSS COSC TG CB FDS6680A · 2 0.1µF 0.22µF 2 15 INTVCC RC 22C0CpF RUN/SS BOOST 20k 3 14 POWER 10k 100k CC2 ITH SW GOOD Q5 470k 220pF 4 PGOOLDTC1735-1 VIN 13 DMBBR0530 0.7L81µH 0R.S0E0N4SΩE 1V.O5UVT Q4 12A 5 12 R2 1000pF SENSE– INTVCC + 4.7µF 100pF 312%.4k + C18O0UµTF 4C7OµF 6 SENSE+ BG 11 QFD2S, Q66380A R1 4· V3 10V 47pF 1µF · 2 215%.5k 7 10 MBRD835L VOSENSE PGND SGND 8 SGND EXTVCC 9 V5VIN CCOINU: TP: APNAANSAOSNOINCI CE EEFEUFEUOEJO1G5118R1R CO: TAIYO YUDEN LMK550BJ476MM-B L1: COILCRAFT 1705022P-781HC Q4, Q5: 2N2222 RSENSE: IRC LRF 2512-01-R004-J *OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF 1735-1 TA03 26

LTC1735-1 PACKAGE DESCRIPTIOUN Dimensions in inches (millimeters) unless otherwise noted. GN Package 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) 0.189 – 0.196* (4.801 – 4.978) 0.009 (0.229) 16 15 14 13 12 11 109 REF 0.229 – 0.244 0.150 – 0.157** (5.817 – 6.198) (3.810 – 3.988) 1 2 3 4 5 6 7 8 0.015 – 0.004· 45(cid:176) 0.053 – 0.068 0.004 – 0.0098 (0.38 – 0.10) (1.351 – 1.727) (0.102 – 0.249) 0.007 – 0.0098 0° – 8° TYP (0.178 – 0.249) 0.016 – 0.050 0.008 – 0.012 0.0250 (0.406 – 1.270) (0.203 – 0.305) (0.635) BSC *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE GN16 (SSOP) 1098 S Package 16-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.386 – 0.394* (9.804 – 10.008) 16 15 14 13 12 11 10 9 0.228 – 0.244 0.150 – 0.157** (5.791 – 6.197) (3.810 – 3.988) 1 2 3 4 5 6 7 8 0.010 – 0.020 · 45(cid:176) 0.053 – 0.069 (0.254 – 0.508) (1.346 – 1.752) 0.004 – 0.010 0.008 – 0.010 (0.203 – 0.254) 0° – 8° TYP (0.101 – 0.254) 0.014 – 0.019 0.050 0.016 – 0.050 (0.355 – 0.483) (1.270) (0.406 – 1.270) TYP BSC S16 1098 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 27 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1735-1 TYPICAL APPLICATIOU High Efficiency Dynamic Output Voltage Selectable CPU Power Supply for SpeedStep Enabled Processors PGOOD RUN VIN 4.5V TO 24V R7 JP1 100k LATCH-OFF R6 R8 INTVCC DISABLE 680k 4.7Ω CIN CF1 22µF CIN: MARCON THCR70E1H226ZT 0.1µF 50V COUT: PANASONIC EEFVE06181R COSC 47pF CSS 0.1µF 12 COSC TG 1165 QFD1S6680A C· E2RAMIC LR1S:E PNSAEN: AIRSCO NCIRCF E2T5Q12P-60F11-RR20H0F4AF CC2 330pF RC1 33k 3 RITUHN/SLSTC1735-1BOOSSWT 14 CB 0.22µF 1.L21µH 0R.S0E0N4SΩE VOUT CC1 47pF 4 13 D1 1.35V OR 1.60V PGOOD VIN CMDSH-3 12A 4C71pF 100C0pSF1 56 SSEENNSSEE–+ INTVBCGC 1121 + C4.27µF C1µ4F MQB2,R QS3340DT32 C472pF R10.015k% + C18O0UµTF 7 VOSENSE PGND 10 F· D2S6680A C3 R3 4V 8 9 5V 47pF 33.2k SP SGND EXTVCC INPUT 1% · 4 (OPTIONAL) Q4 R5 10Ω R2 2N7002 VVSSEELL == 10:: VVOOUUTT == 11..6305VV 14.3k R4 10Ω 0.5% GND 1735-1 TA01 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1149 High Efficiency Synchronous Step-Down Controller 100% DC, Std Threshold MOSFETs, V < 48V IN LTC1159 High Efficiency Synchronous Step-Down Controller 100% DC, Logic Level MOSFETs, V < 40V IN LT1375/LT1376 1.5A 500kHz Step-Down Switching Regulator High Efficiency LTC1435A High Efficiency Low Noise Synchronous Step-Down Controller, N-Ch Drive Burst Mode Operation, 16-Pin Narrow SO LTC1436A/LTC1436A-PLL High Efficiency Low Noise Synchronous Step-Down Converter, N-Ch Drive Adaptive PowerTM Mode 20-Pin, 24-Pin SSOP LTC1474/LTC1475 Ultralow Quiescent Current Step-Down Monolithic Switching Regulator 100% DC, 8-Pin MSOP, I = 10m A Q LTC1628 Dual High Efficiency 2-Phase Step-Down Controller Antiphase Drive, 28-Pin SSOP, 3.5V £ V £ 36V IN LTC1702 550kHz Dual Output Synchronous Step-Down Controller Antiphase Drive, 24-Pin SSOP, V £ 7V IN LTC1709 PolyPhaseTM Synchronous Controller with 5-Bit VID Up to 42A, Minimum Input Capacitors, 1.3V £ V £ 3.5V OUT LTC1735 High Efficiency Synchronous Step-Down Contoller, N-Channel Drive Burst Mode Opertion, 16-Pin Narrow SSOP LTC1736 High Efficiency Synchronous Step-Down Controller with 5-Bit VID Control Output Fault Protection, 24-Pin SSOP LTC1772 SOT-23 High Efficiency Constant Frequency Step-Down Controller 100% DC, 550kHz, SOT-23, Current Mode Adaptive Power and PolyPhase are trademarks of Linear Technology Corporation. 28 Linear Technology Corporation sn17351 17351fs LT/TP 0100 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l w ww.linear-tech.com ª LINEAR TECHNOLOGY CORPORATION 1999