LTC1669 10-Bit Rail-to-Rail Micropower DAC with 2 I C Interface FEATURES DESCRIPTION n Micropower 10-Bit DAC in SOT-23 The LTC®1669 is a 10-bit voltage output DAC with true n Low Operating Current: 60μA buffered rail-to-rail output voltage capability. It operates n Ultralow Power Shutdown Mode: 12μA from a single supply with a range of 2.7V to 5.5V. The n 2-Wire Serial Interface Compatible reference for the DAC is selectable between the supply with I2C™ voltage or an internal bandgap reference. Selecting the n Selectable Internal Reference or Ratiometric to internal bandgap reference will set the full-scale output V voltage range to 2.5V. Selecting the supply as the reference CC n Maximum DNL Error: 0.75LSB sets the output voltage range to the supply voltage. n 8 User Selectable Addresses (MSOP Package) The part features a simple 2-wire serial interface compat- n Single 2.7V to 5.5V Operation ible with I2C that allows communication between many n Buffered True Rail-to-Rail Voltage Output devices. The internal data registers are double buffered to n Power-On Reset allow for simultaneous update of several devices at once. n 1.5V VIL and 2.1V VIH for SDA and SCL The DAC can be put in low current power-down mode for n Small 5-Lead TSOT-23 and 8-Lead MSOP Packages use in power conscious systems. APPLICATIONS Power-on reset ensures the DAC output is at 0V when power is initially applied, and all internal registers are n Digital Calibration cleared. The LTC1669 is pin-for-pin compatible with the n Offset/Gain Adjustment LTC1663. n Industrial Process Control For SMBus-compatible designs, please refer to the n Automatic Test Equipment LTC1663. n Arbitrary Function Generators L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. n Battery-Powered Data Conversion Products All other trademarks are the property of their respective owners. BLOCK DIAGRAM 4 (5) Differential Nonlinearity (DNL) VCC 1.25V BANDGAP 1.0 REFERENCE 0.8 VTAR E=F 2=5 V°CCC = 5V 0.6 REFERENCE SELECT 0.4 SB) 0.2 R (L 0 O 10-BIT RR–0.2 DAC LATCH E –0.4 VOUT 3 (8) 10-BIT BUFFERED VOUT DAC –0.6 –0.8 MSOP COMMAND INPUT PACKAGE LATCH LATCH –1.0 ONLY 0 28 156 384 512 640 768 896 1024 CODE (6) AD0 1669 G02 (2) AD1 2-WIRE INTERFACE (3) AD2 SDA SCL GND 1 (1) 5 (4) 2 (7) 1669 BD NOTE: PIN NUMBERS IN PARENTHESES REFER TO THE MSOP PACKAGE 1669fa 1

LTC1669 ABSOLUTE MAXIMUM RATINGS (Note 1) V to GND .............................................. –0.3V to 7.5V Operating Temperature Range CC SDA, SCL .................................................–0.3V to 7.5V LTC1669C ............................................... 0°C to 70°C AD0, AD1, AD2 (MSOP Only) ........–0.3V to (V + 0.3V) LTC1669I............................................. –40°C to 85°C CC V .............................................–0.3V to (V + 0.3V) Storage Temperature Range .................. –65°C to 150°C OUT CC Lead Temperature (Soldering, 10 sec) ................. 300°C PIN CONFIGURATION TOP VIEW TOP VIEW SDA 1 8VOUT SDA 1 5 SCL AD1 2 7GND GND 2 AD2 3 6AD0 SCL 4 5VCC VOUT 3 4 VCC MS8 PACKAGE S5 PACKAGE 8-LEAD PLASTIC MSOP 5-LEAD PLASTIC SOT-23 TJMAX = 125°C, θJA = 150°C/W TJMAX = 125°C, θJA = 250°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1669CMS8#PBF LTC1669CMS8#TRPBF LTAHV 8-Lead Plastic MSOP 0°C to 70°C LTC1669IMS8#PBF LTC1669IMS8#TRPBF LTAHX 8-Lead Plastic MSOP –40°C to 85°C LTC1669-8CMS8#PBF LTC1669-8CMS8#TRPBF LTAHT 8-Lead Plastic MSOP 0°C to 70°C LTC1669-8IMS8#PBF LTC1669-8IMS8#TRPBF LTAHU 8-Lead Plastic MSOP –40°C to 85°C TAPE AND REEL (MINI) TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1669CS5#TRMPBF LTC1669CS5#TRPBF LTAHW 5-Lead Plastic TSOT-23 0°C to 70°C LTC1669-1CS5#TRMPBF LTC1669-1CS5#TRPBF LTAHR 5-Lead Plastic TSOT-23 0°C to 70°C TRM = 500 pieces. Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. Consult LTC Marketing for information on lead based fi nish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/ 1669fa 2

LTC1669 ELECTRICAL CHARACTERISTICS The ● denotes specifi cations which apply over the full operating tempera- ture range, otherwise specifi cations are at T = 25°C. V = 2.7V to 5.5V, V set as reference, V unloaded, unless otherwise noted. A CC CC OUT SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DAC Resolution l 10 Bits Monotonicity (Note 2) l 10 Bits DNL Differential Nonlinearity Guaranteed Monotonic (Note 2) l ±0.2 ±0.75 LSB INL Integral Nonlinearity (Note 2) l ±0.5 ±2.5 LSB V Offset Error Measured at Code 20 l ±10 ±30 mV OS V Offset Error Temperature Coeffi cient ±15 μV/°C OSTC FSE Full-Scale Error Reference Set to V l ±3 ±15 LSB CC Reference Set to Internal Bandgap l ±3 ±15 LSB V DAC Output Span Reference Set to V 0 to V V OUT CC CC Reference Set to Internal Bandgap 0 to 2.5 V V Full-Scale Voltage Temperature Reference Set to V ±30 μV/°C FSTC CC Coeffi cient Reference Set to Internal Bandgap ±50 μV/°C PSRR Power Supply Rejection Ratio Reference Set to Internal Bandgap, ±0.4 LSB/V Code = 1023 Power Supply V Positive Supply Voltage l 2.7 5.5 V CC I Supply Current V = 3V (Note 3) l 60 100 μA CC CC V = 5V (Note 3) l 75 125 μA CC I Supply Current in Shutdown Mode (Note 3) l 12 24 μA SD Op Amp DC Performance Short-Circuit Current (Sourcing) V Shorted to GND, Input Code = 1023 l 25 100 mA OUT Short-Circuit Current (Sinking) V Shorted to V , Input Code = 0 l 30 120 mA OUT CC Output Impedance to GND Input Code = 0, VCC = 5V 65 Ω Input Code = 0, VCC = 5V 150 Ω In Shutdown Mode 500 kΩ Output Impedance to VCC Input Code = 1023, VCC = 5V 80 Ω Input Code = 1023, VCC = 5V 120 Ω AC Performance Voltage Output Slew Rate Rising (Notes 4, 5) 0.75 V/μs Falling (Notes 4, 5) 0.25 V/μs Voltage Output Settling Time To ±0.5LSB (Notes 4, 5) 30 μs Digital Feedthrough 0.75 nV•s Digital-to-Analog Glitch Impulse 1LSB Change Around Major Carry 70 nV•s Digital Inputs SCL, SDAs V High Level Input Voltage l 2.1 V IH V Low Level Input Voltage l 1.5 V IL V Logic Threshold Voltage 1.8 V LTH I Digital Input Leakage V = 5.5V and 0V, V = GND to V l ±1 μA LEAK CC IN CC C Digital Input Capacitance (Note 7) l 10 pF IN Digital Output SDA V Digital Output Low Voltage I = 3mA l 0.4 V OL PULLUP 1669fa 3

LTC1669 ELECTRICAL CHARACTERISTICS The ● denotes specifi cations which apply over the full operating tempera- ture range, otherwise specifi cations are at T = 25°C. V = 2.7V to 5.5V, V set as reference, V unloaded, unless otherwise noted. A CC CC OUT SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Address Inputs AD0, AD1, AD2 (MSOP Only) I Address Pin Pull-Up Current V = 0V l 0.5 1.5 μA UP IN V High Level Input Voltage l V – 0.3 V IH CC V Low Level Input Voltage l 0.8 V IL TIMING CHARACTERISTICS The ● denotes specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = 2.7V to 5.5V, V set as reference, V unloaded, unless otherwise noted. A CC CC OUT SYMBOL PARAMETER MIN TYP MAX UNITS Timing Characteristics (Notes 6, 7) f Clock Operating Frequency ● 100 kHz SCL t Bus Free Time Between Stop and Start Condition ● 4.7 μs BUF t Hold Time After (Repeated) Start Condition ● 4 μs HD, STA t Repeated Start Condition Setup Time ● 4.7 μs SU, STA t Stop Condition Setup Time ● 4 μs SU, STO t Data Hold Time (Input) ● 0 ns HD, DAT (IN) t Data Hold Time (Output) ● 225 500 3450 ns HD, DAT (OUT) t Data Setup Time ● 250 ns SU, DAT t Clock Low Period ● 4.7 μs LOW t Clock High Period ● 4 μs HIGH t Clock, Data Fall Time ● 20 300 ns f t Clock, Data Rise Time ● 20 1000 ns r Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: Digital inputs at 0V or VCC. may cause permanent damage to the device. Exposure to any Absolute Note 4: Load is 10kΩ in parallel with 100pF. Maximum Rating condition for extended periods may affect device Note 5: V = V = 5V. DAC switched between 0.1V and 0.9V , CC REF FS FS reliability and lifetime. i.e., codes k = 102 and k = 922. Note 2: Nonlinearity and monotonicity are defi ned from code 20 to code Note 6: All values are referenced to V and V levels. IH IL 1003 (full scale). See Applications Information. Note 7: Guaranteed by design and not subject to test. 1669fa 4

LTC1669 TYPICAL PERFORMANCE CHARACTERISTICS Source and Sink Current Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Capability with V = 5V CC 1.0 1.0 5.0 0.8 VTAR E=F 2=5 V°CCC = 5V 0.8 VTAR E=F 2=5 V°CCC = 5V 4.5 DAC CODE = 1023 TA = 25°C 0.6 0.6 4.0 0.4 0.4 V) 3.5 SB) 0.2 SB) 0.2 AGE ( 3.0 RROR (L–0.20 RROR (L–0.20 UT VOLT 22..50 E E P T –0.4 –0.4 U 1.5 O –0.6 –0.6 1.0 DAC CODE = 0 –0.8 –0.8 0.5 –1.0 –1.0 0 0 28 156 384 512 640 768 896 1024 0 28 156 384 512 640 768 896 1024 0 1 2 3 4 5 6 7 8 9 10 CODE CODE OUTPUT CURRENT SOURCE/SINK (mA) 1669 G01 1669 G02 1669 G03 Large-Signal Step Response Midscale Glitch Load Regulation vs Output Current 1.0 5 VCC = VREF = 5V SDA 5V 0.8 VOUT = 2.5V (VOLTS) 0 SDA 0.6 CODE = 512 0V TA = 25°C 5 CODE = 512 TO 511 0.4 4 CODE = 990 SB) 0.2 L 3 VCC = 5V (UT 0 VOUT RL = 4.7k VO–0.2 (VOLTS) 2 CL = 100pF VOUT Δ SOURCE SINK TA = 25°C 10mV/DIV –0.4 1 VCC = 5V CODE = 32 RL = 4.7k –0.6 0 CL = 100pF –0.8 TA = 25°C –1.0 5μs/DIV 1669 G04 2μs/DIV 1669 G05 –4 –3 –2 –1 0 1 2 3 4 IOUT (mA) 1669 G06 Offset Error Voltage vs Full-Scale Output Voltage vs Load Regulation vs Output Current Temperature Temperature 1.0 5 2.510 0.8 VVCOCU T= =V 1R.E5FV = 3V 4 2.508 RINETFEERRNEANLC EB ASNETD GTAOP 0.6 CODE = 512 V) 3 2.506 TA = 25°C m 0.4 E ( 2 V)2.504 V (LSB)ΔOUT––000...2420 SOURCE SINK SET ERROR VOLTAG ––1012 OUTPUT VOLTAGE (2222....554400992086 F –0.6 OF –3 2.494 –0.8 –4 2.492 –1.0 –5 2.490 –1.0–0.8–0.6–0.4–0.2 0 0.2 0.4 0.6 0.8 1.0 –60 –40 –20 0 20 40 60 80 100 –60 –40 –20 0 20 40 60 80 100 IOUT (mA) TEMPERATURE (°C) TEMPERATURE (°C) 1669 G07 1669 G08 1669 G09 1669fa 5

LTC1669 PIN FUNCTIONS SDA (Pin 1, Pin 1 on SOT-23): Serial Data Bidirectional SCL (Pin 4, Pin 5 on SOT-23): Serial Clock Input Pin. Pin. Data is shifted into the SDA pin and acknowledged Data is shifted into the SDA pin at the rising edges of the by the SDA pin. High impedance pin while data is shifted clock. This high impedance pin requires a pull-up resistor in. Open-drain N-channel output during acknowledgment. or current source to V . CC Requires a pull-up resistor or current source to V . CC V (Pin 5, Pin 4 on SOT-23): Power Supply. 2.7V ≤ V CC CC AD1 (Pin 2): Slave Address Select Bit 1. Tie this pin to ≤ 5.5V. Also used as the reference voltage input when the either V or GND to modify the corresponding bit of the part is programmed to use V as the reference. CC CC LTC1669’s slave address. AD0 (Pin 6): Slave Address Select Bit 0. Tie this pin to AD2 (Pin 3): Slave Address Select Bit 2. Tie this pin to either V or GND to modify the corresponding bit of the CC either V or GND to modify the corresponding bit of the LTC1669’s slave address. CC LTC1669’s slave address. GND (Pin 7, Pin 2 on SOT-23): System Ground. V (Pin 8, Pin 3 on SOT-23): Voltage Output. Buffered OUT rail-to-rail DAC output. 1669fa 6

LTC1669 DEFINITIONS Differential Nonlinearity (DNL): The difference between greater than zero. The INL error at a given input code is the measured change and the ideal 1LSB change for any calculated as follows: two adjacent codes. The DNL error between any two codes INL = [V – V – (V – V )(code/1023)]/LSB OUT OS FS OS is calculated as follows: Where V is the output voltage of the DAC measured OUT DNL = (ΔV – LSB)/LSB OUT at the given input code. Where ΔV is the measured voltage difference between OUT Least Signifi cant Bit (LSB): The ideal voltage difference two adjacent codes. between two successive codes. Digital Feedthrough: The glitch that appears at the ana- LSB = V /1024 log output caused by AC coupling from the digital inputs REF when they change state. The area of the glitch is specifi ed Resolution (n): Defi nes the number of DAC output states in (nV)(sec). (2n) that divide the full-scale range. Resolution does not imply linearity. Full-Scale Error (FSE): The deviation of the actual full-scale voltage from ideal. FSE includes the effects of offset and Voltage Offset Error (V ): Nominally, the voltage at the OS gain errors (see Applications Information). output when the DAC is loaded with all zeros. A single supply DAC can have a true negative offset, but the output Integral Nonlinearity (INL): The deviation from a straight cannot go below zero (see Applications Information). line passing through the endpoints of the DAC transfer curve (Endpoint INL). Because the output cannot go For this reason, single supply DAC offset is measured at below zero, the linearity is measured between full scale the lowest code that guarantees the output will be greater and the lowest code that guarantees the output will be than zero. 1669fa 7

LTC1669 TIMING DIAGRAM FULL-SCALEVOLTAGE ZERO-SCALEVOLTAGE1669 TA02 P O ST CK 9 A D8 1 8 D9 1 7 X X 6 ATA X X 5 D tBUFtSU, STO 1669 TD STARTONCONDITION AD0 Set High) MS XXXX XXXX 1234 STOPCONDITI D2 to ACK 9 A D0 1 8 ( ale D1 1 7 c ull S D2 1 6 HD, STA ut for F LS DATA D4D3 11 45 tSU, STAt REPEATED STARTCONDITION ming DAC Outp D7D6D5 ACK111 9123 m a SY 0 8 r g HD, DAT —Pro BGSD 00 67 t m DAT tf Wavefor COMMAND XX XX 45 tSU, tHIGH put X X 3 tr 9 In X X 2 tLOW 166 X X 1 SDA SCL tHD, STA STARTCONDITION Typical LTC AD1AD0WR ACK110 6789 RESS AD2 1 5 D AD 0 0 4 0 0 3 RE A 1 1 2 N’T C O 0 0 1 X = D START NOTE: SDA SCL VOUT 1669fa 8

LTC1669 APPLICATIONS INFORMATION Write Word Protocol Used by the LTC1669 1 7 1 1 8 1 8 1 8 1 1 S Slave Address Wr A Command Byte A LSData Byte A MSData Byte A P S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition 1669 TA03 Serial Digital Interface Write Word Protocol The LTC1669 communicates with a host (master) using The master initiates communication with the LTC1669 with the standard 2-wire interface. The Timing Diagram shows a START condition and a 7-bit address followed by the Write the timing relationship of the signals on the bus. The two Bit (Wr) = 0. The LTC1669 acknowledges and the master bus lines, SDA and SCL, must be high when the bus is delivers the command byte. The LTC1669 acknowledges not in use. External pull-up resistors or current sources, and latches the command byte into the command byte such as the LTC1694 SMBus/I2C Accelerator, are required input register. The master then delivers the least signifi cant on these lines. data byte. Again the LTC1669 acknowledges and the data is latched into the least signifi cant data byte input register. The LTC1669 is a receive-only (slave) device. The master The master then delivers the most signifi cant data byte. can communicate with the LTC1669 using the Quick Com- The LTC1669 acknowledges once more and latches the mand, Send Byte or Write Word protocols as explained data into the most signifi cant data byte input register. later. Lastly, the master terminates the communication with a STOP condition. On the reception of the STOP condition, The START and STOP Conditions the LTC1669 transfers the input register information to When the bus is not in use, both SCL and SDA must be output registers and the DAC output is updated. high. A bus master signals the beginning of a communica- tion to a slave device by transmitting a START condition. Slave Address (MSOP Package Only) A START condition is generated by transitioning SDA The LTC1669 can respond to one of eight 7-bit addresses. from high to low while SCL is high. The fi rst 4 bits (MSBs) have been factory programmed to When the master has fi nished communicating with the 0100. The fi rst 4 bits of the LTC1669-8 have been factory slave, it issues a STOP condition. A STOP condition is programmed to 0011. The three address bits, AD2, AD1 generated by transitioning SDA from low to high while and AD0 are programmed by the user and determine the SCL is high. The bus is then free for communication with LSBs of the slave address, as shown in the table below: another I2C device. LTC1669 LTC-1669-8 Acknowledge AD2 AD1 AD0 0100 xxx 0011 xxx L L L 0100 000 0011 000 The Acknowledge signal is used for handshaking between L L H 0100 001 0011 001 the master and the slave. An Acknowledge (active LOW) L H L 0100 010 0011 010 generated by the slave lets the master know that the latest L H H 0100 011 0011 011 byte of information was received. The Acknowledge related H L L 0100 100 0011 100 clock pulse is generated by the master. The master releases H L H 0100 101 0011 101 the SDA line (HIGH) during the Acknowledge clock pulse. H H L 0100 110 0011 110 The slave-receiver must pull down the SDA line during the Acknowledge clock pulse so that it remains a stable LOW H H H 0100 111 0011 111 during the HIGH period of this clock pulse. 1669fa 9

LTC1669 APPLICATIONS INFORMATION Slave Address (SOT-23 Package) The Bandgap (BG) bit when set to “0” selects the DAC supply voltage as its voltage reference. The full-scale The slave address for the SOT-23 package has been output of the DAC with this setting is equal to the supply factory programmed to be “0100 000” (LTC1669) and voltage. When the BG bit is set to “1,” the internal bandgap “0100 001” (LTC1669-1). If another address is required, reference (≈1.25V) is selected as the DAC’s reference. The please consult the factory. full-scale output voltage for this setting is 2.5V. Command Byte Data Bytes 7 6 5 4 3 2 1 0 Least Signifi cant Data Byte X X X X X BG SD SY 7 6 5 4 3 2 1 0 SY 1 Allows update on Acknowledge of SYNC Address only D7 D6 D5 D4 D3 D2 D1 D0 0 Update on Stop condition only (Power-On Default) SD 1 Puts the device in power-down mode Most Signifi cant Data Byte 0 Puts the device in standard operating mode (Power-On Default) 7 6 5 4 3 2 1 0 BG 1 Selects the internal bandgap reference X X X X X X D9 D8 0 Selects the supply as the reference (Power-On Default) X = Don’t care X X Don’t Care Send Byte Protocol The stop condition normally initiates the update of the The Send Byte protocol used on the LTC1669 is actually a DAC’s output latches. Simultaneous update of more than subset of the Write Word protocol described previously. one DAC or other devices on the bus can be achieved by The Send Byte protocol can only be used to send the reissuing new start bit, address, command and data bytes command byte information to the LTC1669. before issuing a fi nal stop condition (which will update 1 7 1 1 8 1 1 all the devices). An alternate way to achieve simultaneous S Slave Address Wr A Command Byte A P LTC1669 updates is to override the stop condition update S = Start Condition, Wr = Write Bit, A = Acknowledge, P = Stop Condition by setting the “SY” bit of the command byte. Setting this 1669 TA04 bit sets the device to update the DAC output latches only The Send Byte protocol is also used whenever the Write at the reception of a SYNC address quick command. The Word protocol is interrupted for any reason. Reception of actual update occurs on the rising edge of SCL during the a START or STOP condition after the Acknowledge of the Acknowledge. In this way, all devices can update on the command byte, but before the Acknowledge of the last reception of the SYNC address quick command instead data byte, will cause both data bytes to be ignored and of the STOP condition. the command byte to be accepted. A Shutdown (SD) bit = HIGH will put the device in a low Reception of a START or STOP condition before the Ac- power state but retain all data latch information. Shutdown knowledge of the command byte will cause the interrupted will occur at the reception of a STOP condition. This way command byte to be ignored. shutdown could be synchronized to other devices. The output impedance of the DAC will go to a high impedance state (≈500kΩ to GND). 1669fa 10

LTC1669 APPLICATIONS INFORMATION SYNC Address/Quick Command Rail-to-Rail Output Considerations In addition to the slave address, the LTC1669 has an address As in any rail-to-rail device, the output is limited to volt- that can be shared by other devices so that they may be ages within the supply range. updated synchronously. The address is called to the SYNC If the DAC offset is negative, the output for the lowest address and uses the quick command protocol. codes limits at 0V as shown in Figure 1b. The SYNC Address is 1111 110 Similarly, limiting can occur near full scale when V is CC 1 7 1 1 1 used as the reference. If VREF = VCC and the DAC full-scale Start 1111 110 SY/CLR Ack Stop error (FSE) is positive, the output for the highest codes SYNC Address 1669 TA05 limits at V as shown in Figure 1c. No full-scale limiting CC can occur if the internal reference is used. SY/CLR 1 Update output latches on rising edge of SCL during Acknowledge of SYNC Address Offset and linearity are defi ned and tested over the region 0 Clear all internal latches on rising edge of SCL during of the DAC transfer function where no output limiting can Acknowledge of SYNC Address occur. The SY/CLR bit set high only has meaning when the “SY” Internal Reference bit of the command byte was previously set HIGH. On In applications where a predictable output is required the otherhand, the SY/CLR bit set LOW will always clear that is independent of supply voltage, the LTC1669 has a the part, independent of the state of the “SY” bit in the user-selectable internal reference. Selecting the internal command byte. reference will set the full-scale output voltage to 2.5V. This can be useful in applications where the supply voltage is Voltage Output poorly regulated. The output amplifi er contained in the LTC1669 can source or sink up to 5mA. The output stage swings to within a Using the LT®1460 Micropower Series Reference as a few millivolts of either supply rail when unloaded and Power Supply for the LTC1669 has an equivalent output resistance of 85Ω when driving In applications where the advantages of using the internal a load to the rails. The output amplifi er is stable driving reference are required but the full-scale range needs to capacitive loads up to 1000pF. be greater than 2.5V, an external series reference can be A small resistor placed in series with the output can be used. The LT1460 is ideal for use as a power supply for used to achieve stability for any load capacitance greater the LTC1669 and can provide 3V, 3.3V and 5V full-scale than 1000pF. For example, a 0.1μF load can be driven output voltage ranges. The LT1460 provides accuracy, noise by the LTC1669 if a 110Ω series resistance is used. The immunity and extended supply range to the LTC1669 when phase margin of the resulting circuit is 45° and increases the LTC1669 is operated ratiometric to V . Since both CC monotonically from this point if larger values of resistance, parts are available in SOT-23 packages, the PC board space capacitance or both are substituted for the values given. for this application is extremely small. See Figure 2. 1669fa 11

LTC1669 APPLICATIONS INFORMATION POSITIVE VREF = VCC FSE OUTPUT VOLTAGE INPUT CODE (c) VREF = VCC OUTPUT VOLTAGE 0 512 1023 INPUT CODE (a) OUTPUT VOLTAGE 0V NEGATIVE INPUT CODE OFFSET (b) 1669 F01 Figure 1. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V = V REF CC 1669fa 12

LTC1669 APPLICATIONS INFORMATION LT1460S3-3 1 2 3V 3.9V TO 20V IN OUT + 0.1μF GND 0.01μF 3 4 (5) VCC 5 (4) SCL 3 (8) TO LTC1669 OUT 0V≤ VOUT≤ 3V μP 1 (1) SDA GND LTC1669 PIN NUMBERS IN PARENTHESES 2 (7) REFER TO MSOP PACKAGE 1669 F02 Figure 2. LT1460 As Power Supply for the LTC1669 1669fa 13

LTC1669 PACKAGE DESCRIPTION S5 Package 5-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1635) 0.62 0.95 2.90 BSC MAX REF (NOTE 4) 1.22 REF 1.50 – 1.75 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC (NOTE 4) PIN ONE RECOMMENDED SOLDER PAD LAYOUT 0.95 BSC 0.30 – 0.45 TYP PER IPC CALCULATOR 5 PLCS (NOTE 3) 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 1.90 BSC NOTE: (NOTE 3) S5 TSOT-23 0302 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 1669fa 14

LTC1669 PACKAGE DESCRIPTION MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) 3.00 ± 0.102 0.889 ± 0.127 (.118 ± .004) 0.52 (.035 ± .005) (NOTE 3) 8 7 6 5 (.0205) REF 5.23 (.206) 3.20 – 3.45 4.90 ± 0.152 3.00 ± 0.102 MIN (.126 – .136) 0.254 DETAIL “A” (.193 ± .006) (.1(1N8O ±TE . 040)4) (.010) 0° – 6° TYP GAUGE PLANE 0.42 ± 0.038 0.65 (.0165 ± .0015) (.0256) 1 2 3 4 TYP BSC 0.53 ± 0.152 RECOMMENDED SOLDER PAD LAYOUT (.021 ± .006) (1.0.1403) (0.0.8364) DETAIL “A” MAX REF 0.18 (.007) SEATING N1.O DTIEM:ENSIONS IN MILLIMETER/(INCH) PLANE 0.22 – 0.38 0.127 ± 0.076 2. DRAWING NOT TO SCALE (.009 – .015) (.005 ± .003) 0.65 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. TYP MSOP (MS8) 0603 (.0256) MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE BSC 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 1669fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 15 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1669 TYPICAL APPLICATION Program Up to 16 Control Outputs Per BUS and Place Them Where They Are Needed VCC = 2.7V TO 5.5V 1 5 VCC SMBus 1 + LTC1694 0.1μF 4 SMBus 2 GND 2 + 5 4 0.1μF 1 SCL VCC SDA 6 AD0LTC1669CMS8 VOUT 8 COOUNTPTRUOT L0 2 μ SPCL 3 AADD12 GND 0V≤ VOUT0 < VCC SDA 7 + 5 4 0.1μF 1 SCL VCC SDA 6 AD0LTC1669CMS8 VOUT 8 COOUNTPTRUOT L1 2 3 AD1 0V≤ VOUT1 < VCC AD2 GND 7 + 5 4 0.1μF 1 SCL VCC SDA 6 ADL0TC1669-8CMS8VOUT 8 COOUNTPTRUOT L15 2 3 AD1 0V≤ VOUT15 < VCC AD2 GND TO OTHER I2C 7 DEVICES 1669 TA06 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1694 SMBus/I2C Accelerator Dual SMBus Accelerator with Active AC and DC Pull-Up Current Sources LTC1694-1 SMBus/I2C Accelerator Dual SMBus Accelerator with Active AC Pull-Up Current Only DACs Single Rail-to-Rail 12-Bit V DAC in 8-Lead MSOP Low Power Multiplying V DAC. Output Swings from GND to REF. REF LTC1659 OUT OUT Package. V = 2.7V to 5.5V Input Can Be Tied to V . 3-Wire Interface. CC CC LTC1660/LTC1664 Octal/Quad 10-Bit V DACs in 16-Pin Narrow SSOP V = 2.7V to 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface. OUT CC LTC1661 Dual 10-Bit V in 8-Lead MSOP Package V = 2.7V to 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface. OUT CC LTC1663 10-Bit V in SOT-23, SMBUS Interface Pin Compatible with LTC1669 OUT ADCs LTC1285/LTC1288 8-Pin SO, 3V Micropower ADCs 1- or 2-Channel, Autoshutdown LTC1286/LTC1298 8-Pin SO, 5V Micropower ADCs 1- or 2-Channel, Autoshutdown 1669fa 16 Linear Technology Corporation LT 1007 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007

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