LTC1663 10-Bit Rail-to-Rail Micropower DAC with 2-Wire Interface FEATURES DESCRIPTION n Micropower 10-Bit DAC in SOT-23 The LTC®1663 is a 10-bit voltage output DAC with true n Low Operating Current: 60μA buffered rail-to-rail output voltage capability. It operates n Ultralow Power Shutdown Mode: 10μA from a single supply with a range of 2.7V to 5.5V. The n 2-Wire Serial Interface Compatible reference for the DAC is selectable between the supply with SMBus voltage or an internal bandgap reference. Selecting the n Selectable Internal Reference or Ratiometric to internal bandgap reference will set the full-scale output V voltage range to 2.5V. Selecting the supply as the reference CC n Maximum DNL Error: 0.75LSB sets the output voltage range to the supply voltage. n 8 User Selectable Addresses (MSOP Package) The part features a simple 2-wire serial interface compat- n Single 2.7V to 5.5V Operation ible with SMBus that allows communication between many n Buffered True Rail-to-Rail Voltage Output devices. The internal data registers are double buffered to n Power-On Reset allow for simultaneous update of several devices at once. n 0.6V V and 1.4V V for SDA and SCL IL IH The DAC can be put in low current power-down mode for n Small 5-Lead SOT-23 and 8-Lead MSOP Packages use in power conscious systems. APPLICATIONS Power-on reset ensures the DAC output is at 0V when power is initially applied, and all internal registers are n Digital Calibration cleared. n Offset/Gain Adjustment n Industrial Process Control For I2C designs, please refer to the LTC1669. n Automatic Test Equipment L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other n Arbitrary Function Generators trademarks are the property of their respective owners. n Battery-Powered Data Conversion Products BLOCK DIAGRAM 4 (5) VCC Differential Nonlinearity (DNL) 1.25V RBEAFNERDEGNACPE 1.0 0.8 VTAR E=F 2=5 V°CCC = 5V REFERENCE 0.6 SELECT 0.4 SB) 0.2 R (L 0 O 10-BIT + RR–0.2 DAC LATCH VOUT 3 (8) E–0.4 – –0.6 MSOP COMMAND INPUT R –0.8 PACKAGE LATCH LATCH –1.0 ONLY R 0 28 156 384 512 640 768 896 1024 CODE (6) AD0 (2) AD1 1663 TA01 2-WIRE INTERFACE (3) AD2 SDA SCL GND 1 (1) 5 (4) 2 (7) 1663 BD NOTE: PIN NUMBERS IN PARENTHESES REFER TO THE MSOP PACKAGE 1663fd 1

LTC1663 ABSOLUTE MAXIMUM RATINGS (Note 1) V to GND .............................................. –0.3V to 7.5V Operating Temperature Range CC SDA, SCL .................................................–0.3V to 7.5V LTC1663C ............................................... 0°C to 70°C AD0, AD1, AD2 (MSOP Only) ........–0.3V to (V + 0.3V) LTC1663I............................................. –40°C to 85°C CC V .............................................–0.3V to (V + 0.3V) LTC1663E (Note 8) .............................. –40°C to 85°C OUT CC Storage Temperature Range .................. –65°C to 150°C Lead Temperature (Soldering, 10 sec) ................. 300°C PACKAGE/ORDER INFORMATION ORDER PART ORDER PART NUMBER NUMBER TOP VIEW TOP VIEW LTC1663CMS8 LTC1663CS5 SDA 1 8VOUT LTC1663IMS8 SDA 1 5 SCL LTC1663-1CS5 AD1 2 7GND GND 2 AD2 3 6AD0 LTC1663-8CMS8 LTC1663-2CS5 SCL 4 5VCC LTC1663-8IMS8 VOUT 3 4 VCC LTC1663ES5 MS8 PACKAGE S5 PACKAGE 8-LEAD PLASTIC MSOP 5-LEAD PLASTIC SOT-23 TJMAX = 125°C, θJA = 150°C/W MS8 PART MARKING TJMAX = 125°C, θJA = 250°C/W S5 PART MARKING* LTEQ LTA6 LTEP LTSB LTJJ LTA7 LTSA LTEP Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container. ELECTRICAL CHARACTERISTICS The ● denotes specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = 2.7V to 5.5V, V set as reference, V unloaded, unless otherwise noted. A CC CC OUT SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DAC Resolution l 10 Bits Monotonicity (Note 2) l 10 Bits DNL Differential Nonlinearity Guaranteed Monotonic (Note 2) l ±0.2 ±0.75 LSB INL Integral Nonlinearity (Note 2) l ±0.5 ±2.5 LSB LTC1663E (Note 2) l ±0.5 ±3 LSB V Offset Error Measured at Code 20 l ±10 ±30 mV OS Measured at Code 20 (LTC1663E) l ±10 ±35 mV V Offset Error Temperature Coeffi cient ±15 μV/°C OSTC FSE Full-Scale Error Reference Set to V l ±3 ±15 LSB CC Reference Set to Internal Bandgap l ±3 ±15 LSB Reference Set to VCC (LTC1663E) l ±20 LSB Reference Set to Internal Bandgap (LTC1663E) l ±20 LSB V DAC Output Span Reference Set to V 0 to V V OUT CC CC Reference Set to Internal Bandgap 0 to 2.5 V V Full-Scale Voltage Temperature Reference Set to V ±30 μV/°C FSTC CC Coeffi cient Reference Set to Internal Bandgap ±50 μV/°C PSRR Power Supply Rejection Ratio Reference Set to Internal Bandgap, ±0.4 LSB/V Code = 1023 1663fd 2

LTC1663 ELECTRICAL CHARACTERISTICS The ● denotes specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = 2.7V to 5.5V, V set as reference, V unloaded, unless otherwise noted. A CC CC OUT SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Positive Supply Voltage l 2.7 5.5 V CC I Supply Current V = 3V (Note 3) l 60 100 μA CC CC VCC = 5V (Note 3) l 75 125 μA I Supply Current in Shutdown Mode (Note 3) l 10 16 μA SD LTC1663E (Note 3) l 12 24 μA Op Amp DC Performance Short-Circuit Current (Sourcing) V Shorted to GND, Input Code = 1023 l 25 100 mA OUT Short-Circuit Current (Sinking) V Shorted to V , Input Code = 0 l 30 120 mA OUT CC Output Impedance to GND Input Code = 0, VCC = 5V 65 Ω Input Code = 0, VCC = 3V 150 Ω In Shutdown Mode 500 kΩ Output Impedance to VCC Input Code = 1023, VCC = 5V 80 Ω Input Code = 1023, VCC = 3V 120 Ω AC Performance Voltage Output Slew Rate Rising (Notes 4, 5) 0.75 V/μs Falling (Notes 4, 5) 0.25 V/μs Voltage Output Settling Time To ±0.5LSB (Notes 4, 5) 30 μs Digital Feedthrough 0.75 nV•s Digital-to-Analog Glitch Impulse 1LSB Change Around Major Carry 70 nV•s Digital Inputs SCL, SDA V High Level Input Voltage l 1.4 V IH V Low Level Input Voltage l 0.6 V IL V Logic Threshold Voltage 1 V LTH I Digital Input Leakage V = 5.5V and 0V, V = GND to V l ±1.0 μA LEAK CC IN CC VCC = 5.5V and 0V, VIN = GND to VCC (LTC1663E) l ±1.2 μA C Digital Input Capacitance (Note 7) l 10 pF IN Digital Output SDA V Digital Output Low Voltage I = 350μA l 0.4 V OL PULLUP Address Inputs AD0, AD1, AD2 (MSOP Only) I Address Pin Pull-Up Current V = 0V l 0.5 1.5 μA UP IN V High Level Input Voltage l V – 0.3 V IH CC V Low Level Input Voltage l 0.8 V IL TIMING CHARACTERISTICS The ● denotes specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = 2.7V to 5.5V, V set as reference, V unloaded, unless otherwise noted. A CC CC OUT SYMBOL PARAMETER MIN TYP MAX UNITS SMBus Timing Characteristics (Notes 6, 7) f SMBus Operating Frequency ● 10 100 kHz SMB t Bus Free Time Between Stop and Start Condition ● 4.7 μs BUF t Hold Time After (Repeated) Start Condition ● 4.0 μs HD, STA t Repeated Start Condition Setup Time ● 4.7 μs SU, STA t Stop Condition Setup Time ● 4.0 μs SU, STO t Data Hold Time ● 300 ns HD, DAT 1663fd 3

LTC1663 TIMING CHARACTERISTICS The ● denotes specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = 2.7V to 5.5V, V set as reference, V unloaded, unless otherwise noted. A CC CC OUT SYMBOL PARAMETER MIN TYP MAX UNITS t Data Setup Time ● 250 ns SU, DAT t Clock Low Period ● 4.7 μs LOW t Clock High Period ● 4.0 50 μs HIGH t Clock, Data Fall Time ● 300 ns f t Clock, Data Rise Time ● 1000 ns r Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: V = V = 5V. DAC switched between 0.1V and 0.9V , i.e., CC REF FS FS may cause permanent damage to the device. Exposure to any Absolute codes k = 102 and k = 922. Maximum Rating condition for extended periods may affect device Note 6: All values are referenced to V and V levels. IH IL reliability and lifetime. Note 7: Guaranteed by design and not subject to test. Note 2: Nonlinearity and monotonicity are defi ned from code 20 to code Note 8: The LTC1663E is guaranteed to meet performance specifi cations 1003 (full scale). See Applications Information. from 0°C to 70°C. Specifi cations over the –40°C to 85°C operating Note 3: Digital inputs at 0V or VCC. temperature range are assured by design, characterization and correlation Note 4: Load is 10kΩ in parallel with 100pF. with statistical process controls. TYPICAL PERFORMANCE CHARACTERISTICS Source and Sink Current Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Capability with V = 5V CC 1.0 1.0 5.0 0.8 VTAR E=F 2=5 V°CCC = 5V 0.8 VTAR E=F 2=5 V°CCC = 5V 4.5 DAC CODE = 1023 TA = 25°C 0.6 0.6 4.0 0.4 0.4 V) 3.5 SB) 0.2 SB) 0.2 AGE ( 3.0 L L T R ( 0 R ( 0 OL 2.5 RRO–0.2 RRO–0.2 UT V 2.0 E E P T –0.4 –0.4 U 1.5 O –0.6 –0.6 1.0 DAC CODE = 0 –0.8 –0.8 0.5 –1.0 –1.0 0 0 28 156 384 512 640 768 896 1024 0 28 156 384 512 640 768 896 1024 0 1 2 3 4 5 6 7 8 9 10 CODE CODE OUTPUT CURRENT SOURCE/SINK (mA) 1663 G01 1663 G02 1663 G03 Large-Signal Step Response Midscale Glitch Load Regulation vs Output Current 1.0 5 VCC = VREF = 5V SDA 5V 0.8 VOUT = 2.5V (VOLTS) 0 SDA CODE = 512 0.6 0V TA = 25°C 5 CODE = 512 TO 511 0.4 CODE = 990 4 B) 0.2 S L (VOVLOTUST) 32 VRCTACLL C === = 214 505.7°0VkCpF 10mVV/ODUIVT V (ΔOUT––00..420 SOURCE SINK 1 VCC = 5V CODE = 32 RL = 4.7k –0.6 0 CL = 100pF –0.8 TA = 25°C –1.0 5μs/DIV 1663 G04 2μs/DIV 1663 G05 –4 –3 –2 –1 0 1 2 3 4 IOUT (mA) 1663fd 1663 G06 4

LTC1663 TYPICAL PERFORMANCE CHARACTERISTICS Offset Error Voltage vs Full-Scale Output Voltage vs Load Regulation vs Output Current Temperature Temperature 1.0 5 2.510 0.8 VVCOCU T= =V 1R.E5FV = 3V 4 2.508 RINETFEERRNEANLC EB ASNETD GTAOP 0.6 CODE = 512 V) 3 2.506 TA = 25°C m 0.4 E ( 2 V)2.504 V (LSB)ΔOUT––000...2420 SOURCE SINK SET ERROR VOLTAG ––1012 OUTPUT VOLTAGE (2222....554400992086 F –0.6 OF –3 2.494 –0.8 –4 2.492 –1.0 –5 2.490 –1.0–0.8–0.6–0.4–0.2 0 0.2 0.4 0.6 0.8 1.0 –60 –40 –20 0 20 40 60 80 100 –60 –40 –20 0 20 40 60 80 100 IOUT (mA) TEMPERATURE (°C) TEMPERATURE (°C) 1663 G07 1663 G08 1663 G09 PIN FUNCTIONS SDA (Pin 1, Pin 1 on SOT-23): Serial Data Bidirectional SCL (Pin 4, Pin 5 on SOT-23): Serial Clock Input Pin. Pin. Data is shifted into the SDA pin and acknowledged Data is shifted into the SDA pin at the rising edges of the by the SDA pin. High impedance pin while data is shifted clock. This high impedance pin requires a pull-up resistor in. Open-drain N-channel output during acknowledgment. or current source to V . CC Requires a pull-up resistor or current source to V . CC V (Pin 5, Pin 4 on SOT-23): Power Supply. 2.7V ≤ V CC CC AD1 (Pin 2): Slave Address Select Bit 1. Tie this pin to ≤ 5.5V. Also used as the reference voltage input when the either V or GND to modify the corresponding bit of the part is programmed to use V as the reference. CC CC LTC1663’s slave address. AD0 (Pin 6): Slave Address Select Bit 0. Tie this pin to AD2 (Pin 3): Slave Address Select Bit 2. Tie this pin to either V or GND to modify the corresponding bit of the CC either V or GND to modify the corresponding bit of the LTC1663’s slave address. CC LTC1663’s slave address. GND (Pin 7, Pin 2 on SOT-23): System Ground. V (Pin 8, Pin 3 on SOT-23): Voltage Output. Buffered OUT rail-to-rail DAC output. DEFINITIONS Differential Nonlinearity (DNL): The difference between Digital Feedthrough: The glitch that appears at the ana- the measured change and the ideal 1LSB change for any log output caused by AC coupling from the digital inputs two adjacent codes. The DNL error between any two codes when they change state. The area of the glitch is specifi ed is calculated as follows: in (nV)(sec). DNL = (ΔV – LSB)/LSB Full-Scale Error (FSE): The deviation of the actual full-scale OUT voltage from ideal. FSE includes the effects of offset and Where ΔV is the measured voltage difference between OUT gain errors (see Applications Information). two adjacent codes. 1663fd 5

LTC1663 TIMING DIAGRAM FULL-SCALEVOLTAGE ZERO-SCALEVOLTAGE1663 TA02 P O ST CK 9 A D8 1 8 D9 1 7 X X 6 ATA X X 5 D h) MS X X 4 g Hi X X 3 tBUFtSU, STO 1663 TD STARTONCONDITION 2 to AD0 Set XX XXACK 912 STOPCONDITI e (AD D0 1 8 al D1 1 7 c ull S D2 1 6 tSU, STAtHD, STA REPEATED STARTCONDITION ming DAC Output for F LS DATA D7D6D5D4D3 ACK11111 912345 m a SY 0 8 r g tHD, DAT m—Pro BGSD 00 67 tSU, DAT tHIGH tf ut Wavefor COMMAND XXX XXX 345 tr np X X 2 tLOW 663 I X X 1 N 1 SDA SCL tHD, STA STARTCONDITIO Typical LTC AD0WR ACK10 789 D1 1 6 A RESS AD2 1 5 D AD 0 0 4 0 0 3 RE A 1 1 2 N’T C O 0 0 1 X = D START NOTE: SDA SCL VOUT 1663fd 6

LTC1663 DEFINITIONS Integral Nonlinearity (INL): The deviation from a straight Resolution (n): Defi nes the number of DAC output states line passing through the endpoints of the DAC transfer (2n) that divide the full-scale range. Resolution does not curve (Endpoint INL). Because the output cannot go imply linearity. below zero, the linearity is measured between full scale Voltage Offset Error (V ): Nominally, the voltage at the OS and the lowest code that guarantees the output will be output when the DAC is loaded with all zeros. A single greater than zero. The INL error at a given input code is supply DAC can have a true negative offset, but the output calculated as follows: cannot go below zero (see Applications Information). INL = [V – V – (V – V )(code/1023)]/LSB OUT OS FS OS For this reason, single supply DAC offset is measured at Where V is the output voltage of the DAC measured the lowest code that guarantees the output will be greater OUT at the given input code. than zero. Least Signifi cant Bit (LSB): The ideal voltage difference between two successive codes. LSB = V /1024 REF APPLICATIONS INFORMATION Write Word Protocol Used by the LTC1663 1 7 1 1 8 1 8 1 8 1 1 S Slave Address Wr A Command Byte A LSData Byte A MSData Byte A P S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition 1663 TA03 Serial Digital Interface When the master has fi nished communicating with the slave, it issues a STOP condition. A STOP condition is The LTC1663 communicates with a host (master) using generated by transitioning SDA from low to high while the standard 2-wire interface. The Timing Diagram shows SCL is high. The bus is then free for communication with the timing relationship of the signals on the bus. The two another SMBus device. bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources, Acknowledge such as the LTC1694 SMBus Accelerator, are required on these lines. The Acknowledge signal is used for handshaking between the master and the slave. An Acknowledge (active LOW) The LTC1663 is a receive-only (slave) device. The master generated by the slave lets the master know that the latest can communicate with the LTC1663 using the Quick Com- byte of information was received. The Acknowledge related mand, Send Byte or Write Word protocols as explained clock pulse is generated by the master. The master releases later. the SDA line (HIGH) during the Acknowledge clock pulse. The slave-receiver must pull down the SDA line during the The START and STOP Conditions Acknowledge clock pulse so that it remains a stable LOW When the bus is not in use, both SCL and SDA must be during the HIGH period of this clock pulse. high. A bus master signals the beginning of a communica- tion to a slave device by transmitting a START condition. Write Word Protocol A START condition is generated by transitioning SDA The master initiates communication with the LTC1663 with from high to low while SCL is high. a START condition and a 7-bit address followed by the Write 1663fd 7

LTC1663 APPLICATIONS INFORMATION Bit (Wr) = 0. The LTC1663 acknowledges and the master Command Byte delivers the command byte. The LTC1663 acknowledges 7 6 5 4 3 2 1 0 and latches the command byte into the command byte X X X X X BG SD SY input register. The master then delivers the least signifi cant data byte. Again the LTC1663 acknowledges and the data SY 1 Allows update on Acknowledge of SYNC Address only is latched into the least signifi cant data byte input register. 0 Update on Stop condition only (Power-On Default) The master then delivers the most signifi cant data byte. SD 1 Puts the device in power-down mode The LTC1663 acknowledges once more and latches the 0 Puts the device in standard operating mode data into the most signifi cant data byte input register. (Power-On Default) Lastly, the master terminates the communication with a BG 1 Selects the internal bandgap reference 0 Selects the supply as the reference (Power-On Default) STOP condition. On the reception of the STOP condition, X X Don’t Care the LTC1663 transfers the input register information to output registers and the DAC output is updated. The stop condition normally initiates the update of the Slave Address (MSOP Package Only) DAC’s output latches. Simultaneous update of more than one DAC or other devices on the bus can be achieved by The LTC1663 can respond to one of eight 7-bit addresses. reissuing new start bit, address, command and data bytes The fi rst 4 bits (MSBs) have been factory programmed to before issuing a fi nal stop condition (which will update 0100. The fi rst 4 bits of the LTC1663-8 have been factory all the devices). An alternate way to achieve simultaneous programmed to 0011. The three address bits, AD2, AD1 LTC1663 updates is to override the stop condition update and AD0 are programmed by the user and determine the by setting the “SY” bit of the command byte. Setting this LSBs of the slave address, as shown in the table below: bit sets the device to update the DAC output latches only LTC1663 LTC1663-8 at the reception of a SYNC address quick command. The AD2 AD1 AD0 0100 xxx 0011 xxx actual update occurs on the rising edge of SCL during the Acknowledge. In this way, all devices can update on the L L L 0100 000 0011 000 reception of the SYNC address quick command instead L L H 0100 001 0011 001 of the STOP condition. L H L 0100 010 0011 010 L H H 0100 011 0011 011 A Shutdown (SD) bit = HIGH will put the device in a low H L L 0100 100 0011 100 power state but retain all data latch information. Shutdown H L H 0100 101 0011 101 will occur at the reception of a STOP condition. This way H H L 0100 110 0011 110 shutdown could be synchronized to other devices. The H H H 0100 111 0011 111 output impedance of the DAC will go to a high impedance state (≈500kΩ to GND). Slave Address (SOT-23 Package) The Bandgap (BG) bit when set to “0” selects the DAC The slave address for the SOT-23 package has been supply voltage as its voltage reference. The full-scale factory programmed to be “0100 000” (LTC1663), output of the DAC with this setting is equal to the supply “0100 001” (LTC1663-1) and “0100 010” (LTC1663-2) If voltage. When the BG bit is set to “1,” the internal bandgap another address is required, please consult the factory. reference (≈1.25V) is selected as the DAC’s reference. The full-scale output voltage for this setting is 2.5V. 1663fd 8

LTC1663 APPLICATIONS INFORMATION Data Bytes The SY/CLR bit set high only has meaning when the “SY” bit of the command byte was previously set HIGH. On Least Signifi cant Data Byte the otherhand, the SY/CLR bit set LOW will always clear 7 6 5 4 3 2 1 0 the part, independent of the state of the “SY” bit in the D7 D6 D5 D4 D3 D2 D1 D0 command byte. Most Signifi cant Data Byte 7 6 5 4 3 2 1 0 Input Threshold X X X X X X D9 D8 Anticipating the trend toward lower supply voltages, X = Don’t care the SMBus is specifi ed with a V of 1.4V and a V of IH IL 0.6V. While some SMBus parts may violate this stringent Send Byte Protocol SMBus specifi cation by allowing a higher V value for a IH The Send Byte protocol used on the LTC1663 is actually a correspondingly higher input supply voltage, the LTC1663 subset of the Write Word protocol described previously. meets and maintains the constant SMBus input threshold The Send Byte protocol can only be used to send the specifi cation across the entire supply voltage range of command byte information to the LTC1663. 2.7V to 5.5V. The logic input threshold is designed to be 1 7 1 1 8 1 1 1V with 50mV of hysteresis. S Slave Address Wr A Command Byte A P S = Start Condition, Wr = Write Bit, A = Acknowledge, P = Stop Condition Voltage Output 1663 TA04 The output amplifi er contained in the LTC1663 can source The Send Byte protocol is also used whenever the Write or sink up to 5mA. The output stage swings to within a Word protocol is interrupted for any reason. Reception of few millivolts of either supply rail when unloaded and a START or STOP condition after the Acknowledge of the has an equivalent output resistance of 85Ω when driving command byte, but before the Acknowledge of the last a load to the rails. The output amplifi er is stable driving data byte, will cause both data bytes to be ignored and capacitive loads up to 1000pF. the command byte to be accepted. A small resistor placed in series with the output can be Reception of a START or STOP condition before the Ac- used to achieve stability for any load capacitance greater knowledge of the command byte will cause the interrupted than 1000pF. For example, a 0.1μF load can be driven command byte to be ignored. by the LTC1663 if a 110Ω series resistance is used. The phase margin of the resulting circuit is 45° and increases SYNC Address/Quick Command monotonically from this point if larger values of resistance, In addition to the slave address, the LTC1663 has an address capacitance or both are substituted for the values given. that can be shared by other devices so that they may be Rail-to-Rail Output Considerations updated synchronously. The address is called to the SYNC address and uses the quick command protocol. As in any rail-to-rail device, the output is limited to volt- ages within the supply range. The SYNC Address is 1111 110 If the DAC offset is negative, the output for the lowest 1 7 1 1 1 codes limits at 0V as shown in Figure 1b. Start 1111 110 SY/CLR Ack Stop SYNC Address 1663 TA05 Similarly, limiting can occur near full scale when V is CC used as the reference. If V = V and the DAC full-scale REF CC SY/CLR 1 Update output latches on rising edge of SCL during error (FSE) is positive, the output for the highest codes Acknowledge of SYNC Address 0 Clear all internal latches on rising edge of SCL during limits at VCC as shown in Figure 1c. No full-scale limiting Acknowledge of SYNC Address can occur if the internal reference is used. 1663fd 9

LTC1663 APPLICATIONS INFORMATION POSITIVE VREF = VCC FSE OUTPUT VOLTAGE INPUT CODE (c) VREF = VCC OUTPUT VOLTAGE 0 512 1023 INPUT CODE (a) OUTPUT VOLTAGE 0V NEGATIVE INPUT CODE OFFSET (b) 1663 F01 Figure 1. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V = V REF CC Offset and linearity are defi ned and tested over the region used. The LT1460 is ideal for use as a power supply for of the DAC transfer function where no output limiting can the LTC1663 and can provide 3V, 3.3V and 5V full-scale occur. output voltage ranges. The LT1460 provides accuracy, noise immunity and extended supply range to the LTC1663 when Internal Reference the LTC1663 is operated ratiometric to V . Since both CC parts are available in SOT-23 packages, the PC board space In applications where a predictable output is required for this application is extremely small. See Figure 2. that is independent of supply voltage, the LTC1663 has a user-selectable internal reference. Selecting the internal reference will set the full-scale output voltage to 2.5V. This LT1460S3-3 1 2 3V can be useful in applications where the supply voltage is 3.9V TO 20V IN OUT + 0.1μF GND 0.01μF poorly regulated. 3 4 (5) VCC 5 (4) UPosiwnegr tSheu pLpTl®y1 f4o6r0 t hMei LcTroCp1o6w63er Series Reference as a μTOP 1 (1) SSCDLA LTC1663 OUT 3 (8)0V≤ VOUT≤ 3V GND LTC1663 PIN NUMBERS IN PARENTHESES 2 (7) In applications where the advantages of using the internal REFER TO MSOP PACKAGE 1663 F02 reference are required but the full-scale range needs to be greater than 2.5V, an external series reference can be Figure 2. LT1460 As Power Supply for the LTC1663 1663fd 10

LTC1663 PACKAGE DESCRIPTION S5 Package 5-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1635) 0.62 0.95 MAX REF 2.90 BSC (NOTE 4) 1.22 REF 1.50 – 1.75 3.85 MAX2.62 REF 1.4 MIN 2.80 BSC (NOTE 4) PIN ONE RECOMMENDED SOLDER PAD LAYOUT 0.95 BSC 0.30 – 0.45 TYP PER IPC CALCULATOR 5 PLCS (NOTE 3) 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 1.90 BSC NOTE: (NOTE 3) S5 TSOT-23 0302 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) 0.889 ± 0.127 3.00 ± 0.102 (.035 ± .005) (.118 ± .004) 0.52 (NOTE 3) 8 7 6 5 (.0205) REF 5.23 (.M20IN6) (3.1.2206 –– 3.1.4356) 4.90 ± 0.152 3.00 ± 0.102 0.254 DETAIL “A” (.193 ± .006) (.1(1N8O ±TE . 040)4) (.010) 0° – 6° TYP 0.42 ± 0.038 0.65 GAUGE PLANE (.0165 ± .0015) (.0256) TYP BSC 1 2 3 4 0.53 ± 0.152 RECOMMENDED SOLDER PAD LAYOUT (.021 ± .006) 1.10 0.86 (.043) (.034) DETAIL “A” MAX REF 0.18 (.007) SEATING N1.O DTIEM:ENSIONS IN MILLIMETER/(INCH) PLANE 0.22 – 0.38 0.127 ± 0.076 23.. DDRIMAEWNISNIGO NN ODTO ETSO NSOCAT LIENCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. (.009T Y–P .015) (.00.26556) (.0M0S5OP ±(M S.08) 002304) MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE BSC 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 1663fd Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 11 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1663 TYPICAL APPLICATION Program Up to 8 Control Outputs Per BUS (8 LTC1663 and 8 LTC1663-8 DACs) and Place Them Where They Are Needed μP VCC = 2.7V TO 5.5V SDA SCL 1 5 VCC SMBus 1 + LTC1694 0.1μF 4 SMBus 2 GND 2 + + 5 5 4 0.1μF 4 0.1μF 1 SCL VCC 1 SCL VCC SDA SDA 6 ADL0TC1663-8CMS8VOUT 8 COOUNTPTRUOT L0 6 AD0LTC1663CMS8 VOUT 8 COOUNTPTRUOT L8 2 2 3 AD1 0V≤ VOUT0 < VCC 3 AD1 0V≤ VOUT8 < VCC AD2 GND AD2 GND 7 7 + + 5 5 4 0.1μF 4 0.1μF 1 SCL VCC 1 SCL VCC SDA SDA 62 ADL0TC1663-8CMS8VOUT 8 COOUNTPTRUOT L1 62 AD0LTC1663CMS8 VOUT 8 COOUNTPTRUOT L9 3 AD1 0V≤ VOUT1 < VCC 3 AD1 0V≤ VOUT9 < VCC AD2 GND AD2 GND 7 7 + + 5 5 4 0.1μF 4 0.1μF 1 SCL VCC 1 SCL VCC SDA SDA 6 ADL0TC1663-8CMS8VOUT 8 COOUNTPTRUOT L7 6 AD0LTC1663CMS8 VOUT 8 COOUNTPTRUOT L15 2 2 3 AD1 0V≤ VOUT7 < VCC 3 AD1 0V≤ VOUT15 < VCC AD2 GND AD2 GND TO OTHER SMBus 7 TO OTHER SMBus 7 DEVICES DEVICES 1663 TA06 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1694 SMBus I2C Accelerator Dual SMBus Accelerator with Active AC and DC Pull-Up Current Sources LTC1694-1 SMBus I2C Accelerator Dual SMBus Accelerator with Active AC Pull-Up Current Only DACs LTC1659 Single Rail-to-Rail 12-Bit V DAC in 8-Lead MSOP Low Power Multiplying V DAC. Output Swings from GND to REF. OUT OUT Package. V = 2.7V to 5.5V REF Input Can Be Tied to V . 3-Wire Interface. CC CC LTC1660/LTC1664 Octal/Quad 10-Bit V DACs in 16-Pin Narrow SSOP V = 2.7V to 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface OUT CC LTC1661 Dual 10-Bit V in 8-Lead MSOP Package V = 2.7V to 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface. OUT CC LTC1669 10-Bit V DAC in SOT-23, I2C Interface Pin-Compatible with LTC1663 OUT ADCs LTC1285/LTC1288 8-Pin SO, 3V Micropower ADCs 1- or 2-Channel, Autoshutdown LTC1286/LTC1298 8-Pin SO, 5V Micropower ADCs 1- or 2-Channel, Autoshutdown LTC1594/LTC1598 4/8-Channel, 5V Micropower 12-Bit ADCs Low Power, Small Size, Low Cost 1663fd 12 Linear Technology Corporation LT 1007 REV D • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: LTC1663ES5 LTC1663ES5#TRM LTC1663IMS8#TR LTC1663CS5 LTC1663-8CMS8#TR LTC1663CS5#TRM LTC1663-8IMS8#PBF LTC1663-1CS5#TRPBF LTC1663CMS8 LTC1663ES5#TRMPBF LTC1663-8CMS8#TRPBF LTC1663-2CS5#TR LTC1663-1CS5#TRM LTC1663-2CS5#TRPBF LTC1663-1CS5#PBF LTC1663CMS8#PBF LTC1663-8IMS8#TRPBF LTC1663-2CS5 LTC1663IMS8#TRPBF LTC1663CS5#PBF LTC1663-8CMS8 LTC1663CMS8#TR LTC1663-8CMS8#PBF LTC1663-1CS5 LTC1663-2CS5#PBF LTC1663CMS8#TRPBF LTC1663CS5#TRPBF LTC1663IMS8#PBF LTC1663-8IMS8 LTC1663IMS8 LTC1663ES5#TR LTC1663- 1CS5#TRMPBF LTC1663-1CS5#TR LTC1663CS5#TRMPBF LTC1663-2CS5#TRM LTC1663-8IMS8#TR LTC1663ES5#TRPBF LTC1663ES5#PBF LTC1663-2CS5#TRMPBF LTC1663CS5#TR