LTC1400 Complete SO-8, 12-Bit, 400ksps ADC with Shutdown FEATURES DESCRIPTIOU ■ Complete 12-Bit ADC in SO-8 The LTC®1400 is a complete 400ksps, 12-bit A/D converter ■ Single Supply 5V or ±5V Operation which draws only 75mW from 5V or ±5V supplies. This ■ Sample Rate: 400ksps easy-to-use device comes complete with a 200ns sample- ■ Power Dissipation: 75mW (Typ) and-hold and a precision reference. Unipolar and bipolar ■ 72dB S/(N + D) and –80dB THD at Nyquist conversion modes add to the flexibility of the ADC. The ■ No Missing Codes over Temperature LTC1400 has two power saving modes: Nap and Sleep. ■ Nap Mode with Instant Wake-Up: 6mW In Nap mode, it consumes only 6mW of power and can ■ Sleep Mode: 30μW wake up and convert immediately. In the Sleep mode, it ■ High Impedance Analog Input consumes 30μW of power typically. Upon power-up from ■ Input Range (1mV/LSB): 0V to 4.096V or ±2.048V Sleep mode, a reference ready (REFRDY) signal is available ■ Internal Reference Can Be Overdriven Externally in the serial data word to indicate that the reference has ■ 3-Wire Interface to DSPs and Processors (SPI and settled and the chip is ready to convert. MICROWIRETM Compatible) The LTC1400 converts 0V to 4.096V unipolar inputs from APPLICATIOUS a single 5V supply and ±2.048V bipolar inputs from ±5V supplies. Maximum DC specs include ±1LSB INL, ±1LSB ■ High Speed Data Acquisition DNL and 45ppm/°C drift over temperature. Guaranteed AC ■ Digital Signal Processing performance includes 70dB S/(N + D) and –76dB THD at ■ Multiplexed Data Acquisition Systems an input frequency of 100kHz, over temperature. ■ Audio and Telecom Processing The 3-wire serial port allows compact and efficient data ■ Digital Radio transfer to a wide range of microprocessors, microcon- ■ Spectrum Analysis trollers and DSPs. ■ Low Power and Battery-Operated Systems ■ Handheld or Portable Instruments , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATIOU Single 5V Supply, 400kHz, 12-Bit Sampling A/D Converter Power Consumption vs Sample Rate 100 5V NORMAL CONVERSION 10 + VCC VSS mA) NAP MODE 10µF 0.1µF NT ( 1 BETWEEN CONVERSION LTC1400 MPU RE R A(0NVA LTOOG 4 .I0N9P6UVT) AIN CONV P1.4 Y CU 0.1 SBLEETEWPE AENN DC ONNAVPE MROSIDOEN L P 2.42V REFOUT + VREF CLK P1.3 SUP SCLOENEVPE RMSOIDOEN BETWEEN 10µF 0.1µF GND DOUT P1.2 0.01 SERIAL 6.4MHz CLOCK DATA LINK 1400 TA01 0.001 0.01 0.1 1 10 100 1k 10k 100k 1M SAMPLE RATE (Hz) 1400 TA02 1400fa 1

LTC1400 ABSOLUTE WAXIWUW RATIUGS PACKAGE/ORDER IUFORWATIOU (Note 1, 2) TOP VIEW Supply Voltage (V ) ..................................................7V CC Negative Supply Voltage (VSS) .....................–6V to GND VCC 1 8 VSS Total Supply Voltage (VCC to VSS) AIN 2 7 CONV Bipolar Operation Only ..........................................12V VREF 3 6 CLK Analog Input Voltage (Note 3) GND 4 5 DOUT Unipolar Operation ....................–0.3V to (VCC + 0.3V) S8 PACKAGE Bipolar Operation ...........(V – 0.3V) to (V + 0.3V) 8-LEAD PLASTIC SO SS CC TJMAX = 150°C, θJA = 130°C/W Digital Input Voltage (Note 4) ORDER PART NUMBER S8 PART MARKING Unipolar Operation .................................–0.3V to 12V Bipolar Operation .........................(VSS – 0.3V) to 12V LTC1400CS8 1400 Digital Output Voltage LTC1400IS8 1400I Unipolar Operation ....................–0.3V to (V + 0.3V) CC Order Options Tape and Reel: Add #TR Bipolar Operation ...........(V – 0.3V) to (V + 0.3V) SS CC Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Power Dissipation ..............................................500mW Lead Free Part Marking: http://www.linear.com/leadfree/ Operation Temperature Range Consult LTC Marketing for parts specified with wider operating temperature ranges. LTC1400C ................................................0°C to 70°C LTC1400I .............................................–40°C to 85°C Storage Temperature Range ...................–65°C to 150°C Lead Temperature (Soldering, 10 sec) ..................300°C POWER REQUIREW E U TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C unless otherwise noted. (Note 5) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Positive Supply Voltage (Note 6) Unipolar 4.75 5.25 V CC Bipolar 4.75 5.25 V V Negative Supply Voltage (Note 6) Bipolar Only –2.45 –5.25 V SS I Positive Supply Current f = 400ksps ● 15 30 mA CC SAMPLE Nap Mode ● 1.0 3.0 mA Sleep Mode ● 5.0 20.0 μA I Negative Supply Current f = 400ksps, V = –5V ● 0.3 0.6 mA SS SAMPLE SS Nap Mode ● 0.2 0.5 mA Sleep Mode ● 1 5 μA P Power Dissipation f = 400ksps ● 75 160 mW D SAMPLE Nap Mode ● 6 20 mW Sleep Mode ● 30 125 μW AU ALOG IU PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C unless otherwise noted. (Note 5) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Analog Input Range (Note 7) 4.75V ≤ V ≤ 5.25V (Unipolar) ● 0 to 4.096 V IN CC 4.75V ≤ V ≤ 5.25V, –5.25V ≤ V ≤ –2.45V (Bipolar) ● ±2.048 V CC SS IIN Analog Input Leakage Current During Conversions (Hold Mode) ● ±1 μA C Analog Input Capacitance Between Conversions (Sample Mode) 45 pF IN During Conversions (Hold Mode) 5 pF 1400fa 2

LTC1400 COU VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C unless otherwise noted. With internal reference (Notes 5, 8) A PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) ● 12 Bits Integral Linearity Error (Note 9) ● ±1 LSB Differential Linearity Error ● ±1 LSB Offset Error (Note 10) ±6 LSB ● ±8 LSB Full-Scale Error ±15 LSB Full-Scale Tempco I = 0 ● ±10 ±45 ppm/°C OUT(REF) DYU AW IC ACCURACY The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 5V, V = –5V, f = 400kHz unless otherwise noted. (Note 5) A CC SS SAMPLE SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS S/(N + D) Signal-to-Noise 100kHz Input Signal Commercial ● 70 72 dB Plus Distortion Ratio Industrial ● 69 dB 200kHz Input Signal 72 dB THD Total Harmonic Distortion 100kHz Input Signal ● –82 –76 dB Up to 5th Harmonic 200kHz Input Signal –80 dB Peak Harmonic or 100kHz Input Signal ● –84 –76 dB Spurious Noise 200kHz Input Signal –82 dB IMD Intermodulation Distortion f = 99.51kHz, f = 102.44kHz –82 dB IN1 IN2 f = 199.12kHz, f = 202.05kHz –70 dB IN1 IN2 Full Power Bandwidth 4 MHz Full Linear Bandwidth (S/(N + D) ≥ 68dB) 900 kHz IU TERU AL REFEREU CE CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C unless otherwise noted. (Note 5) A PARAMETER CONDITIONS MIN TYP MAX UNITS V Output Voltage I = 0 2.400 2.420 2.440 V REF OUT V Output Tempco I = 0 ● ±10 ±45 ppm/°C REF OUT V Load Regulation 4.75V ≤ V ≤ 5.25V 0.01 LSB/V REF CC –5.25V ≤ V ≤ 0V 0.01 LSB/V SS V Load Regulation 0 ≤ |I | ≤ 1mA 2 LSB/mA REF OUT VREF Wake-Up Time from Sleep Mode (Note 7) CVREF = 10μF 4 ms DIGITAL I U PUTS AU D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C unless otherwise noted. (Note 5) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V High Level Input Voltage V = 5.25V ● 2.0 V IH CC V Low Level Input Voltage V = 4.75V ● 0.8 V IL CC IIN Digital Input Current VIN = 0V to VCC ● ±10 μA C Digital Input Capacitance 5 pF IN VOH High Level Output Voltage VCC = 4.75V, IO = –10μA 4.7 V VCC = 4.75V, IO = –200μA ● 4.0 V 1400fa 3

LTC1400 DIGITAL I U PUTS AU D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C unless otherwise noted. (Note 5) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOL Low Level Output Voltage VCC = 4.75V, IO = 160μA 0.05 V V = 4.75V, I = 1.6mA ● 0.10 0.4 V CC O IOZ Hi-Z Output Leakage DOUT VOUT = 0V to VCC ● ±10 μA C Hi-Z Output Capacitance D (Note 7) 15 pF OZ OUT I Output Source Current V = 0V –10 mA SOURCE OUT I Output Sink Current V = V 10 mA SINK OUT CC TI W I U G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C unless otherwise noted. (Note 5) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f Maximum Sampling Frequency (Note 6) ● 400 kHz SAMPLE(MAX) tCONV Conversion Time fCLK = 6.4MHz ● 2.1 μs t Acquisition Time (Unipolar Mode) (Note 7) ● 230 300 ns ACQ (Bipolar Mode V = –5V) ● 200 270 ns SS f CLK Frequency ● 0.1 6.4 MHz CLK t CLK Pulse Width (Notes 7, 12) ● 50 ns CLK t Time to Wake Up from Nap Mode (Note 7) 350 ns WK(NAP) t CLK Pulse Width to Return to Active Mode ● 50 ns 1 t2 CONV↑ to CLK↑ Setup Time ● 80 ns t3 CONV↑ After Leading CLK↑ ● 0 ns t CONV Pulse Width (Note 11) ● 50 ns 4 t5 Time from CLK↑ to Sample Mode (Note 7) 80 ns t Aperture Delay of Sample-and-Hold Jitter < 50ps (Note 7) ● 45 65 ns 6 t Minimum Delay Between Conversion (Unipolar Mode) ● 265 385 ns 7 (Bipolar Mode V = –5V) ● 235 355 ns SS t8 Delay Time, CLK↑ to DOUT Valid CLOAD = 20pF ● 40 80 ns t9 Delay Time, CLK↑ to DOUT Hi-Z CLOAD = 20pF ● 40 80 ns t10 Time from Previous Data Remains Valid After CLK↑ CLOAD = 20pF ● 14 25 ns t Minimum Time between Nap/Sleep Request to Wake Up Request (Notes 7, 12) ● 50 ns 11 Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 7: Guaranteed by design, not subject to test. may cause permanent damage to the device. Exposure to any Absolute Note 8: Linearity, offset and full-scale specifications apply for unipolar and Maximum Rating condition for extended periods may affect device bipolar modes. reliability and lifetime. Note 9: Integral nonlinearity is defined as the deviation of a code from a Note 2: All voltage values are with respect to GND. straight line passing through the actual endpoints of the transfer curve. Note 3: When these pin voltages are taken below V (ground for unipolar The deviation is measured from the center of the quantization band. SS mode) or above VCC, they will be clamped by internal diodes. This product Note 10: Bipolar offset is the offset voltage measured from –0.5LSB when can handle input currents greater than 40mA below VSS (ground for the output code flickers between 0000 0000 0000 and 1111 1111 1111. unipolar mode) or above V without latch-up. CC Note 11: The rising edge of CONV starts a conversion. If CONV returns Note 4: When these pin voltages are taken below VSS (ground for unipolar low at a bit decision point during the conversion, it can create small errors. mode), they will be clamped by internal diodes. This product can handle For best performance ensure that CONV returns low either within 120ns input currents greater than 40mA below VSS (ground for unipolar mode) after conversion starts (i.e., before the first bit decision) or after the 14 without latch-up. These pins are not clamped to VCC. clock cycle. (Figure 13 Timing Diagram). Note 5: VCC = 5V, fSAMPLE = 400kHz, tr = tf = 5ns unless otherwise Note 12: If this timing specification is not met, the device may not respond specified. to a request for a conversion. To recover from this condition a NAP Note 6: Recommended operating conditions. request is required. 1400fa 4

LTC1400 TYPICAL PERFORW AU CE CHARACTERISTICS Differential Nonlinearity vs Integral Nonlinearity vs S/(N + D) vs Input Frequency Output Code Output Code and Amplitude 1.00 1.00 80 fSAMPLE = 400kHz fSAMPLE = 400kHz VIN = 0dB TIAL NONLINEARITY (LSBs) –0000....752250505 AL NONLINEARITY (LSBs) –0000....752250505 NOISE + DISTORTION) (dB) 7654300000 VIN = –20dB EREN –0.50 TEGR –0.50 NAL/( 20 VIN = –60dB DIFF –0.75 IN –0.75 SIG 10 fSAMPLE = 400kHz –1.00 –1.00 0 0 512 1024153620482560307235844096 0 512 1024153620482560307235844096 10 100 1000 OUTPUT CODE OUTPUT CODE INPUT FREQUENCY (kHz) 1400 TPC01 1400 TPC02 1400 TPC06 Signal-to-Noise Ratio (Without Peak Harmonic or Spurious Noise Acquisition Time vs Harmonics) vs Input Frequency vs Input Frequency Source Impedance 80 0 4500 70 dB) –10 fSAMPLE = 400kHz 4000 TA = 25°C B) GE ( –20 3500 AL-TO-NOISE RATIO (d 65430000 S-FREE DYNAMIC RAN –––––3456700000 CQUISITION TIME (ns)3221050500000000 SIGN 20 RIOU –80 A1000 10 fSAMPLE = 400kHz SPU –90 500 0 –100 0 10 100 1000 10 100 1000 10 100 1000 10000 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) RSOURCE (Ω) 1400 TPC08 1400 TPC05 1400 TPC07 Reference Voltage vs Power Supply Feedthrough vs Load Current Ripple Frequency Supply Current vs Temperature B) 22.,443350 UGH (d –100 fSAMPLE = 400kHz 20 fSAMPLE = 400kHz O NCE VOLTAGE (V)2222....444422115050 ER SUPPLY FEEDTHR –––––2345600000 VSS (VRIPPLE = 10mV) Y CURRENT (mA) 1150 REFERE22..440050 OF POW ––7800 SUPPL 5 2.395 UDE –90 VCC (VRIPPLE = 1mV) T 2.390 MPLI–100 0 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 A 1 10 100 1000 –50 –25 0 25 50 75 100 125 LOAD CURRENT (mA) RIPPLE FREQUENCY (kHz) TEMPERATURE (°C) 1400 TPC07.5 1400 TPC03 1400 TPC04 1400fa 5

LTC1400 PIU FUUCTIOUS V (Pin 1): Positive Supply, 5V. Bypass to GND (10μF CLK (Pin 6): Clock. This clock synchronizes the serial data CC tantalum in parallel with 0.1μF ceramic). transfer. A minimum CLK pulse of 50ns will cause the ADC to wake up from Nap or Sleep mode. A (Pin 2): Analog Input. 0V to 4.096V (Unipolar), ±2.048V IN (Bipolar). CONV (Pin 7): Conversion Start Signal. This active high signal starts a conversion on its rising edge. Keeping CLK V (Pin 3): 2.42V Reference Output. Bypass to GND REF low and pulsing CONV two/four times will put the ADC (10μF tantalum in parallel with 0.1μF ceramic). into Nap/Sleep mode. GND (Pin 4): Ground. GND should be tied directly to an V (Pin 8): Negative Supply. –5V for bipolar operation. analog ground plane. SS Bypass to GND with 0.1μF ceramic. V should be tied to SS DOUT (Pin 5): The A/D conversion result is shifted out GND for unipolar operation. from this pin. FUU CTIOU AL BLOCK DIAGRAW CSAMPLE ZEROING SWITCH AIN VCC GND VSS VREF 2.42V REF 12-BIT CAPACITIVE DAC COMP CLK CONTROL 12 LOGIC CONV SUCCESSIVE APPROXIMATION REGISTER/PARALLEL TO DOUT SERIAL CONVERTER 1400 BD01 TEST CIRCUITS 5V 3k DOUT DOUT 3k CLOAD CLOAD Hi-Z TO VOH Hi-Z TO VOL VOL TO VOH VOH TO VOL VOH TO Hi-Z VOL TO Hi-Z 1400 TC01 1400fa 6

LTC1400 APPLICATIOU S IU FORW ATIOU Conversion Details Dynamic Performance The LTC1400 uses a successive approximation algorithm The LTC1400 has excellent high speed sampling capability. and an internal sample-and-hold circuit to convert an FFT (Fast Fourier Transform) test techniques are used to analog signal to a 12-bit serial output based on a preci- test the ADC’s frequency response, distortion and noise sion internal reference. The control logic provides easy at the rated throughput. By applying a low distortion interface to microprocessors and DSPs through 3-wire sine wave and analyzing the digital output using an FFT connections. algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 2a shows a A rising edge on the CONV input starts a conversion. At typical LTC1400 FFT plot. the start of a conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun Signal-to-Noise Ratio it cannot be restarted. The signal-to-noise plus distortion ratio [S/(N + D)] is the During conversion, the internal 12-bit capacitive DAC ratio between the RMS amplitude of the fundamental input output is sequenced by the SAR from the most significant frequency to the RMS amplitude of all other frequency bit (MSB) to the least significant bit (LSB). Referring to components at the A/D output. The output is band limited Figure 1, the A input connects to the sample-and-hold to frequencies from DC to half the sampling frequency. IN capacitor during the acquired phase and the comparator Figure 2a shows a typical spectral content with a 400kHz offset is nulled by the feedback switch. In this acquire sampling rate and a 100kHz input. The dynamic perfor- phase, it typically takes 200ns for the sample-and-hold mance is excellent for input frequencies up to the Nyquist capacitor to acquire the analog signal. During the convert limit of 200kHz as shown in Figure 2b. phase, the comparator feedback switch opens, putting the 0 comparator into the compare mode. The input switches –10 fSAMPLE = 400kHz connect C to ground, injecting the analog input fIN = 94.824kHz SAMPLE –20 SINAD = 72.5dB charge onto the summing junction. This input charge is –30 THD = –82dB successively compared with the binary-weighted charges B) –40 d supplied by the capacitive DAC. Bit decisions are made by DE ( –50 U –60 T the high speed comparator. At the end of a conversion, PLI –70 M the DAC output balances the A input charge. The SAR A –80 IN –90 contents (a 12-bit data word) which represent the input –100 voltage, are output through the serial pin D . OUT –110 –120 0 20 40 60 80 100120 140160180200 SAMPLE FREQUENCY (kHz) 1400 F02a S1 SAMPLE CSAMPLE Figure 2a. LTC1400 Nonaveraged, 4096 Point FFT AIN – Plot with 100kHz Input Frequency in Bipolar Mode COMP HOLD DAC + Effective Number of Bits CDAC The effective number of bits (ENOBs) is a measurement S of the effective resolution of an ADC and is directly related VDAC A R to the S/(N + D) by the equation: DOUT S/(N+D)–1.76 N= 1400 F01 6.02 Figure 1. A Input IN 1400fa 7

LTC1400 APPLICATIOUS IUFORWATIOU 0 –10 fSAMPLE = 400kHz V22+V32+V42+…Vn2 –20 fSININ =A D19 =9 .7122.11kdHBz THD=20log –30 THD = –80dB V1 dB) –40 where V1 is the RMS amplitude of the fundamental fre- E ( –50 UD –60 quency and V2 through Vn are the amplitudes of the second T PLI –70 through nth harmonics. THD vs input frequency is shown M A –80 in Figure 4. The LTC1400 has good distortion performance –90 up to the Nyquist frequency and beyond. –100 –110 –120 0 20 40 60 80 100120 140160180200 0 FREQUENCY (kHz) TAL) –10 fSAMPLE = 400kHz N 1400 F02b ME –20 A D Figure 2b. LTC1400 Nonaveraged, 4096 Point FFT N –30 U Plot with 200kHz Input Frequency in Bipolar Mode HE F –40 T W –50 where N is the effective number of bits of resolution and O L E –60 B S/(N + D) is expressed in dB. At the maximum sampling B d –70 3RD HARMONIC rate of 400kHz, the LTC1400 maintains very good ENOBs E ( THD UD –80 up to the Nyquist input frequency of 200kHz (refer to MPLIT –90 2ND HARMONIC Figure 3). A–100 10k 100k 1M INPUT FREQUENCY (Hz) 12 74 1400 F04 11 68 10 NYQUIST 62SIG Figure 4. Distortion vs Input Frequency in Bipolar Mode S FREQUENCY N UMBER OF BIT 9876 5560AL/(NOISE + D IInf ttheerm AoDdCu ilnaptiuotn s iDginsatol crtoinosnists of more than one spectral EFFECTIVE N 5432 ISTORTION) (d cpTorHomDdp.u oIcMne eDinn tti,se rttmhheeo dAcuDhlaaCnt igtorena nidnsi fsoetnro erft uisoninnc uti(soIMoni dDna)ol niinnli npaeudatd ricittaiyou ncs aetnod B 1 fSAMPLE = 400kHz ) by the presence of another sinusoidal input at a different 0 frequency. 10k 100k 1M INPUT FREQUENCY (Hz) If two pure sine waves of frequencies fa and fb are applied 1400 F03 to the ADC input, nonlinearities in the ADC transfer func- Figure 3. Effective Bits and Signal-to-Noise + tion can create distortion products at sum and difference Distortion vs Input Frequency in Bipolar Mode frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb) Total Harmonic Distortion and (fa – fb) while the 3rd order IMD terms includes (2fa Total harmonic distortion (THD) is the ratio of the RMS + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). If the two input sum of all harmonics of the input signal to the fundamental sine waves are equal in magnitude, the value (in decibels) itself. The out-of-band harmonics alias into the frequency of the 2nd order IMD products can be expressed by the band between DC and half of the sampling frequency. THD following formula. is expressed as: Amplitude at (fa ±fb) IMD(fa ±fb)=20log Amplitude at fa 1400fa 8

LTC1400 APPLICATIOUS IUFORWATIOU 0 settles in 200ns to small load current transient will allow –10 fSAMPLE = 400kHz fa = 99.512kHz maximum speed operation. If a slower op amp is used, –20 fb = 102.441kHz –30 fa fb more settling time can be provided by increasing the time B) –40 between conversions. Suitable devices capable of driving d PLITUDE ( –––567000 22ffaa +– ffbb 32fafbf a– +fa fb2fa tohpe aAmDpCs’s. AIN input include the LT®1360 and the LT1363 M 2fb + fa A –80 fb – fa 3fb 2fb LTC1400 comes with a built-in unipolar/bipolar detection –90 circuit. If V potential is forced below GND, the internal –100 SS –110 circuitry will automatically switch to bipolar mode. –120 0 20 40 60 80 100120 140160180200 The following list is a summary of the op amps that are FREQUENCY (kHz) suitable for driving the LTC1400, more detailed informa- 1400 F05 tion is available in the Linear Technology databooks or the Figure 5. Intermodulation Distortion Plot in Bipolar Mode Linear Technology Website. Figure 5 shows the IMD performance at a 100kHz input. LT1215/LT1216: Dual and quad 23MHz, 50V/μs single supply op amps. Single 5V to ±15V supplies, 6.6mA Peak Harmonic or Spurious Noise specifications, 90ns settling to 0.5LSB. The peak harmonic or spurious noise is the largest spectral LT1223: 100MHz video current feedback amplifier. ±5V component excluding the input signal and DC. This value to ±15V supplies, 6mA supply current. Low distortion up is expressed in decibels relative to the RMS value of a to and above 400kHz. Low noise. Good for AC applica- full-scale input signal. tions. LT1227: 140MHz video current feedback amplifier. ±5V to Full Power and Full Linear Bandwidth ±15V supplies, 10mA supply current. Lowest distortion The full power bandwidth is the input frequency at which at frequencies above 400kHz. Low noise. Best for AC the amplitude of the reconstructed fundamental is reduced applications. by 3dB for a full-scale input signal. LT1229/LT1230: Dual and quad 100MHz current feedback The full linear bandwidth is the input frequency at which amplifiers. ±2V to ±15V supplies, 6mA supply current each the S/(N + D) has dropped to 68dB (11 effective bits). The amplifier. Low noise. Good AC specs. LTC1400 has been designed to optimize input bandwidth, LT1360: 37MHz voltage feedback amplifier. ±5V to ±15V allowing the ADC to undersample input signals with fre- supplies. 3.8mA supply current. Good AC and DC specs. quencies above the converter’s Nyquist Frequency. The 70ns settling to 0.5LSB. noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far LT1363: 50MHz, 450V/μs op amps. ±5V to ±15V supplies. beyond Nyquist. 6.3mA supply current. Good AC and DC specs. 60ns settling to 0.5LSB. Driving the Analog Input LT1364/LT1365: Dual and quad 50MHz, 450V/μs op amps. The analog input of the LTC1400 is easy to drive. It draws ±5V to ±15V supplies, 6.3mA supply current per amplifier. only one small current spike while charging the sample- 60ns settling to 0.5LSB. and-hold capacitor at the end of a conversion. During conversion, the analog input draws only a small leakage Internal Reference current. The only requirement is that the amplifier driv- The LTC1400 has an on-chip, temperature compensated, ing the analog input must settle after the small current curvature corrected, bandgap reference, which is factory spike before the next conversion starts. Any op amp that 1400fa 9

LTC1400 APPLICATIOU S IU FORW ATIOU trimmed to 2.42V. It is internally connected to the DAC Unipolar/Bipolar Operation and Adjustment and is available at Pin 3 to provide up to 1mA of current to Figure 8 shows the ideal input/output characteristics for an external load. For minimum code transition noise, the the LTC1400. The code transitions occur midway between reference output should be decoupled with a capacitor to successive integer LSB values (i.e., 0.5LSB, 1.5LSB, filter wideband noise from the reference (10μF tantalum in 2.5LSB, … FS – 1.5LSB). The output code is straight parallel with a 0.1μF ceramic). The V pin can be driven REF binary with 1LSB = 4.096V/4096 = 1mV. Figure 9 shows with a DAC or other means to provide input span adjust- the input/output transfer characteristics for the bipolar ment in bipolar mode. The V pin must be driven to at REF mode in two’s complement format. least 2.45V to prevent conflict with the internal reference. The reference should not be driven to more than 5V. FS Figure 6 shows an LT1360 op amp driving the reference 111...111 1LSB =4096 111...110 pin. Figure 7 shows a typical reference, the LT1019A-5 111...101 connected to the LTC1400. This will provide an improved E 111...100 D drift (equal to the maximum 5ppm/°C of the LT1019A- O C T 5) and a ±4.231V full scale. If V is forced lower than U REF P T 2.42V, the REFRDY bit in the serial data output will be OU UNIPOLAR ZERO forced to low. 000...011 000...010 5V 000...001 000...000 ±0.84IN6P •U VTR REFA(ONUGTE) AIN VCC 0V LS1B FS – 1LSB INPUT VOLTAGE (V) + LTC1400 1400 F08 VREF(OUT) ≥ 2.45V LT1360 VREF Figure 8. LTC1400 Unipolar Transfer Characteristics – 3Ω 10µF GND VSS 011...111 011...110 BIPOLAR ZERO –5V 1400 F06 E 000...001 D Figure 6. Driving the VREF with the LT1360 Op Amp T CO 000...000 U P 111...111 T U O 111...110 5V 100...001 INPUT RANGE ±4.231V (= ±0.846 • VREF) AIN VCC 100...000 10V LTC1400 –FS/2 –1 0V 1 FS/2 – 1LSB VIN LSB LSB VOUT VREF INPUT VOLTAGE (V) 11400 F09 3Ω LT1019A-5 Figure 9. LTC1400 Bipolar Transfer Characteristics 10µF GND GND VSS Unipolar Offset and Full-Scale Error Adjustments –5V 1400 F07 In applications where absolute accuracy is important, Figure 7. Supplying a 5V Reference Voltage offset and full-scale errors can be adjusted to zero. Figure to the LTC1400 with the LT1019A-5 10a shows the extra components required for full-scale 1400fa 10

LTC1400 APPLICATIOU S IU FORW ATIOU R1 error adjustment. Figure 10b shows offset and full-scale 50Ω VIN + adjustment. Offset error must be adjusted before full- A1 AIN scale error. Zero offset is achieved by applying 0.5mV – (i.e., 0.5LSB) at the input and adjusting the offset trim R4 R2 100Ω until the LTC1400 output code flickers between 0000 10k LTC1400 0000 0000 and 0000 0000 0001. For zero full-scale er- R3 ror, apply an analog input of 4.0945V (FS – 1.5LSB or 10k FULL-SCALE ADJUST last code transition) at the input and adjust R5 until the GND LTC1400 output code flickers between 1111 1111 1110 ADDITIONAL PINS OMITTED FOR CLARITY and 1111 1111 1111. ±20LSB TRIM RANGE 1400 F10a Bipolar Offset and Full-Scale Error Adjustments Figure 10a. LTC1400 Full-Scale Adjust Circuit Bipolar offset and full-scale errors are adjusted in a similar R1 ANALOG 10k fashion to the unipolar case. Bipolar offset error adjust- INPUT + 0V TO 4.096V ment is achieved by applying an input voltage of –0.5mV R2 A1 AIN 10k 10k – R4 (–0.5LSB) to the input in Figure 10c and adjusting the 5V 100k op amp until the ADC output code flickers between 0000 LTC1400 R9 R5 0000 0000 and 1111 1111 1111. For full-scale adjustment, 20Ω 4.3k an input voltage of 2.0465V (FS – 1.5LSBs) is applied to FULL-SCALE ADJUST the input and R5 is adjusted until the output code flickers R3 between 0111 1111 1110 and 0111 1111 1111. 100k 5V R7 R8 100k 10k Board Layout and Bypassing OFFSET ADJUST R6 To obtain the best performance from the LTC1400, a 400Ω printed circuit board is required. Layout for the printed circuit board should ensure that digital and analog signal 1400 F10b lines are separated as much as possible. In particular, care Figure 10b. LTC1400 Offset and Full-Scale Adjust Circuit should be taken not to run any digital track alongside an R1 analog signal track or underneath the ADC. The analog ANALOG 10k INPUT + input should be screened by GND. ±2.048V R102k A1 AIN High quality tantalum and ceramic bypass capacitors – R4 100k should be used at the VCC and VREF pins as shown in the LTC1400 Typical Application on the first page of this data sheet. R5 4.3k For the bipolar mode, a 0.1μF ceramic provides adequate FULL-SCALE ADJUST bypassing for the V pin. For optimum performance, a SS R3 10μF surface mount AVX capacitor with a 0.1μF ceramic 100k 5V R7 R8 is recommended for the V and V pins. The capacitors 100k 20k CC REF OFFSET must be located as close to the pins as possible. The traces ADJUST connecting the pins and the bypass capacitors must be R6 200Ω –5V kept short and should be made as wide as possible. In unipolar mode operation, V should be isolated from 1400 F10c SS Figure 10c. LTC1400 Bipolar Offset and Full-Scale Adjust Circuit any noise source before shorting to the GND pin. 1400fa 11

LTC1400 APPLICATIOU S IU FORW ATIOU Input signal leads to A and signal return leads from GND the LTC1400 GND pin. The ground return from the LTC1400 IN (Pin 4) should be kept as short as possible to minimize Pin 4 to the power supply should be low impedance for noise coupling. In applications where this is not possible, a noise free operation. Digital circuitry grounds must be shielded cable between source and ADC is recommended. connected to the digital supply common. Also, since any potential difference in grounds between the In applications where the ADC data outputs and control sig- signal source and ADC appears as an error voltage in series nals are connected to a continuously active microprocessor with the input signal, attention should be paid to reducing bus, it is possible to get errors in the conversion results. the ground circuit impedance as much as possible. These errors are due to feedthrough from the micropro- cessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor ANALOG SUPPLY DIGITAL SUPPLY into a Wait state during conversion or by using three-state –5V GND 5V GND 5V buffers to isolate the ADC data bus. Power-Down Mode + + + Upon power-up, the LTC1400 is initialized to the active state and is ready for conversion. However, the chip can be easily placed into the Nap or Sleep mode by exercising VSS GND VCC GND VCC the right combination of CLK and CONV signal. In the Nap LTC1400 DIGITAL CIRCUITRY mode all power is off except the internal reference, which is 1400 F11 still active and provides 2.42V output voltage to the other Figure 11. Power Supply Connection circuitry. In this mode, the ADC draws only 6mW of power instead of 75mW (for minimum power, the logic inputs Figure 11 shows the recommended system ground connec- must be within 500mV of the supply rails). The wake-up tions. All analog circuitry grounds should be terminated at time from the Nap mode to the active mode is 350ns. t11 t11 CLK t1 t1 CONV NAP SLEEP VREF REFRDY 1400 F12 NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS. REFRDY APPEARS AS A BIT IN THE DOUT WORD. Figure 12. Nap Mode and Sleep Mode Waveforms 1400fa 12

LTC1400 APPLICATIOU S IU FORW ATIOU In the Sleep mode, power consumption is reduced to a Digital Interface minimum by cutting off the supply to all internal circuitry The digital interface requires only three digital lines. CLK including the reference. Figure 12 shows the ways to power and CONV are both inputs, and the D output provides OUT down the LTC1400. The chip can enter the Nap mode by the conversion result in serial form. keeping the CLK signal low and pulsing the CONV signal twice. For Sleep mode operation, CONV signal should be Figure 13 shows the digital timing diagram of the LTC1400 pulsed four times while CLK is kept low. during the A/D conversion. The CONV rising edge starts the conversion. Once initiated, it can not be restarted until The LTC1400 can be returned to active mode easily. The the conversion is completed. If the time from CONV signal rising edge of CLK will wake-up the LTC1400. During the to CLK rising edge is less than t , the digital output will 2 transition from Sleep mode to active mode, the V volt- REF be delayed by one clock cycle. age ramp-up time is a function of the loading conditions. With a 10μF bypass capacitor, the wake-up time from The digital output data is updated on the rising edge of the Sleep mode is typically 4ms. A REFRDY signal will be CLK line. DOUT data should be captured by the receiving activated once the reference has settled and is ready for system on the rising CLK edge. Data remains valid for a an A/D conversion. This REFRDY bit is output to the DOUT minimum time of t10 after the rising CLK edge to allow pin before the rest of the A/D converted code. capture to occur. t2 t3 t7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 CLK t4 t5 CONV t6 tACQ INTERNAL SAMPLE HOLD SAMPLE HOLD S/H STATUS t8 Hi-Z Hi-Z DOUT REFRDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 REFRDY tCONV tSAMPLE 1400 F13 Figure 13. ADC Digital Timing Diagram CLK VIH CLK VIH t8 t9 t10 VOH 90% DOUT DOUT VOL 10% 1400 F14 Figure 14. CLK to D Delay OUT 1400fa 13

LTC1400 TYPICAL APPLICATIOU S Hardware Interface to TMS320C50’s TDM Serial Port (Frame Sync is Generated from TFSX) TMS320C50 5V TCLKX 1 6 VCC CLK TCLKR + UNIPOLAR 2 7 TFSX 10µF 0.1µF INPUT AIN LTC140C0ONV TFSR 3 5 VREF DOUT TDR + VSS GND 10µF 0.1µF 8 4 1400 TA04a Logic Analyzer Waveforms Show 3.2μs Throughput Rate (Input Voltage = 3.046V, Output Code = 1011 1110 0110 = 3046 ) 10 Data from LTC1400 Loaded into TMS320C50’s TRCV Register X RDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 1400 TA05c Data Stored in TMS320C50’s Memory (in Right Justified Format) 0 0 0 RDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1400 TA05d 1400fa 14

LTC1400 TYPICAL APPLICATIOU S TMS320C50 Code for Circuit THIS PROGRAM DEMONSTRATES LTC1400 INTERFACE TO TMS320C50 *Start Serial Communication* FRAME SYNC PULSE IS GENERATED FROM TFSX SACL TDXR ; Generate frame sync pulse SPLK #040h, IMR ; Turn on TRNT receiver interrupt *Initialization* CLRC INTM ; Enable interrupt .mmregs ; Defines global symbolic names CLRC SXM ; For Unipolar input, set for right shift ;- - Initialized data memory to zero ; with no sign extension .ds 0F00h ; Initialize data to zero MAR *AR7 ; Load the auxiliary register pointer with seven DATA0 .word 0 ; Begin sample data location LAR AR7, #0F00h ; Load the auxiliary register seven with #0F00h DATA1 .word 0 ; . ; as the begin address for data storage DATA2 .word 0 ; Location of data WAIT: NOP ; Wait for a receive interrupt DATA3 .word 0 ; . NOP ; DATA4 .word 0 ; . NOP ; DATA5 .word 0 ; End sample data location SACL TDXR ; !! regenerate the frame sync pulse ;- - Set up the ISR vector B WAIT ; .ps 080Ah ; Serial ports interrupts ; - - - - - - - end of main program - - - - - - - - - - ; rint : B RECEIVE ; 0A; xint : B TRANSMIT ; 0C; *Receiver Interrupt Service Routine* trnt : B TREC ; 0E; TREC: txnt : B TTRANX ; 10; LAMM TRCV ; Load the data received from LTC1400 ;- - Setup the reset vector SFR ; Shift right two times .ps 0A00h SFR ; .entry AND #1FFFh, 0 ; ANDed with #1FFFh START: ; For converting the data to right *TMS32C050 Initialization* ; justified format SETC INTM ; Temporarily disable all interrupts ; LDP #0 ; Set data page pointer to zero SACL *+, 0 ; Write to data memory pointed by AR7 and OPL #0834h, PMST ; Set up the PMST status and control register ; increase the memory address by one LACC #0 LACC AR7 ; SAMM CWSR ; Set software wait state to 0 SUB #0F05h,0 ; Compare to end sample address #0F05h SAMM PDWSR ; BCND END_TRCV, GEQ ; If the end sample address has exceeded jump to END_TRCV *Configure Serial Port* ; SPLK #0038h, TSPC ; Set TDM Serial Port SPLK #040h, IMR ; Else Re-enable the TRNT receive interrupt ; TDM = 0 Stand Alone mode RETE ; Return to main program and enable interrupt ; DLB = 0 Not loop back ; FO = 0 16 Bits *After Obtained the Data from LTC1400, Program Jump to END_TRCV* ; FSM = 1 Burst Mode END_TRCV: ; MCM = 1 CLKX is generated internally SPLK #002h, IMR ; Enable INT2 for program to halt ; TXM = 1 FSX as output pin CLRC INTM ; Put serial port into reset SUCCESS: ; (XRST = RRST =0) B SUCCESS SPLK #00F8h, TSPC ; Take Serial Port out of reset ; (XRST = RRST = 1) *Fill the Unused Interrupt with RETE, to avoid program get “lost”* SPLK #0FFFFh, IFR ; Clear all the pending interrupts TTRANX: RETE RECEIVE: RETE TRANSMIT: RETE INT2: B halt ; Halts the running CPU 1400fa 15

LTC1400 TYPICAL APPLICATIOU S LTC1400 Interface to ADSP2181’s SPORT0 (Frame Sync is Generated from RFS0) 5V ADSP2181 1 6 VCC CLK SCLKO + UNIPOLAR 2 7 10µF 0.1µF INPUT AIN LTC140C0ONV RFSO 3 5 VREF DOUT DR0 + VSS GND 10µF 0.1µF 8 4 1400 TA05a Logic Analyzer Waveforms Show 2.88μs Throughput Rate (Input Voltage = 2.240V, Output Code = 1000 1100 0000 = 2240 ) 10 Data from LTC1400 (Normal Mode) X RDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 1400 TA05c Data Stored in ADSP2181’s Memory (Normal Mode, SLEN = D) 0 0 0 RDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1400 TA05d 1400fa 16

LTC1400 TYPICAL APPLICATIOU S ADSP2181 Code for Circuit THIS PROGRAM DEMONSTRATES LTC1400 INTERFACE TO ADSP-2181 /*Section 3: configure CLKDIV and RFSDIV, setup interrupts*/ FRAME SYNC PULSE IS GENERATED FROM RFS0 /*to configure CLKDIV reg*/ /*Section 1: Initialization*/ ax0 = 2; .module/ram/abs = 0 adspltc; /*define the program module*/ dm(0x3FF5) = ax0; /*set the serial clock divide modulus reg SCLKDIV*/ jump start; /*jump over interrupt vectors*/ /*the input clock frequency = 16.67MHz*/ nop; nop; nop; /*CLKOUT frequency = 2x = 33MHz*/ rti; rti; rti; rti; /*code vectors here upon IRQ2 int*/ /*SCLK= 1/2*CLKOUT*1/(SCLKDIV+1)*/ rti; rti; rti; rti; /*code vectors here upon IRQL1 int*/ /*for SCLKDIV = 2, SCLK = 33/6 = 5.5MHz*/ rti; rti; rti; rti; /*code vectors here upon IRQL0 int*/ /*to Configure RFSDIV*/ rti; rti; rti; rti; /*code vectors here upon SPORT0 TX int*/ ax0 = 15; /*set the RFSDIV reg = 15*/ ax0 = rx0; /*Section 5*/ /*= > the frame sync pulse for every 16 SCLK*/ dm (0x2000) = ax0; /*begin of SPORT0 receive interrupt*/ /*if frame sync pulse in every 15 SCLK, ax0 = 14*/ rti; /* */ dm(0x3FF4) = ax0; /* */ /*to setup interrupt*/ /*end of SPORT0 receive interrupt*/ ifc = 0x0066; /*clear any extraneous SPORT interrupts*/ rti; rti; rti; rti; /*code vectors here upon /IRQE int*/ icntl = 0; /*IRQXB = level sensitivity*/ rti; rti; rti; rti; /*code vectors here upon BDMA interrupt*/ /*disable nesting interrupt*/ rti; rti; rti; rti; /*code vectors here upon SPORT1 TX (IRQ1) int*/ imask= 0x0020; /*bit 0 = timer int = 0*/ rti; rti; rti; rti; /*code vectors here upon SPORT1 RX (IRQ0) int*/ /*bit 1 = SPORT1 or IRQ0B int = 0*/ rti; rti; rti; rti; /*code vectors here upon TIMER int*/ /*bit 2 = SPORT1 or IRQ1B int = 0*/ rti; rti; rti; rti; /*code vectors here upon POWER DOWN int*/ /*bit 3 = BDMA int = 0*/ /*Section 2: Configure SPORT0*/ /*bit 4 = IRQEB int = 0*/ start: /*bit 5 = SPORT0 receive int = 1*/ /*to configure SPORT0 control reg*/ /*bit 6 = SPORT0 transmit int = 0*/ /*SPORT0 address = 0X3FF6*/ /*bit 7 = IRQ2B int = 0*/ /*RFS is used for frame sync generation*/ /*enable SPORT0 receive interrupt*/ /*RFS0 is internal, TFS is not use*/ /*Section 4: Configure System Control Register and Start Communication*/ /*bit 0-3 = Slen*/ /*to configure system control reg*/ /*F = 15 = 1111*/ ax0 = dm(0x3FFF); /*read the system control reg*/ /*E = 14 = 1110*/ ay0 = 0xFFF0; /*D = 13 = 1101*/ ar = ax0 AND ay0; /*set wait state to zero*/ /*bit 4,5 data type right justified zero filled MSB*/ ay0 = 0x1000; /*bit 6 INVRFS = 0*/ ar = ar OR ay0; /*bit12 = 1, enable SPORT0*/ /*bit 7 INVTFS = 0*/ dm(0x3FFF) = ar; /*bit 8 IRFS = 1 receive internal frame sync*/ /*frame sync pulse regenerated automatically*/ /*bit 9,10,11 are for TFS (don’t care)*/ cntr = 5000; /*bit 12 TFSW = 1 receive is Normal mode*/ do waitloop until ce; /*bit 13 RTFS = 1 receive is framed mode*/ nop; /*bit 14 ISCLK internal = 1*/ nop; /*bit 15 multichannel mode = 0*/ nop; ax0 = 0x6B0D; /*normal mode, bit12 = 0*/ nop; /*if alternate mode bit12 = 1, ax0 = 0x7F0E*/ nop; dm (0x3FF6) =ax0; nop; waitloop: nop; rts; .endmod; 1400fa 17

LTC1400 TYPICAL APPLICATIOUS Quick Look Circuit for Converting Data to Parallel Format 5V 5V + 1 VCC VSS 8 10µF 0.1µF CONV LTC1400 10 7 12 SRCLR 15 A(0NVA LTOOG 4 .I0N9P6UVT) 2 AIN CONV RCK QQAB 1 DD01 2.42V 6 11 2 REFERENCE 3 VREF CLK SRCK QC 3 D2 OUTPUT + 4 5 14 74HC595QD 4 D3 10µF 0.1µF GND DOUT SER QE 5 D4 QF D5 13 6 G QG D6 7 QH D7 9 3-WIRE SERIAL QH' INTERFACE LINK 10 12 SRCLR 15 RCK QA D8 1 QB D9 11 2 CLK SRCK QC D10 3 14 74HC595QD 4 D11 SER QE REFRDY 5 QF 13 6 G QG 7 QH 9 QH' 1400 TA03 1400fa 18

BLOCK DIAGRAW LTC1400 PACKAGE DESCRIPTIOU Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.228 – 0.244 0.150 – 0.157** (5.791 – 6.197) (3.810 – 3.988) 1 2 3 4 0.010 – 0.020 × 45° 0.053 – 0.069 (0.254 – 0.508) (1.346 – 1.752) 0.004 – 0.010 0.008 – 0.010 (0.203 – 0.254) 0°– 8° TYP (0.101 – 0.254) 0.016 – 0.050 0.014 – 0.019 0.050 0.406 – 1.270 (0.355 – 0.483) (1.270) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH BSC SO8 0695 SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 1400fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 19 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1400 TYPICAL APPLICATIOU S LTC1400 Interface to TMS320C50 TMS320C50 5V TCLKX 1 6 VCC CLK TCLKR + UNIPOLAR 2 7 TFSX 10µF 0.1µF INPUT AIN LTC140C0ONV TFSR 3 5 VREF DOUT TDR + VSS GND 10µF 0.1µF 8 4 1400 TA04a LTC1400 Interface to ADSP2181 5V ADSP2181 1 6 VCC CLK SCLKO + UNIPOLAR 2 7 10µF 0.1µF INPUT AIN LTC140C0ONV RFSO 3 5 VREF DOUT DR0 + VSS GND 10µF 0.1µF 8 4 1400 TA05a RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1285/LTC1288 12-Bit, 3V, 7.5/6.6ksps, Micropower Serial ADCs 0.48mW, 1 or 2 Channel Input, SO-8 LTC1286/LTC1298 12-Bit, 5V 12.5/11.16ksps, Micropower Serial ADCs 1.25mW, 1 or 2 Channel Input, SO-8 LTC1290 12-Bit, 50ksps 8-Channel Serial ADC 5V or ± 5V Input Range, 30mW, Full-duplex LTC1296 12-Bit, 46.5ksps 8-Channel Serial ADC 5V or ± 5V Input Range, 30mW, Half-duplex LTC1403/LTC1403A 12-/14-Bit, 2.8Msps Serial ADCs 3V, 15mW, MSOP Package LTC1407/LTC1407A 12-/14-Bit, 3Msps Simultaneous Sampling ADCs 3V, 14mW, 2-Channel Differential Inputs, MSOP Package LTC1417 14-Bit, 400ksps Serial ADC 5V or ± 5V, 20mW, Internal Reference, SSOP-16 LTC1609 16-Bit, 200ksps Serial ADC 5V, Configurable Bipolar or Unipolar Inputs to ±10V LTC1860L/LTC1861L 12-Bit, 3V, 150ksps Serial ADCs 1.22mW, 1-/2-Channel Inputs, MSOP and SO-8 LTC1860/LTC1861 12-Bit, 5V, 250ksps Serial ADCs 4.25mW, 1-/2-Channel Inputs, MSOP and SO-8 LTC1864L/LTC1864L 16-Bit, 3V, 150KSPS Serial ADCs 1.22mW, 1-/2-Channel Inputs, MSOP and SO-8 LTC1864/LTC1864 16-Bit, 5V, 250ksps Serial ADCs 4.25mW, 1-/2-Channel Inputs, MSOP and SO-8 1400fa 20 Linear Technology Corporation LT 0606 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2006

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: LTC1400IS8 LTC1400IS8#TRPBF LTC1400IS8#PBF LTC1400CS8#PBF LTC1400CS8#TR LTC1400IS8#TR LTC1400CS8 LTC1400CS8#TRPBF