LTC1344A Software-Selectable Cable Terminator FEATURES DESCRIPTIOUN n Software-Selectable Cable Termination for: The LTC®1344A features six software-selectable RS232 (V.28) multiprotocol cable terminators. Each terminator can be RS423 (V.10) configured as an RS422 (V.11) 100W minimum differen- RS422 (V.11) tial load, V.35 T-network load or an open circuit for use RS485 with RS232 (V.28) or RS423 (V.10) transceivers that RS449 provide their own termination. When combined with the EIA530 LTC1543 and LTC1544, the LTC1344A forms a complete EIA530-A software-selectable multiprotocol serial port. A data bus V.35 latch feature allows sharing of the select lines between V.36 multiple interface ports. X.21 The LTC1344A is similar to the LTC1344 except for a n Outputs Won’t Load the Line with Power Off difference in the Mode Selection table. APPLICATIOUNS The LTC1344A is available in a 24-lead SSOP. n Data Networking n CSU and DSU n Data Routers , LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATIONU DTE or DCE Multiprotocol Serial Interface with DB-25 Connector LL CTS DSR DCD DTR RTS RXD RXC TXC SCTE TXD Daisy-Chained Control Outputs LTC1544 LTC1543 D4 D3 D2 D1 D3 D2 D1 R4 R3 R2 R1 R3 R2 R1 LTC1344A 18 13 5 10 8 22 6 23 20 19 4 1 7 16 3 9 17 12 15 11 24 14 2 LL A (141) CTS B CTS A (106) DSR B DSR A (109) DCD B DCD A (107) DTR B DTR A (108) RTS B RTS A (105) SHIELD (101) SG (102) RXD B RXD A (104) RXC B RXC A (115) TXC B TXC A (114) SCTE B SCTE A (113) TXD B TXD A (103) DB-25 CONNECTOR 1344A TA01 1

LTC1344A ABSOLUTE WMAXIWMUWM RATINUGS PACKAGE/ORDER IUFORWATIOU (Note 1) Positive Supply Voltage (VCC)................................... 7V TOP VIEW ORDER PART Negative Supply Voltage (VEE)........................... –13.2V M0 1 24 M1 NUMBER Input Voltage VEE 2 23 M2 LTC1344ACG (Logic Inputs).................... (V – 0.3V) to (V + 0.3V) R1C 3 22 DCE/DTE EE CC LTC1344AIG Input Voltage (Load Inputs).................................. – 18V R1B 4 21 LATCH Power Dissipation..............................................600mW R1A 5 20 R6B Operating Temperature Range R2A 6 19 R6A LTC1344AC ............................................ 0(cid:176) C to 70(cid:176) C R2B 7 18 R5A LTC1344AI ......................................... –40(cid:176) C to 85(cid:176) C R2C 8 17 R5B R3A 9 16 R4A Storage Temperature Range................ –65(cid:176) C to 150(cid:176) C R3B 10 15 R4B Lead Temperature (Soldering, 10 sec)................. 300(cid:176) C R3C 11 14 VCC GND 12 13 GND G PACKAGE 24-LEAD PLASTIC SSOP TJMAX = 150(cid:176)C, q JA = 100(cid:176)C/W Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS V = 5V – 5%, V = –5V – 5%, T = T to T (Notes 2, 3) unless otherwise noted. CC EE A MIN MAX SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supplies I Supply Current All Digital Pins = GND or V l 0.4 1.0 mA CC CC Terminator Pins R Differential Mode Impedance All Loads (Figure 1), –2V £ V £ 2V (Commercial) l 90 104 110 W V.35 CM Common Mode Impedance All Loads (Figure 2), –2V £ V £ 2V (Commercial) l 135 153 165 W CM All Loads (Figure 1), –2V £ V £ 2V (Industrial) l 90 104 115 W CM All Loads (Figure 2), –2V £ V £ 2V (Industrial) l 130 153 170 W CM R Differential Mode Impedance All Loads (Figure 1), V = 0V (Commercial) l 100 104 110 W V.11 CM All Loads (Figure 1), –7V £ V £ 7V (Commercial) 100 104 W CM All Loads (Figure 1), V = 0V (Industrial) l 95 104 115 W CM All Loads (Figure 1), –7V £ V £ 7V (Industrial) 100 104 W CM I High Impedance Leakage Current All Loads, –7V £ V £ 7V l – 1 – 50 m A LEAK CM Logic Inputs V Input High Voltage All Logic Input Pins l 2 V IH V Input Low Voltage All Logic Input Pins l 0.8 V IL I Input Current All Logic Input Pins l – 10 m A IN The l denotes specifications which apply over the full operating Note 2: All currents into device pins are positive; all currents out of device temperature range. pins are negative. All voltages are reference to ground unless otherwise Note 1: Absolute Maximum Ratings are those values beyond which the life specified. of a device may be impaired. Note 3: All typicals are given at V = 5V, V = –5V, T = 25(cid:176) C. CC EE A 2

LTC1344A TYPICAL PERFORWMANUCE CHARACTERISTICS V.11 or V.35 Differential Mode V.11 or V.35 Differential Mode V.11 or V.35 Differential Mode Impedance vs Common Mode Impedance vs Supply Voltage Impedance vs Temperature Voltage (V ) CC 120 105 ) ) 108 TA = 25°C ) TA = 25°C WNCE ( 115 VCM = –7V WNCE ( WNCE ( A A A PED PED 106 PED M M M DE I 110 VCM = –2V DE I DE I104 MO MO 104 MO NTIAL VCM = 0V NTIAL NTIAL RE 105 RE 102 RE DIFFE VCM = 7V DIFFE DIFFE 100 100 103 –40 –20 0 20 40 60 80 100 –8 –6 –4 –2 0 2 4 6 8 4.6 4.8 5.0 5.2 5.4 TEMPERATURE (°C) COMMON MODE VOLTAGE (V) VCC VOLTAGE (V) 1344 G01 1344 G02 1344 G03 V.11 or V.35 Differential Mode Impedance vs Negative Supply V.35 Common Mode Impedance V.35 Common Mode Impedance Voltage (V ) vs Temperature vs Common Mode Voltage EE 105 165 158 TA = 25°C TA = 25°C ) WMODE IMPEDANCE (104 WODE IMPEDANCE () 115650 VCM = –2V WODE IMPEDANCE () 115546 L M M RENTIA MMON 150 VCM = 0V MMON 152 FFE CO VCM = 2V CO DI 103 145 150 –5.4 –5.2 –5.0 –4.8 –4.6 –40 –20 0 20 40 60 80 100 –2 –1 0 1 2 VEE VOLTAGE (V) TEMPERATURE (°C) COMMON MODE VOLTAGE (V) 1344 G04 1344 G05 1344 G06 V.35 Common Mode Impedance V.35 Common Mode Inpedance vs Supply Voltage (V ) vs Negative Supply Voltage (V ) Supply Current vs Temperature CC EE 153 154 500 TA = 25°C TA = 25°C ) ) WCE ( WCE ( 153 A) 420 N N DA DA mT ( E E N P P E M M R E I152 E I 152 UR 340 D D C MO MO LY MON MON 151 SUPP 260 M M O O C C 151 150 180 4.6 4.8 5.0 5.2 5.4 –5.4 –5.2 –5.0 –4.8 –4.6 –40 –20 0 20 40 60 80 100 VCC VOLTAGE (V) VEE VOLTAGE (V) TEMPERATURE (°C) 1344 G07 1344 G08 1344 G09 3

LTC1344A PIUN FUUNCTIOUNS M0 (Pin 1): TTL Level Mode Select Input. The data on M0 R4B (Pin 15): Load 4 Node B. is latched when LATCH is high. R4A (Pin 16): Load 4 Node A. V (Pin 2): Negative Supply Voltage Input. Can connect EE R5B (Pin 17): Load 5 Node B. directly to the LTC1543 V pin. Connect a 1m F capacitor EE to ground. R5A (Pin 18): Load 5 Node A. R1C (Pin 3): Load 1 Center Tap. R6A (Pin 19): Load 6 Node A. R1B (Pin 4): Load 1 Node B. R6B (Pin 20): Load 6 Node B. R1A (Pin 5): Load 1 Node A. LATCH (Pin 21): TTL Level Logic Signal Latch Input. When LATCH is low the input buffers on M0, M1, M2 and DCE/ R2A (Pin 6): Load 2 Node A. DTE are transparent. When LATCH is high the logic pins R2B (Pin 7): Load 2 Node B. are latched into their respective input buffers. The data latch allows the select lines to be shared between multiple R2C (Pin 8): Load 2 Center Tap. I/O ports. R3A (Pin 9): Load 3 Node A. DCE/DTE (Pin 22): TTL Level Mode Select Input. DCE R2B (Pin 10): Load 2 Node B. mode is selected when high and DTE mode when low. The data on DCE/DTE is latched when LATCH is high. R3C (Pin 11): Load 3 Center Tap. M2 (Pin 23): TTL Level Mode Select Input 1. The data on GND (Pin 12): Ground Connection for Load 1 to Load 3. M2 is latched when LATCH is high. GND (Pin 13): Ground Connection for Load 4 to Load 6. M1 (Pin 24): TTL Level Mode Select Input 2. The data on V (Pin 14): Positive Supply Input. 4.75V £ V £ 5.25V. CC CC M1 is latched when LATCH is high. TEST CIRCUITS C C A LTC1344A LTC1344A R1 R1 51.5W 51.5W S1 S2 R3 S1 S2 R3 W ON OFF 124W ON ON 124W A, B R2 R2 51.5W 51.5W W B V – 7V OR – 2V V – 2V 1344 F01 1344 F02 Figure 1. Differential V.11 or V.35 Impedance Measurement Figure 2. V.35 Common Mode Impedance Measurement 4

LTC1344A W O DE SELECTIOU LTC1344A MODE NAME DCE/DTE M2 M1 M0 R1 R2 R3 R4 R5 R6 V.10/RS423 X 0 0 0 Z Z Z Z Z Z RS530A 0 0 0 1 Z Z Z V.11 V.11 V.11 1 0 0 1 Z Z Z Z V.11 V.11 RS530 0 0 1 0 Z Z Z V.11 V.11 V.11 1 0 1 0 Z Z Z Z V.11 V.11 X.21 0 0 1 1 Z Z Z V.11 V.11 V.11 1 0 1 1 Z Z Z Z V.11 V.11 V.35 0 1 0 0 V.35 V.35 Z V.35 V.35 V.35 1 1 0 0 V.35 V.35 V.35 Z V.35 V.35 RS449/V.36 0 1 0 1 Z Z Z V.11 V.11 V.11 1 1 0 1 Z Z Z Z V.11 V.11 V.28/RS232 X 1 1 0 Z Z Z Z Z Z No Cable X 1 1 1 V.11 V.11 V.11 V.11 V.11 V.11 X = don’t care, 0 = logic low, 1 = logic high C C C A LTC1344A A LTC1344A A LTC1344A R1 R1 R1 51.5W 51.5W 51.5W S1 S2 S1 S1 S2 R3 S2 R3 R3 ON OFF 124W ON ON 124W OFF OFF 124W R2 R2 R2 51.5W 51.5W 51.5W B B B V.11 Mode V.35 Mode High-Z Mode 1344 F03 Figure 3. LTC1344A Modes 5

LTC1344A APPLICATIOUNS INUFORWMATIOUN Multiprotocol Cable Termination BALANCED INTERCONNECTING One of the most difficult problems facing the designer of GENERATOR CABLE LOAD a multiprotocol serial interface is how to allow the trans- CABLE TERMINATION RECEIVER mitters and receivers for different electrical standards to share connector pins. In some cases the transmitters and A A' receivers for each interface standard can be simply tied C C' together and the appropriate circuitry enabled. But the 1344 F04 biggest problem still remains: how to switch the various Figure 4. Typical V.10 Interface cable termination required by the different standards. A Traditional implementations have included switching re- sistors with expensive relays or requiring the user to 51.5W LTC1344A V.10 change termination modules every time the interface RECEIVER standard has changed. Custom cables have been used S1 S2 Z OFF OFF 124W with the termination in the cable head. Another method Z uses separate termination built on the board, and a custom 51.5W cable which routes the signals to the appropriate termina- B tion. Switching the termination using FETs is difficult C because the FETs must remain off even though the signal IZ voltage is beyond the supply voltage for the FET drivers or 3.25mA the power is off. –10V –3V Z VZ The LTC1344A solves the cable termination switching 3V 10V problem via software control. The LTC1344A provides –3.25mA 1344 F05 termination for the V.10 (RS423), V.11 (RS422), V.28 (RS232) and V.35 electrical protocols. Figure 5. V.10 Interface Using the LTC1344A V.10 (RS423) Termination V.11 (RS422) Termination A typical V.10 unbalanced interface is shown in Figure 4. A typical V.11 balanced interface is shown in Figure 6. A A V.10 single-ended generator output A with ground C is V.11 differential generator with outputs A and B with connected to a differential receiver with input A' con- ground C is connected to a differential receiver with nected to A and input C' connected to the signal return ground C', inputs A' connected to A, B' connected to B. The ground C. Usually no cable termination is required for V.10 V.11 interface requires a differential termination at the interfaces but the receiver inputs must be compliant with receiver end that has a minimum value of 100W . The the impedance curve shown in Figure 5. receiver inputs must also be compliant with the imped- ance curve shown in Figure 7. In V.10 mode, both switches S1 and S2 are turned off so the only cable termination is the input impedance of the In V.11 mode, switch S1 is turned on and S2 is turned off V.10 receiver. so the cable is terminated with a 103W impedance. 6

LTC1344A APPLICATIOUNS INUFORWMATIOUN BALANCED BALANCED INTERCONNECTING INTERCONNECTING GENERATOR CABLE LOAD GENERATOR CABLE LOAD CABLE CABLE TERMINATION RECEIVER TERMINATION RECEIVER A A' 100W A A' B B' MIN C C' 1344 F08 C C' 1344 F06 Figure 8. Typical V.28 Interface Figure 6. Typical V.11 Interface A A 51.5W LTC1344A V.11 51.5W LTC1344A V.28 RECEIVER RECEIVER S1 S2 Z S1 S2 ON OFF 124W OFF OFF 124W 5k Z 51.5W 51.5W B B C C 1344 F09 IZ Figure 9. V.28 Interface Using the LTC1344A 3.25mA –10V –3V Z VZ 3V 10V V.35 Termination –3.25mA 1344 F07 A typical V.35 balanced interface is shown in Figure 10. A Figure 7. V.11 Interface Using the LTC1344A V.35 differential generator with outputs A and B with ground C is connected to a differential receiver with ground C', inputs A' connected to A, B' connected to B. The V.28 (RS232) Termination V.35 interface requires a T-network termination at the receiver end and the generator end. In V.35 mode both A typical V.28 unbalanced interface is shown in Figure 8. switches S1 and S2 in the LTC1344A are turned on as A V.28 single-ended generator output A with ground C is shown in Figure 11. connected to a single-ended receiver with input A' con- nected to A, ground C' connected via the signal return The differential impedance measured at the connector ground to C. The V.28 standard requires a 5k terminating must be 100W – 10W and the impedance between shorted resistor to ground which is included in almost all compli- terminals A' and B' to ground C' must be 150W – 15W . The ant receivers as shown in Figure 9. Because the termina- input impedance of the V.35 receiver is connected in tion is included in the receiver, both switches S1 and S2 in parallel with the T-network inside the LTC1344A, which the LTC1344A are turned off. could cause the overall impedance to fail the specification 7

LTC1344A APPLICATIOUNS INUFORWMATIOUN BALANCED A INTERCONNECTING GENERATOR CABLE LOAD LTC1344A 51.5W V.35 CABLE DRIVER TERMINATION RECEIVER S1 S2 A A' 124W ON ON 50W 125W 125W 50W 51.5W B 50W 50W B B' C1 100pF C C C' 1344 F10 1344 F12 Figure 12. V.35 Driver Using the LTC1344A Figure 10. Typical V.35 Interface A The generator differential impedance must be 50W to 51.5W LTC1344A V.35 150W and the impedance between shorted terminals A RECEIVER and B to ground C must be 150W – 15W . For the generator OSN1 OSN2 124W Z termination, switches S1 and S2 are both on and the top Z side of the center resistor is brought out to a pin so it can 51.5W be bypassed with an external capacitor to reduce common B mode noise as shown in Figure 12. C Any mismatch in the driver rise and fall times or skew in IZ the driver propagation delays will force current through 1mA the center termination resistor to ground causing a high –7V –3V frequency common mode spike on the A and B terminals. Z VZ 3V 12V The common mode spike can cause EMI problems that are reduced by capacitor C1 which shunts much of the com- –0.8mA 1344 F11 mon mode energy to ground rather than down the cable. Figure 11. V.35 Receiver Using the LTC1344A The LATCH Pin The LATCH pin (21) allows the select lines (M0, M1, M2 if the receiver input impedance is on the low side. All of and DCE/DTE) to be shared with multiple LTC1344As, Linear Technology’s V.35 receivers meet the RS485 input each with its own LATCH signal. When the LATCH pin is impedance specification as shown in Figure 11, which held low the select line input buffers are transparent. When insures compliance with the V.35 specification when used the LATCH pin is pulled high, the select line input buffers with the LTC1344A. latch the state of the Select pins so that changes on the select lines are ignored until LATCH is pulled low again. If the latch feature is not used, the LATCH pin should be tied to ground. 8

LTC1344A TYPICAL APPLICATIONUS N Controller Selectable Multiprotocol DTE/DCE Port with DB-25 Connector C6 C7 C8 100pF100pF100pF 3 8 11 12 13 LTC1344A VCC 5V 14 21 VCC LATCH 1 C13 44 1µF C2 C1µ3F 2 43 1µF 1Cµ1F 34 CPHUAMRGPE 4421 +C3.43µF 2 VEE DCE/DTE M2 M1 M0 C5 8 C12 5 4 6 7 9 10 16 15 1817 19 20 22 23 24 1 1µF LTC1343 1µF DTE DCE 5 39 18 DTE_LL/DCE_TM D1 LL A TM A 38 2 6 TXD A RXD A DTE_TXD/DCE_RXD D2 37 14 TXD B RXD B 36 24 7 SCTE A RXC A DTE_SCTE/DCE_RXC D3 35 11 SCTE B RXC B 34 9 D4 33 10 12 32 15 13 TXC A TXC A DTE_TXC/DCE_TXC R1 31 12 TXC B TXC B 14 30 17 RXC A SCTE A DTE_RXC/DCE_SCTE R2 29 9 RXC B SCTE B 15 28 3 RXD A TXD A DTE_RXD/DCE_TXD R3 27 16 RXD B TXD B DTE_TM/DCE_LL 16 R4 26 25 TM A LL A 20 21 7 CTRL DCE SG 22 19 LATCH M2 11 INVERT M1 18 1 SHIELD 25 17 423SET M0 10R01k VCC 40 24 GND EC LB 23 DB-25 LB CONNECTOR C9, 1µF VCC 12 VCC VEE 2278 C11 VDD GND 1µF C10 1µF 3 26 4 RTS A CTS A DTE_RTS/DCE_CTS D1 25 19 RTS B CTS B 24 20 4 DTR A DSR A DTE_DTR/DCE_DSR D2 23 23 DTR B DSR B 5 D3 LTC1544 22 8 6 DCD A DCD A DTE_DCD/DCE_DCD R1 21 10 DCD B DCD B 20 6 7 DSR A DTR A DTE_DSR/DCE_DTR R2 19 22 DSR B DTR B 18 5 8 CTS A RTS A DTE_CTS/DCE_RTS R3 17 13 CTS B RTS B 10 16 21 DTE_RL/DCE_RL R4 RL A RL A 9 D4 11 15 M0 INVERT NC 12 M1 13 M2 14 DCE/DTE DCE/DTE M2 M1 1344A TA04 M0 9

LTC1344A TYPICAL APPLICATIONUS N Cable Selectable Multiprotocol DTE/DCE Port with DB-25 Connector C6 C7 C8 100pF100pF 100pF 3 8 11 12 13 LTC1344A VCC 5V 14 21 VCC LATCH C13 3 28 1µF C2 C1µ3F 1 27 1µF 1Cµ1F 24 CPHUAMRGPE 2265 +C3.43µF 2 VEE DCE/DTE M2 M1 M0 C5 C12 5 4 6 7 9 10 16 15 18 17 19 20 22 23 24 1 1µF LTC1543 24 1µF VCC 2 DTE DCE 5 TXD A RXD A DTE_TXD/DCE_RXD D1 23 14 TXD B RXD B 22 24 6 SCTE A RXC A DTE_SCTE/DCE_RXC D2 21 11 SCTE B RXC B 7 D3 20 15 8 TXC A TXC A DTE_TXC/DCE_TXC R1 19 12 TXC B TXC B 18 17 9 RXC A SCTE A DTE_RXC/DCE_SCTE R2 17 9 RXC B SCTE B 16 3 10 RXD A TXD A DTE_RXD/DCE_TXD R3 15 16 11 RXD B TXD B M0 7 12 M1 SG 13 NC M2 1 14 SHIELD DCE/DTE DB-25 CONNECTOR C9, 1µF VCC 1 28 25 DCE/DTE 2 VCC VEE 27 C11 21 M1 C10 VDD GND 1µF 18 M0 1µF 3 26 4 RTS A CTS A DTE_RTS/DCE_CTS D1 25 19 RTS B CTS B 24 20 4 DTR A DSR A DTE_DTR/DCE_DSR D2 23 23 DTR B DSR B 5 D3 LTC1544 22 8 6 DCD A DCD A DTE_DCD/DCE_DCD R1 21 10 DCD B DCD B 20 6 7 DSR A DTR A DTE_DSR/DCE_DTR R2 19 22 DSR B DTR B 18 5 8 CTS A RTS A DTE_CTS/DCE_RTS R3 17 13 CTS B RTS B 10 16 R4 CABLE WIRING FOR MODE SELECTION CABLE WIRING FOR 9 MODE PIN 18 PIN 21 DTE/DCE SELECTION D4 V.35 PIN 7 PIN 7 MODE PIN 25 11 M0 RS449, V.36 NC PIN 7 DTE PIN 7 12 M1 RS232 PIN 7 NC DCE NC 13 NC M2 14 15 DCE/DTEINVERT NC 1344A TA05 10

LTC1344A PACKAGE DESCRIPTIOUN Dimensions in inches (millimeters) unless otherwise noted. G Package 24-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 0.318 – 0.328* (8.07 – 8.33) 24 232221 20 19181716151413 0.301 – 0.311 (7.65 – 7.90) 1 2 3 4 5 6 7 8 9 10 1112 0.205 – 0.212** 0.068 – 0.078 (5.20 – 5.38) (1.73 – 1.99) 0° – 8° 0.0256 0.005 – 0.009 0.022 – 0.037 (0.65) (0.13 – 0.22) (0.55 – 0.95) BSC 0.002 – 0.008 0.010 – 0.015 (0.05 – 0.21) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH (0.25 – 0.38) SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE G24 SSOP 0595 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 11 However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1344A TYPICAL APPLICATIOU Figure 13 shows a typical application for the LTC1344A DCE/DTE are shared by both chips. Each driver output and using the LTC1543 mixed mode transceiver chip to gener- receiver input is connected to one of the LTC1344A ate the clock and data signals for a serial interface. The termination ports. Each electrical protocol can then be LTC1344A V supply is generated from the LTC1543 chosen using the digital select lines. EE charge pump and the select lines M0, M1, M2 and 100pF 100pF 100pF 3 8 11 12 13 1 M0 M0 24 M1 M1 23 M2 M2 LTC1344A 22 DCE/DTE DCE/DTE 21 LATCH VCC VEE 14 2 5 4 6 7 9 10 16 15 18 17 19 20 C1 C2 1m F 4 26 3.3m F LTC1543 11 M0 12 M1 13 M2 14 DCE/DTE 24 DTXTDE+ DRCXED+ 5 23 TXD– RXD– 22 SCTE+ RXC+ 6 21 SCTE– RXC– 7 8 20 TXC+ TXC+ 19 TXC– TXC– 9 18 RXC+ SCTE+ 17 RXC– SCTE– 10 16 RXD+ TXD+ 15 RXD– TXD– 1344 F13 Figure 13. Typical Application Using the LTC1344A RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1334 Single Supply RS232/RS485 Transceiver 2 RS485 Dr/Rx or 4 RS232 Dr/Rx Pairs LTC1343 Multiprotocol Serial Transceiver Software Selectable Mulitprotocol Interface LTC1345 Single Supply V.35 Transceiver 3 Dr/3 Rx for Data and CLK Signals LTC1346A Dual Supply V.35 Transceiver 3 Dr/3 Rx for Data and CLK Signals LTC1543 Multiprotocol Serial Transceiver Software-Selectable Transceiver for Data and CLK Signals LTC1544 Multiprotocol Serial Transceiver Software-Selectable Transceiver for Control Signals 12 Linear Technology Corporation 1344af, sn1344a LT/TP 0898 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l w ww.linear-tech.com ª LINEAR TECHNOLOGY CORPORATION 1998

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: LTC1344ACG#PBF LTC1344AIG#TRPBF LTC1344AIG#PBF LTC1344AIG#TR LTC1344ACG#TR LTC1344ACG LTC1344ACG#TRPBF LTC1344AIG