LTC1286/LTC1298 Micropower Sampling 12-Bit A/D Converters In S0-8 Packages FEATURES DESCRIPTIOUN n 12-Bit Resolution The LTC1286/LTC1298 are micropower, 12-bit, succes- n 8-Pin SOIC Plastic Package sive approximation sampling A/D converters. They typi- n Low Cost cally draw only 250m A of supply current when converting n Low Supply Current: 250m A Typ. and automatically power down to a typical supply current n Auto Shutdown to 1nA Typ. of 1nA whenever they are not performing conversions. n Guaranteed – 3/4LSB Max DNL They are packaged in 8-pin SO packages and operate on n Single Supply 5V to 9V Operation 5V to 9V supplies. These 12-bit, switched-capacitor, suc- n On-Chip Sample-and-Hold cessive approximation ADCs include sample-and-holds. n 60m s Conversion Time The LTC1286 has a single differential analog input. The n Sampling Rates: LTC1298 offers a software selectable 2-channel MUX. 12.5 ksps (LTC1286) On-chip serial ports allow efficient data transfer to a wide 11.1 ksps (LTC1298) n I/O Compatible with SPI, Microwire, etc. wires. This, coupled with micropower consumption, makes n Differential Inputs (LTC1286) remote location possible and facilitates transmitting data n 2-Channel MUX (LTC1298) through isolation barriers. n 3V Versions Available: LTC1285/LTC1288 These circuits can be used in ratiometric applications or APPLICATIONUS with an external reference. The high impedance analog inputs and the ability to operate with reduced spans (to n Battery-Operated Systems 1.5V full scale) allow direct connection to sensors and n Remote Data Acquisition transducers in many applications, eliminating the need for n Battery Monitoring gain stages. n Handheld Terminal Interface n Temperature Measurement n Isolated Data Acquisition TYPICAL APPLICATIONUS N 25m W, S0-8 Package, 12-Bit ADC Supply Current vs Sample Rate Samples at 200Hz and Runs Off a 5V Supply 1000 TA = 25°C 4.7m F 5V VCC = VREF = 5V fCLK = 200kHz A) mT (100 N MPU RE (e.g., 8051) UR 1 VREF VCC 8 P1.4 LY C 2 7 PP 10 ANALOG INPUT +IN LTC1286 CLK P1.3 U S 3 6 0V TO 5V RANGE –IN DOUT P1.2 4 5 SERIAL DATA LINK GND CS/SHDN LTC1286/98 • TA01 1 0.1k 1k 10k 100k SAMPLE FREQUENCY (Hz) LTC1286/98 • TA02 1

LTC1286/LTC1298 ABSOLUTE WMAXIWMUWM RATINGS (Notes 1 and 2) Supply Voltage (V ) to GND................................... 12V Power Dissipation..............................................500mW CC Voltage Operating Temperature Range Analog and Reference................–0.3V to V + 0.3V LTC1286C/LTC1298C............................. 0(cid:176) C to 70(cid:176) C CC Digital Inputs.........................................–0.3V to 12V LTC1286I/LTC1298I...........................–40(cid:176) C to 85(cid:176) C Digital Output.............................–0.3V to V + 0.3V Storage Temperature Range.................–65(cid:176) C to 150(cid:176) C CC Lead Temperature (Soldering, 10 sec.)................ 300(cid:176) C PACKAGE/ORDER INUFORWMATIOUN TOP VIEW ORDER PART TOP VIEW ORDER PART VREF 1 8 VCC NUMBER VREF 1 8 VCC NUMBER +IN 2 7 CLK +IN 2 7 CLK LTC1286CN8 LTC1286CS8 –IN 3 6 DOUT –IN 3 6 DOUT LTC1286IN8 LTC1286IS8 GND 4 5 CS/SHDN GND 4 5 C S/SHDN PART MARKING N8 PACKAGE S8 PACKAGE 8-LEAD PLASTIC DIP 8-LEAD PLASTIC SOIC TJMAX = 150(cid:176)C, q JA = 130(cid:176)C/W TJMAX = 150(cid:176)C, q JA = 175(cid:176)C/W 1286 1286I TOP VIEW ORDER PART TOP VIEW ORDER PART NUMBER NUMBER CS/SHDN 1 8 VCC (VREF) CS/SHDN 1 8 VCC (VREF) CH0 2 7 CLK LTC1298CN8 CH0 2 7 CLK LTC1298CS8 CH1 3 6 DOUT LTC1298IN8 CH1 3 6 DOUT LTC1298IS8 GND 4 5 DIN GND 4 5 DIN PART MARKING N8 PACKAGE S8 PACKAGE 8-LEAD PLASTIC DIP 8-LEAD PLASTIC SOIC 1298 TJMAX = 150(cid:176)C, q JA = 130(cid:176)C/W TJMAX = 150(cid:176)C, q JA = 175(cid:176)C/W 1298I Consult factory for military grade parts. RECOWM W ENUDED OPERATINUG CONUDITIONUS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Supply Voltage (Note 3) LTC1286 4.5 9.0 V CC LTC1298 4.5 5.5 V f Clock Frequency V = 5V (Note 4) 200 kHz CLK CC t Total Cycle Time LTC1286, f = 200kHz 80 m s CYC CLK LTC1298, f = 200kHz 90 m s CLK t Hold Time, D After CLK› V = 5V 150 ns hDI IN CC t Setup Time CSfl Before First CLK› (See Operating Sequence) LTC1286, V = 5V 2 m s suCS CC LTC1298, V = 5V 2 m s CC t Setup Time, D Stable Before CLK› V = 5V 400 ns suDI IN CC t CLK High Time V = 5V 2 m s WHCLK CC t CLK Low Time V = 5V 2 m s WLCLK CC t CS High Time Between Data Transfer Cycles V = 5V 2 m s WHCS CC t CS Low Time During Data Transfer LTC1286, f = 200kHz 75 m s WLCS CLK LTC1298, f = 200kHz 85 m s CLK 2

LTC1286/LTC1298 CONUVERTER ANUD WMULTIPLEXER CHARACTERISTICS (Note 5) LTC1286 LTC1298 PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Resolution (No Missing Codes) l 12 12 Bits Integral Linearity Error (Note 6) l – 3/4 – 2 – 3/4 – 2 LSB Differential Linearity Error l – 1/4 – 3/4 – 1/4 – 3/4 LSB Offset Error l 3/4 – 3 3/4 – 3 LSB Gain Error l – 2 – 8 – 2 – 8 LSB Analog Input Range (Note 7 and 8) l –0.05V to VCC + 0.05V V REF Input Range (LTC1286) 4.5 £ VCC £ 5.5V 1.5V to VCC + 0.05V V (Notes 7, 8, and 9) 5.5V < V £ 9V 1.5V to 5.55V V CC Analog Input Leakage Current (Note 10) l – 1 – 1 m A DIGITAL ANUD DC ELECTRICAL CHARACTERISTICS (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V High Level Input Voltage V = 5.25V l 2 V IH CC V Low Level Input Voltage V = 4.75V l 0.8 V IL CC I High Level Input Current V = V l 2.5 m A IH IN CC I Low Level Input Current V = 0V l –2.5 m A IL IN V High Level Output Voltage V = 4.75V, I = 10m A l 4.0 4.64 V OH CC O V = 4.75V, I = 360m A l 2.4 4.62 V CC O V Low Level Output Voltage V = 4.75V, I = 1.6mA l 0.4 V OL CC O I Hi-Z Output Leakage CS = High l – 3 m A OZ I Output Source Current V = 0V –25 mA SOURCE OUT I Output Sink Current V = V 45 mA SINK OUT CC R Reference Input Resistance CS = V 5000 MW REF CC (LTC1286) CS = GND 55 kW I Reference Current (LTC1286) CS = V l 0.001 2.5 m A REF CC t ‡ 640m s, f £ 25kHz l 90 140 m A CYC CLK t = 80m s, f = 200kHz l 90 140 m A CYC CLK I Supply Current CS = V l 0.001 – 3.0 m A CC CC LTC1286, t ‡ 640m s, f £ 25kHz l 220 460 m A CYC CLK LTC1286, t = 80m s, f = 200kHz l 260 500 m A CYC CLK LTC1298, t ‡ 720m s, f £ 25kHz l 320 600 m A CYC CLK LTC1298, t = 90m s, f = 200kHz l 360 640 m A CYC CLK DYNUAWMIC ACCURACY f = 12.5kHz (LTC1286), f = 11.1kHz (LTC1298) (Note 5) SMPL SMPL SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS S/(N +D) Signal-to-Noise Plus Distortion Ratio 1kHz/7kHz Input Signal 71/68 dB THD Total Harmonic Distortion (Up to 5th Harmonic) 1kHz/7kHz Input Signal –84/–80 dB SFDR Spurious-Free Dynamic Range 1kHz/7kHz Input Signal 90/86 dB Peak Harmonic or Spurious Noise 1kHz/7kHz Input Signal –90/–86 dB 3

LTC1286/LTC1298 AC CHARACTERISTICS (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t Analog Input Sample Time See Operating Sequence 1.5 CLK Cycles SMPL f Maximum Sampling Frequency LTC1286 l 12.5 kHz SMPL(MAX) LTC1298 l 11.1 kHz t Conversion Time See Operating Sequence 12 CLK Cycles CONV t Delay Time, CLKfl to D Data Valid See Test Circuits l 250 600 ns dDO OUT t Delay Time, CS› to D Hi-Z See Test Circuits l 135 300 ns dis OUT t Delay Time, CLKfl to D Enable See Test Circuits l 75 200 ns en OUT t Time Output Data Remains Valid After CLKfl C = 100pF 230 ns hDO LOAD t D Fall Time See Test Circuits l 20 75 ns f OUT t D Rise Time See Test Circuits l 20 75 ns r OUT C Input Capacitance Analog Inputs, On Channel 20 pF IN Analog Inputs, Off Channel 5 pF Digital Input 5 pF The l denotes specifications which apply over the full operating Note 7: Two on-chip diodes are tied to each reference and analog input temperature range. which will conduct for reference or analog input voltages one diode drop Note 1: Absolute maximum ratings are those values beyond which the life below GND or one diode drop above VCC. This spec allows 50mV forward of a device may be impaired. bias of either diode for 4.5V £ VCC £ 5.5V. This means that as long as the Note 2: All voltage values are with respect to GND. reference or analog input does not exceed the supply voltage by more than 50mV the output code will be correct. To achieve an absolute 0V to 5V Note 3: These devices are specified at 5V. For 3V specified devices, see input voltage range will therefore require a minimum supply voltage of LTC1285 and LTC1288. 4.950V over initial tolerance, temperature variations and loading. For 5.5V Note 4: Increased leakage currents at elevated temperatures cause the S/H to droop, therefore it is recommended that f ‡ 120kHz at 85(cid:176) C, f ‡ < VCC £ 9V, reference and analog input range cannot exceed 5.55V. If CLK CLK reference and analog input range are greater than 5.55V, the output code 75kHz at 70(cid:176) and fCLK ‡ 1kHz at 25(cid:176) C. will not be guaranteed to be correct. Note 5: VCC = 5V, VREF = 5V and CLK = 200kHz unless otherwise specified. Note 8: The supply voltage range for the LTC1286 is from 4.5V to 9V, but Note 6: Linearity error is specified between the actual end points of the the supply voltage range for the LTC1298 is only from 4.5V to 5.5V. A/D transfer curve. Note 9: Recommended operating conditions Note 10: Channel leakage current is measured after the channel selection. TYPICAL PERFORWMANUCE CHARACTERISTICS Shutdown Supply Current vs Clock Supply Current vs Sample Rate Supply Current vs Temperature Rate with CS High and CS Low 1000 450 35 SUPPLY CURRENT (µA)11000 TVfCACL CK= L ==2T 5V2C°R01CE02Fk9 H=8 z5V LTC1286 UPPLY CURRENT (µA)343005000 TVfCACL CK= ==2 5V2°R0CE0Fk H= z5LVTC1298 fSMPL =11.1kHz SUPPLY CURRENT (µA) 21312000555 TVAC C= =2 5V°RCEF = 5VC(ASF T=E 0R CONVERSION) S 250 1 LTC1286 fSMPL =12.5kHz 0.002 CS = VCC 1 200 0 0.1k 1k 10k 100k –55–35 –15 5 25 45 65 85 105 125 1 20 40 60 80 100120 140160 180200 SAMPLE RATE (kHz) TEMPERATURE (°C) FREQUENCY (kHz) LT1286/98 G03 LT1286/98 G04 LT1286/98 G01 4

LTC1286/LTC1298 TYPICAL PERFORWMANUCE CHARACTERISTICS Reference Current vs Change in Offset vs Sample Rate (LTC1286) Reference Current vs Temperature Reference Voltage 100 95 3 mRENT (A) 68970000 VTVfCACRL CEK=F = =2= 55 25°V0CV0kHz RENT (µA)949.45 VfTfSCACML CK=P =L=2 5V=2°R 01CE02Fk. 5H=k z5HVz B = 1/4096 V)REF 2.25 TfVfCSACLM CK=P =L=2 55=2°V 01C02k.5HkzHz R R S NCE CU 4500 NCE CU93.5 FSET (L 1.5 REFERE 2300 REFERE 93 GE IN OF 1 92.5 N 0.5 10 HA C 0 92 0 0 2 4 6 8 10 12 14 –55–35 –15 5 25 45 65 85 105 125 1 1.5 2 2.5 3 3.5 4 4.5 5 FREQUENCY (kHz) TEMPERATURE (°C) REFERENCE VOLTAGE (V) LT1286/98 G06 LT1286/98 G07 LT1286/98 G08 Change In Linearity vs Change In Gain vs Change in Offset vs Temperature Reference Voltage Reference Voltage 0 –0.5 –10 –0.45 VTAC C= =2 55°VC –9 TVAC C= =2 55°VC ET (LSB)-0-.15 RITY (LSB)–––000.3..354 ffCSLMKP L= =2 0102k.5HkzHz N (LSB) –––678 ffCSLMKP L= =2 0102k.5HkzHz ANGE IN OFFS 1.-52 NGE IN LINEA––0–0..12.525 HANGE IN GAI –––345 H A C C VCC = VREF = 5V CH –0.1 –2 -2.5 fCLK = 200kHz fSMPL = fSMPL (MAX) –0.05 –1 -3 0 0 -55 -35 -15 5 25 45 65 85 1 1.5 2 2.5 3 3.5 4 4.5 5 1 1.5 2 2.5 3 3.5 4 4.5 5 TEMPERATURE (°C) REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) LT1286/98 G09 LT1286/98 G10 LT1286/98 G11 Peak-to-Peak ADC Noise vs Effective Bits and S/(N + D) Reference Voltage Differential Nonlinearity vs Code vs Input Frequency 2 1.0 12 74 VfTCACL CK= ==2 552°V0C0kHz OR (LBS) 00..6800 OBs) 1101 6628 OISE IN LBSs 1.15 NLINEARITY ERR 000...420000 BER OF BITS (EN 8796 54530468 N O–0.20 M 5 C N U AD 0.5 DIFFERENTIAL –––000...864000 EFFECTIVE N 4321 fTVfCSACLM CK=P =L=2 55=2°V 01C02k.5HkzHz 0 –1.0 0 1 2 3 4 5 0 2048 4096 1 10 100 1000 REFERENCE VOLTAGE (V) CODE INPUT FREQUENCY (kHz) LT1286/98 G15 LTC 1286/98 G20 5

LTC1286/LTC1298 TYPICAL PERFORWMANUCE CHARACTERISTICS Spurious Free Dynamic Range Attenuation vs vs Frequency S/(N+D) vs Input Level Input Frequency 100 80 0 MIC RANGE (dB) 67890000 DISTORTION (dB) 657000 TVffISANCM C ==P = L21 5Vk=°HR 1CEz2F. 5=k 5HVz N (%) 23140000 S FREE DYNA 435000 NOISE PLUS 4300 ATTENUATIO 675000 SPURIOU 21000 fTVSACM C=P =L2 5V=°R 1CE2F. 5=k 5HVz SIGNAL-TO- 21000 1089000 TVfSACM C=P =L2 5V=°R 1CE2F. 5=k 5HVz 1k 10k 100k 1M –40 –30 –20 –10 0 1 10k 100k 1M 10M INPUT FREQUENCY (Hz) INPUT LEVEL (dB) INPUT FREQUENCY (Hz) LTC 1286/98 G27 LTC 1286/98 G26 LT1286/98 G25 Power Supply Feedthrough 4096 Point FFT Plot Intermodulation Distortion vs Ripple Frequency 0 0 0 TA = 25°C TA = 25°C TA = 25°C –20 VCC = VREF = 5V –20 VCC = VREF = 5V VCC = 5V (VRIPPLE = 20mV) fIN = 5kHz f1 = 5kHz VREF = 5V fCLK = 200kHz f2 = 6kHz fCLK = 200kHz GNITUDE (dB) –––684000 fSMPL = 12.5kHz GNITUDE (dB) –––684000 fSMPL = 12.5kHz THROUGH (dB)–50 MA–100 MA–100 FEED –120 –120 –140 –140 –100 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 10 100 1000 10000 FREQUENCY (kHz) FREQUENCY (kHz) RIPPLE FREQUENCY (kHz) LTC 1286/98 G21 LTC 1286/98 G24 LTC 1286/98 G22 Maximum Clock Frequency vs Sample and Hold Aquisition Maximum Clock Frequency vs Source Resistance Time vs Source Resistance Supply Voltage 300 10000 300 TA = 25°C TA = 25°C VCC = VREF = 5V VCC = VREF = 5V 250 s) 290 LOCK FREQUENCY (kHz)211005000 VIN RSO+–IIUNNRPPCUUE–TT &H ACQUISITION TIME (n1000 VINRSOURCE+ +INPUT LOCK FREQUENCY (kHz)228700 C S C 260 50 –INPUT TA = 25°C 0 V CC = VREF = 5V 100 250 0.1 1 10 0.1 1 10 100 1000 10000 5 6 7 8 9 SOURCE RESISTANCE (kW ) SOURCE RESISTANCE (W ) SUPPLY VOLTAGE (V) LT1286/98 G16 LT1286/98 G12 LT1286/98 G13 6

LTC1286/LTC1298 TYPICAL PERFORWMANUCE CHARACTERISTICS Minimum Clock Frequency Digital Input Logic Threshold Input Channel Leakage Current for 0.1 LSB Error vs Temperature vs Supply Voltage vs Temperature 200 3 1000 VCC = VREF = 5V GE (V) TA = 25°C VVCRCEF = = 5 5VV A 100 K FREQUENCY (kHz) 110500 C THRESHOLD VOLT 2 AGE CURRENT (nA) 101 ON CHANNEL CLOC 50 L LOGI LEAK 0.1 OFF CHANNEL A T GI DI 0 1 0.01 –55 –35 –15 5 25 45 65 85 3 4 5 6 7 8 9 –60–40–20 0 20 40 60 80 100120140 TEMPERATURE (°C) SUPPLY VOLTAGE (V) TEMPERATURE (°C) LT1286/98 • G14 LTC 1286/98 G17 1196/98 G19 PIUN FUNUCTIONUS LTC1286 LTC1298 V (Pin 1): Reference Input. The reference input defines CS/SHDN (Pin 1): Chip Select Input. A logic low on this REF the span of the A/D converter. input enables the LTC1298. A logic high on this input disables and powers down the LTC1298. IN+ (Pin 2): Positive Analog Input. CH0 (Pin 2): Analog Input. IN– (Pin 3): Negative Analog Input. CH1 (Pin 3): Analog Input. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. CS/SHDN (Pin 5): Chip Select Input. A logic low on this input enables the LTC1286. A logic high on this input D (Pin 5): Digital Data Input. The multiplexer address is IN disables and powers down the LTC1286. shifted into this input. D (Pin 6): Digital Data Output. The A/D conversion D (Pin 6): Digital Data Output. The A/D conversion OUT OUT result is shifted out of this output. result is shifted out of this output. CLK (Pin 7): Shift Clock. This clock synchronizes the serial CLK (Pin 7): Shift Clock. This clock synchronizes the data transfer and determines conversion speed. serial data transfer and determines conversion speed. V (Pin 8): Power Supply Voltage. This pin provides V /V (Pin 8): Power Supply and Reference Voltage. CC CC REF power to the A/D converter. It must be kept free of noise This pin provides power and defines the span of the A/D and ripple by bypassing directly to the analog ground converter. It must be kept free of noise and ripple by plane. bypassing directly to the analog ground plane. 7

LTC1286/LTC1298 BLOCK DIAGRAWM CS/SHDN VCC (VCC/VREF) (DIN) CLK BIAS AND SHUTDOWN CIRCUIT SERIAL PORT DOUT IN+ (CH0) CSAMPLE – IN– (CH1) SAR + MICROPOWER COMPARATOR CAPACITIVE DAC GND VREF PIN NAMES IN PARENTHESES REFER TO THE LTC1298 TEST CIRCUITS Load Circuit for t , t and t Voltage Waveforms for D Rise and Fall Times, t, t dDO r f OUT r f 1.4V VOH DOUT 3k VOL DOUT TEST POINT 100pF tr tf LTC1286/98 • TC02 LTC1286/98 • TC01 Voltage Waveforms for D Delay Times, t Load Circuit for t and t OUT dDO dis en TEST POINT CLK VIL tdDO 3k VCC tdis WAVEFORM 2, ten DOUT VOH tdis WAVEFORM 1 DOUT 100pF VOL LTC1286/98 • TC04 LTC1286/98 • TC03 8

LTC1286/LTC1298 TEST CIRCUITS Voltage Waveforms for t Voltage Waveforms for t dis en LTC1286 CS VIH CS DOUT 90% WAVEFORM 1 (SEE NOTE 1) CLK 1 2 tdis DOUT WAVEFORM 2 10% (SEE NOTE 2) B11 NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH DOUT VOL THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH ten LTC1286/98 • TC06 THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL. LTC1286/98 • TC05 Voltage Waveforms for t en LTC1298 CS DIN START CLK 1 2 3 4 B11 DOUT VOL ten LTC1286/98 • TC07 APPLICATIOUN INUFORWMATIOUN OVERVIEW while the LTC1298 operates from a 4.5V to 5.5V supply. The LTC1286 and LTC1298 are micropower, 12-bit, suc- Both the LTC1286 and the LTC1298 contain a 12-bit, cessive approximation sampling A/D converters. The switched-capacitor ADC, a sample-and-hold, and a LTC1286 typically draws 250m A of supply current when serial port (see Block Diagram). Although they share sampling at 12.5kHz while the LTC1298 nominally con- the same basic design, the LTC1286 and LTC1298 sumes 350m A of supply current when sampling at differ in some respects. The LTC1286 has a differential 11.1 kHz. The extra 100m A of supply current on the input and has an external reference input pin. It can LTC1298 comes from the reference input which is inten- measure signals floating on a DC common-mode volt- tionally tied to the supply. Supply current drops linearly as age and can operate with reduced spans to 1V. Reduc- the sample rate is reduced (see Supply Current vs Sample ing the spans allows it to achieve 244m V resolution. The Rate). The ADCs automatically power down when not LTC1298 has a two-channel input multiplexer and can performing conversions, drawing only leakage current. convert either channel with respect to ground or the They are packaged in 8-pin SO and DIP packages. The difference between the two. The reference input is tied LTC1286 operates on a single supply from 4.5V to 9V, to the supply pin. 9

LTC1286/LTC1298 APPLICATIOUN INUFORWMATIOUN SERIAL INTERFACE A/D conversion result is output on the D line. Bringing OUT CS high resets the LTC1286 for the next data exchange. The 2-channel LTC1298 communicates with micropro- cessors and other external circuitry via a synchronous, The LTC1298 first receives input data and then transmits half duplex, 4-wire serial interface. The single channel back the A/D conversion result (half duplex). Because of LTC1286 uses a 3-wire interface (see Operating Sequence the half duplex operation, D and D may be tied IN OUT in Figures 1 and 2). together allowing transmission over just 3 wires: CS, CLK and DATA (D /D ). IN OUT Data Transfer Data transfer is initiated by a falling chip select (CS) signal. The CLK synchronizes the data transfer with each bit being After CS falls the LTC1298 looks for a start bit. After the transmitted on the falling CLK edge and captured on the start bit is received, the 3-bit input word is shifted into the rising CLK edge in both transmitting and receiving systems. D input which configures the LTC1298 and starts the IN The LTC1286 does not require a configuration input word conversion. After one null bit, the result of the conversion and has no D pin. A falling CS initiates data transfer as is output on the D line. At the end of the data exchange IN OUT shown in the LTC1286 operating sequence. After CS falls CS should be brought high. This resets the LTC1298 in the second CLK pulse enables D . After one null bit the preparation for the next data exchange. OUT tCYC CS tsuCS POWER DOWN CLK DOUT HI-Z NBUILTL B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* HI-Z NBUILTL B11 B10 B9 B8 tSMPL (MSB) tCONV tDATA *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY. tCYC CS tsuCS POWER DOWN CLK NULL DOUT HI-Z BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11* HI-Z (MSB) tSMPL tCONV tDATA *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY. tDAT A: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES. LTC1286/98 • F01 Figure 1. LTC1286 Operating Sequence 10

LTC1286/LTC1298 APPLICATIOUN INUFORWMATIOUN CS DIN 1 DIN 2 DOUT 1 DOUT 2 SHIFT MUX ADDRESS IN 1 NULL BIT SHIFT A/D CONVERSION RESULT OUT LTC1096/98 • AI01 MSB-First Data (MSBF = 0) tCYC CS tsuCS POWER DOWN CLK ODD/ START SIGN DIN DON'T CARE SGL/ MSBF DIFF NULL DOUT HI-Z BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11* HI-Z tSMPL (MSB) tCONV tDATA MSB-First Data (MSBF = 1) tCYC CS POWER tsuCS DOWN CLK ODD/ START SIGN DIN DON'T CARE SGL/ MSBF DIFF NULL DOUT HI-Z BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* HI-Z (MSB) tSMPL tCONV tDATA *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY. tDAT A: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES. LTC1286/98 • F02 Figure 2. LTC1298 Operating Sequence Example: Differential Inputs (CH+, CH–) 11

LTC1286/LTC1298 APPLICATIOUN INUFORWMATIOUN Input Data Word MSBF bit is a logical zero, LSB first data will follow the normal MSB first data on the D line. (see Operating The LTC1286 requires no D word. It is permanently OUT IN Sequence) configured to have a single differential input. The conver- sion result appears on the D line. The data format is OUT Transfer Curve MSB first followed by the LSB sequence. This provides easy interface to MSB or LSB first serial ports. For MSB The LTC1286/LTC1298 are permanently configured for first data the CS signal can be taken high after B0 (see unipolar only. The input span and code assignment for Figure 1). The LTC1298 clocks data into the D input on this conversion type are shown in the following figures. IN the rising edge of the clock. The input data words are Transfer Curve defined as follows: SGL/ ODD/ START MSBF DIFF SIGN 1 1 1 1 1 1 1 1 1 1 1 1 MUX MSB FIRST/ 1 1 1 1 1 1 1 1 1 1 1 0 ADDRESS LSB FIRST LTC1096/9 • AI02 • Start Bit • • The first “logical one” clocked into the D input after CS goes low is the start bit. The start bit inINitiates the data 0 0 0 0 0 0 0 0 0 0 0 1 VIN 0 0 0 0 0 0 0 0 0 0 0 0 tprraencsefdeer. tThhise l oLgTiCc1a2l o9n8e w. Aillf tiegrn tohree satlal rlet abditi nisg r zeecreoivse wd,h tichhe 0V 1LSB 1LSB = V40R9E6F REF–2V REFV–1 REFV L L remaining bits of the input word will be clocked in. Further SB SB LTC1286/98 • AI04 inputs on the D pin are then ignored until the next CS IN cycle. Output Code Multiplexer (MUX) Address INPUT VOLTAGE OUTPUT CODE INPUT VOLTAGE (VREF = 5.000V) The bits of the input word following the START bit assign 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VREF – 1LSB 4.99878V 1 1 1 1 1 1 1 1 1 1 1 1 1 0 VREF – 2LSB 4.99756V the MUX configuration for the requested conversion. For • • • • • • a given channel selection, the converter will measure the • • • 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1LSB 0.00122V voltage between the two channels indicated by the + and 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0V 0V LTC1286/98 • AI05 – signs in the selected row of the following tables. In single-ended mode, all input channels are measured with Operation with D and D Tied Together IN OUT respect to GND. The LTC1298 can be operated with D and D tied IN OUT LTC1298 Channel Selection together. This eliminates one of the lines required to MUX ADDRESS CHANNEL # communicate to the microprocessor (MPU). Data is trans- SGL/DIFF ODD/SIGN 0 1 GND mitted in both directions on a single wire. The processor SINGLE-ENDED 1 0 + – MUX MODE 1 1 + – pin connected to this data line should be configurable as DIFFERENTIAL 0 0 + – either an input or an output. The LTC1298 will take control MUX MODE 0 1 – + of the data line and drive it low on the 4th falling CLK edge LTC1096/8 • AI03 MSB First/LSB First (MSBF) after the start bit is received (see Figure 3). Therefore the processor port line must be switched to an input before The output data of the LTC1298 is programmed for this happens to avoid a conflict. MSB first or LSB first sequence using the MSBF bit. When the MSBF bit is a logical one, data will appear on In the Typical Applications section, there is an example of the D line in MSB first format. Logical zeros will be interfacing the LTC1298 with D and D tied together to OUT IN OUT filled in indefinitely following the last data bit. When the the Intel 8051 MPU. 12

LTC1286/LTC1298 APPLICATIOUN INUFORWMATIOUN MSBF BIT LATCHED CS BY LTC1298 1 2 3 4 CLK DATA (DIN/DOUT) START SGL/DIFF ODD/SIGN MSBF B11 B10 • • • MPU CONTROLS DATA LINE AND SENDS LTC1298 CONTROLS DATA LINE AND SENDS MUX ADDRESS TO LTC1298 A/D RESULT BACK TO MPU PROCESSOR MUST RELEASE LTC1298 TAKES CONTROL OF DATA LINE DATA LINE AFTER 4TH RISING CLK ON 4TH FALLING CLK AND BEFORE THE 4TH FALLING CLK LTC1286/98 F03 Figure 3. LTC1298 Operation with D and D Tied Together IN OUT ACHIEVING MICROPOWER PERFORMANCE With typical operating currents of 250m A and automatic input becomes high impedance at the end of each conver- shutdown between conversions, the LTC1286/LTC1298 sion leaving the CLK running to clock out the LSB first data achieves extremely low power consumption over a wide or zeroes (see Figures 1 and 2). If the CS is not running rail- range of sample rates (see Figure 4). The auto-shutdown to-rail, the input logic buffer will draw current. This current allows the supply curve to drop with reduced sample rate. may be large compared to the typical supply current. To Several things must be taken into account to achieve such obtain the lowest supply current, bring the CS pin to a low power consumption. ground when it is low and to supply voltage when it is high. When the CS pin is high (= supply voltage), the converter 1000 TA = 25°C is in shutdown mode and draws only leakage current. The VCC = VREF = 5V status of the D and CLK input have no effect on supply fCLK = 200kHz IN T (µA)100 current during this time. There is no need to stop DIN and N CLK with CS = high; they can continue to run without RE LTC1298 UR drawing current. C LTC1286 Y L P UP 10 Minimize CS Low Time S In systems that have significant time between conver- sions, lowest power drain will occur with the minimum CS 1 0.1k 1k 10k 100k low time. Bringing CS low, transferring data as quickly as SAMPLE RATE (kHz) possible, and then bringing it back high will result in the LT1286/98 G03 lowest current drain. This minimizes the amount of time Figure 4. Automatic Power Shutdown Between Conversions the device draws power. After a conversion the ADC Allows Power Consumption to Drop with Sample Rate. automatically shuts down even if CS is held low (see Figures 1 and 2). If the clock is left running to clock out Shutdown LSB-data or zero, the logic will draw a small current. The LTC1286/LTC1298 are equipped with automatic shut- Figure 5 shows that the typical supply current with CS = down features. They draw power when the CS pin is low ground varies from 1m A at 1kHz to 35m A at 200kHz. When and shut down completely when that pin is high. The bias CS = V , the logic is gated off and no supply current is CC circuit and comparator powers down and the reference drawn regardless of the clock frequency. 13

LTC1286/LTC1298 APPLICATIOUN INUFORWMATIOUN 35 Clock Frequency TA = 25°C 30 VCC = VREF = 5V The maximum recommended clock frequency is 200kHz µA) 25 for the LTC1286/LTC1298 running off a 5V supply. With ENT ( 20 the supply voltage changing, the maximum clock fre- R R 15 U quency for the devices also changes (see the typical curve C PLY 10 C(ASF T=E 0R CONVERSION) of Maximum Clock Rate vs Supply Voltage). If the maxi- P SU 5 mum clock frequency is used, care must be taken to 1 ensure that the device converts correctly. 0.002 CS = VCC 0 Mixed Supplies 1 20 40 60 80 100120 140160 180200 FREQUENCY (kHz) It is possible to have a microprocessor running off a 5V LT1286/98 G01 supply and communicate with the LTC1286 operating on Figure 5. Shutdown current with CS high is 1nA typically, a 9V supply. The requirement to achieve this is that the regardless of the clock. Shutdown current with CS = ground outputs of CS and CLK from the MPU have to be able to trip varies from 1m A at 1kHz to 35m A at 200kHz. the equivalent inputs of the LTC1286 and the output of D Loading D from the LTC1286 must be able to toggle the OUT OUT equivalent input of the MPU (see typical curve of Digital Capacitive loading on the digital output can increase power Input Logic Threshold vs Supply Voltage). With the consumption. A 100pF capacitor on the D pin can add OUT LTC1286 operating on a 9V supply, the output of D may more than 50m A to the supply current at a 200kHz clock OUT go between 0V and 9V. The 9V output may damage the frequency. An extra 50m A or so of current goes into MPU running off a 5V supply. The way to get around this charging and discharging the load capacitor. The same possibility is to have a resistor divider on D (Figure 6) goes for digital lines driven at a high frequency by any logic. OUT and connect the center point to the MPU input. It should The C · V · f currents must be evaluated and the trouble- be noted that to get full shutdown, the CS input of the some ones minimized. LTC1286 must be driven to the V voltage to keep the CS CC input buffer from drawing current. An alternative is to OPERATING ON OTHER THAN 5V SUPPLIES (LTC1286) leave CS low after a conversion, clock data until DOUT outputs zeros, and then stop the clock low. The LTC1286 operates from 4.5V to 9V supplies and the LTC1298 operates from a 5V supply. To operate the LTC1286 on other than 5V supplies a few things must be kept in 9V 4.7m F mind. MPU 5V Input Logic Levels (e.g. 8051) 5V VREF VCC P1.4 The input logic levels of CS, CLK and D are made to meet IN DIFFERENTIAL INPUTS +IN CLK P1.3 TTL on a 5V supply. When the supply voltage varies, the COMMON-MODE RANGE 50k 0V TO 5V –IN DOUT P1.2 input logic levels also change. For the LTC1286 to sample GND CS 50k and convert correctly, the digital inputs have to be in the LTC1286 proper logical low and high levels relative to the operating LTC1286/98 • F06 supply voltage (see typical curve of Digital Input Logic Threshold vs Supply Voltage). If achieving micropower Figure 6. Interfacing a 9V Powered LTC1286 to a 5V System consumption is desirable, the digital inputs must go rail-to- rail between supply voltage and ground (see ACHIEVING MICROPOWER PERFORMANCE section). 14

LTC1286/LTC1298 APPLICATIOUN INUFORWMATIOUN BOARD LAYOUT CONSIDERATIONS SAMPLE-AND-HOLD Both the LTC1286 and the LTC1298 provide a built-in Grounding and Bypassing sample-and-hold (S&H) function to acquire signals. The The LTC1286/LTC1298 are easy to use if some care is S&H of the LTC1286 acquires input signals from “+” input taken. They should be used with an analog ground plane relative to “–” input during the t time (see Figure 1). SMPL and single point grounding techniques. The GND pin However, the S&H of the LTC1298 can sample input should be tied directly to the ground plane. signals in the single-ended mode or in the differential inputs during the t time (see Figure 7). The V pin should be bypassed to the ground plane with SMPL CC a 10m F tantalum capacitor with leads as short as possible. Single-Ended Inputs If the power supply is clean, the LTC1286/LTC1298 can also operate with smaller 1m F or less surface mount or The sample-and-hold of the LTC1298 allows conversion ceramic bypass capacitors. All analog inputs should be of rapidly varying signals. The input voltage is sampled referenced directly to the single point ground. Digital during the t time as shown in Figure 7. The sampling SMPL inputs and outputs should be shielded from and/or routed interval begins as the bit preceding the MSBF bit is shifted away from the reference and analog circuitry. in and continues until the falling CLK edge after the MSBF bit is received. On this falling edge, the S&H goes into hold mode and the conversion begins. SAMPLE HOLD "+" INPUT MUST SETTLE DURING THIS TIME CS tSMPL tCONV CLK DIN START SGL/DIFF MSBF DON'T CARE DOUT B11 1ST BIT TEST "–" INPUT MUST SETTLE DURING THIS TIME "+" INPUT "–" INPUT LTC1096/8 • F07 Figure 7. LTC1298 “+” and “–” Input Settling Windows 15

LTC1286/LTC1298 APPLICATIOUN INUFORWMATIOUN Differential Inputs sample time can be increased by using a slower CLK frequency. With differential inputs, the ADC no longer converts just a single voltage but rather the difference between two volt- “–” Input Settling ages. In this case, the voltage on the selected “+” input is still sampled and held and therefore may be rapidly time At the end of the tSMPL, the input capacitor switches to the varying just as in single-ended mode. However, the volt- “–” input and conversion starts (see Figures 1 and 7). age on the selected “–” input must remain constant and be During the conversion, the “+” input voltage is effectively free of noise and ripple throughout the conversion time. “held” by the sample-and-hold and will not affect the Otherwise, the differencing operation may not be per- conversion result. However, it is critical that the “–” input formed accurately. The conversion time is 12 CLK cycles. voltage settles completely during the first CLK cycle of the Therefore, a change in the “–” input voltage during this conversion time and be free of noise. Minimizing RSOURCE– interval can cause conversion errors. For a sinusoidal and C2 will improve settling time. If a large “–” input voltage on the “–” input this error would be: source resistance must be used, the time allowed for settling can be extended by using a slower CLK frequency. V = V · 2 · p · f(“–”) · 12/f ERROR (MAX) PEAK CLK Where f(“–”) is the frequency of the “–” input voltage, Input Op Amps V is its peak amplitude and f is the frequency of the PEAK CLK When driving the analog inputs with an op amp it is CLK. In most cases V will not be significant. For a ERROR important that the op amp settle within the allowed time 60Hz signal on the “–” input to generate a 1/4LSB error (see Figure 7). Again, the“+” and “–” input sampling times (305m V) with the converter running at CLK = 200kHz, its can be extended as described above to accommodate peak value would have to be 13.48mV. slower op amps. Most op amps, including the LT1006 and LT1413 single supply op amps, can be made to settle well ANALOG INPUTS even with the minimum settling windows of 6m s (“+” Because of the capacitive redistribution A/D conversion input) which occur at the maximum clock rate of 200kHz. techniques used, the analog inputs of the LTC1286/ LTC1298 have capacitive switching input current spikes. Source Resistance These current spikes settle quickly and do not cause a The analog inputs of the LTC1286/LTC1298 look like a problem. However, if large source resistances are used or 20pF capacitor (C ) in series with a 500W resistor (R ) IN ON if slow settling op amps drive the inputs, care must be as shown in Figure 8. C gets switched between the IN taken to insure that the transients caused by the current selected “+” and “–” inputs once during each conversion spikes settle completely before the conversion begins. cycle. Large external source resistors and capacitances “+” Input Settling “+” The input capacitor of the LTC1286 is switched onto “+” RSOURCE + INPUT input during the tSMPL time (see Figure 1) and samples the VIN + LTC1286/98 input signal within that time. However, the input capacitor C1 RON = 500W of the LTC1298 is switched onto “+” input during the “–” sample phase (t , see Figure 7). The sample phase is RSOURCE – INPUT CIN = 20pF SMPL VIN – 1 1/2 CLK cycles before conversion starts. The voltage on C2 the “+” input must settle completely within t for the SMPLE LTC1286/98 • F08 LTC1286 and the LTC1298 respectively. Minimizing R + and C1 will improve the input settling time. If a SOURCE large “+” input source resistance must be used, the Figure 8. Analog Input Equivalent Circuit 16

LTC1286/LTC1298 APPLICATIOUN INUFORWMATIOUN will slow the settling of the inputs. It is important that the converter, the reference input should be driven by a overall RC time constants be short enough to allow the reference with low R (ex. LT1004, LT1019 and LT1021) OUT analog inputs to completely settle within the allowed time. or a voltage source with low R . OUT RC Input Filtering REF+ 1 LTC1286 It is possible to filter the inputs with an RC network as shown in Figure 9. For large values of C (e.g., 1m F), the ROUT F capacitive input switching currents are averaged into a net VREF GND DC current. Therefore, a filter should be chosen with a 4 small resistor and large capacitor to prevent DC drops LTC1286/98 • F10 across the resistor. The magnitude of the DC current is approximately I = 20pF · V /t and is roughly Figure 10. Reference Input Equivalent Circuit DC IN CYC proportional to V . When running at the minimum cycle IN Reduced Reference Operation time of 64m s, the input current equals 1.56m A at V = 5V. IN In this case, a filter resistor of 75W will cause 0.1LSB of The minimum reference voltage of the LTC1298 is limited full-scale error. If a larger filter resistor must be used, to 4.5V because the V supply and reference are inter- CC errors can be eliminated by increasing the cycle time. nally tied together. However, the LTC1286 can operate with reference voltages below 1V. RFILTER IDC The effective resolution of the LTC1286 can be increased VIN “+” by reducing the input span of the converter. The LTC1286 CFILTER LTC1286 exhibits good linearity and gain over a wide range of reference voltages (see typical curves of Change in Linear- “–” ity vs Reference Voltage and Change in Gain vs Reference LTC1286/98 • F09 Voltage). However, care must be taken when operating at Figure 9. RC Input Filtering low values of V because of the reduced LSB step size REF and the resulting higher accuracy requirement placed on Input Leakage Current the converter. The following factors must be considered when operating at low V values: Input leakage currents can also create errors if the source REF resistance gets too large. For instance, the maximum 1. Offset input leakage specification of 1m A (at 125(cid:176) C) flowing 2. Noise through a source resistance of 240W will cause a voltage 3. Conversion speed (CLK frequency) drop of 240m V or 0.2LSB. This error will be much reduced at lower temperatures because leakage drops rapidly (see Offset with Reduced VREF typical curve of Input Channel Leakage Current vs Tem- The offset of the LTC1286 has a larger effect on the output perature). code. When the ADC is operated with reduced reference voltage. The offset (which is typically a fixed voltage) REFERENCE INPUTS becomes a larger fraction of an LSB as the size of the LSB The reference input of the LTC1286 is effectively a 50kW is reduced. The typical curve of Change in Offset vs resistor from the time CS goes low to the end of the Reference Voltage shows how offset in LSBs is related to conversion. The reference input becomes a high impedence reference voltage for a typical value of V . For example, OS node at any other time (see Figure 10). Since the voltage a V of 122m V which is 0.1LSB with a 5V reference OS on the reference input defines the voltage span of the A/D becomes 0.5LSB with a 1V reference and 2.5LSBs with a 17

LTC1286/LTC1298 APPLICATIOUN INUFORWMATIOUN 0.2V reference. If this offset is unacceptable, it can be tortion and noise at the rated throughput. By applying a low corrected digitally by the receiving system or by offsetting distortion sine wave and analyzing the digital output using the “–” input of the LTC1286. an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure Noise with Reduced VREF 11 shows a typical LTC1286 plot. The total input referred noise of the LTC1286 can be reduced to approximately 400m V peak-to-peak using a 0 TA = 25°C ground plane, good bypassing, good layout techniques –20 VCC = VREF = 5V fIN = 5kHz and minimizing noise on the reference inputs. This noise fCLK = 200kHz is insignificant with a 5V reference but will become a larger B) –40 fSMPL = 12.5kHz d fraction of an LSB as the size of the LSB is reduced. E ( –60 D U T For operation with a 5V reference, the 400m V noise is GNI –80 A M only 0.33LSB peak-to-peak. In this case, the LTC1286 –100 noise will contribute virtually no uncertainty to the –120 output code. However, for reduced references the noise may become a significant fraction of an LSB and cause –140 0 1 2 3 4 5 6 7 undesirable jitter in the output code. For example, with FREQUENCY (kHz) a 2.5V reference this same 400m V noise is 0.66LSB LTC 1286/98 G21 peak-to-peak. This will reduce the range of input volt- Figure 11. LTC1286 Non-Averaged, 4096 Point FFT Plot ages over which a stable output code can be achieved by 1LSB. If the reference is further reduced to 1V, the 400m V Signal-to-Noise Ratio noise becomes equal to 1.65LSBs and a stable code may The Signal-to-Noise plus Distortion Ratio (S/N + D) is the be difficult to achieve. In this case averaging multiple ratio between the RMS amplitude of the fundamental readings may be necessary. input frequency to the RMS amplitude of all other fre- This noise data was taken in a very clean setup. Any setup quency components at the ADC’s output. The output is induced noise (noise or ripple on V , V or V ) will add band limited to frequencies above DC and below one half CC REF IN to the internal noise. The lower the reference voltage to be the sampling frequency. Figure 12 shows a typical spec- used the more critical it becomes to have a clean, noise free tral content with a 12.5kHz sampling rate. setup. Effective Number of Bits Conversion Speed with Reduced V REF The Effective Number of Bits (ENOBs) is a measurement of With reduced reference voltages, the LSB step size is the resolution of an ADC and is directly related to S/(N+D) reduced and the LTC1286 internal comparator over- by the equation: drive is reduced. Therefore, it may be necessary to ENOB = [S/(N + D) – 1.76]/6.02 reduce the maximum CLK frequency when low values of V are used. where S/(N + D) is expressed in dB. At the maximum REF sampling rate of 12.5kHz with a 5V supply, the LTC1286 DYNAMIC PERFORMANCE maintains above 11 ENOBs at 10kHz input frequency. Above 10kHz the ENOBs gradually decline, as shown in The LTC1286/LTC1298 have exceptional sampling capa- Figure 12, due to increasing second harmonic distortion. bility. Fast Fourier Transform (FFT) test techniques are The noise floor remains low. used to characterize the ADC’s frequency response, dis- 18

LTC1286/LTC1298 APPLICATIOUN INUFORWMATIOUN 12 74 If two pure sine waves of frequencies f and f are applied a b 11 68 s) to the ADC input, nonlinearities in the ADC transfer func- OB 10 62 N tion can create distortion products at sum and difference E 9 56 BITS ( 8 50 frequencies of mfa – nfb, where m and n = 0, 1, 2, 3, etc. R OF 76 4348 For example, the 2nd order IMD terms include (fa + fb) and MBE 5 (fa – fb) while 3rd order IMD terms include (2fa + fb), E NU 4 (2fa – fb), (fa + 2fb), and (fa – 2fb). If the two input sine TIV 3 TA = 25°C waves are equal in magnitudes, the value (in dB) of the 2nd EFFEC 21 fVfCSCLMCKP =L= 5=2V 0102k.5HkzHz oforrdmeru lIaM:D products can be expressed by the following 0 1 10 100 1000 INPUT FREQUENCY (kHz) ( ) LTC 1286/98 G20 ( ) Ø amplitude f – f ø IMD f – f =20logŒ a b œ Figure 12. Effective Bits and S/(N + D) vs Input Frequency a b Œ amplitude at f œ º a ß Total Harmonic Distortion For input frequencies of 5kHz and 6kHz, the IMD of the Total Harmonic Distortion (THD) is the ratio of the RMS LTC1286/LTC1298 is 73dB with a 5V supply. sum of all harmonics of the input signal to the fundamental Peak Harmonic or Spurious Noise itself. The out-of-band harmonics alias into the frequency band between DC and half of the sampling frequency. THD The peak harmonic or spurious noise is the largest spec- is defined as: tral component excluding the input signal and DC. This value is expressed in dBs relative to the RMS value of a full- V2+V2+V2+...+V2 scale input signal. THD=20log 2 3 4 N V 1 Full-Power and Full-Linear Bandwidth where V1 is the RMS amplitude of the fundamental fre- The full-power bandwidth is that input frequency at which quency and V2 through VN are the amplitudes of the the amplitude of the reconstructed fundamental is re- second through the Nth harmonics. The typical THD speci- duced by 3dB for a full-scale input. fication in the Dynamic Accuracy table includes the 2nd The full-linear bandwidth is the input frequency at which through 5th harmonics. With a 7kHz input signal, the the effective bits rating of the ADC falls to 11 bits. Beyond LTC1286/LTC1298 have typical THD of 80dB with V = 5V. CC this frequency, distortion of the sampled input signal increases. The LTC1286/LTC1298 have been designed to Intermodulation Distortion optimize input bandwidth, allowing the ADCs to If the ADC input signal consists of more than one spectral undersample input signals with frequencies above the component, the ADC transfer function nonlinearity can converters’ Nyquist Frequency. produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. 19

LTC1286/LTC1298 TYPICAL APPLICATIONUS N MICROPROCESSOR INTERFACES The LTC1286/LTC1298 can interface directly without ex- Table 1. Microprocessor with Hardware Serial Interfaces Compatible with the LTC1286/LTC1298 ternal hardware to most popular microprocessor (MPU) synchronous serial formats (see Table 1). If an MPU PART NUMBER TYPE OF INTERFACE without a dedicated serial port is used, then 3 or 4 of the Motorola MPU's parallel port lines can be programmed to form the MC6805S2,S3 SPI serial link to the LTC1286/LTC1298. Included here is one MC68HC11 SPI MC68HC05 SPI serial interface example and one example showing a RCA parallel port programmed to form the serial interface. CDP68HC05 SPI Motorola SPI (MC68HC11) Hitachi HD6305 SCI Synchronous The MC68HC11 has been chosen as an example of an MPU HD63705 SCI Synchronous with a dedicated serial port. This MPU transfers data MSB HD6301 SCI Synchronous HD63701 SCI Synchronous -first and in 8-bit increments. The D word sent to the data IN HD6303 SCI Synchronous register starts with the SPI process. With three 8-bit HD64180 CSI/O transfers, the A/D result is read into the MPU. The second National Semiconductor 8-bit transfer clocks B11 through B8 of the A/D conversion COP400 Family MICROWIRE† result into the processor. The third 8-bit transfer clocks COP800 Family MICROWIRE/PLUS† NS8050U MICROWIRE/PLUS† the remaining bits, B7 through B0, into the MPU. The data HPC16000 Family MICROWIRE/PLUS† is right justified into two memory locations. ANDing the Texas Instruments second byte with OF clears the four most significant HEX TMS7002 Serial Port bits. This operation was not included in the code. It can be TMS7042 Serial Port TMS70C02 Serial Port inserted in the data gathering loop or outside the loop TMS70C42 Serial Port when the data is processed. TMS32011* Serial Port TMS32020 Serial Port MC68HC11 Code Intel In this example the DIN word configures the input MUX for 8051 Bit Manipulation on Parallel Port a single-ended input to be applied to CHO. The conversion *Requires external hardware result is output MSB-first. † MICROWIRE and MICROWIRE/PLUS are trademarks of NationalSemiconductor Corp. 20

LTC1286/LTC1298 TYPICAL APPLICATIONUS N Timing Diagram for Interface to the MC68HC11 CS CLK DIN START SDGIFLF/ OSIDGDN/ MSBF DON'T CARE DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 MPU TRA NWSOMRIDT 0 0 0 0 0 0 0 1 SDGIFLF/ OSIDGDN/ MSBF X X X X X X X X X X X X X BYTE 1 BYTE 2 BYTE 3 (DUMMY) MPU RECEIVED ? ? ? ? ? ? ? ? ? ? ? 0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 WORD BYTE 1 BYTE 2 BYTE 3 LTC1286/98 AI06 Hardware and Software Interface to the MC68HC11 DOUT FROM LTC1298 STORED IN MC68HC11 RAM MSB CH0 CS D0 #62 0 0 0 0 B11 B10 B9 B8 BYTE 1 CLK SCK ANALOG LTC1298 MC68HC11 LSB INPUTS DOUT MISO #63 B7 B6 B5 B4 B3 B2 B1 B0 BYTE 2 CH1 DIN MOSI LTC1286/98 AI07 LABEL MNEMONIC OPERAND COMMENTS LABEL MNEMONIC OPERAND COMMENTS LDAA #$50 CONFIGURATION DATA FOR SPCR WAIT1 BPL WAIT1 CHECK IF TRANSFER IS DONE STAA $1028 LOAD DATA INTO SPCR ($1028) LDAA $51 LOAD DIN INTO ACC A FROM $51 LDAA #$1B CONFIG. DATA FOR PORT D DDR STAA $102A LOAD DIN INTO SPI, START SCK STAA $1009 LOAD DATA INTO PORT D DDR WAIT2 LDAA $1029 CHECK SPI STATUS REG LDAA #$01 LOAD DIN WORD INTO ACC A BPL WAIT2 CHECK IF TRANSFER IS DONE STAA $50 LOAD DIN DATA INTO $50 LDAA $102A LOAD LTC1291 MSBs INTO ACC A LDAA #$A0 LOAD DIN WORD INTO ACC A STAA $62 STORE MSBs IN $62 STAA $51 LOAD DIN DATA INTO $51 LDAA $52 LOAD DUMMY INTO ACC A LDAA #$00 LOAD DUMMY DIN WORD INTO FROM $52 ACC A STAA $102A LOAD DUMMY DIN INTO SPI, STAA $52 LOAD DUMMY DIN DATA INTO $52 START SCK LDX #$1000 LOAD INDEX REGISTER X WITH WAIT3 LDAA $1029 CHECK SPI STATUS REG $1000 BPL WAIT3 CHECK IF TRANSFER IS DONE LOOP BCLR $08,X,#$01 D0 GOES LOW (CS GOES LOW) BSET $08,X#$01 DO GOES HIGH (CS GOES HIGH) LDAA $50 LOAD DIN INTO ACC A FROM $50 LDAA $102A LOAD LTC1291 LSBs IN ACC STAA $102A LOAD DIN INTO SPI, START SCK STAA $63 STORE LSBs IN $63 LDAA $1029 CHECK SPI STATUS REG JMP LOOP START NEXT CONVERSION 21

LTC1286/LTC1298 TYPICAL APPLICATIONUS N Interfacing to the Parallel Port of the INTEL 8051 LABEL MNEMONIC OPERAND COMMENTS Family MOV A, #FFH D word for LTC1298 IN SETB P1.4 Make sure CS is high The Intel 8051 has been chosen to demonstrate the CLR P1.4 CS goes low interface between the LTC1298 and parallel port micro- MOV R4, #04 Load counter LOOP 1 RLC A Rotate D bit into Carry processors. Normally the CS, CLK and D signals would IN IN CLR P1.3 SCLK goes low be generated on 3 port lines and the DOUT signal read on MOV P1.2, C Output DIN bit to LTC1298 a 4th port line. This works very well. However, we will SETB P1.3 SCLK goes high DJNZ R4, LOOP 1 Next bit demonstrate here an interface with the D and D of the IN OUT MOV P1, #04 Bit 2 becomes an input LTC1298 tied together as described in the SERIAL INTER- CLR P1.3 SCLK goes low MOV R4, #09 Load counter FACE section. This saves one wire. LOOP 2 MOV C, P1.2 Read data bit into Carry RLC A Rotate data bit into Acc. The 8051 first sends the start bit and MUX address to the SETB P1.3 SCLK goes high LTC1298 over the data line connected to P1.2. Then P1.2 CLR P1.3 SCLK goes low is reconfigured as an input (by writing to it a one) and the DJNZ R4, LOOP 2 Next bit MOV R2, A Store MSBs in R2 8051 reads back the 12-bit A/D result over the same data CLR A Clear Acc. line. MOV R4, #04 Load counter LOOP 3 MOV C, P1.2 Read data bit into Carry RLC A Rotate data bit into Acc. CS P1.4 SETB P1.3 SCLK goes high ANALOG CLK P1.3 CLR P1.3 SCLK goes low LTC1298 8051 INPUTS DOUT P1.2 DJNZ R4, LOOP 3 Next bit DIN MUX ADDRESS MOV R4, #04 Load counter LOOP 4 RRC A Rotate right into Acc. A/D RESULT DJNZ R4, LOOP 4 Next Rotate LTC1286/98 TA01 MOV R3, A Store LSBs in R3 SETB P1.4 CS goes high D FROM 1298 STORED IN 8501 RAM OUT MSB R2 B11 B10 B9 B8 B7 B6 B5 B4 LSB R3 B3 B2 B1 B0 0 0 0 0 MSBF BIT LATCHED INTO LTC1298 CS CLK DATA SGL/ (DIN/DOUT) START DIFF ODD/ MSBF B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 SIGN 8051 P1.2 OUTPUTS DATA LTC1298 SENDS A/D RESULT TO LTC1298 BACK TO 8051 P1.2 8051 P1.2 RECONFIGURED LTC1298 TAKES CONTROL OF DATA AS IN INPUT AFTER THE 4TH RISING CLK AND BEFORE THE 4TH FALLING CLK LINE ON 4TH FALLING CLK LTC1286/98 TA02 22

LTC1286/LTC1298 TYPICAL APPLICATIONUS N A “Quick Look” Circuit for the LTC1286 Users can get a quick look at the function and timing of the Micropower Battery Voltage Monitor LT1286 by using the following simple circuit (Figure 13). A common problem in battery systems is battery voltage V is tied to V . V is applied to the +IN input and the REF CC IN monitoring. This circuit monitors the 10 cell stack of NiCad –IN input is tied to the ground. CS is driven at 1/16 the or NiMH batteries found in laptop computers. It draws only clock rate by the 74C161 and D outputs the data. The OUT 67m A from the 5V supply at f = 0.1kHz and 25m A to SMPL output data from the D pin can be viewed on an OUT 55m A from the battery. The 12-bits of resolution of the oscilloscope that is set up to trigger on the falling edge of LTC1286 are positioned over the desired range of 8V to CS (Figure 14). Note the LSB data is partially clocked out 16V. This is easily accomplished by using the ADC’s before CS goes high. differential inputs. Tying the –input to the reference gives an ADC input span of V to 2V (2.5V to 5V). The REF REF resistor divider then scales the input voltage for 8V to 16V. 4.7m F 5V CLR VCC 5V BATTERY MONITOR 5V VREF VCC CLK RC INPUT 8V TO 16V A QA VIN +IN CLK B QB 0.1m F 74C161 LTC1286 C QC 200k 39k –IN DOUT D QD VCC P T +IN CS GND CS GND LOAD LTC1286 CLK –IN DOUT CLOCK IN 250kHz 1m F VREF GND 91k LT1004-2.5 TO OSCILLOSCOPE 3W LTC1286/98 F13 Figure 13. “Quick Look” Circuit for the LTC1286 LTC1286/98 F15 Figure 15. Micropower Battery Voltage Monitor NULL MSB LSB BIT (B11) (B0) VERTICAL: 5V/DIV HORIZONTAL: 10µs/DIV LTC1286/98 F14 Figure 14. Scope Trace the LTC1286 “Quick Look” Circuit Showing A/D Output 101010101010 (AAA ) HEX Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 23 However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1286/LTC1298 PACKAGE DESCRIPTIONU Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead Plastic DIP 0.400 0.300 – 0.320 0.045 – 0.065 0.130 ± 0.005 (10.160) (7.620 – 8.128) (1.143 – 1.651) (3.302 ± 0.127) MAX 8 7 6 5 0.065 (1.651) 0.009 – 0.015 TYP 0.250 ± 0.010 (0.229 – 0.381) 0.125 (6.350 ± 0.254) (3.175) 0.020 0.325+0.025 0.045 ± 0.015 MIN (0.508) ( –0.015) MIN +0.635 (1.143 ± 0.381) 1 2 3 4 8.255 –0.381 0.100 ± 0.010 0.018 ± 0.003 (2.540 ± 0.254) (0.457 ± 0.076) S8 Package 8-Lead Plastic SOIC 0.189 – 0.197* (4.801 – 5.004) 0.010 – 0.020 · 45(cid:176) 0.053 – 0.069 8 7 6 5 (0.254 – 0.508) (1.346 – 1.752) 0.004 – 0.010 0.008 – 0.010 (0.203 – 0.254) 0°– 8° TYP (0.101 – 0.254) 0.228 – 0.244 0.150 – 0.157* 0.016 – 0.050 (5.791 – 6.197) (3.810 – 3.988) 0.014 – 0.019 0.050 0.406 – 1.270 (0.355 – 0.483) (1.270) BSC 1 2 3 4 SO8 0294 *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm). 24 Linear Technology Corporation sn128698 128698fs LT/GP 0394 10K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7487 (408) 432-1900 l F AX: (408) 434-0507 l TELEX: 499-3977 ª LINEAR TECHNOLOGY CORPORATION 1994

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: LTC1286IS8 LTC1298CN8 LTC1298CS8#PBF LTC1286IS8#TRPBF LTC1298CN8#PBF LTC1286CS8 LTC1298IS8#TRPBF LTC1286CS8#TRPBF LTC1298IN8#PBF LTC1298CS8#TR LTC1298CS8 LTC1298IS8 LTC1286IN8#PBF LTC1286CS8#TR LTC1286IS8#TR LTC1298IN8 LTC1298IS8#PBF LTC1298IS8#TR LTC1286CS8#PBF LTC1286CN8 LTC1286CN8#PBF LTC1298CS8#TRPBF LTC1286IS8#PBF LTC1286IN8