LTC1143/LTC1143L LTC1143L-ADJ Dual High Efficiency SO-16 Step-Down Switching Regulator Controllers FEATURES DESCRIPTIOUN n Dual Outputs The LTC1143 series is a dual step-down switching regulator LTC1143, LTC1143L: 3.3V, 5V controller featuring automatic Burst ModeTM operation to LTC1143L-ADJ: Dual Adjustable maintain high efficiencies at low output currents. This n Very High Efficiency: Over 95% Possible device is composed of two separate regulator blocks, n Current Mode Operation for Excellent Line and Load each driving an external power MOSFET at switching Transient Response frequencies up to 400kHz using a constant off-time current mode architecture. Both fixed and adjustable voltages are n High Efficiency Maintained over Three Decades of available. Output Current n Low Standby Current at Light Loads: 160m A/Output The operating current level for both regulators is user- n Logic-Controlled Shutdown (LTC1143, LTC1143L) programmable via an external current sense resistor. n Wide V Range: 3.5V to 16V Wide input supply range allows operation from 4V to 14V IN (LTC1143L, LTC1143L-ADJ) (16V maximum). The LTC1143L and LTC1143L-ADJ n Very Low Dropout Operation: 100% Duty Cycle extend operation to V = 3.5V. 100% duty cycle provides IN n Available in Narrow 16-Pin SO Package low dropout regulation limited only by the R of the DS(ON) external MOSFET and resistance of the inductor and APPLICATIOUNS current sense resistor. n Personal Digital Assistants The LTC1143 series is ideal for applications requiring dual output voltages with high conversion efficiencies over a n Notebook and Palmtop Computers wide load current range in a small amount of board space. n Battery-Operated Digital Devices n Portable Instruments , LTC and LT are registered trademarks of Linear Technology Corporation. n DC Power Distribution Systems Burst Mode is a trademark of Linear Technology Corporation. TYPICAL APPLICATIONU VIN(cid:13) 4V TO 14V + 2C2INm1F(cid:13)(cid:13) 0.22m F 0.22m F + C22INm2F(cid:13)(cid:13) 25V(cid:13) 2· 52V(cid:13) 13 5 · 2 P1A VIN1 VIN2 P1B VOUT1(cid:13) R0S.E0N5SWE1(cid:13) 27Lm1H(cid:13) 4 P-DRIVE 1 P-DRIVE 2 12 27Lm2H(cid:13) R0S.E0N5SWE2(cid:13) VOUT2(cid:13) 3.3V/2A 1 SENSE+ 1 SENSE+ 2 9 2.5V/2A 1000pF LTC1143L-ADJ 1000pF 2C2O10U· 0mTV2F1(cid:13)(cid:13)(cid:13) + R812%2.(cid:13)5k(cid:13) DM1B(cid:13)RS320T3162 VSFEBN1SE– 1 SENSVEF–B 22 81M0BRS320DT23(cid:13) 491.R9%4k(cid:13)(cid:13) + C21· 20O20VUm(cid:13)T2F(cid:13)(cid:13) R1(cid:13) GND1 CT1 ITH1 ITH2 CT2 GND2 R3(cid:13) 49.9k(cid:13) 100pF 3 14 15 7 6 11 100pF 49.9k(cid:13) 1% 1% RC1(cid:13) RC2(cid:13) 1k 1k (cid:13)L1, L2: SUMIDA CDRH125-270(cid:13) 300CpTF1(cid:13) 3C3C01(cid:13)0pF(cid:13) 330C0pCF2(cid:13) C30T20(cid:13)pF P1: SILICONIX Si4953DY/FAIRCHILD NDS8947(cid:13) (cid:13) RSENSE1, RSENSE2: DALE WSL-2010-.05 1143 F01 Figure 1. High Efficiency Dual 3.3V/2.5V Regulator 1

LTC1143/LTC1143L LTC1143L-ADJ ABSOLUTE WMAXIWMUWM RATINUGS Input Supply Voltage (Pins 5,13)...............16V to –0.3V V Current (LTC1143L-ADJ, Pins 2, 10) ............... 1mA FB Continuous Output Current (Pins 4,12) ................ 50mA Operating Temperature Range Sense Voltages (Pins 1, 8, 9, 16) Ambient ..................................................0(cid:176) C to 70(cid:176) C V ‡ 12.7V.......................................... 13V to –0.3V Extended Commercial (Note 4) ...........–40(cid:176) C to 85(cid:176) C IN V < 12.7V ..............................(V + 0.3V) to –0.3V Junction Temperature (Note 1).............................125(cid:176) C IN IN Shutdown Voltage Storage Temperature Range..................–65(cid:176) C to 150(cid:176) C (LTC1143, LTC1143L, Pins 2, 10)...........7V to –0.3V Lead Temperature (Soldering, 10 sec)..................300(cid:176) C PACKAGE/ORDER IUNFORWMATIOUN TOP VIEW ORDER PART TOP VIEW ORDER PART SENSE+3(cid:13) 1(cid:13) 16(cid:13) SENSE–3(cid:13) NUMBER SENSE+1(cid:13) 1(cid:13) 16(cid:13) SENSE–1(cid:13) NUMBER SHUTDOWN 3(cid:13) 2(cid:13) 15(cid:13) ITH3(cid:13) VFB1(cid:13) 2(cid:13) 15(cid:13) ITH1(cid:13) GND3(cid:13) 3(cid:13) 14(cid:13) CT3(cid:13) LTC1143CS GND1(cid:13) 3(cid:13) 14(cid:13) CT1(cid:13) LTC1143LCS-ADJ P-DRIVE 3(cid:13) 4(cid:13) 13(cid:13) VIN3(cid:13) LTC1143LCS P-DRIVE 1(cid:13) 4(cid:13) 13(cid:13) VIN1(cid:13) VIN5(cid:13) 5(cid:13) 12(cid:13) P-DRIVE 5(cid:13) VIN2(cid:13) 5(cid:13) 12(cid:13) P-DRIVE 2(cid:13) CT5(cid:13) 6(cid:13) 11(cid:13) GND5(cid:13) CT2(cid:13) 6(cid:13) 11(cid:13) GND2(cid:13) ITH5(cid:13) 7(cid:13) 10(cid:13) SHUTDOWN 5(cid:13) ITH2(cid:13) 7(cid:13) 10(cid:13) VFB2(cid:13) SENSE–5(cid:13) 8 9 SENSE+5 SENSE–2 8 9 SENSE+2 (cid:13) S PACKAGE(cid:13) S PACKAGE(cid:13) 16-LEAD PLASTIC SO 16-LEAD PLASTIC SO TJMAX = 125(cid:176)C, q JA = 95(cid:176)C/W TJMAX = 125(cid:176)C, q JA = 95(cid:176)C/W Consult factory for Industrial and Military grade parts. ELECTRICAL CHARACTERISTICS T = 25(cid:176) C, V = 10V unless otherwise noted. A IN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V , V Feedback Voltage (LTC1143L-ADJ) V = 9V l 1.21 1.25 1.29 V 2 10 IN I , I Feedback Current (LTC1143L-ADJ) l 0.2 1 m A 2 10 V Regulated Output Voltage (LTC1143/LTC1143L) V V = 9V, V = V = 0V OUT IN3, IN5 2 10 3.3V Output I = 700mA l 3.23 3.33 3.43 V LOAD 5V Output I = 700mA l 4.90 5.05 5.20 V LOAD D V Output Voltage Line Regulation V = 7V to 12V, I = 50mA –40 0 40 mV OUT IN LOAD Output Voltage Load Regulation V = V = 0V 2 10 LTC1143/LTC1143L 3.3V Output 5mA < I < 2.0A l 40 65 mV LOAD 5V Output 5mA < I < 2.0A l 60 100 mV LOAD Output Ripple (Burst Mode) I = 0A 50 mV LOAD P-P I , I Input DC Supply Current (Note 2) 5 13 LTC1143: Normal Mode V = V = 0V, 4V < V < 12V 1.6 2.1 mA 2 10 IN Sleep Mode V = V = 0V, 4V < V < 12V, 6V < V < 12V 160 230 m A 2 10 IN3 IN5 Shutdown V = V = 2.1V, 4V < V < 12V 10 20 m A 2 10 IN LTC1143L: Normal Mode V = V = 0V, 3.5V < V < 12V 1.6 2.1 mA 2 10 IN Sleep Mode V = V = 0V, 3.5V < V < 12V, 6V < V < 12V 160 230 m A 2 10 IN3 IN5 Shutdown V = V = 2.1V, 3.5V < V < 12V 10 20 m A 2 10 IN LTC1143L-ADJ: Normal Mode 3.5V < V < 12V 1.6 2.1 mA IN Sleep Mode 3.5V < V < 12V, V £ 3.3V 160 230 m A IN OUT 2

LTC1143/LTC1143L LTC1143L-ADJ ELECTRICAL CHARACTERISTICS T = 25(cid:176) C, V = 10V unless otherwise noted. A IN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V to V , Current Sense Threshold Voltage 1 16 V to V LTC1143/LTC1143L V = V = 0V 8 9 2 10 V –= V + 100mV (Forced) 25 mV SENSE OUT V – = V – 100mV (Forced) l 130 150 170 mV SENSE OUT LTC1143L-ADJ V – = 5V, V = V /4 + 25mV (Forced) 25 mV SENSE FB OUT V – = 5V, V = V /4 – 25mV (Forced) l 130 150 170 mV SENSE FB OUT V , V Shutdown Pin Threshold 0.5 0.8 2 V 2 10 LTC1143/LTC1143L I , I Shutdown Pin Input Current 0V < V = < 8V, V V = 16V 1.2 5 m A 2 10 SHUTDOWN IN3, IN5 LTC1143/LTC1143L I , I C Pin Discharge Current V in Regulation, V = V 50 70 90 m A 6 14 T OUT SENSE- OUT V = 0V 2 10 m A OUT t Off-Time (Note 3) C = 390pF, I = 700mA 4 5 6 m s OFF T LOAD t, t Driver Output Transition Times C = 3000pF (Pins 4, 12), V = 6V 100 200 ns r f L IN –40(cid:176) C £ T £ 85(cid:176) C (Note 4), V = 10V unless otherwise noted. A IN V , V Feedback Voltage (LTC1143L-ADJ) V = 9V 1.20 1.25 1.30 V 2 10 IN V Regulated Output Voltage V V = 9V OUT IN3, IN5 LTC1143/LTC1143L 3.3V Output I = 700mA 3.17 3.33 3.43 V LOAD 5V Output I = 700mA 4.85 5.05 5.20 V LOAD I , I Input DC Supply Current (Note 2) 5 13 LTC1143: Normal Mode V = V = 0V, 4V < V < 12V 1.6 2.4 mA 2 10 IN Sleep Mode V = V = 0V, 4V < V < 12V, 6V < V < 12V 160 260 m A 2 10 IN3 IN5 Shutdown V = V = 2.1V, 4V < V < 12V 10 22 m A 2 10 IN LTC1143L: Normal Mode V = V = 0V, 3.5V < V < 12V 1.6 2.4 mA 2 10 IN Sleep Mode V = V = 0V, 3.5V < V < 12V, 6V < V < 12V 160 260 m A 2 10 IN3 IN5 Shutdown V = V = 2.1V, 3.5V < V < 12V 10 22 m A 2 10 IN LTC1143L-ADJ: Normal Mode 3.5V < V < 12V 1.6 2.4 mA IN Sleep Mode 3.5V < V < 12V, V £ 3.3V 160 260 m A IN OUT V to V , Current Sense Threshold Voltage 1 16 V to V LTC1143/LTC1143L V = V = 0V 8 9 2 10 V –= V + 100mV (Forced) 25 mV SENSE OUT V – = V – 100mV (Forced) 125 150 185 mV SENSE OUT LTC1143L-ADJ V – = 5V, V = V /4 + 25mV (Forced) 25 mV SENSE FB OUT V – = 5V, V = V /4 – 25mV (Forced) 125 150 185 mV SENSE FB OUT V , V Shutdown Pin Threshold 0.55 0.8 2 V 2 10 LTC1143/LTC1143L The l denotes specifications which apply over the specified temperature is higher due to the gate charge being delivered at the switching range. frequency. See Applications Information. Note 1: T is calculated from the ambient temperature T and power Note 3: In applications where R is placed at ground potential, the J A SENSE dissipation P according to the following formula: off-time increases approximately 40%. D LTC1143 series: T = T + (P • 125(cid:176) C/W) Note 4: The LTC1143 series is guaranteed to meet specified performance J A D Note 2: This supply current is for one regulator block. Total supply from 0(cid:176) C to 70(cid:176) C and is designed, characterized and expected to meet current is the sum of Pin 5 and Pin 13 currents. Dynamic supply current these extended temperature limits, but is not tested at –40(cid:176) C to 85(cid:176) C. 3

LTC1143/LTC1143L LTC1143L-ADJ TYPICAL PERFORWMAUNCE CHARACTERISTICS 5V Output Efficiency 3.3V Output Efficiency 5V Efficiency vs Input Voltage 100 100 100(cid:13) VIN = 6V 98(cid:13) VOUT = 5V 95 95 96(cid:13) VIN = 5V 94(cid:13) CY (%) 90 VIN = 10V CY (%) 90 Y (%) 92(cid:13) ILOAD = 1A EN 85 EN 85 VIN = 10V NC 90(cid:13) EFFICI 80 EFFICI 80 EFFICIE 88(cid:13) ILOAD = 100mA 86(cid:13) 84(cid:13) 75 75 82(cid:13) 70 70 80(cid:13) 1 10 100 1000 1 10 100 1000 0 4 8 12 16 (cid:13) INPUT VOLTAGE (V) LOAD CURRENT (mA) LOAD CURRENT (mA) (cid:13) LTC1143 G01 LTC1143 G02 1143 G03 3.3V Efficiency vs Input Voltage Line Regulation Load Regulation 100(cid:13) 40(cid:13) 20(cid:13) 98(cid:13) V(cid:13) OUT = 3.3V(cid:13) 30(cid:13) VILOOUATD == 51VA(cid:13) 0(cid:13) RSENSE = 0.05W 96(cid:13) 20(cid:13) 94(cid:13) VIN = 6V Y (%) 92(cid:13) mV) 10(cid:13) mV) –20(cid:13) VIN = 12V EFFICIENC 988086(cid:13)(cid:13)(cid:13) ILOAD = 100mA ILOAD = 1A DV (OUT–100(cid:13)(cid:13) DV (OUT––4600(cid:13)(cid:13) VIN = 6V –20(cid:13) 84(cid:13) VIN = 12V –30(cid:13) –80(cid:13) VOUT = 5V(cid:13) 82(cid:13) VOUT = 3.3V 80 –40 –100(cid:13) 0 4 8 12 16 0 4 8 12 16 0 0.5 1.0 1.5 2.0 2.5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) LOAD CURRENT (A) (cid:13) LTC1143 G04 LTC1143 G05 LTC1143 G06 DC Supply Current Supply Current in Shutdown Operating Frequency vs V – V IN OUT 2.1 20(cid:13) 1.6(cid:13) NOT INCLUDING(cid:13) PINS 5, 13 18(cid:13) PER LTC1143/LTC1143L(cid:13) VOUT = 5V 1.8 GATE CHARGE CURRENT REGULATOR BLOCK(cid:13) 1.4(cid:13) 16(cid:13) PINS 5, 13(cid:13) Y 0°C mA) 1.5 ACTIVE MODE A) 14(cid:13) VSHUTDOWN = 2V ENC 1.2(cid:13) 25°C RRENT ( 1.2 mRRENT ( 1120(cid:13)(cid:13) D FREQU 10..08(cid:13)(cid:13) 70°C U PER REGULATOR BLOCK U E SUPPLY C 00..96 (cid:13) SUPPLY C 86(cid:13)(cid:13) NORMALIZ 00..64(cid:13)(cid:13) 4(cid:13) 0.3 SLEEP MODE 2(cid:13) 0.2(cid:13) 0 0 0 0 2 4 6 8 10 12 14 16 18 0 2 4 6 8 10 12 14 16 18 0 2 4 6 8 10 12 INPUT VOLTAGE (V) INPUT VOLTAGE (V) (VIN – VOUT) VOLTAGE (V) LTC1143 G08 LTC1143 G09 LTC1143 • G07 4

LTC1143/LTC1143L LTC1143L-ADJ TYPICAL PERFORWMAUNCE CHARACTERISTICS Gate Charge Supply Current Off-Time vs V Current Sense Threshold Voltage OUT 14(cid:13) 80(cid:13) 175(cid:13) VSENSE = VOUT MAXIMUM(cid:13) 12(cid:13) 70(cid:13) 150(cid:13) THRESHOLD A) m 60(cid:13) ATE CHARGE CURRENT ( 10864(cid:13)(cid:13)(cid:13)(cid:13) QP = 100QnPC = 29nC mOFF-TIME (s) 54320000(cid:13)(cid:13)(cid:13)(cid:13) SENSE VOLTAGE (mV) 1120755050(cid:13)(cid:13)(cid:13)(cid:13) MINIMUM(cid:13) G 2(cid:13) 10(cid:13) VOUT = 5V 25(cid:13) THRESHOLD VOUT = 3.3V 0 0 0 20 80 140 200 260 0 1 2 3 4 5 0 20 40 60 80 100 OPERATING FREQUENCY (kHz) OUTPUT VOLTAGE (V) TEMPERATURE (°C) LTC1143 G10 LTC1143 G11 LTC1143 G12 PIUN FUUNCTIOUNS LTC1143/LTC1143L I (Pin 7): Gain Amplifier Decoupling Point, 5V Section. TH5 The 5V section current comparator threshold increases SENSE+3 (Pin 1): The (+) Input to the 3.3V Section Current with the Pin 7 voltage. Comparator. A built-in offset between Pins 1 and 16 in conjunction with R sets the current trip threshold SENSE– 5 (Pin 8): Connects to internal resistive divider SENSE 3 for the 3.3V section. which sets the output voltage for the 5V section. Pin 8 is also the (–) input for the current comparator on the 5V SHUTDOWN 3 (Pin 2): When grounded, the 3.3V section section. operates normally. Pulling Pin 2 high holds the MOSFET off and puts the 3.3V section in micropower shutdown SENSE+ 5 (Pin 9): The (+) Input to the 5V Section Current mode. Requires CMOS logic level signal with t, t < 1m s. Comparator. A built-in offset between Pins 9 and 8 in r f Do not “float” Pin 2. conjunction with RSENSE 5 sets the current trip threshold for the 5V section. GND3 (Pin 3): 3.3V Section Ground. Two independent ground lines must be routed separately from other grounds SHUTDOWN 5 (Pin 10): When grounded, the 5V section to: 1) the (–) terminal of the 3.3V section output capacitor operates normally. Pulling Pin 10 high holds the 5V section and 2) the cathode of the Schottky diode D1 and (–) MOSFET off and puts the 5V section in micropower shut- terminal of CIN3 (see Figure 9). down mode. Requires CMOS logic level signal with tr, tf < 1m s. Do not “float” Pin 10. P-DRIVE 3 (Pin 4): High Current Drive for Top P-Channel MOSFET, 3.3V Section. Voltage swing at this pin is from GND5 (Pin 11): 5V Section Ground. Two independent V to ground. ground lines must be routed separately from other grounds IN3 to: 1) the (–) terminal of the 5V section output capacitor V (Pin 5): Supply Pin, 5V Section. Must be closely IN5 and 2) the cathode of the Schottky diode D2 and (–) decoupled to 5V power ground Pin 11. terminal of C (see Figure 9). IN5 C (Pin 6): External capacitor C from Pin 6 to ground sets T5 T5 P-DRIVE 5 (Pin 12): High Current Drive for Top P-Channel the operating frequency for the 5V section. (The actual MOSFET, 5V Section. Voltage swing at this pin is from frequency is also dependent upon the input voltage.) V to ground. IN5 5

LTC1143/LTC1143L LTC1143L-ADJ PIUN FUUNCTIOUNS V (Pin 13): Supply Pin, 3.3V Section. Must be closely I (Pin 7): Gain Amplifier Decoupling Point, Section 2. IN3 TH2 decoupled to 3.3V power ground Pin 3. The section 2 current comparator threshold increases with the Pin 7 voltage. C (Pin 14): External capacitor C from Pin 14 to ground T3 T3 sets the operating frequency for the 3.3V section. (The SENSE– 2 (Pin 8): Pin 8 is the (–) input for the current actual frequency is also dependent upon the input voltage.) comparator on section 2. I (Pin 15): Gain Amplifier Decoupling Point, 3.3V SENSE+ 2 (Pin 9): The (+) Input to the Section 2 Current TH3 Section. The 3.3V section current comparator threshold Comparator. A built-in offset between Pins 9 and 8 in increases with the Pin 15 voltage. conjunction with R sets the current trip threshold SENSE 2 for section 2. SENSE– 3 (Pin 16): Connects to internal resistive divider which sets the output voltage for the 3.3V V (Pin 10): This pin serves as the feedback pin from an FB2 section. Pin 16 is also the (–) input for the current external resistive divider used to set the output voltage for comparator on the 3.3V section. section 2. LTC1143L-ADJ GND2 (Pin 11): Section 2 Ground. Two independent ground lines must be routed separately from other grounds SENSE+ 1 (Pin 1): The (+) Input to the Section 1 Current to: 1) the (–) terminal of section 2 output capacitor and 2) Comparator. A built-in offset between Pins 1 and 16 in the cathode of the Schottky diode D2 and (–) terminal of conjunction with RSENSE 1 sets the current trip threshold CIN2 (see Figure 1). for section 1. P-DRIVE 2 (Pin 12): High Current Drive for Top P-Channel VFB1 (Pin 2): This pin serves as the feedback pin from an MOSFET, Section 2. Voltage swing at this pin is from VIN2 external resistive divider used to set the output voltage for to ground. section 1. V (Pin 13): Supply Pin, Section 1. Must be closely IN1 GND1 (Pin 3): Section 1 Ground. Two independent ground decoupled to power ground Pin 3. lines must be routed separately from other grounds to: 1) C (Pin 14): External capacitor C from Pin 14 to ground the (–) terminal of the section 1 output capacitor and 2) the T1 T1 sets the operating frequency for section 1. (The actual cathode of the Schottky diode D1 and (–) terminal of C IN1 frequency is also dependent upon the input voltage.) (see Figure 1). I (Pin 15): Gain Amplifier Decoupling Point, Section 1. P-DRIVE 1 (Pin 4): High Current Drive for Top P-Channel TH1 The section 1 current comparator threshold increases MOSFET, Section 1. Voltage swing at this pin is from V IN1 with the Pin 15 voltage. to ground. SENSE– 1 (Pin 16): Pin 16 is the (–) input for the V (Pin 5): Supply Pin, Section 2. Must be closely IN2 current comparator on section 1. decoupled to power ground Pin 11. C (Pin 6): External capacitor C from Pin 6 to ground sets T2 T2 the operating frequency for section 2. (The actual frequency is also dependent upon the input voltage.) 6

LTC1143/LTC1143L LTC1143L-ADJ (cid:13) (cid:13) FUUNCTIOUNAL DIAGRAW Only one regulator block shown. Connections shown for LT1143/LTC1143L; changes create LTC1143L-ADJ 13(5) VIN SENSE+ SENSE– 4(12) P-DRIVE 1(9) 16(8) 3(11) GROUND – V SLEEP + – R C 25mV TO 150mV + Q S + – + 5pF S VOS – VTH1 – ITH 13k – X VTH2 T 15(7) G + + 1.25V SHUTDOWN(cid:13) 100k (LTC1143/LTC1143L) 14(6) OFF-TIME(cid:13) VIN 2(10) X REFERENCE CONTROL SENSE– CT VFB(cid:13) (LTC1143L-ADJ) 1143 FD OPERATIOUN Refer to Functional Diagram and Figure 1. The LTC1143 series consists of two individual regulator connected to Pin 14 (6) is now allowed to discharge at a blocks, each using current mode, constant off-time archi- rate determined by the off-time controller. The discharge tectures to switch an external power MOSFET. The two current is made proportional to the feedback voltage to LTC1143/LTC1143L regulators are internally set for 3.3V model the inductor current, which decays at a rate that is and 5V, while the two LTC1143L-ADJ regulators have also proportional to the output voltage. externally programmable output voltages. Operating fre- When the voltage on the timing capacitor has discharged quency is individually set on each section by external past V , comparator T trips, setting the flip-flop. This TH1 capacitors at the timing capacitor Pins 6 and 14. causes the P-drive output to go low, turning the P-channel The output voltage is sensed by voltage comparator V and MOSFET back on. The cycle then repeats. gain block G, which compare the divided output voltage As the load current increases, the output voltage with a reference voltage of 1.25V. To optimize efficiency, decreases slightly. This causes the output of the gain the LTC1143 series automatically switches between two stage [Pin 15 (7)] to increase the current comparator modes of operation, burst and continuous. The voltage threshold, thus tracking the load current. comparator is the primary control element when the device is in Burst Mode operation, while the gain block The sequence of events for Burst Mode operation is very controls the output voltage in continuous mode. similar to continuous operation with the cycle interrupted by the voltage comparator. When the output voltage is at During the switch “ON” cycle in continuous mode, current or above the desired regulated value, the P-channel comparator C monitors the voltage between Pins 1 (9) and MOSFET is held off by comparator V and the timing 16 (8) connected across an external shunt in series with capacitor continues to discharge below V . When the TH1 the inductor. When the voltage across the shunt reaches timing capacitor discharges past V , voltage compara- TH2 its threshold value, the P-drive output is switched to V , IN tor S trips, causing the internal sleep line to go low. turning off the P-channel MOSFET. The timing capacitor 7

LTC1143/LTC1143L LTC1143L-ADJ OPERATIOUN Refer to Functional Diagram and Figure 1 The circuit now enters sleep mode with the power MOSFET rated in the gain stage. This prevents the current compara- turned off. In sleep mode a majority of the circuitry is tor threshold from increasing until the output voltage has turned off, dropping the quiescent current from 1.6mA to dropped below a minimum threshold. 160m A (for one regulator block). The load current is now Using constant off-time architecture the operating fre- being supplied from the output capacitor. When the output quency is a function of the input voltage. To minimize the voltage has dropped by the amount of hysteresis in frequency variation as dropout is approached, the off-time comparator V, the P-channel MOSFET is again turned on controller increases the C discharge current as V drops T IN and the process repeats. below V + 1.5V. In dropout the P-channel MOSFET is OUT To avoid the operation of the current loop interfering with turned on continuously (100% duty cycle), providing Burst Mode operation, a built-in offset (V ) is incorpo- extremely low dropout operation. OS APPLICATIOUNS INUFORWMATIOUN The basic LTC1143L-ADJ application circuit is shown in For Figure 1 applications with V below 2V, or when OUT Figure 1. The LTC1143 and LTC1143L are similar but omit R is moved to ground, the current sense comparator SENSE the external resistive V dividers (see Figures 10 and inputs operate near ground. When the current comparator OUT 13). External component selection is driven by the load is operated at less than 2V common mode, the off-time requirement and begins with V and the selection of increases approximately 40%, requiring the use of a OUT R . Once R is known, C and L can be chosen. smaller timing capacitor C . SENSE SENSE T T Next, the power MOSFET and D1 are selected. Finally, C IN R Selection for Output Current and C are selected and the loop is compensated. Since SENSE OUT the two regulator sections are identical, the process of R is chosen based on the required output current. SENSE component selection is the same for both sections. The The LTC1143 series current comparators have a threshold circuit shown in Figure 1 can be configured for operation range that extends from a minimum of 25mV/R to a SENSE up to an input voltage of 16V. maximum of 150mV/R . The current comparator SENSE threshold sets the peak of the inductor ripple current, Output Voltage Selection yielding a maximum output current I equal to the peak MAX The LTC1143/LTC1143L output voltages are internally set value less half the peak-to-peak ripple current. For proper to 3.3V and 5V. The LTC1143L-ADJ requires an external Burst Mode operation, I must be less than or RIPPLE(P-P) resistive divider from V to V on each section as equal to the minimum current comparator threshold. OUT FB shown in Figure 1. The regulated LTC1143L-ADJ output Since efficiency generally increases with ripple current, voltages are given by: the maximum allowable ripple current is assumed, i.e., I = 25mV/R . (See C and L Selection for RIPPLE(P-P) SENSE T (cid:230) (cid:246) (cid:82)(cid:50) Operating Frequency). Solving for R and allowing a (cid:86)(cid:79)(cid:85)(cid:84)(cid:49)=(cid:49).(cid:50)(cid:53)Ł(cid:231) (cid:49)+ (cid:82)(cid:49)ł(cid:247) margin for variations in the LTC1143S EsNeSrEies and external component values yields: (cid:230) (cid:246) (cid:82)(cid:52) (cid:86)(cid:79)(cid:85)(cid:84)(cid:50)=(cid:49).(cid:50)(cid:53)(cid:231) (cid:49)+ (cid:247) Ł (cid:82)(cid:51)ł 100mV(cid:13) R = SENSE I MAX To prevent stray pickup, a 100pF capacitor is suggested A graph for selecting R versus maximum output across R1 and R3 located close to the LTC1143L-ADJ. SENSE current is given in Figure 2. 8

LTC1143/LTC1143L LTC1143L-ADJ APPLICATIOUNS INUFORWMATIOUN 0.20(cid:13) (cid:49) (cid:230) (cid:86) - (cid:86) (cid:246) 0.15(cid:13) (cid:67)(cid:84) =(cid:49).(cid:51)(cid:230)Ł (cid:49)(cid:48)(cid:52)(cid:246)ł (cid:102)Ł(cid:231) (cid:73)(cid:86)(cid:78)(cid:73)(cid:78)+(cid:79)(cid:86)(cid:85)(cid:68)(cid:84)ł(cid:247) ) W (SE0.10(cid:13) where VD is the drop across the diode. N SE R A graph for selecting C versus frequency including the T 0.05(cid:13) effects of input voltage is given in Figure 3. 1000(cid:13) 0 0 1 2 3 4 5 VSENSE = VOUT = 5V MAXIMUM OUTPUT CURRENT (A) 800(cid:13) 1143 F02 F) Figure 2. Selecting RSENSE E (p600(cid:13) C N A CIT VIN = 12V The load current below which Burst Mode operation A400(cid:13) P A C commences, I , and the peak short circuit current, BURST 200(cid:13) VIN = 7V ISC(PK), both track IMAX. Once RSENSE has been chosen, VIN = 10V I and I can be predicted from the following: BURST SC(PK) 0 0 50 100 150 200 250 300 FREQUENCY (kHz) 15mV(cid:13) I » LTC1143 F03 BURST R SENSE Figure 3. Timing Capacitor Value 150mV(cid:13) I = SC(PK) R As the operating frequency is increased the gate charge SENSE losses will be higher, reducing efficiency (see Efficiency The LTC1143 series automatically extends t during a Considerations). The complete expression for operating OFF short circuit to allow sufficient time for the inductor frequency of the circuit in Figure 1 is given by: current to decay between switch cycles. The resulting (cid:230) (cid:246) I to be reduced to approximately I . (cid:49) (cid:86) SC(AVG) MAX (cid:102)» (cid:231) -(cid:49) (cid:79)(cid:85)(cid:84)(cid:247) (cid:116) Ł (cid:86) ł (cid:79)(cid:70)(cid:70) (cid:73)(cid:78) L and C Selection for Operating Frequency T Each regulator section of the LTC1143 series uses a where: constant off-time architecture with t determined by an OFF (cid:230) (cid:246) (cid:230) (cid:246) (cid:86) external timing capacitor CT. Each time the P-channel (cid:116)(cid:79)(cid:70)(cid:70)=(cid:49).(cid:51)Ł (cid:49)(cid:48)(cid:52)ł (cid:67)(cid:84)(cid:231) (cid:82)(cid:69)(cid:71)(cid:247) MOSFET switch turns on the voltage on CT is reset to Ł (cid:86)(cid:79)(cid:85)(cid:84)ł approximately 3.3V. During the off-time, CT is discharged VREG is the desired output voltage (i.e., 5V, 3.3V). VOUT by a current that is proportional to VOUT. The voltage on CT is the measured output voltage. Thus VREG/VOUT = 1 in is analogous to the current in inductor L, which likewise regulation. decays at a rate proportional to V . Thus the inductor OUT Note that as V decreases, the frequency decreases. value must track the timing capacitor value. IN When the input-to-output voltage differential drops below The value of CT is calculated from the desired continuous 1.5V for a particular section, the LTC1143 series reduces mode operating frequency: t in that section by increasing the discharge current in OFF C . This prevents audible operation prior to dropout. T 9

LTC1143/LTC1143L LTC1143L-ADJ APPLICATIOUNS INUFORWMATIOUN Once the frequency has been set by C , the inductor L must Power MOSFET Selection T be chosen to provide no more than 25mV/R of peak- SENSE An external power MOSFET must be selected for use with to-peak inductor ripple current. This results in a minimum each section of the LTC1143 series. The main selection required inductor value of: criteria for the power MOSFETs are the threshold voltage LMIN = 5.1(105)(RSENSE)(CT)VREG VGS(TH), maximum VGS rating and on resistance RDS(ON). Surface mount P-channel power MOSFETs are widely As the inductor value is increased from the minimum available in both single and dual configurations. Logic value, the ESR requirements for the output capacitor are level MOSFETs are specified for operation up to 20V eased at the expense of efficiency. If too small an inductor maximum V and guarantee a maximum R with is used, the inductor current will become discontinuous GS DS(ON) V = 4.5V. Newer ‘sub’ logic level MOSFETs allow only 8V before the LTC1143 series enters Burst Mode operation. A GS maximum V but guarantee R with V = 2.7V. If consequence of this is that the LTC1143 series will delay GS DS(ON) GS V will exceed 8V, logic level MOSFETs must be used; if entering Burst Mode operation and efficiency will be IN conservatively specified, they are generally usable down degraded at low currents. to the 3.5V minimum V rating of the LTC1143L and IN Inductor Core Selection LTC1143L-ADJ. The maximum output current I determines the R Once the minimum value for L is known, the type of MAX DS(ON) requirement for the two MOSFETs. When the LTC1143 inductor must be selected. The highest efficiency will be series is operating in continuous mode, the simplifying obtained using Ferrite, Kool Mm ® or Molypermalloy (MPP) assumption can be made that either the MOSFET or cores. Lower cost powdered iron cores provide suitable Schottky diode is always conducting the average load performance, but cut efficiency by 3% to 7%. Actual core current. The duty cycles for the MOSFET and diode are loss is independent of core size for a fixed inductor value, given by: but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and (cid:80)(cid:45)(cid:67)(cid:104)(cid:32)(cid:68)(cid:117)(cid:116)(cid:121)(cid:32)(cid:67)(cid:121)(cid:99)(cid:108)(cid:101)(cid:32)» (cid:86)(cid:79)(cid:85)(cid:84) therefore copper losses will increase. (cid:86) (cid:73)(cid:78) ( ) Ferrite designs have very low core loss, so design goals (cid:86) - (cid:86) + (cid:86) (cid:73)(cid:78) (cid:79)(cid:85)(cid:84) (cid:68) can concentrate on copper loss and preventing saturation. (cid:83)(cid:99)(cid:104)(cid:111)(cid:116)(cid:116)(cid:107)(cid:121)(cid:32)(cid:68)(cid:105)(cid:111)(cid:100)(cid:101)(cid:32)(cid:68)(cid:117)(cid:116)(cid:121)(cid:32)(cid:67)(cid:121)(cid:99)(cid:108)(cid:101)(cid:32)(cid:61)(cid:32) (cid:86) Ferrite core material saturates “hard,” which means that (cid:73)(cid:78) inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor From the duty cycles the required R for each MOSFET DS(ON) ripple current and consequent output voltage ripple that can be derived: can cause Burst Mode operation to be falsely triggered. Do ( ) not allow the core to saturate! (cid:86) (cid:80) (cid:73)(cid:78) (cid:80) (cid:80)(cid:45)(cid:67)(cid:104)(cid:32)(cid:82) (cid:61) Kool Mm (from Magnetics, Inc.) is a very good, low loss core (cid:68)(cid:83)(cid:40)(cid:79)(cid:78)(cid:41) (cid:230) (cid:246) ( ) material for toroids with a “soft” saturation characteristic. (cid:86)(cid:79)(cid:85)(cid:84)Ł(cid:231) (cid:73)(cid:77)(cid:65)(cid:88)(cid:50)ł(cid:247) (cid:49)+d (cid:80) Molypermalloy is slightly more efficient at high ( > 200 kHz) where P is the allowable power dissipation and d is the switching frequencies but quite a bit more expensive. P P temperature dependencies of R . P will be determined Toroids are very space efficient, especially when you can DS(ON) P by efficiency and/or thermal requirements (see Efficiency use several layers of wire, while inductors wound on Considerations). (1+ d ) is generally given for a MOSFET in bobbins are generally easier to surface mount. New designs P the form of a normalized R vs temperature curve, for surface mount are available from Coiltronics, Coilcraft DS(ON) and Sumida. Kool Mm is a registered trademark of Magnetics, Inc. 10

LTC1143/LTC1143L LTC1143L-ADJ APPLICATIOUNS INUFORWMATIOUN but d = 0.005/(cid:176) C can be used as an approximation for low RMS current must be used. The maximum RMS capacitor voltage MOSFETs. current is given by: When selecting the P-channel power MOSFET for each [ ( )](cid:49)/(cid:50) section, consideration should be given to using a dual MOSFET (cid:86) (cid:86) - (cid:86) (cid:79)(cid:85)(cid:84) (cid:73)(cid:78) (cid:79)(cid:85)(cid:84) with the other half used for the second regulator. Assuming (cid:67) (cid:32)(cid:82)(cid:101)(cid:113)(cid:117)(cid:105)(cid:114)(cid:101)(cid:100)(cid:32)(cid:73) » (cid:73) (cid:73)(cid:78) (cid:82)(cid:77)(cid:83) (cid:77)(cid:65)(cid:88) both sections are operating at similar currents, the required (cid:86)(cid:73)(cid:78) R will be half the value of a single MOSFET to stay within DS(ON) the package dissipation limit. Remember that worst-case This formula has a maximum at V = 2V , where I MOSFET dissipation occurs at minimum V . IN OUT RMS IN = I /2. This simple worst-case condition is commonly OUT used for design because even significant deviations do not Output Diode Selection (D1, D2) offer much relief. Note that capacitor manufacturer’s The Schottky diodes D1 and D2 shown in Figure 1 conduct ripple current ratings are often based on only 2000 hours during the off-time. It is important to adequately specify of life. This makes it advisable to further derate the the diode peak current and average power dissipation to capacitor, or to choose a capacitor rated at a higher not exceed the diode ratings. temperature than required. Several capacitors may also be The most stressful condition for the output diode is under paralleled to meet size or height requirements in the short circuit (V = 0V). Under this condition the diode design. Always consult the manufacturer if there is any OUT must safely handle I at close to 100% duty cycle. question. An additional 0.1m F to 1m F ceramic capacitor is SC(PK) Under normal load conditions the average current con- also required on each V line (Pins 5, 13) for high IN ducted by the diode is: frequency decoupling. ( ) The selection of C is driven by the required (ESR). The OUT (cid:86) - (cid:86) + (cid:86) ( ) (cid:73)(cid:78) (cid:79)(cid:85)(cid:84) (cid:68) ESR of C must be less than twice the value of R (cid:73) = (cid:73) OUT SENSE (cid:68)(cid:73)(cid:79)(cid:68)(cid:69) (cid:76)(cid:79)(cid:65)(cid:68) for proper operation of the LTC1143 series: (cid:86) (cid:73)(cid:78) C Required ESR < 2R Remember to keep lead lengths short and observe proper OUT SENSE grounding (see Board Layout Checklist) to avoid ringing Optimum efficiency is obtained by making the ESR equal and increased dissipation. to R . As the ESR is increased up to 2R the SENSE SENSE efficiency degrades by less than 1%. If the ESR is greater The forward voltage drop allowable in the diode is calcu- than 2R , the voltage ripple on the output capacitor lated from the maximum short-circuit current as: SENSE will prematurely trigger Burst Mode operation, resulting in disruption of continuous mode and an efficiency hit which (cid:80) (cid:86) » (cid:68) can be several percent. (cid:70) (cid:73)(cid:83)(cid:67)((cid:80)(cid:75)) Manufacturers such as Nichicon and United Chemicon where P is the allowable power dissipation and will be should be considered for high performance capacitors. D determined by efficiency and/or thermal requirements The OS-CON semiconductor dielectric capacitor available (see Efficiency Considerations). from Sanyo has the lowest ESR size/ratio of any aluminum electrolytic at a somewhat higher price. Once the ESR C and C Selection requirement for C has been met, the RMS current IN OUT OUT rating generally far exceeds the I requirement. In continuous mode, the source current of the P-channel RIPPLE(P-P) MOSFET is a square wave of duty cycle VOUT/VIN. To In surface mount applications multiple capacitors may prevent large voltage transients, a low effective series have to be parallel to meet the capacitance, ESR or RMS resistance (ESR) input capacitor sized for the maximum current handling requirements of the application. 11

LTC1143/LTC1143L LTC1143L-ADJ APPLICATIOUNS INUFORWMATIOUN Aluminum electrolytic and dry tantalum capacitors are During this recovery time V can be monitored for OUT both available in surface mount configurations. In the case overshoot or ringing which would indicate a stability of tantalum it is critical that the capacitors are surge tested problem. The Pin 15(7) external components shown in the for use in switching power supplies. An excellent choice is Figure 1 circuit will prove adequate compensation for the AVX TPS series of surface mount tantalums, available most applications. in case heights ranging from 2mm to 4mm. For example, A second, more severe transient is caused by switching in if 200m F/10V is called for in an application requiring 3mm loads with large (>1m F) supply bypass capacitors. The height, (2) AVX 100m F/10V (P/N TPSD 107M010) could be discharged bypass capacitors are effectively put in parallel used. Consult the manufacturer for other specific with C causing a rapid drop in V . No regulator can OUT OUT recommendations. deliver enough current to prevent this problem if the load At low supply voltages a minimum capacitance at C is switch resistance is low and it is driven quickly. The only OUT needed to prevent an abnormal low frequency operating solution is to limit the rise time of the switch drive so that mode (see Figure 4). When C is made too small the the load rise time is limited to approximately 25 • C . OUT LOAD output ripple at low frequencies will be large enough to trip Thus a 10m F capacitor would require a 250m s rise time, the voltage comparator. This causes Burst Mode operation limiting the charging current to about 200mA. to be activated when the LTC1143 series would normally be in continuous operation. The output remains in Efficiency Considerations regulation at all times. The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. 1000(cid:13) It is often useful to analyze individual losses to determine L = 50m H(cid:13) what is limiting the efficiency and which change would RSENSE = 0.02W 800(cid:13) produce the most improvement. Percent efficiency can be L = 25m H(cid:13) expressed as: F) 600(cid:13) RSENSE = 0.02W m (UT %Efficiency = 100% – (L1 + L2 + L3 + ...) O C 400(cid:13) where L1, L2, etc. are the individual losses as a percentage L = 50m H(cid:13) of input power. (For high efficiency circuits only small 200(cid:13) RSENSE = 0.05W errors are incurred by expressing losses as a percentage of output power.) 0 0 1 2 3 4 5 Although all dissipative elements in the circuit produce VIN – VOUT VOLTAGE (V) 1143 F04 losses, four main sources usually account for most of the losses in LTC1143 series circuits: Figure 4. Minimum Value of C OUT 1) DC bias current Checking Transient Response 2) MOSFET gate charge current 3) I2R losses The regulator loop response can be checked by looking at 4) Voltage drop of the Schottky diode. the load transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load 1) The DC supply current is the current that flows into current. When a load step occurs, V shifts by an V (Pin 13 and Pin 5) less the gate charge current. For OUT IN amount equal to D I · ESR, where ESR is the effective V = 10V the DC supply current for each section is 160m A LOAD IN series resistance of C . D I also begins to charge or for no load and increases proportionally with load up to OUT LOAD discharge C until the regulator loop adapts to the a constant 1.6mA after the LTC1143 series has entered OUT current change and returns V to its steady-state value. continuous mode. Because the DC bias current is OUT 12

LTC1143/LTC1143L LTC1143L-ADJ APPLICATIOUNS INUFORWMATIOUN drawn from V , the resulting loss increases with 8% as the load current increases from 0.5A to 2A. If IN input voltage. For V = 10V the DC bias losses are Schotky diode losses routinely exceed 5% consider IN generally less than 1% for load currents over 30mA. using the synchronously switched LTC1142 series. However at very low load currents the DC bias current Figure 5 shows how the efficiency losses in one section of accounts for nearly all of the loss. a typical LTC1143 series regulator end up being appor- 2) MOSFET gate charge current results from switching tioned. The gate charge loss is responsible for the majority the gate capacitance of the power MOSFET. Each time of the efficiency lost in the midcurrent region. If Burst a MOSFET gate is switched from low to high to low again, Mode operation was not employed at low currents, the a packet of charge dQ moves from V to ground. The gate charge loss alone would cause efficiency to drop to IN resulting dQ/dt is a current out of V that is typically unacceptable levels. With Burst Mode operation, the DC IN much larger than the DC supply current. In continuous supply current represents the lone (and unavoidable) loss mode, I = ƒ(Q ). The typical gate charge for component, which continues to become a higher percent- GATECHG P a 0.05W P-channel power MOSFET is 40nC. This age as output current is reduced. As expected, the I2R results in I = 4mA in 100kHz continuous opera- losses and Schottky diode loss dominate at high load GATECHG tion, for a 2% to 3% typical midcurrent loss with currents. V = 10V. IN Other losses including C and C ESR dissipative IN OUT Note that the gate charge loss increases directly with losses, MOSFET switching losses and inductor core losses, both input voltage and operating frequency. This is the generally account for less than 2% total additional loss. principal reason why the highest efficiency circuits operate at moderate frequencies. Furthermore, it 100 argues against using a larger MOSFET than necessary I2R to control I2R losses, since overkill can cost efficiency GATE CHARGE as well as money! 95 1⁄2 LTC1143 IQ %) 3) I2R losses are easily predicted from the DC resistances Y ( C SCHOTTKY(cid:13) N 90 of the MOSFET, inductor and current shunt. In continuous E DIODE CI mode the average output current flows through L and FFI E RSENSE, but is “chopped” between the P-channel 85 MOSFET and Schottky diode. The MOSFET R multi- DS(ON) plied by the P-channel duty cycle can be summed with 80 the resistances of L and R to obtain I2R losses. 0.01 0.03 0.1 0.3 1 3 SENSE For example, if the R = 0.1W , R = 0.15W , and OUTPUT CURRENT (A) DS(ON) L R = 0.05W , then the total resistance is 0.3W . This LTC1143 • F05 SENSE results in losses ranging from 3% to 10% as the output Figure 5. Efficiency Loss current increases from 0.5A to 2A. I2R losses cause the efficiency to roll off at high output currents. Shutdown Considerations 4) The Schottky diode is a major source of power loss at high currents and gets worse at high input voltages. Pins 2 and 10 on the LTC1143 and LTC1143L shut down The diode loss is calculated by multiplying the forward their respective sections when pulled high. They require voltage drop times the Schottky diode duty cycle CMOS logic level signals with t , t < 1m s and must never r f multiplied by the load current. For example, assuming be floated. The LTC1143L-ADJ gives up the pin-controlled a duty cycle of 50% with a Schottky diode forward shutdown function in order to gain feedback pins for voltage drop of 0.4V, the loss increases from 0.5% to programming the output voltages. 13

LTC1143/LTC1143L LTC1143L-ADJ APPLICATIOUNS INUFORWMATIOUN The LTC1143L-ADJ outputs can be turned off in one of two d = 0.005(100 – 25) = 0.38. The maximum R for P DS(ON) ways: 1) by placing a power MOSFET switch in the V line each MOSFET can now be calculated: IN to the entire regulator or 2) by pulling the V pin over FB Ø ( ) ø 1.4V, which trips comparator V and forces P-DRIVE high Œ (cid:52) (cid:49) œ (cid:49) (see Functional Diagram). VFB can be pulled high with a (cid:80)(cid:45)(cid:67)(cid:104)(cid:32)(cid:82)(cid:68)(cid:83)(cid:40)(cid:79)(cid:78)(cid:41)= Œ ( ) ( )œ =(cid:48).(cid:49)(cid:49)W small current, but any circuitry used to shut down the (cid:50)Œ (cid:51).(cid:51) (cid:50) (cid:50) (cid:49).(cid:51)(cid:56) œ º ß LTC1143L-ADJ in this manner must minimize V lead FB length to prevent noise coupling during normal operation. Allowing for V being slightly below the V used to IN GS specify R , this requirement can be met by half of In the Figure 6 circuit, taking SHUTDOWN high turns on DS(ON) a Siliconix Si4953DY, Fairchild NDS8947 or similar PNP Q that sources a current into V . To shut down SD FB SO-8 dual P-channel MOSFET. properly, RSD must be chosen to pull V above 1.4V with FB VOUT at 0V and minimum VIN. Note that this technique The most stringent requirement for the Schottky diode is depends on the load resistance to prevent VOUT from with VOUT = 0V (i.e. short circuit). During a continuous short floating up due to the current flowing into VFB. circuit, the worst-case Schottky diode dissipation rises to: (cid:13) ( )(cid:230) (cid:86) (cid:246) VOUT VIN (cid:80)(cid:68)=(cid:73)(cid:83)(cid:67)((cid:65)(cid:86)(cid:71)) (cid:86)(cid:68) (cid:231) (cid:49)- (cid:79)(cid:85)(cid:84)(cid:247) Ł (cid:86) ł (cid:73)(cid:78) R2 RSD 200k With the 0.05W sense resistor, I = 2A will result, QSD SC(AVG) increasing the 0.4V Schottky diode dissipation to 0.8W. VFB 100k C will require an RMS current rating of at least 1A at 100pF R501k(cid:13) SHUTDOWN teImNperature and C will require an ESR of 0.05W for OUT 1143 F06 optimum efficiency. Figure 6. Local V Pull-Up Shuts Down LTC1143L-ADJ Troubleshooting Hints FB Since efficiency is critical to LTC1143 series applications it is very important to verify that the circuit is functioning Design Example correctly in both continuous and Burst Mode operation. As a design example, assume VIN = 12V(nominal), VOUT = The waveform to monitor is the voltage on the timing 3.3V, IMAX = 2A and ƒ = 200kHz. RSENSE, CT and L can capacitor Pins 6 and 14. immediately be calculated: In continuous mode (I > I ) the voltage on the C LOAD BURST T R = 100mV/2 = 0.05W pin should be a sawtooth with a 0.9V swing. This SENSE P-P t = (1/200kHz)[1 – (3.3/12)] = 3.63m s voltage should never dip below 2V as shown in Figure 7a. OFF CT = 3.63m s/(1.3 · 104) = 280pF (use 300pF) When load currents are low (ILOAD < IBURST) Burst Mode L = 5.1(105 )(0.05W) (300pF) 3.3V = 25m H operation occurs. The voltage on the C pin now falls to MIN T ground for periods of time as shown in Figure 7b. Assume a dual P-channel power MOSFET is to be used and dissipation is to be limited to 1W total at If Pin 6 or Pin 14 is observed falling to ground at high worst-case lowest V = 4V. If T = 50(cid:176) C and the output currents, it indicates poor decoupling or improper IN A thermal resistance of the MOSFET package is 50(cid:176) C/W, grounding. Refer to the Board Layout Checklist. then the junction temperature will be 100(cid:176) C and 14

LTC1143/LTC1143L LTC1143L-ADJ APPLICATIOUNS INUFORWMATIOUN 3.3V With the addition of R3 a current is generated though R1, causing an offset of: 0V (a) CONTINUOUS MODE OPERATION (cid:230) (cid:246) (cid:82)(cid:49) 3.3V (cid:86)(cid:79)(cid:70)(cid:70)(cid:83)(cid:69)(cid:84) =(cid:86)(cid:79)(cid:85)(cid:84)(cid:231) (cid:247) Ł (cid:82)(cid:49)+(cid:82)(cid:51)ł 0V If V > 25mV, the built-in offset will be cancelled and OFFSET (b) Burst Mode OPERATION LTC1143 • F07(cid:13) Burst Mode operation is prevented from occurring. Since (cid:13) V is constant, the maximum load current is also Figure 7. C Waveforms OFFSET T decreased by the same offset. Thus, to get back to the same I , the value of the sense resistor must be lower: MAX Auxiliary Windings––Suppressing Burst Mode Operation (cid:55)(cid:53)(cid:109)(cid:86) (cid:82) » The LTC1143 series operates nonsynchronously with the (cid:83)(cid:69)(cid:78)(cid:83)(cid:69) (cid:73) (cid:77)(cid:65)(cid:88) normal limitation that the power drawn from the inductor primary winding must not be less than twice the power To prevent noise spikes from erroneously tripping the drawn from the auxiliary windings. (With synchronous current comparator, a 1000pF capacitor is needed across switching, using the LTC1142 series, auxiliary outputs Pins 1 (16) and 9 (8). may be loaded without regard to the primary output load, providing that the loop remains in continuous mode Board Layout Checklist operation.) When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the Burst Mode operation can be suppressed at low output LTC1143 series. These items are also illustrated graphi- currents with a simple external network that cancels the cally in the layout diagram of Figure 9. In general, each 25mV minimum current comparator threshold. This tech- block should be self-contained with little cross coupling nique is also useful for eliminating audible noise from for best performance. Check the following in your layout: certain types of inductors in high current (I > 5A) OUT applications when they are lightly loaded. 1) Are the signal and power grounds segregated? The LTC1143 series GND Pin 3 (11) must return separately An external offset is put in series with the Sense– pin to to: a) the power and b) the signal grounds. The subtract from the built-in 25mV offset. An example of this power ground returns to the anode of the Schottky technique is shown in Figure 8. Two 100W resistors are diode and (–) plate of C , which should have as short IN inserted in series with the sense leads from the sense lead lengths as possible.The signal ground (b) con- resistor. nects to the (–) plate of C . OUT 2) Does the LTC1143 series SENSE– Pin 16 (8) connect R2(cid:13) SENSE+(cid:13) 100W to a point close to RSENSE and the (+) plate of COUT? [PIN 16 (8)] 3) Are the SENSE– and SENSE+ leads routed together 1000pF R1(cid:13) RSENSE [PSINEN 1S(9E)–](cid:13) 100W + VOUT wcaitpha cmitoinr ibmetuwme ePn CP intsra 1c (e9 )s apnadc i1n6g (?8 )T shheo u1ld0 0be0 paFs R3 COUT close as possible to the LTC1143 series. 1143 F08 4) Does the (+) plate of C connect to the source of the IN P-channel MOSFET as closely as possible? This Figure 8. Suppression of Burst Mode Operation capacitor provides the AC current to the P-channel MOSFET. 15

LTC1143/LTC1143L LTC1143L-ADJ APPLICATIOUNS INUFORWMATIOUN 5) Is the V decoupling capacitor (1m F, 0.1m F) con- high impedance and must not be allowed to float. Both IN nected closely between Pin 13 (5) and GND Pin 3 pins can be driven by the same external signal if (11)? This capacitor carries the MOSFET driver peak needed. currents. 7) For the LTC1143L-ADJ, are the V Pins 2 and 10 FB 6) For the LTC1143 and LTC1143L, are the SHUT- decoupled with 100pF as close to the device as DOWN Pins 2 and 10 actively pulled to ground possible? The V line is sensitive to noise pickup and FB during normal operation? Both SHUTDOWN pins are should be kept away from the P-channel MOSFET. P-CH L1 RSENSE5 + + + + VIN5 CIN5 D1 COUT5 VOUT5 – – SHUTDOWN (cid:13) VIN3 (5V OUTPUT) 1k CT3 0.0033µF –SENSE3(cid:13) (cid:13)ITH3(cid:13) CT3(cid:13)VIN3 (cid:13) P-DRIVES5(cid:13) GND5(cid:13) UTDOWN 5(cid:13) +5SENSE 3 1000pF* SH 114 1000pF* 0.22µF* +SENSE3(cid:13) SHUTDOWN 3(cid:13) GND3(cid:13) P-DRIVES3 (cid:13)VIN5 (cid:13) (cid:13)CT5 (cid:13)ITH5 –5SENSE LTC 0.22µF* SHUTDOWN(cid:13) VIN5 (3.3V OUTPUT) 1k CT5 0.0033µF RSENSE3 L2 P-CH + + + D2 + VOUT3 COUT3 CIN3 VIN3 – – 1143 F09 *MUST BE LOCATED CLOSE TO LTC1143 BOLD LINES INDICATE HIGH CURRENT PATHS Figure 9. LTC1143 Layout Diagram (see Board Layout Checklist) 16

LTC1143/LTC1143L LTC1143L-ADJ TYPICAL APPLICATIONUS VIN RANGE(cid:13) VOUT5 ON: 5.2V TO 8V(cid:13) VOUT5 SHUTDOWN: 3.5V TO 8V 2C22I5mNVF3(cid:13)(cid:13)(cid:13) + + 0.22m F 0V = NORMAL(cid:13) 0.22m F + + 2C2INm5F(cid:13)(cid:13) · 2 >1.5V = SHUTDOWN 2· 52V(cid:13) 13 2 10 5 P1A VIN3 SHUTDOWN 3 SHUTDOWN 5 VIN5 P1B VOUT3(cid:13) R0S.E1N0SWE3(cid:13) 50Lm1H(cid:13) 4 P-DRIVE 3 P-DRIVE 5 12 25Lm2H(cid:13) R0S.E0N5SWE5(cid:13) VOUT5(cid:13) 3.3V/1A(cid:13) 1 SENSE+ 3 SENSE+ 5 9 5V/2A LTC1143L (cid:13) 0.01m F 0.01m F (cid:13) SENSE– 3 SENSE– 5 + 21C20O0VUmT3F(cid:13)(cid:13) MBRS140DT13(cid:13) 16 GND3 CT3 ITH3 ITH5 CT5 GND5 8 D2(cid:13) + C2120O0VUm(cid:13)T5F(cid:13)(cid:13) 3 14 15 7 6 11 MBRS140T3 · 2 RC3(cid:13) RC5(cid:13) 1k(cid:13) 1k 1143 F10 (cid:13) CT3(cid:13) CC3(cid:13) CC5(cid:13) CT5(cid:13) CIN3, CIN5: AVX TPSD226K025R0200(cid:13) 270pF 3300pF(cid:13) 3300pF(cid:13) 220pF COUT3, COUT5: AVX TPSE227M010R0080(cid:13) (cid:13) (cid:13) (cid:13)L2: COILTRONICS CTX50-4(cid:13) (cid:13) L2: COILTRONICS CTX25-4(cid:13) P(cid:13) 1: FAIRCHILD NDS8934(cid:13) RSENSE3: IRC LR251(cid:13)2-01-OR100G (cid:13) RSENSE5: IRC LR2512-01-ORO5OG (cid:13) (cid:13) Figure 10. All Surface Mount Low Dropout Dual 5V/2A, 3.3V/1A Converter VIN(cid:13) 4V TO 14V + 2C2INm1F(cid:13)(cid:13) 0.22m F 0.22m F + 2C2INm2F(cid:13)(cid:13) 25V(cid:13) 2· 53V(cid:13) 13 5 · 2 P1 VIN1 VIN2 P2 VOUT1(cid:13) R0S.0E2N5SWE1(cid:13) 15Lm1H(cid:13) 4 P-DRIVE 1 P-DRIVE 2 12 27Lm2H(cid:13) R0S.E0N4SWE2(cid:13) VOUT2(cid:13) 1.8V/3A 1 SENSE+ 1 SENSE+ 2 9 2.5V/2A 100W 100W 1000pF LTC1143L-ADJ 1000pF 100W 100W 3C3O60U.3mTVF1(cid:13)(cid:13)(cid:13) + 221.R1%2k(cid:13)(cid:13) MBRS320DT13(cid:13) 5.6k 16 SENSE– 1 SENSE– 2 8 8.2k DM2B(cid:13)RS320T3 R419%4.(cid:13)9k(cid:13) + C22O0UmT2F(cid:13)(cid:13) · 2 2 VFB1 VFB2 10 10V(cid:13) 49.R91k(cid:13)(cid:13) 100pF GND1 CT1 ITH1 ITH2 CT2 GND2 100pF 100pF R493.(cid:13)9k(cid:13) · 2 3 14 15 7 6 11 1% 1% RC1(cid:13) RC2(cid:13) 510Ω 1k (cid:13) 220CpTF1(cid:13) 3C3C01(cid:13)0pF(cid:13) 330C0pCF2(cid:13) C30T20(cid:13)pF (cid:13) CIN1, CIN2: AVX TPSD226K025R0200(cid:13) COUT1: AVX TPSE337M006R0100(cid:13) L1: SUMIDA CDRH125-150(cid:13) P1: IR IRF7406(cid:13) RSENSE1: DALE WSL-2010-.025(cid:13) 1143 F11 COUT2: AVX TPSE227M010R0100(cid:13) L2: SUMIDA CDRH125-270(cid:13) P2: IR IRF7204(cid:13) RSENSE2: DALE WSL-2010-.04 (cid:13) (cid:13) (cid:13) Figure 11. Dual 1.8V/3A and 2.5V/2A with Burst Mode Defeated 17

LTC1143/LTC1143L LTC1143L-ADJ TYPICAL APPLICATIONUS VIN(cid:13) 3.5V TO 10V + CIN1(cid:13) P2 + C22INm2F(cid:13)(cid:13) 22m F(cid:13) 0.22m F 0.22m F 220m F(cid:13) 25V(cid:13) 25V(cid:13) 10V · 2 · 2 P1 VIN113 5VIN2 + L2B V5VO/U1TA2(cid:13) VOUT1(cid:13) R0S.E0N5SWE1(cid:13) 27Lm1H(cid:13) 4 P-DRIVE 1 P-DRIVE 2 12 L2A DM2B(cid:13)RS130L 3.3V/2A 1 SENSE+ 1 SENSE+ 2 9 1000pF LTC1143L-ADJ 1000pF RSENSE2(cid:13) 2C2O0UmTF1(cid:13)(cid:13) + 82.R52k(cid:13)(cid:13) D1(cid:13) 16 SENSE– 1 SENSE– 2 8 0.082W R1540(cid:13)k(cid:13) 2C2O0UmT2F(cid:13)(cid:13) 10V(cid:13) 1% MBRS130L 1% 10V · 2 2 VFB1 VFB2 10 R3(cid:13) 49.R91k(cid:13)(cid:13) 100pF GND31 CT114 ITH115 ITH72 CT26 GND121 100pF 419%.9k(cid:13) 1% 300CpTF1(cid:13) R1kC1(cid:13) 1RkC2(cid:13) C18T20(cid:13)pF CC1(cid:13) CC2(cid:13) 3300pF(cid:13) 3300pF OVERVOLTAGE(cid:13) (cid:13) PROTECTION Z1(cid:13) (cid:13) 5.1V CIN1, CIN2: AVX TPSD226K025R0200(cid:13) P1, P2: SILICONIX Si9803DY(cid:13) MMBT2222ALT1 COUT1, COUT2: AVX TPSE227M010R0100(cid:13) RSENSE1: IRC 1206-R050F(cid:13) L1: SUMIDA(cid:13) CDRH125-270(cid:13) RSENSE2: IRC 1206-R082F(cid:13) 1k L2: PULSE ENGINEERING PE-53718(cid:13) Z1: MMBZ5231B (cid:13) 1143 F12 Figure 12. Dual 3.3V/5V Buck-Boost Regulator 18

LTC1143/LTC1143L LTC1143L-ADJ PACKAGE DESCRIPTIOUN Dimensions in inches (millimeters) unless otherwise noted. S Package 16-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.386 – 0.394*(cid:13) (9.804 – 10.008) 16 15 14 13 12 11 10 9 0.228 – 0.244(cid:13) 0.150 – 0.157**(cid:13) (5.791 – 6.197) (3.810 – 3.988) 1 2 3 4 5 6 7 8 0.010 – 0.020(cid:13) · 45(cid:176) 0.053 – 0.069(cid:13) (0.254 – 0.508) (1.346 – 1.752) 0.004 – 0.010(cid:13) 0.008 – 0.010(cid:13) (0.203 – 0.254) 0° – 8° TYP (0.101 – 0.254) 0.014 – 0.019(cid:13) 0.050(cid:13) 0.016 – 0.050(cid:13) (0.355 – 0.483) (1.270)(cid:13) 0.406 – 1.270 TYP S16 0695 *(cid:13)DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH (cid:13) (cid:13)SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE(cid:13) **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD (cid:13) FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE(cid:13) (cid:13) (cid:13) 19 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1143/LTC1143L LTC1143L-ADJ TYPICAL APPLICATIONU VIN(cid:13) 5.2V TO 14V CIN3(cid:13) + + + + CIN5(cid:13) 22m F(cid:13) 0.22m F 0V = NORMAL(cid:13) 0.22m F 22m F(cid:13) 25V(cid:13) >1.5V = SHUTDOWN 25V(cid:13) · 3 · 2 13 2 10 5 P1 VIN3 SHUTDOWN 3 SHUTDOWN 5 VIN5 P2 VOUT3(cid:13) R0S.0E3N3SWE3(cid:13) 10Lm1H(cid:13) 4 P-DRIVE 3 P-DRIVE 5 12 25Lm2H(cid:13) R0S.E0N5SWE5(cid:13) VOUT5(cid:13) 3.3V/3A 1 SENSE+ 3 SENSE+ 5 9 5V/2A LTC1143 (cid:13) 0.01m F 0.01m F (cid:13) SENSE– 3 SENSE– 5 16 8 + COUT5(cid:13) + 220m F(cid:13) C22O0UmT3F(cid:13)(cid:13) MBRD3D410(cid:13) GND3 CT3 ITH3 ITH5 CT5 GND5 DM2B(cid:13)RD340 1· 02V(cid:13) 10V(cid:13) 3 14 15 7 6 11 · 3 RC3(cid:13) RC5(cid:13) 510Ω 1k CT3(cid:13) CC3(cid:13) CC5(cid:13) CT5(cid:13) LTC1143.F13 200pF 3300pF(cid:13) 3300pF(cid:13) 220pF (cid:13) (cid:13) CIN3, CIN5: AVX TPSD226K025R0200(cid:13) P1: SILICONIX Si4431DY(cid:13) COUT3, COUT5: AVX TPSE227M010R0080(cid:13) P2: SILICONIX Si9435DY(cid:13) L1: COILTRONICS CTX10-4(cid:13) RSENSE3: KRL SL-1/2-C1-0R033J(cid:13) L2: COILTRONICS CTX25-4 RSENSE5: KRL SL-1/2-C1-0R050J Figure 13. All Surface Mount Dual 5V/2A, 3.3V/3A Converter RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1142 Dual High Efficiency Synchronous Step-Down Switching Regulator Synchronous Equivalent to LTC1143, 4V < V < 16V IN LTC1142L-ADJ Dual High Efficiency Synchronous Step-Down Switching Regulator Synchronous Equivalent to LTC1143L-ADJ, 3.5V < V < 16V IN LTC1142HV-ADJ Dual High Efficiency Synchronous Step-Down Switching Regulator 4V < V < 20V IN LTC1147L High Efficiency Step-Down Switching Regulator Controller (1/2) LTC1143L-ADJ in SO-8 LTC1265 1.2A, High Efficiency Step-Down DC/DC Converter Single Channel with Internal Switch LTC1438 Dual Synchronous Controller with Power-On Reset and Constant Frequency Current Mode, Drives Synchronous an Extra Comparator N-Channel MOSFETS LTC1538-AUX Dual Synchronous Controller with Auxiliary Linear Regulator Up to Four Output Voltages from G28 Package Controller and 5V Standby LTC1539 Dual Synchronous Controller with Phase-Locked Loop Full Featured Dual Controller in G36 Package and Adaptive PowerTM Operation Adaptive Power is a trademark of Linear Technology Corporation. 20 Linear Technology Corporation 1143fa LT/TP 0598 REV A 2K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l w ww.linear-tech.com ª LINEAR TECHNOLOGY CORPORATION 1994