LTC1052/LTC7652 Zero-Drift Operational Amplifier FEATURES DESCRIPTIOU ■ Guaranteed Max Offset: 5µV The LTC®1052 and LTC7652 are low noise zero-drift op ■ Guaranteed Max Offset Drift: 0.05µV/°C amps manufactured using Linear Technology’s enhanced ■ Typ Offset Drift: 0.01µV/°C LTCMOSTM silicon gate process. Chopper-stabilization ■ Excellent Long Term Stability: 100nV/√Month constantly corrects offset voltage errors. Both initial offset ■ Guaranteed Max Input Bias Current: 30pA and changes in the offset due to time, temperature and ■ Over Operating Temperature Range: common mode voltage are corrected. This, coupled with Guaranteed Min Gain: 120dB picoampere input currents, gives these amplifiers Guaranteed Min CMRR: 120dB unmatched performance. Guaranteed Min PSRR: 120dB Low frequency (1/f) noise is also improved by the ■ Single Supply Operation: 4.75V to 16V chopping technique. Instead of increasing continuously (Input Voltage Range Extends to Ground) at a 3dB/octave rate, the internal chopping causes noise to ■ External Capacitors can be Returned to V– with No decrease at low frequencies. Noise Degradation The chopper circuitry is entirely internal and completely transparent to the user. Only two external capacitors APPLICATIOU S are required to alternately sample-and-hold the offset correction voltage and the amplified input signal. Control ■ Thermocouple Amplifiers circuitry is brought out on the 14-pin and 16-pin versions ■ Strain Gauge Amplifiers to allow the sampling of the LTC1052 to be synchronized ■ Low Level Signal Processing with an external frequency source. ■ Medical Instrumentation , LTC and LT are registered trademarks of Linear Technology Corporation. LTCMOS is a trademark of Linear Technology Corporation. Teflon is a trademark of DuPont. TYPICAL APPLICATIOU Ultralow Noise, Low Drift Amplifier Noise Spectrum 5V 160 3 + 7 LTC1052 6 Hz) 140 √ 2 –1 4 8 0.1µF TY (nV/ 112000 0.1µF –5V 0.1µF DENSI 80 E S 5V OI 60 100k 3K 1 5V 68k 1.5k E N INPUT 3 + 7 8 5V LTAG 40 O LT®1007 OUTPUT V 20 6 2 – 4 100k 0 –5V 0 100 200 300 400 500 FREQUENCY (Hz) VOS = 3µV 100Ω VOS∆T = 50nV/°C LTC1052/7652 • TA02 NOISE = 0.06µVP-P 0.1Hz TO 10Hz LTC1052/7652 • TA01 1052fa 1

LTC1052/LTC7652 ABSOLUTE W AXIW UW RATIU GS (Notes 1 and 2) Total Supply Voltage (V+ to V–)............................... 18V Operating Temperature Range Input Voltage........................ (V+ + 0.3V) to (V– – 0.3V) LTC1052C/LTC7652C..........................–40°C to 85°C Output Short Circuit Duration..........................Indefinite LTC1052M (OBSOLETE).....................–55°C to 125°C Storage Temperature Range..................–55°C to 150°C Lead Temperature (Soldering, 10 sec)..................300°C PACKAGE/ORDER IU FORW ATIOU TOP VIEW TOP VIEW CEXTB CEXTB 1 14 INT/EXT 8 CEXTA 1 7 V+/CASE CEXTA 2 13 CLK IN NC (GUARD) 3 12 CLK OUT – –IN 2 6 OUTPUT –IN 4 – 11 V+ + +IN 5 + 10 OUTPUT +IN 3 5 LTC1052 OUTPUT CLAMP NC (GUARD) 6 9 OUTPUT CLAMP 4 LTC7652 CRETURN V– 7 8 CRETURN V– METAL CAN H PACKAGE N PACKAGE, 14-LEAD CERDIP TJMAX = 110°C, θJA = 130°C/W J PACKAGE, 14-LEAD CERDIP OBSOLETE PACKAGE OBSOLETE PACKAGE Consider the N8 Package for Alternate Source Consider the N14 Package for Alternate Source ORDER PART NUMBER REPLACES ORDER PART NUMBER REPLACES LTC7652CH ICL7652CTV LTC1052CN ICL7652CPD ICL7652ITV ICL7650CPD ICL7650CTV-1 LTC1052CJ ICL7652IJD ICL7650ITV-1 ICL7650IJD LTC1052CH ICL7650CTV LTC1052MJ ICL7650MJD ICL7650ITV LTC1052MH ICL7650MTV TOP VIEW TOP VIEW CEXTA 1 8 CEXTB CEXTB 1 16 INT/EXT –IN 2 – 7 V+ CEXTA 2 15 CLK IN NC (GUARD) 3 14 CLK OUT +N 3 + 6 OUTPUT V– 4 5 OUTPUT –IN 4 13 V+ CLAMP +IN 5 12 OUTPUT N8 PACKAGE NC (GUARD) 6 11 OUTPUT CLAMP 8-LEAD PDIP TJMAX = 110°C, θJA = 150°C/W V– 7 10 CRETURN NC 8 9 NC J8 PACKAGE, 8-LEAD CERDIP SW PACKAGE OBSOLETE PACKAGE 16-LEAD PLASTIC (WIDE) SO Consider the N8 Package for Alternate Source TJMAX = 110°C, θJA = 150°C/W ORDER PART NUMBER REPLACES ORDER PART NUMBER REPLACES LTC1052CN8 ICL7650CPA LTC1052CSW LTC1052CS LTC1052CJ8 ICL7650IJA LTC1052MJ8 Consult LTC Marketing for parts specified with wider operating temperature ranges. 1052fa 2

LTC1052/LTC7652 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, test circuit TC1, unless otherwise noted. LTC1052M LTC1052C/LTC7652C SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS VOS Input Offset Voltage (Note 3) ±0.5 ±5 ±0.5 ±5 µV ∆VOS/∆Temp Average Input Offset Drift (Note 3) ● ±0.01 ±0.05 ±0.01 ±0.05 µV/°C ∆VOS/∆Time Long-Term Offset Voltage Stability 100 100 nV/√Month IOS Input Offset Current ±30 ±90 ±30 ±90 pA ● ±2000 ±350 pA IB Input Bias Current ±1 ±30 ±1 ±30 pA ● ±1000 ±175 pA enP-P Input Noise Voltage RS = 100Ω, DC to 10HZ, TC3 1.5 1.5 µVP-P RS = 100Ω, DC to 1HZ, TC3 0.5 0.5 µVP-P In Input Noise Current f = 10Hz (Note 5) 0.6 0.6 fA/√Hz CMRR Common Mode Rejection Ratio V = V– to 2.7V ● 120 140 120 140 dB CM PSRR Power Supply Rejection Ratio VSUPPLY = ±2.375V to ±8V ● 120 150 120 150 dB AVOL Large-Signal Voltage Gain RL = 10k, VOUT = ±4V ● 120 150 120 150 dB VOUT Maximum Output Voltage Swing RL = 10k ● ±4.7 ±4.85 ±4.7 ±4.85 V (Note 4) RL = 100k ±4.95 ±4.95 V SR Slew Rate RL = 10k, CL = 50pF 4 4 V/µs GBW Gain Bandwidth Product 1.2 1.2 MHz I Supply Current No Load 1.7 2.0 1.7 2.0 mA S ● 3.0 3.0 mA f Internal Sampling Frequency 330 330 Hz S Clamp On Current RL = 100k ● 25 100 25 100 µA Clamp Off Current –4V < V < 4V 10 100 10 100 pA OUT ● 2 1 nA Note 1: Absolute Maximum Ratings are those values beyond which the life testing. V is measured to a limit determined by test equipment OS of a device may be impaired. capability. Voltages on C and C , A , CMRR and PSRR are EXTA EXTB VOL Note 2: Connecting any terminal to voltages greater than V+, or less than measured to insure proper operation of the nulling loop to ensure meeting V–, may cause destructive latch-up. It is recommended that no sources the VOS and VOS drift specifications. See Package-Induced VOS in the operating from external supplies be applied prior to power-up of the Applications Information section. LTC1052/LTC7652. Note 4: Output clamp not connected. Note 3: These parameters are guaranteed by design. Thermocouple effects Note 5: Current noise is calculated from the formula: i = (2q I )1/2, where n B preclude measurement of the voltage levels in high speed automatic q = 1.6 • 10–19 coulomb. TYPICAL PERFORW AU CE CHARACTERISTICS Input Noise Voltage VS = ±5V, TEST CIRCUIT (TC3) 5µV DC TO 1Hz 0 5µV DC TO 10Hz 0 10 SEC. 1052fa 3

LTC1052/LTC7652 TYPICAL PERFORW AU CE CHARACTERISTICS Offset Voltage vs Sampling 1OHz Noise vs Sampling Input Bias Current vs P-P Frequency Frequency Temperature 12 5 1000 VSUPPLY= ±5V VSUPPLY= ± 5V 900 GUARANTEED 10 V)µ 4 A)800 V (V)µOS 468 AK-TO-PEAK NOISE ( 23 BIAS CURRENT, I (pB457600000000 2 10Hz PE 1 INPUT 320000 GUARANTEED 100 0 0 0 0 500 1000 1500 2000 100 1k 10k –50 –25 0 25 50 75 100 125 SAMPLING FREQUENCY, fS (Hz) SAMPLING FREQUENCY, fS (Hz) AMBIENT TEMPERATURE, TA(°C) LTC1052/7652 • TPC03 LTC1052/7652 • TPC01 LTC1052/7652 • TPC02 Common Mode Input Range vs Overload Recovery Aliasing Error Supply Voltage (Output Clamp Not Used) 8 OUTPUT SPECTRUM (dB)(3Hz BANDWIDTH) VATESV S==T –± C15IVRCUIT TC2 MON MODE RANGE (V) –04226 IV/DIV VS = ±5V M VCM = V– O –4 C fI–fS fS fI –6 OVERDRIVE 50ms/DIV 50Hz/DIV REMOVED –8 AV = –100 0 1 2 3 4 5 6 7 8 SUPPLY VOLTAGE (±V) LTC1052/7652 • TPC04 Small-Signal Transient Response* Large-Signal Transient Response* Gain Phase vs Frequency 120 60 VS=±5V OUTPUT VOLTAGE (20mV/DIV) OUTPUT VOLTAGE (2mV/DIV) VOLTAGE GAIN (dB)12608400000 GAIN PHASCEL=100pF 11811620040000PHASE SHIFT (DEGREE 0 180S ) AV = 1 2µs/DIV AV = 1 2µs/DIV –20 200 RL = 10k RL = 10k CL = 100pF CL = 100pF –40 220 VS = ±5V VS = ±5V 100 103 104 105 106 107 *RESPONSE IS NOT DEPENDENT ON PHASE OF CLOCK FREQUENCY (Hz) LTC1052/LTC7652 • TPC06 1052fa 4

LTC1052/LTC7652 TYPICAL PERFORW AU CE CHARACTERISTICS Broadband Noise, CEXT = 0.1µF Broadband Noise, CEXT = 1.0µF Broadband Noise Test Circuit (TC2) R2 1M NPUT REFERRED NOISE(5V/DIV)µ NPUT REFERRED NOISE(5V/DIV)µ R1R1k1k3 32 +–LT1C150V5742 8 6 I I CEXTA CEXTB AV = –1000 1ms/DIV AV = –1000 1ms/DIV –5V LTC1052/7652 • TPC07 Output Short-Circuit Current vs Supply Current vs Supply Voltage Supply Current vs Temperature Supply Voltage 2.5 3.0 8 SUPPLY VOLTAGE = ±5V mA) UT ( 6 O mA) 2.0 mA) NT, I 4 ISOURCE VOUT = V– SUPPLY CURRENT, I(S011...505 SUPPLY CURRENT, I(S 12..00 CIRCUIT OUTPUT CURRE –1200 RT- –20 ISINK VOUT = V+ O H 0 0 S –30 4 5 6 8 10 12 14 16 –50 –25 0 25 50 75 100 125 4 5 6 8 10 12 14 16 TOTAL SUPPLY VOLTAGE, V+ TO V– (V) AMBIENT TEMPERATURE, TA (°C) TOTAL SUPPLY VOLTAGE, V+ TO V– (V) LTC1052/LTC7652 • TPC08 LTC1052/LTC7652 • TPC09 LTC1052/LTC7652 • TPC10 Sampling Frequency vs Sampling Frequency vs Voltage Temperature Comparator Operation 600 600 TA = 25°C SUPPLY VOLTAGE = ±5V MPLING FREQUENCY, f (Hz)S523400000000 MPLING FREQUENCY, f (Hz)S523400000000 VRVEFIN* 11kk 0.1µ32F –+LT1C5105425V78 60.1µF SA100 SA 100 * –5V ≤ VREF ≤ 2.7V –5V 0 0 LTC1052/7652 • TPC13 4 5 6 8 10 12 14 16 –50 –25 0 25 50 75 100 125 TOTAL SUPPLY VOLTAGE, V+ TO V– (V) AMBIENT TEMPERATURE, TA (°C) LTC1052/LTC7652 • TPC11 LT1052/LTC7652 • TPC12 1052fa 5

LTC1052/LTC7652 TYPICAL PERFORW AU CE CHARACTERISTICS Response Time vs Overdrive {VREF + OVERDRIVE INPUT VREF – 1mV 10µV { 5V 50µV OUTPUT 5µV –5V 20ms/DIV TEST CIRCUITS Electrical Characteristics Test Circuit (TC1) DC to 10Hz and DC to 1HZ Noise Test Circuit (TC3) C2 C3 R2 1M R1 V+ R2 R4 3 + 1k 2 – 7 V+ 6 OUTPUT C4 LT1001 LTC1052 6 OUTPUT 2 – 7 R3 2 – (NOISE x 20,000) 3 +1 4 8 RL R1 3 +LTC1052 8 6 34k 4 0.1µF 0.1µF 1 34k 0.1µF 0.1µF V– LTC1052/7652 • TC01 V– BANDWIDTH R1 R2 R3 R4 C2 C3 C4 10Hz 16.2Ω 162k 16.2k 16.2k 0.1µF 1.0µF 1.0µF 1Hz 16.2Ω 162k 162k 162k 1.0µF 1.0µF 1.0µF LTC1052/7652 • TC02 THEORY OF OPERATIOU DC OPERATION The shaded portion of the LTC1052 block diagram stage. C and S2 act as a sample-and-hold to store the EXTB (Figure 1a) entirely determines the amplifier’s DC amplified input signal during the auto zero cycle. characteristics. During the auto zero portion of the cycle, By switching between these two states at a frequency the g inputs are shorted together and a feedback path is much higher than the signal frequency, a continuous m1 closed around the input stage to null its offset. Switch S2 output results. and capacitor C act as a sample-and-hold to store the EXTA Notice that during the auto zero cycle the g inputs are m1 nulling voltage during the next step—the sampling cycle. not only shorted together, but are also shorted to the In the sampling cycle, the zeroed amplifier is used to inverting input. This forces nulling with the common mode amplify the differential input voltage. Switch S2 connects voltage present and accounts for the extremely high the amplified input voltage to C and the output gain CMRR of the LTC1052. In the same fashion, variations in EXTB 1052fa 6

LTC1052/LTC7652 THEORY OF OPERATIOU power supply are also nulled. For nulling to take place, the For frequencies above this pole, I is: 2 offset voltage, common mode voltage and power supply 1 I = V g • • SC1 2 IN m6 must not change at a frequency which is high compared to SC2 the frequency response of the nulling loop. and C1 I – I = V g – V g • 1 2 IN m1 IN m6 AC OPERATION AND ALIASING ERRORS C2 The LTC1052 is very carefully designed so that g = g m1 m6 So far, the DC performance of the LTC1052 has been and C1 = C2. Substituting these values in the above equa- explained. As the input signal frequency increases, the tion shows I – I = 0. 1 2 problem of aliasing must be addressed. Aliasing is the spurious formation of low and high frequency signals The gm6 input stage, with Cl and C2, not only filters the caused by the mixing of the input signal with the sampling input to the sampling loop, but also acts as a high frequency, f . The frequency of the error signals, f , is: frequency path to give the LTC1052 good high frequency S E response. The unity-gain cross frequencies for both the f = f ±f E S I DC path and high frequency path are identical where f = input signal frequency. 1 1 I [f3dB = (g /C1) = (g /C2)] m1 m6 2π 2π Normally it is the difference frequency (f – f ) which is of S I thereby making the frequency response smooth and con- concern because the high frequency (f + f) can be easily S I tinuous while eliminating sampling noise in the output as filtered. As the input frequency approaches the sampling the loop transitions from the high gain DC loop to the high frequency, the difference frequency approaches zero and frequency loop. will cause DC errors—the exact problem that the zero-drift amplifier is meant to eliminate. The typical curves show just how well the amplifier works. The output spectrum shows that the difference frequency The solution is simple; filter the input so the sampling loop (f –f = 100Hz) is down by 80dB and the frequency I S never sees any frequency near the sampling frequency. response curve shows no abnormalities or perturbations. At a frequency well below the sampling frequency, the Also note the well-behaved small and large-signal step LTC1052 forces I to equal I (see Figure 1b). This makes responses and the absence of the sampling frequency in 1 2 δ l zero, thus the gain of the sampling loop zero at this and the output spectrum. If the dynamics of the amplifier higher frequencies (i.e., a low pass filter). The corner (i.e., slew rate and overshoot), depend on the sampling frequency of this low pass filter is set by the output stage clock, the sampling frequency will appear in the output pole (1/R g R C2). spectrum. L4 m5 L5 C1 S3 VREF C2 +IN S1 + S2 – – gm1 +– gm2 gm4 ++ gm5 VOUT –IN – RL1 RL2 CEXT B RL4 RL5 VNULL CEXT A gm3 – V– gm6 + LTC1052/7652 • TPC13 Figure 1a. LTC1052 Block Diagram Auto Zero Cycle 1052fa 7

LTC1052/LTC7652 THEORY OF OPERATIOU C1 S3 VREF C2 l2 +IN S1 + δl S2 gm1 +–– gm2 gm4 +–+ gm5 VOUT –IN – l1 RL1 RL2 CEXT B RL4 RL5 CEXT A gm3 – V– l3 gm6 LTC1052/7652 • TO02 + Figure 1b. LTC1052 Block Diagram Sampling Cycle APPLICATIOU S IU FORW ATIOU EXTERNAL CAPACITORS C and C are the holding elements of a sample- On competitive devices, connecting C and C to EXTA EXTB EXTA EXTB and-hold circuit. The important capacitor characteristics V– causes an increase in amplifier noise. Design changes are leakage current and dielectric absorption. A high have eliminated this problem on the LTC1052. On the quality film-type capacitor such as mylar or polypropylene 14-pin LTC1052 and 8-pin LTC7652, the capacitors can provides excellent performance. However, low grade be returned to V– or C with no change in noise RETURN capacitors such as ceramic are suitable in many performance. applications. Capacitors with very high dielectric absorption (ceramic) ACHIEVING PICOAMPERE/MICROVOLT PERFORMANCE can take several seconds to settle after power is first Picoamperes turned on. This settling appears as clock ripple on the output and, as the capacitor settles, the ripple gradually In order to realize the picoampere level of accuracy of the disappears. If fast settling after power turn-on is LTC1052, proper care must be exercised. Leakage important, mylar or polypropylene is recommended. currents in circuitry external to the amplifier can significantly degrade performance. High quality insulation Above 85°C, leakage, both from the holding capacitors should be used (e.g., Teflon, Kel-F); cleaning of all and the printed circuit board, becomes important. To insulating surfaces to remove fluxes and other residues maintain the capabilities of the LTC1052 it may be will probably be necessary—particularly for high necessary to use Teflon™ capacitors and Teflon standoffs temperature performance. Surface coating may be when operating at 125°C (see Achieving Picoampere/ necessary to provide a moisture barrier in high humidity Microvolt Performance). environments. C and C are normally in the range of 0.1µF EXTA EXTB Board leakage can be minimized by encircling the input to 1.0µF. All specifications are guaranteed with 0.1µF and connections with a guard ring operated at a potential the broadband noise (refer to Typical Performance Char- close to that of the inputs: in inverting configurations, the acteristics) is only very slightly degraded with 0.1µF. guard ring should be tied to ground; in noninverting Output clock ripple is not present for capacitors of 0.1µF or greater at any temperature. Teflon is a trademark of Dupont. 1052fa 8

LTC1052/LTC7652 APPLICATIOU S IU FORW ATIOU connections, to the inverting input. Guarding both sides Figure 2 is an example of the introduction of an of the printed circuit board is required. Bulk leakage unnecessary resistor to promote differential thermal reduction depends on the guard ring width. balance. Maintaining compensating junctions in close physical proximity will keep them at the same temperature and reduce thermal EMF errors. NOMINALLY UNNECESSARY RESISTOR USED TO THERMALLY BALANCE OTHER LEAD WIRE/SOLDER/COPPER INPUT RESISTOR TRACE JUNCTION + LTC1052 OUTPUT – RESISTOR LEAD, SOLDER, COPPER TRACE JUNCTION Microvolts Thermocouple effects must be considered if the LTC1052’s LTC1052/7652 • AI03 ultralow drift is to be fully utilized. Any connection Figure 2 of dissimilar metals forms a thermoelectric junction producing an electric potential which varies with When connectors, switches, relays and/or sockets are temperature (Seebeck effect). As temperature sensors, necessary they should be selected for low thermal EMF thermocouples exploit this phenomenon to produce activity. The same techniques of thermally balancing and useful information. In low drift amplifier circuits the effect coupling the matching junctions are effective in reducing is a primary source of error. the thermal EMF errors of these components. Connectors, switches, relay contacts, sockets, resistors, Resistors are another source of thermal EMF errors. solder, and even copper wire are all candidates for Table1 shows the thermal EMF generated for different thermal EMF generation. Junctions of copper wire from resistors. The temperature gradient across the resistor is different manufacturers can generate thermal EMFs of important, not the ambient temperature. There are two 200nV/°C—4 times the maximum drift specification of junctions formed at each end of the resistor and if these the LTC1052. The copper/kovar junction, formed when junctions are at the same temperature, their thermal EMFs wire or printed circuit traces contact a package lead, has will cancel each other. The thermal EMF numbers are a thermal EMF of approximately 35µV/°C–700 times the approximate and vary with resistor value. High values give maximum drift specification of the LTC1052. higher thermal EMF. Minimizing thermal EMF-induced errors is possible if Table 1. Resistor Thermal EMF judicious attention is given to circuit board layout and component selection. It is good practice to minimize the RESISTOR TYPE THERMAL EMF/°C GRADIENT number of junctions in the amplifier’s input signal path. Tin Oxide ~mV/’C Avoid connectors, sockets, switches and relays where Carbon Composition ~450µV/°C possible. In instances where this is not possible, attempt Metal Film ~20µV/°C to balance the number and type of junctions so that Wire Wound differential cancellation occurs. Doing this may involve Evenohm ~2µV/°C deliberately introducing junctions to offset unavoidable Manganin ~2µV/°C junctions. 1052fa 9

LTC1052/LTC7652 APPLICATIOU S IU FORW ATIOU When all of these errors are considered, it may seem Figure 4 shows the response of this circuit under impossible to take advantage of the extremely low drift temperature transient conditions. Metal film resistors and specifications of the LTC1052. To show that this is not the an 8-pin DIP socket were used. Care was taken in the case, examine the temperature test circuit of Figure 3. The construction to thermally balance the inputs to the lead lengths of the resistors connected to the amplifier’s amplifier. The units were placed in an oven and allowed to inputs are identical. The thermal capacity and thermal stabilize at 25°C. The recording was started and after resistance each input sees is balanced because of the 100 seconds the oven, preset to 125°C, was switched on. symmetrical connection of resistors and their identical The test was first performed on an 8-pin plastic package size. Thermal EMF-induced shifts are equal in phase and and then was repeated for a TO-5 package plugged into the amplitude, thus cancellation occurs. same test board. It is significant that the change in V , OS even under these severe thermal transient conditions, 50k is quite good. As temperature stabilizes, note that the 5V steady-state change of V is well within the maximum 2 – 7 OS 6 ±0.05µV/°C drift specification. 100Ω LTC1052 3 + 8 Very slight air currents can still affect even this 1 4 VOS • 1000 arrangement. Figure 5 shows strip charts of output noise 0.1µF 50k 0.1µF 0.1µF both with the circuit covered and with no cover in “still” air. –5V This data illustrates why it is often prudent to enclose the LTC1052/7652 • AI04 LTC1052 and its attendant components inside some form Figure 3. Offset Drift Test Circuit of thermal baffle. 0 MIN 5 MIN 20 MIN 25 MIN 10 25°C TO 125°C PLASTIC V) 0 ±0.05µV/°C DI V/ µ 0 1 (OS V E, G A T L O V T E S OFF 10 25°C TO 125°C METAL CAN 0 ±0.05µV/°C OVEN SWITCHED OVEN STABILIZED ON (25°C) AT 12 MIN 100 SECONDS/IN Figure 4. Transient Response of Offset Drift Test Circuit with 100°C Temperature Step 1052fa 10

LTC1052/LTC7652 APPLICATIOU S IU FORW ATIOU #1 COVERED 1µV #1 UNCOVERED #2 UNCOVERED 20 SEC Figure 5. DC to 1Hz (Test Circuit TC3) PACKAGE-INDUCED OFFSET VOLTAGE CLOCK Since the LTC1052 is constantly fixing its own offset, it The LTC1052 has an internal clock, setting the nominal may be asked why there is any error at all, even under sampling frequency at 330Hz. On 8-pin devices, there is transient temperature conditions. The answer is simple. no way to control the clock externally. In some applica- The LTC1052 can only fix offsets inside its own nulling tions it may be desirable to control the sampling clock and loop. There are many thermal junctions outside this loop this is the function of the 14-pin device. that cannot be distinguished from legitimate signals. CLK IN, CLK OUT and INT/EXT are provided to accomplish Some have been discussed previously, but the package this. With no external connection, an internal pull-up holds thermal EMF effects are an important source of errors. INT/EXT at the V+ supply and the 14-pin device self- oscillates at 330Hz. In this mode there is a signal on the Notice the difference in the thermal response curves of CLK IN pin of 660Hz (2 times sampling frequency) with a Figure 4. This can only be attributed to the package since 30% duty cycle. A divide-by-two drives the CLK OUT pin everything else is identical. In fact, the V specification is OS and sets the sampling frequency. set by the package-induced warm-up drift, not by the LTC1052. TO-99 metal cans exhibit the worst warm-up To use an external clock, connect INT/EXT to V– and the drift and Linear Technology sample tests TO-99 lots to external clock to CLK IN. The logic threshold of CLK IN is minimize this problem. 2.5V below the positive supply; this allows CMOS logic to drive it directly with logic supplies of V+ and ground. CLK Two things make 100% screening costly: (1) The extreme IN can be driven from V+ to V– if desired. The duty cycle of precision required on the LTC1052 and (2) the thermal the external clock is not particularly critical but should be time constant of the package is 0.5 to 3 minutes, depend- kept between 30% and 60%. ing on package type. The first precludes the use of auto- matic handling equipment and the second takes a long Capacitance between CLK IN and CLK OUT (pins 13 and time. Bench test equipment is available to 100% test for 12) can cause the divide-by-two circuit to malfunction. To warmed-up drift if offsets of less than ±5µV are required. avoid this, keep this capacitance below 5pF. 1052fa 11

LTC1052/LTC7652 APPLICATIOU S IU FORW ATIOU OUTPUT CLAMP within approximately 1V of either supply rail. This switch is in parallel with the amplifier’s feedback resistor. As the If the LTC1052 is driven into saturation, the nulling loop, output moves closer to the rail, the switch on attempting to force the differential input voltage to zero, resistance decreases, reducing the closed loop gain. The will drive C and C to a supply rail. After the EXTA EXTB output swing is reduced when the clamp function is used. saturating drive is removed, the capacitors take a finite time to recover—this is the overload recovery time. The How much current the output clamp leaks when off overload recovery is longest when the capacitors are is important because, when used, it is connected to the driven to the negative rail (refer to Overload Recovery in amplifier’s negative input. Any current acts like input bias the Typical Performance Characteristics section). The current and will degrade accuracy. At the other extreme, overload recovery time in this case is typically 225ms. In the maximum current the clamp conducts when on deter- the opposite direction (i.e., C and C at positive mines how much overdrive the clamp will take, and still EXTA EXTB rail), it is about ten times faster (25ms). The overload keep the amplifier from saturating. Both of these numbers recovery time for the LTC1052 is much faster than com- are guaranteed in the Electrical Characteristics section. petitive devices; however, if a faster overload recovery time is necessary, the output clamp function can be used. LOW SUPPLY OPERATION When the output clamp is connected to the negative input The minimum supply voltage for proper operation of the it prevents the amplifier from saturating, thus keeping LTC1052 is typically 4.0V (±2.0V). In single supply C and C at their nominal voltages. The output applications, PSRR is guaranteed down to 4.7V (±2.35V). EXTA EXTB clamp is a switch that turns on when the output gets to This assures proper operation down to the minimum TTL specified voltage of 4.75V. TYPICAL APPLICATIOU S 5V Powered Ultraprecision Instrumentation Amplifier Fast Precision Inverter 5V 4 5V 10k* 10k* +IN 7 8 3 + 7 INPUT LTC1052 6 VOUT 10k 8pF 2 – 8 11 1 4 1N4148 C1 C2 1µF 1µF 0.1µF 0.1µF 1000pF 12 R2 300pF R1 100k 5V 100 –IN 13 14 5V 2 + 7 LTC1043 0.22µF 2 + 7 LT318A 6 OUTPUT 6 3 5V 43k 6 5 10k 3 –LTC10542 8 10k – –5V4 + 1 2 C4 1N914 C3 1µF 10k 0.1µF 0.1µF 1µF 3 –5V *1% METAL FILM 18 15 ≈–0.5V FULL POWER BANDWIDTH = 2MHz SLEW RATE = 40V/µs 0.0047µF CIRCUITRY WITHIN DASHED LINES MAY BE DELETED IF OUTPUT SETTLING (10V STEP) = 12µs TO 0.01% 17 16 DOES NOT HAVE TO SWING ALL THE WAY TO GROUND BOIFAFSS ECTU DRRRIEFNTT = D 5C0 n=V 3/°0CpA VDORSIF =T 3=µ 5V0nV/°C OFFSET VOLTAGE = 5µV LTC1052/7652 • TA04 GAIN =R2+ 1 R1 CMRR = >120dB DC – 20kHz BANDWIDTH=10Hz LTC1052/7652 • TA03 1052fa 12

LTC1052/LTC7652 TYPICAL APPLICATIOU S Offset Stabilized Comparator 5V 4 5V + 14 13 8 330Ω 150Ω 2k 12 2 + 6 COMPARATOR 7 COMPARATOR INPUTS 11 3 –LT1011 5 OUTPUT (±5V) 1 4 10k –5V GROUND OR – 8 7 1µF INPUT COMMON- MODE VOLTAGE 5 LTC1043 6 1M 2 + 5V7 6 LTC1052 3 – 8 4 2 1 3 0.1µF 0.1µF –5V STATUS OUTPUT 5V 15 18 OV = ZERO 5V = COMPARE ZERO COMMAND 5V=ZERO 16 17 –5V=COMPARE –5V LTC1052/7652 • TA05 1HZ to 1.25MHz Voltage-to-Frequency Converter (5V Supply) 5V 470Ω 0.01µF 470Ω 10k 3 + 7 6 3.3k Q1 NC LTC1052 2N2907 2 8 – 4 2N3904 1 5V 74C04 0.1µF 0.1µF 330pF 10k OUTPUT 1H to 1.25MHz 0.01µF 10k FULL-SCALE TRIM 2k 5V 3.3pF VIN 30.1k* (1.25MHz) 5V 10k OV TO 5V 4 8 7 0.22µF 11 100pF** LT1004-1.2V 0.1µF *TRW MTR–5/+1200ppm/°C 12 **POLYSTYRENE–WESCO #32–P/ – 120ppm/°C ±0.05% LINEARITY >120dB DYNAMIC RANGE 14 13 0.01Hz/°C ZERO POINT DRIFT 1/2LTC1043 20ppm/°C GAIN DRIFT 16 LTC1052/7652 • TA06 17 1052fa 13

LTC1052/LTC7652 TYPICAL APPLICATIOU S No V Adjust* CMOS DAC Buffer—Single Supply Air Flow Detector OS 15V RFB CF* 1k 2 5 15V 10k 5V lOUT1 + 7 6 100k 12–BIT CMOS lDOAUTC2 3 –LTC10542 8 FVOORU THIGHER SPEED, REFER TO ±1% 2 + 5 7 15V 0.1µF 1 0.1µF “UFNADSETR P TRYEPCIICSAIOLN A IPNPVLEICRATTEIRO”NS LT1004-1.2 1k 3 –LTC1052 86 50VV== NAIOR AFILRO FWLOW 43.2Ω 4 ±1% 1 43k 4 0.1µF 0.1µF 6 5 AMBIENT– – 10k TEMPSETRIALTLU ARIRE+ TYPE K + 240Ω 11 LTC1052/7652 • TA08 + 1N914 0.1µF 1NµOFN POLARIZED *OFFSET VOLTAGE CAUSES AIR FLOW 12 NONLINEARITY ERRORS. SEE: “APPLICATION GUIDE TO CMOS MULTIPLYING D/A CONVERTERS,” 15 15 ≈ –0.5V ANALOG DEVICES, INC. 1pF LTC1052/7652 • TA07 1/2LTC1043 16 17 1Hz to 30MHz Voltage-to-Frequency Converter 5V 120Ω CURRENT STABILIZING SOURCE 12k 0.1µF AMP 120Ω 3 + 7 6 7.5k LTC1052 2N3906 2 – 4 8 FET BUFFER NC 1 2N5486 RESET DIODE 1Hz TO 30MHz 0.1µF 0.1µF 2N3904 OUTPUT 100pF 5V 50Ω 74S132 0.0.1µF –5V OUT 2k 30MHz 10k 2N5486 16.2k* TRIM 0.22µF 5V IN OV TO 3V CHARGE 50Ω TRIGGER PUMP 2k HP5082-2810 5V 8 7 –5V 100k 10k 1000M 11 LT1004–1.2V 1Hz TRIM 100pF† 0.22µF 100k 12 10 –5V *TRW MTR-5/ + 120ppm/°C †WESCO #32-P/ – 120ppm/°C 14 13 5V 5V 0.3Hz/°C ZERO-DRIFT 5 14 ±0.08% LINEARITY 1/2LTC1043 16 11 7490 14 5 1/274S74 3 2105p0pdmB /D°YCN GAAMINIC D RRAIFNTGE 10 11 12 7 LTC1052/7652 • TA09 1052fa 14

LTC1052/LTC7652 TYPICAL APPLICATIOU S ±100mA Output Drive Increasing Output Current 5V 100k 220pF VIN 74C04 5V 5V 2 – 7 100pF 1M 5V LTC1052 6 LTC1010 VOUT INPUT 10k 2 – 7 3 + 1 4 8 ±100mA 3 +LTC1052 86 OUTPUT –5V 4 RL 1 0.1µF 0.1µF 0.1µF 0.1µF –5V 100k VOS=5µV GVOASIN/∆=T1=050µV/°C LOAD OUTPUT SWING 100Ω FULL POWER BANDWIDTH=1kHz LTC1052/7652 • TA10 10k 5k ± 4.92V 2.5k ± 4.84V 2000pF 1k ± 4.65V 220Ω ± 3.65V LTC1052/7652 • TA11 Single 5V Thermocouple Amplifier with Cold Junction Compensation 5V + VT– 100k 1k LT1004-1.2 R1 5V 1690Ω 5k AT 25°C† 4 5V 7 8 3 – 7 ( ) 187Ω 1820Ω 2 +LTC1052 8 6 VOUT = VT 1+RRFl 11 4 1 1µF 1µF 0.1µF 0.1µF RF CF* 12 13 14 43k 5V 6 5 Rl 2 + IN914 1µF 1µF NONPOLARIZED 3 ≈–0.5V 10k 18 15 LTC1052/7652 • TA12 THERMOCOUPLE 16 LTC1043 TYPE R1 †YELLOW SPRINGS INST. CO. PART #44007 J 232k 0.0047µF 17 *CHOOSE CF TO FILTER NOISE KT 330011kk S 2.1M 1052fa 15

LTC1052/LTC7652 TYPICAL APPLICATIOU S Increasing Output Current and Voltage (VSUPPLY = ±15V) DC Stabilized FET Probe INPUT CAPACITANCE BOOTSTRAP 5V FAST SOURCE Q1 FOLLOWER INPUT 7V 2N3904 15V 2N5486 5V 0.1µF 30k 33pF 1N4148 INPUT 3k 2 – 7 NC LT1010 OUTPUT LTC1052 6 3 + 7 10M V+ 10M 3 +1 4 8 2 –LT318A 6 O±U12TVP UATT 20mA | LIMIT DRAIN CURRENT SIN–K5V 7 + 3 0.1µF 0.1µF 4 3k 2N22Q222 10k 6 LTC1052 0.1µF 0.01µF 8 – 2 –7V 2N3904 –15V 100Ω 4 1 1k 0.1µF NC –5V 0.1µF 0.1µF 2000pF DC STABILIZATION STABLE FOR ALL GAINS, INVERTING AND NONINVERTING, OBSERVE LTC1052 COMMON MODE INPUT LIMITS LTC1052/7652 • TA13 0.1µF 1k BANDWIDTH: 20MHz †RISE: 100ns DELAY: 5ns LTC1052/7652 • TA14 Precision Multiplexed Differential Thermocouple Amplifier 5V COLD JUNCTION COMPENSATOR 100k LT1004–1.2V R1 4 7 8 3 – 7 6 52k5 °ACT† 2 +LTC10542 8 VOUT=1001 • VTHERMOCOUPLE 1690Ω 11 1 1µF 1µF 0.1µF 0.1µF 0.1µF 187Ω 1820Ω 12 –5V 1M 13 14 5V 6 5 1k 16 12 13 2 1 3 1µF 1µF 3 14 †YELLOW SPRINGS INST. CO. PART #44007 5 18 15 LTC1043 THERMOCOUPLE 16 TYPE R1 15 J 232k 0.0047µF 17 K 301k 2 T 301k S 2.1M –5V 11 9 ADDRESS 4 10 8 7 CD4052B –5V LTC1052/7652 • TA15 1052fa 16

LTC1052/LTC7652 TYPICAL APPLICATIOU S Direct Thermocouple-to-Frequency Converter RT COLD JUNCTION TEMPERATURE TRACKING – + THERMOCOTYUPPEL EK 41.4µV/°C STABILIZING AMP5V 1.8k* 1N4148 470Ω 3 + 7 6 33k A 10k B C D E 100k 1N914 LTC1052 2 – 8 74C04 4 1µF 1 0.68µF OPTIONAL INPUT 0.1µF 0.1µF FILTER-AND-OVERLOAD 820pF CLAMP –5V 3300pF 150k** 5V 5V 60°C5 0TkRIM 74C04 F O0HUzT PTOU T600Hz 5V 0°C TO 60°C 33k** 16 –5V 3k A† LTC1043 4.75k* 74C903 5 6 1µF 0.1µF 1k* LT1004–1.2V ***0T.R0W1%/M FTIRLM/5-/T +R 1W2 0MAR-6 2 RT = YELLOW SPRINGS INST. #44007 100pF = POLYSTYRENE 100pF †FOR GENERAL PURPOSE (1mV FULL-SCALE) COLD JUNCTION BIAS 10-BIT A-TO-D, REMOVE THERMOCOUPLE— 487Ω* 301k* COLD JUNCTION NETWORK, GROUND POINT A, AND DRIVE LTC1052 POSITIVE INPUT 187Ω* LTC1052/7652 • TA16 Direct 10-Bit Strain Gauge Digitizer 5V 74C00 5V 1000pF 20Ω STRAIN GAUGE 28k –5V 14k 0.003µF 3 + 1 20Ω TZIRNA =N 3S5D0UΩCER CLOCK 5V LM301A 8 6 1k 2N2905 ZOUT = 350Ω INTEGRATOR 5V 2 –5V7 –5V4 470k* 1000pF 2 –LTC150V572 6 2 141/21 74C4743 5 10k5V 1/2 74C903 FORUETQ BUENCY 3 + 4 8 7 6 FREQUENCY 3.3MΩ* 1 –5V OUT A –5V BRIDGE DRIVE 1/2 LTC1043 0.01µF 0.01µF OUTPUT 7 8 GATING SW1 –5V DATA OUTPUT = OUT A= 1000 COUNTS FULL-SCALE 1N4148 OUT B *0.1% METAL FILM TRW MAR-5 1N4148 11 SW1=MAIN CURRENT SWITCH 16 SW2=CURRENT LOADING COMPENSATION SWITCH –5V 3.3M 12 SW2 CONNECT DIRECTLY 100k CONNECT TO BRIDGE ACROSS BRIDGE 13 14 DRIVE POINTS 10k END OF 470k RESISTOR (OPTIONAL) TRANSDUCER ZERO NETWORK + LTC1052/7652 • TA17 22.3k* 1k* 33µF 1052fa 17

LTC1052/LTC7652 TYPICAL APPLICATIOU S 16-Bit A/D Converter 74C00 5V 28k 14k 820pF CLOCK 0.01µF BOUT 10k 5V 5V EIN 95k* 2 – 7 1/3 74C903 OV TO 5V 14 1 4 2 10k 6 2 10pF 5V FULL-SCALE LTC1052 1/2 74C74 TRIM 3 + 8 IAN2TEGRATOR 7 5 6 AOUT 4 1 –5V 0.1µF 0.1µF 5V –5V 5V 1k 16 4 7 3 + 13 14 6 2N4338 LTC1052 8 – 2 12 4 1 0.1µF 0.1µF LT1009 1µF 0.01µF 39pF 11 –5V 75k* 20k 7 8 LINEARITY TRIM 18 15 CURRENT SINK –5V 3 DATA OUTPUT = AOUT BOUT LTC1043 100,000 COUNTS FULL-SCALE NO ZERO TRIM 17 20ppm/°C GAIN DRIFT –5V *VISHAY S-102 RESISTOR CURRENT SWITCH LTC1052/7652 • TA18 1052fa 18

LTC1052/LTC7652 TYPICAL APPLICATIOU S Precision Isolation Amplifier 1k* INPUT SIDE OUTPUT SIDE 74C04 10k 10k 20k ZERO TRIM 4 – 4 1 –15V 15V 100k* 2N5434 2N5434 30pF 22M 1 LTC1052 10 5 2 100k 3 + 14–PIN 2 L2 8 7 STANCOR PCT-39 1000pF LTC1052 6 OUT INPUT 5 + 14 1 2N5434 2N5434 2 – 7 –154V 1k GAIN TRIM 100k 13 0.1µF 0.1µF 6 3 15V 11 10k 13.3k* 5 5 74C04 11 74C90 1411 74C90 14 10k IN4148 ÷10 ÷10 100pF 10M 2k 2k (SELECT) 10k* 10 1 12 10 1 12 330Ω 15V 68pF 1N4148 1N4148 1.8k NC 2N3904 1k –15V 25mA 7 1 FLOATING +2.2µF 2N2222 74C04 SUPPLY NC 2N3904 L1 OUTPUTS 11k DALE TC–10–11 POWER 251m5VA + 1N4148 4.3k 8 DR2IVER15V 1000pF –15V 20k 2.2µF 20k FLOATING COMMON 2N2222 68pF 9 3 1k LTC1052/7652 • TA19 250V ISOLATION 1.8k 0.03% ACCURACY *1% FILM RESISTOR 15V 1052fa 19

LTC1052/LTC7652 PACKAGE DESCRIPTIOU H Package 8-Lead TO-5 Metal Can (.200 Inch PCD) (Reference LTC DWG # 05-08-1320) .335 – .370 (8.509 – 9.398) DIA .305 – .335 (7.747 – 8.509) .040 (1.016) .050 MAX (1.270) .165 – .185 MAX (4.191 – 4.699) REFERENCE SEATING PLANE PLANE GPLAAUNGEE .500 – .750 (12.700 – 19.050) .010 – .045* (0.254 – 1.143) .016 – .021** (0.406 – 0.533) .027 – .045 (0.686 – 1.143) 45°TYP PIN 1 .028 – .034 (0.711 – 0.864) .200 (5.080) TYP .110 – .160 (2.794 – 4.064) INSULATING STANDOFF *LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE AND THE SEATING PLANE .016 – .024 **FOR SOLDER DIP LEAD FINISH, LEAD DIAMETER IS (0.406 – 0.610) H8(TO-5) 0.200 PCD 0801 OBSOLETE PACKAGE 1052fa 20

LTC1052/LTC7652 PACKAGE DESCRIPTIOU J Package 14-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) .785 (19.939) .005 MAX (0.127) MIN 14 13 12 11 10 9 8 .025 .220 – .310 (0.635) (5.588 – 7.874) RAD TYP 1 2 3 4 5 6 7 .200 .300 BSC (5.080) (7.62 BSC) MAX .015 – .060 (0.381 – 1.524) .008 – .018 0° – 15° (0.203 – 0.457) .045 – .065 .100 .125 (1.143 – 1.651) (2.54) (3.175) .014 – .026 BSC MIN NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS (0.360 – 0.660) J14 0801 OBSOLETE PACKAGE 1052fa 21

LTC1052/LTC7652 PACKAGE DESCRIPTIOU J8 Package 8-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) CORNER LEADS OPTION .405 (4 PLCS) (10.287) .005 MAX (0.127) MIN 8 7 6 5 .023 – .045 (0.584 – 1.143) HALF LEAD OPTION .025 .220 – .310 .045 – .068 (0.635) (5.588 – 7.874) (1.143 – 1.650) RAD TYP FULL LEAD OPTION 1 2 3 4 .200 .300 BSC (5.080) (7.62 BSC) MAX .015 – .060 (0.381 – 1.524) .008 – .018 0° – 15° (0.203 – 0.457) .045 – .065 .125 NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE (1.143 – 1.651) OR TIN PLATE LEADS 3.175 .014 – .026 .100 MIN (0.360 – 0.660) (2.54) BSC J8 0801 OBSOLETE PACKAGE N8 Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) .400* (10.160) MAX 8 7 6 5 .255 ± .015* (6.477 ± 0.381) 1 2 3 4 .300 – .325 .045 – .065 .130 ± .005 (7.620 – 8.255) (1.143 – 1.651) (3.302 ± 0.127) .065 (1.651) .008 – .015 TYP (0.203 – 0.381) .120 (3.048) .020 .325+–..003155 .100 .018 ± .0M0I3N (0M.5I0N8) (8.255–+00..838891) (2B.S5C4) (0.457 ± 0.076) N8 1002 NOTE: INCHES 1. DIMENSIONS ARE MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) 1052fa 22

LTC1052/LTC7652 PACKAGE DESCRIPTIOU N Package 14-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) .770* (19.558) MAX 14 13 12 11 10 9 8 .255 ± .015* (6.477 ± 0.381) 1 2 3 4 5 6 7 .300 – .325 .130 ± .005 .045 – .065 (7.620 – 8.255) (3.302 ± 0.127) (1.143 – 1.651) .020 (0.508) MIN .065 .008 – .015 (1.651) (0.203 – 0.381) TYP +.035 .325–.015 .120 .005 .018 ± .003 (8.255–+00..838891) (3M.0I4N8) (0M.1I2N5) (.21.0504) (0.457 ± 0.076) BSC NOTE: INCHES 1. DIMENSIONS ARE N14 1002 MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) 1052fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 23 However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1052/LTC7652 PACKAGE DESCRIPTIOU SW Package 16-Lead Plastic Small Outline (Wide .300 Inch) (Reference LTC DWG # 05-08-1620) .030 ±.005 .050 BSC .045 ±.005 .398 – .413 TYP (10.109 – 10.490) NOTE 4 N 16 15 14 13 12 11 10 9 N .420 .325 ±.005 MIN NOTE 3 .394 – .419 (10.007 – 10.643) N/2 1 2 3 N/2 RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 .291 – .299 (7.391 – 7.595) NOTE 4 .093 – .104 .037 – .045 .010 – .029 × 45°(cid:31) (2.362 – 2.642) (0.940 – 1.143) (0.254 – 0.737) .005 (0.127) RAD MIN 0° – 8° TYP .050 .009 – .013 (1.270) .004 – .012 (0.229 – 0.330) NOTE 3 BSC (0.102 – 0.305) .014 – .019 .016 – .050 (0.356 – 0.482) (0.406 – 1.270) TYP NOTE: INCHES 1. DIMENSIONS IN (MILLIMETERS) S16 (WIDE) 0502 2. DRAWING NOT TO SCALE 3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS 4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 1052fa 24 Linear Technology Corporation LW/TP 1202 1K REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 1985

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: LTC1052CSW#PBF LTC1052CN#PBF LTC1052CN8 LTC1052CN LTC1052CSW#TR LTC1052CSW LTC1052CSW#TRPBF LTC1052CN8#PBF