LT6411 650MHz Differential ADC Driver/Dual Selectable Gain Amplifi er FEATURES DESCRIPTION ■ 650MHz –3dB Small-Signal Bandwidth The LT®6411 is a dual amplifi er with individually selectable ■ 600MHz –3dB Large-Signal Bandwidth gains of +1, +2 and –1. The amplifi ers have excellent dis- ■ High Slew Rate: 3300V/µs tortion performance for driving ADCs as well as excellent ■ Easily Confi gured for Single-Ended to Differential bandwidth and slew rate for video, data transmission and Conversion other high speed applications. Single-ended to differential ■ 200MHz ±0.1dB Bandwidth conversion with a system gain of 2 is particularly straight- ■ User Selectable Gain of +1, +2 and –1 forward by confi guring one amplifi er with a gain of +1 ■ No External Resistors Required and the other amplifi er with a gain of –1. The LT6411 can ■ 46.5dBm Equivalent OIP3 at 30MHz When Driving an be used on split supplies as large as ±6V and on a single ADC supply as low as 4.5V. ■ IM3 with 2V Composite, Differential Output: P-P Each amplifi er draws only 8mA of quiescent current when –87dBc at 30MHz, –83dBc at 70MHz enabled. When disabled, the output pins become high ■ –77dB SFDR at 30MHz, 2V Differential Output P-P impedance and each amplifi er draws less than 350µA. ■ 6ns 0.1% Settling Time for 2V Step ■ Low Supply Current: 8mA per Ampifi er The LT6411 is manufactured on Linear Technology’s ■ Differential Gain of 0.02%, Differential Phase of 0.01° proprietary, low voltage, complimentary, bipolar process ■ 50dB Channel Separation at 100MHz and is available in the ultra-compact, 3mm × 3mm, 16pin ■ Wide Supply Range: ±2.25V (4.5V) to ±6.3V (12.6V) QFN package. ■ 3mm × 3mm 16-Pin QFN Package , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. APPLICATIONS ■ Differential ADC Driver ■ Single-Ended to Differential Conversion ■ Differential Video Line Driver TYPICAL APPLICATION 30MHz 2-Tone 32768 Point FFT, LT6411 Differential ADC Driver Driving an LTC®2249 14-Bit ADC 5V 0 –10 32768 POINT FFT TONE 1 AT 29.5MHz, –7dBFS VCC –20 TONE 2 AT 30.5MHz, –7dBFS LT6411 –30 IM3 = –87dBc –40 + 24Ω BFS) –50 1.9VDC – E (d –60 370Ω 370Ω AIN– UD –70 30MHz LTC2249 LIT –80 INPUT 370Ω 370Ω 14-BIT ADC MP –90 AIN+ 80Msps A–100 –110 1.9VDC – 24Ω –120 + 6411 TA01a –130 –140 VEE 0 5 10 15 20 25 30 35 40 DGND FREQUENCY (MHz) 6411 TA01b EN 6411f 1

LT6411 ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION (Note 1) Total Supply Voltage (V to V ) ..........................12.6V CC EE TOP VIEW Input Current (Note 2) ..........................................±10mA +2 –2 –1 +1 N N N N Output Current (Continuous) ...............................±70mA I I I I 16 15 14 13 EN to DGND Voltage (Note 2) ..................................5.5V VEE 1 12 DGND Output Short-Circuit Duration (Note 3) ............Indefi nite VEE 2 11 EN 17 Operating Temperature Range (Note 4) ...–40°C to 85°C VEE 3 10 VCC Specifi ed Temperature Range (Note 5) ....–40°C to 85°C NC 4 9 VCC 5 6 7 8 Storage Temperature Range ...................–65°C to 125°C Junction Temperature ...........................................125°C UT2 VCC VEE UT1 O O UD PACKAGE 16-LEAD (3mm × 3mm) PLASTIC QFN TJMAX = 125°C, θJA = 68°C/W, θJC = 4.2°C/W EXPOSED PAD (PIN 17) IS VEE, MUST BE SOLDERED TO PCB ORDER PART NUMBER UD PART MARKING* LT6411CUD LCGP LT6411IUD LCGP Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *Temperature grade is identifi ed by a label on the shipping container. ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = ±5V, A = 2, R = 150Ω, C = 1.5pF, V = 0.4V, V = 0V, A S V L L EN DGND unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Referred Offset Voltage V = 0V, V = V /2 3 ±10 mV OS IN OS OUT ● ±20 mV I Input Current ● –17 ±50 µA IN R Input Resistance V = ±1V ● 150 500 kΩ IN IN C Input Capacitance f = 100kHz 1 pF IN V Maximum Input Common Mode Voltage V – 1 V CMR CC Minimum Input Common Mode Voltage V + 1 V EE PSRR Power Supply Rejection Ratio V (Total) = 4.5V to 12V (Note 6) ● 56 62 dB S I Input Current Power Supply Rejection V (Total) = 4.5V to 12V (Note 6) ● 1 ±4 µA/V PSRR S A ERR Gain Error V = ±2V ● –1.2 ±5 % V OUT A MATCH Gain Matching V = ±2V ±1 % V OUT V Maximum Output Voltage Swing R = 1k ±3.70 ±3.95 V OUT L R = 150Ω ±3.25 ±3.6 V L R = 150Ω ● ±3.10 V L I Supply Current, Per Amplifi er 8 11 mA S ● 14 mA Supply Current, Disabled, per Amplifi er V = 4V ● 22 350 µA EN V = Open ● 0.5 350 µA EN I Enable Pin Current V = 0.4V ● –200 –95 µA EN EN V = V+ ● 0.5 50 µA EN 6411f 2

LT6411 ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = ±5V, A = 2, R = 150Ω, C = 1.5pF, V = 0.4V, V = 0V, A S V L L EN DGND unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I Output Short-Circuit Current R = 0Ω, V = ±1V ● ±50 ±105 mA SC L IN SR Slew Rate ±1V on ±2V Output Step (Note 9) 1700 3300 V/µs –3dB BW Small-Signal –3dB Bandwidth V = 200mV , Single Ended 650 MHz OUT P-P 0.1dB BW Gain Flatness ±0.1dB Bandwidth V = 200mV , Single Ended 200 MHz OUT P-P FPBW Full Power Bandwidth 2V Differential V = 2V Differential, –3dB 600 MHz OUT P-P Full Power Bandwidth 2V V = 2V (Note 7) 270 525 MHz OUT P-P Full Power Bandwidth 4V V = 4V (Note 7) 263 MHz OUT P-P All Hostile Crosstalk f = 10MHz, V = 2V –75 dB OUT P-P f = 100MHz, V = 2V –50 dB OUT P-P t Settling Time 0.1% to V , V = 2V 6 ns s FINAL STEP t, t Small-Signal Rise and Fall Time 10% to 90%, V = 200mV 550 ps r f OUT P-P dG Differential Gain (Note 8) 0.02 % dP Diffi erential Phase (Note 8) 0.01 Deg The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. A V = 5V, V = 0V, A = 2, No R , V = 0.4V, V = 0V, unless otherwise noted. CC EE V LOAD EN DGND SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Noise/Harmonic Performance Input/Output Characteristics 1MHz Signal HD Second/Third Harmonic Distortion 2V Differential –88 dBc P-P 2V Differential, R = 200Ω Differential –87 dBc P-P L IMD3 Third-Order IMD 2V Differential Composite, f1 = 0.95MHz, –93 dBc 1M P-P f2 = 1.05MHz 2V Differential Composite, f1 = 0.95MHz, –91 dBc P-P f2 = 1.05MHz, R = 200Ω Differential L OIP3 Output Third-Order Intercept Differential, f1 = 0.95MHz, f2 = 1.05MHz (Note 10) 49.5 dBm 1M NF Noise Figure Single Ended 25.1 dB e Input Referred Noise Voltage Density 8 nV/√Hz n1M P1dB 1dB Compression Point (Note 10) 19.5 dBm 10MHz Signal HD Second/Third Harmonic Distortion 2V Differential –85 dBc P-P 2V Differential, R = 200Ω Differential –76 dBc P-P L IMD3 Third-Order IMD 2V Differential Composite, R = 1k, –92 dBc 10M P-P L f1 = 9.5MHz, f2 = 10.5MHz 2V Differential Composite, f1 = 9.5MHz, –89 dBc P-P f2 = 10.5MHz, R = 200Ω Differential L OIP3 Output Third-Order Intercept Differential, f1 = 9.5MHz, f2 = 10.5MHz (Note 10) 49 dBm 10M NF Noise Figure Single Ended 24.7 dB e Input Referred Noise Voltage Density 7.7 nV/√Hz n10M P1dB 1dB Compression Point (Note 10) 19.5 dBm 6411f 3

LT6411 ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V = 5V, V = 0V, A = 2, No R , V = 0.4V, V = 0V, A CC EE V LOAD EN DGND unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 30MHz Signal HD Second/Third Harmonic Distortion 2V Differential –77 dBc P-P 2V Differential, R = 200Ω Differential –64 dBc P-P L IMD3 Third-Order IMD 2V Differential Composite, f1 = 29.5MHz, –87 dBc 30M P-P Differential, f2 = 30.5MHz 2V Differential Composite, f1 = 29.5MHz, –75 dBc P-P f2 = 30.5MHz, R = 200Ω Differential L OIP3 Output Third-Order Intercept Differential, f1 = 29.5MHz, f2 = 30.5MHz (Note 10) 46.5 dBm 30M NF Noise Figure Single Ended 24.6 dB e Input Referred Noise Voltage Density 7.6 nV/√Hz n30M P1dB 1dB Compression Point (Note 10) 19.5 dBm 70MHz Signal HD Second/Third Harmonic Distortion 2V Differential –63 dBc P-P 2V Differential, R = 200Ω Differential –52 dBc P-P L IMD3 Third-Order IMD 2V Differential Composite, f1 = 69.5MHz, –83 dBc 70M P-P Differential, f2 = 70.5MHz 2V Differential Composite, f1 = 69.5MHz, –64 dBc P-P f2 = 70.5MHz, R = 200Ω Differential L OIP3 Output Third-Order Intercept Differential, f1 = 69.5MHz, f2 = 70.5MHz (Note 10) 44.5 dBm 70M NF Noise Figure Single Ended 24.7 dB e Input Referred Noise Voltage Density 7.7 nV/√Hz n70M P1dB 1dB Compression Point (Note 10) 19.5 dBm Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 7: Full power bandwidth is calculated from the slew rate: may cause permanent damage to the device. Exposure to any Absolute FPBW = SR/(π • V ) P-P Maximum Rating condition for extended periods may affect device Note 8: Differential gain and phase are measured using a Tektronix reliability and lifetime. TSG120YC/NTSC signal generator and a Tektronix 1780R video Note 2: This parameter is guaranteed to meet specifi ed performance measurement set. The resolution of this equipment is better than 0.05% through design and characterization. It is not production tested. and 0.05°. Ten identical amplifi er stages were cascaded giving an effective Note 3: As long as output current and junction temperature are kept resolution of better than 0.005% and 0.005°. below the Absolute Maximum Ratings, no damage to the part will occur. Note 9: Slew rate is 100% production tested on channel 1. Slew rate of Depending on the supply voltage, a heat sink may be required. channel 2 is guaranteed through design and characterization. Note 4: The LT6411C is guaranteed functional over the operating Note 10: Since the LT6411 is a feedback amplifi er with low output temperature range of –40°C to 85°C. impedance, a resistive load is not required when driving an ADC. Note 5: The LT6411C is guaranteed to meet specifi ed performance from Therefore, typical output power is very small. In order to compare the 0°C to 70°C. The LT6411C is designed, characterized and expected to LT6411 with typical gm amplifi ers that require 50Ω output loading, the meet specifi ed performance from –40°C and 85°C but is not tested or LT6411 output voltage swing driving an ADC is converted to OIP3 and QA sampled at these temperatures. The LT6411I is guaranteed to meet P1dB as if it were driving a 50Ω load. specifi ed performance from –40°C to 85°C. Note 6: The two supply voltage settings for power supply rejection are shifted from the typical ±V points for ease of testing. The fi rst S measurement is taken at V = 3V, V = –1.5V to provide the required 3V CC EE headroom for the enable circuitry to function with EN, DGND and all inputs connected to 0V. The second measurement is taken at V = 8V, V = –4V. CC EE 6411f 4

LT6411 TYPICAL PERFORMANCE CHARACTERISTICS All measurements are per amplifi er with single-ended outputs unless otherwise noted. Supply Current per Amplifi er Supply Current per Ampifi er Supply Current per Amplifi er vs Temperature vs Supply Voltage vs EN Pin Voltage 12 12 12 VS = ±5V VCC = –VEE VS = ±5V 10 RVILN =+, ∞VIN– = 0V 10 VTAE N=, 2V5D°GCND, VIN+, VIN– = 0V 10 TA = –55°C VVDING+N, DV I=N –0 V= 0V SUPPLY CURRENT (mA) 864 VENV E=N 0 =.4 0VV SUPPLY CURRENT (mA) 864 SUPPLY CURRENT (mA) 864 TA T=A 1 =2 52°5C°C 2 2 2 0 0 0 –55–35 –15 5 25 45 65 85 105 125 0 1 2 3 4 5 6 7 8 9 10 11 12 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 TEMPERATURE (°C) TOTAL SUPPLY VOLTAGE (V) EN PIN VOLTAGE (V) 6411 G01 6411 G02 6411 G03 Output Offset Voltage Positive Input Bias Current vs Temperature vs Input Voltage EN Pin Current vs EN Pin Voltage 20 20 0 VS = ±5V VS = ±5V VS = ±5V 15 VAIVN = = 2 0V AV = 2 –20 VDGND = 0V OFFSET VOLTAGE (mV) –1–105050 +µIN BIAS CURRENT (A) ––42000 TTTAAA === 12–2555°5C°°CC µEN PIN CURRENT (A)––––146800000 TA = 125°C TA T=A 2 =5 °–C55°C –15 –120 –20 –60 –140 –55–35 –15 5 25 45 65 85 105 125 –2.5 –1.5 –0.5 0.5 1.5 2.5 0 1 2 3 4 5 TEMPERATURE (°C) INPUT VOLTAGE (V) EN PIN VOLTAGE (V) 6411 G04 6411 G05 6411 G06 Output Voltage Swing vs I Output Voltage Swing vs I LOAD LOAD Output Voltage vs Input Voltage (Output High) (Output Low) 5 5 0 VS = ±5V VS = ±5V VS = ±5V 4 RL = 1k AV = 2 AV = 2 3 AV = 1 4 VIN = 2V –1 VIN = –2V V) 2 TA = 25°C V) V) TA = 25°C GE ( 1 GE ( 3 TA = –55°C GE ( –2 OLTA 0 OLTA TA = 25°C OLTA TA = 125°C V V V UTPUT ––12 TA = –55°C UTPUT 2 TA = 125°C UTPUT –3 TA = –55°C O O O –3 1 –4 –4 TA = 125°C –5 0 –5 –4.5–3.5–2.5–1.5–0.5 0.5 1.5 2.5 3.5 4.5 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 INPUT VOLTAGE (V) SOURCE CURRENT (mA) SINK CURRENT (mA) 6411 G07 6411 G08 6411 G09 6411f 5

LT6411 TYPICAL PERFORMANCE CHARACTERISTICS All measurements are per amplifi er with single-ended outputs unless otherwise noted. Positive Input Impedance Input Noise Spectral Density vs Frequency PSRR vs Frequency 1000 1000 70 Hz) VATASV === 2±255°VC VVTASIN == = 2± 055V°VC 60 ±PSRR VATASV === 2±255°VC √√UT NOISE (nV/Hz OR pA/ 10100 inen ΩINPUT IMPEDANCE (k) 101001 REJECTION RATIO (dB) 54320000 –PSRR +PSRR P N 10 I 1 0.1 0 0.001 0.01 0.1 1 10 100 0.01 0.1 1 10 100 1000 0.001 0.01 0.1 1 10 100 FREQUENCY (kHz) FREQUENCY (MHz) FREQUENCY (MHz) 6553 G10 6411 G11 6411 G12 Frequency Response Frequency Response with vs Gain Confi guration Gain Flatness vs Frequency Capacitive Loads 9 6.5 18 GAIN (dB) 036 AV = 1, AAVV == –21, ,VVAOOVUU TT=A ==1V , 22 =V00 O200,Umm VTVV O=PPU --2TPPV =P -2PVP-P RMALIZED GAIN (dB) 5666665.......8430219 VAVRTASVOL U====T 2 ±21=555 °20VC0Ω0mVP-P CHANCNHEALN 2NEL 1 AMPLITUDE (dB) 111164208642 VAVRTASVOL U====T 2 ±21=555 °20VCVΩP-P CCLL = = 6 2.8.2ppFF CL = 12pF O N 0 –3 VS = ±5V AV = –1, VOUT = 2VP-P 5.7 –2 TRAL == 2155°0CΩ 5.6 –4 –6 5.5 –6 0.1 1 10 100 1000 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) 6411 G13 6411 G14 6553 G15 Harmonic Distortion vs Frequency, Harmonic Distortion vs Amplitude, Harmonic Distortion vs Load, Differential Input 30MHz, Differential Input 30MHz, Differential Input 0 0 0 VOUT = 2VP-P, DIFFERENTIAL AV = 2, VCC = 5V VOUT = 2VP-P, DIFFERENTIAL –10 AV = 2, VCC = 5V –10 VEE = 0V, VCM = 1.6V –10 AV = 2, VCC = 5V –20 VDEIFEF =E R0EVN, VTICAML =R 1LO.6AVD –20 RTAL == 2∞5°C –20 VTAE E= = 2 05V°C, VCM = 1.6V Bc)–30 TA = 25°C Bc) –30 Bc) –30 N (d –40 N (d –40 N (d –40 TIO –50 HD3, RL = 200Ω TIO –50 TIO –50 R R R TO –60 HD3, RL = ∞ TO –60 TO –60 S S S DI –70 HD2, RL = 200Ω DI –70 HD3 DI –70 HD3 –80 –80 –80 –90 HD2, RL = ∞ –90 HD2 –90 HD2 –100 –100 –100 1 10 100 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 1002003004005006007008009001000 FREQUENCY (MHz) DIFFERENTIAL OUTPUT AMPLITUDE (VP-P) DIFFERENTIAL RLOAD (Ω) 6411 G16 6411 G17 1011 G06 6411f 6

LT6411 TYPICAL PERFORMANCE CHARACTERISTICS All measurements are per amplifi er with single-ended outputs unless otherwise noted. Third Order Intermodulation Distortion vs Frequency, Output Third Order Intercept Differential Input vs Frequency, Differential Input Output Impedance vs Frequency 0 60 1000 ––2100 V1AMOV UH=T z 2 =T, O2VVCNCPE - =PS ,5P CVAOCMINPGOSITE, DIFFERENTIAL 50 COMPUTED FORR L5 0=Ω ∞ ENVIRONMENT DVISEANB =L E4DV c) VEE = 0V, VCM = 1.6V Ω) 100 MD (dB––3400 DTAIF =F E2R5E°CNTIAL RLOAD m) 40 RL = 200Ω ANCE ( THIRD ORDER I––––76580000 RL = 200RΩL = ∞ OIP3 (dB 321000 VV1AMOVEE UH= T= z 2 =0T, VO2V,VCN VCPEC - =PSM ,5P C=VAO C1M.I6NPVGOSITE, DIFFERENTIAL OUTPUT IMPED 110 VEENN A=B 0L.E4DV VS = ±5V –90 DIFFERENTIAL RLOAD RL = 150Ω TA = 25°C TA = 25°C –100 0 0.1 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 0.01 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) 6411 G19 6411 G20 6411 G21 Video Amplitude Transient Small-Signal Transient Response Response Large-Signal Transient Response 0.15 2.0 4 00..1005 TVAVRAIVSLN ==== = 22±1 15550°0V0CΩmVP-P 1.5 VARTVAIVSLN ==== = 22±1 75550°0V0CΩmVP-P 32 VAVRTAIVSLN ==== = 22±1 2555.°05VCΩVP-P UT (V) 0 UT (V) 1.0 UT (V) 10 OUTP OUTP 0.5 OUTP –1 –0.05 –2 0 –0.10 –3 –0.15 –0.5 – 4 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 TIME (ns) TIME (ns) TIME (ns) 6411 G22 6411 G23 6411 G24 Crosstalk vs Frequency Gain Error Distribution Gain Matching Distribution 0 40 35 –20 TVVRASOL U===T 2 ±1=555 °20VCVΩP-P %) 3305 VVRTASOL U===T 2 ±1=555 °±0VCΩ2V %) 3205 VVRTASOL U===T 2 ±1=555 °±0VCΩ2V AMPLITUDE (dB) –––864000 LDISRTIEVNE 21 PERCENT OF UNITS ( 21215500 PERCENT OF UNITS ( 211050 DRIVE 1 –100 LISTEN 2 5 5 –120 0 0 1 10 100 1000 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 –3.0 –2.0 –1.0 0 1.0 2.0 3.0 FREQUENCY (MHz) GAIN ERROR–INDIVIDUAL CHANNEL (%) GAIN MATCHING–BETWEEN CHANNELS (%) 1635 G25 6411 G26 6411 G27 6411f 7

LT6411 PIN FUNCTIONS V (Pins 1, 2): Negative Supply Voltage. V pins are not EN (Pin 11): Enable Control Pin. An internal pull-up resis- EE EE internally connected to each other and must all be con- tor of 46k will turn the part off if the pin is allowed to fl oat nected externally. Proper supply bypassing is necessary and defi nes the pin’s impedance. When the pin is pulled for best performance. See the Applications Information low, the part is enabled. section. DGND (Pin 12): Digital Ground Reference for Enable Pin. V (Pins 3, 7): Negative Supply Voltage for Output Stage. This pin is normally connected to ground. EE V pins are not internally connected to each other and EE IN1+ (Pin 13): Channel 1 Positive Input. This pin has a must all be connected externally. Proper supply bypassing nominal impedance of 400kΩ and does not have an internal is necessary for best performance. See the Applications termination resistor. Information section. IN1– (Pin 14): This pin connects to the internal resistor NC (Pin 4): This pin is not internally connected. network of the channel 1 amplifi er, connecting by a 370Ω OUT2 (Pin 5): Output of Channel 2. The gain between the resistor to the inverting input. input and the output of this channel is set by the connection IN2– (Pin 15): This pin connects to the internal resistor of the channel 2 input pins. See Table 1 in Applications network of the channel 2 amplifi er, connecting by a 370Ω Information for details. resistor to the inverting input. V (Pins 6, 9): Positive Supply Voltage for Output Stage. CC IN2+ (Pin 16): Channel 2 Positive Input. This pin has a V pins are not internally connected to each other and CC nominal impedance of 400kΩ and does not have an internal must all be connected externally. Proper supply bypassing termination resistor. is necessary for best performance. See the Applications Information section. Exposed Pad (Pin 17): The pad is internally connected to V (Pin 1). If split supplies are used, do not tie the pad EE OUT1 (Pin 8): Output of Channel 1. The gain between the to ground. input and the output of this channel is set by the connection of the channel 1 input pins. See Table 1 in Applications Information for details. V (Pin 10): Positive Supply Voltage. V pins are not CC CC internally connected to each other and must all be con- nected externally. Proper supply bypassing is necessary for best performance. See the Applications Information section. 6411f 8

LT6411 APPLICATIONS INFORMATION Power Supplies Since the EN pin is referenced to DGND, it may need to be pulled below ground in those cases. In order to protect the The LT6411 can be operated on as little as ±2.25V or a internal enable circuitry, the EN pin should not be forced single 4.5V supply and as much as ±6V or a single 12V more than 0.5V below DGND. supply. Internally, each supply is independent to improve channel isolation. Note that the Exposed Pad is internally In single supply applications above 5.5V, an additional connected to V and must not be grounded when using resistor may be needed from the EN pin to DGND if the EE split supplies. Do not leave any supply pins disconnected pin is ever allowed to fl oat. For example, on a 12V single or the part may not function correctly! supply, a 33k resistor would protect the pin from fl oating too high while still allowing the internal pull-up resistor Enable/Shutdown to disable the part. The LT6411 has a TTL compatible shutdown mode con- The DGND pin should not be pulled above the EN pin since trolled by the EN pin and referenced to the DGND pin. If doing so will turn on an ESD protection diode. If the EN the amplifi er will be enabled at all times, the EN pin can pin voltage is forced a diode drop below the DGND pin, be connected directly to DGND. If the enable function is current should be limited to 10mA or less. desired, either driving the pin above 2V or allowing the The enable/disable times of the LT6411 are fast when internal 46k pull-up resistor to pull the EN pin to the top driven with a logic input. Turn on (from 50% EN input to rail will disable the amplifi er. When disabled, the DC output 50% output) typically occurs in less than 50ns. Turn off impedance will rise to approximately 740Ω through the is slower, but is less than 300ns. internal feedback and gain resistors (assuming inputs at ground). Supply current into the amplifi er in the disabled Gain Selection state will be primarily through V and approximately CC equal to (V – V )/46k. The gain of the internal amplifi ers of the LT6411 is confi g- CC EN ured by connecting the IN+ and IN– pins to the input signal It is important that the two following constraints on the or ground in the combinations shown in Figure 1. DGND pin and the EN pin are always followed: As shown in the Simplifi ed Schematic, the IN– pins connect V – V ≥ 3V CC DGND to the internal gain resistor of each amplifi er, and therefore, –0.5V ≤ V – V ≤ 5.5V EN DGND each pin can be confi gured independently. Floating the Split supplies of ±3V to ±5.5V will satisfy these require- IN– pins is not recommended as the parasitic capacitance ments with DGND connected to 0V. causes an AC gain of 2 at high frequencies, despite a DC gain of +1. Both inputs are connected together in the gain In dual supply cases with V less than 3V, DGND should CC of +1 confi guration to avoid this limitation. be connected to a potential below ground such as V . EE +V +V +V IN+ LT6411 OUT+ AV = +1 LT6411 OUT+ AV = –1 LT6411 OUT– + IN+ + IN+ + – – – AV = +2 IN– IN– OUT+ IN– – OUT– – OUT– – + + + 6411 F01 –V –V –V Figure 1. LT6411 Confi gured in Noninverting Gain of 2, Noninverting Gain of 1 and Inverting Gain of 1, All Shown with Dual Supplies 6411f 9

LT6411 APPLICATIONS INFORMATION Input Considerations the blocking capacitor to the gain setting resistors sets the input and output DC common mode voltages equal. The LT6411 input voltage range is from V + 1V to EE When using the LT6411 to drive an A-to-D converter, the V – 1V. Therefore, on split supplies the LT6411 input CC DC common mode voltage level will affect the harmonic range is always as large as or larger than the output swing. On a single positive supply with a gain of +2 and IN– con- distortion of the combined amplifi er/ADC system. Figure 4 shows the measured distortion of an LTC2249 ADC when nected to ground, however, the input range limit of +1V driven by the LT6411 at different common mode voltage limits the linear output low swing to 2V (1V multiplied by levels with the inputs confi gured as shown in Figure 3. the internal gain of 2). Adjusting the DC bias voltage can optimize the design for The inputs can be driven beyond the point at which the the lowest possible distortion. output clips so long as input currents are limited to If the input signals are within the input voltage range ±10mA. Continuing to drive the input beyond the output and output swing of the LT6411, but outside the input limit can result in increased current drive and slightly range of an ADC or other circuit the LT6411 is driving, increased swing, but will also increase supply current and may result in delays in transient response at larger V+ +V levels of overdrive. IN+ CLARGE R1 LT6411 DC Biasing Differential Amplifi er Applications OV VDC + OUT+ R2 – VDC The inputs of the LT6411 must be DC biased within the input common mode voltage range, typically V + 1V to EE V+ V – 1V. If the inputs are AC coupled or DC biased be- OUT– CC IN– CLARGE R1 – yond the input voltage range of a driven A-to-D converter, VDC VDC OV + DC biasing or level shifting will be required. In the basic R2 circuit confi gurations shown in Figure 1, the DC input 6411 F03 common mode voltage and the differential input signal Figure 3. Using Resistor Dividers to Set the are both multiplied by the amplifi er gain. In the gain of Input Common Mode Voltage When AC Coupling +2 confi guration, the DC common mode voltage gain can be set to unity by adding a capacitor at the IN– pins as shown in Figure 2. –50 VCC = 5V, VEE = 0V If the inputs are AC coupled or the LT6411 is preceded –55 AV= 2 TA = 25°C by a highpass fi lter, the input common mode voltage can –60 be set by resistor dividers as shown in Figure 3. Adding dBc) –65 N ( HD3 +V O TI –70 R O VDC IN+ LT6411 + OUT+ DIST ––7850 IM3 – VDC –85 HD2 CLARGE –901.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 OUT– IN– – VCM (V) VDC 6411 F04 VDC + Figure 4. Harmonic and Intermodulation Distortion of the 6411 F02 LT6411 Driving an LTC2249 Versus DC Common Mode Voltage. Harmonic Distortion Measured with a –1dBFS Signal Figure 2. LT6411 Confi gured with a Differential Gain of 2 at 30.2MHz. Intermodulation Distortion Measured with Two and Unity DC Common Mode Gain –7dBFS Tones at 30.2MHz and 29.2MHz 6411f 10

LT6411 APPLICATIONS INFORMATION the output signals can be AC coupled and DC biased in a +V manner similar to what is shown at the inputs in Figure IN+ LT6411 3. A simpler alternative when using an ADC such as the VCM + OUT+ LTC2249 is to use the ADC’s VCM pin to set the optimal – VCM common mode voltage as shown in Figure 5. If unity common mode gain and difference mode response OUT– to DC is desired, there is another confi guration available. IN– – VCM Figure 6 shows the LT6411 connected to provide a differ- VCM + ential signal gain of +3 with unity common mode gain. For 6411 F06 differential signal gain between unity and +3, three resistors Figure 6. LT6411 Confi gured for a Differential Gain of +3 can be added to provide attenuation and set the differential and Unity Common Mode Gain with Response to DC input impedance of the stage as illustrated in Figure 7. The general expression for the differential gain is: +V IN+ AV(DIFF) =1+k2+•k2 VCM R = 13.7Ω LT6411 +– OUT+ VCM Scaling factor ‘k’ is the multiple between the two equal- k • R = 27.4Ω value series input resistors and the resistor connected OUT– between the two positive inputs. The correct value of R for IN– – VCM the external resistors can be computed from the desired VCM + R = 13.7Ω differential input impedance, Z , as a function of k and IN 6411 F07 the 370Ω internal gain setting resistors, as described in Figure 7. LT6411 Confi gured with a Differential Input Impedance the equation: of 50Ω, a Differential Gain of +2 and Unity Common Mode Gain Z •370Ω R= ( IN ) ( ) 370Ω k+2 –Z k+1 IN In Figure 7 k = 2 and R = 13.7Ω, setting the differential gain to +2 and the differential input impedance to ap- proximately 50Ω. +V IN+ LT6411 CLARGE OV + – 10k LTC2249 CLARGE IN– – VCM OV + 10k 2.2µF 6411 F05 –V Figure 5. Level Shifting the Output Common Mode Voltage of the LT6411 Using the V Pin of an LTC2249 CM 6411f 11

LT6411 APPLICATIONS INFORMATION Layout and Grounding supply. The smallest value capacitors should be placed closest to the LT6411 package. It is imperative that care is taken in PCB layout in order to utilize the very high speed and very low crosstalk of If the undriven input pins are not connected directly to a low the LT6411. Separate power and ground planes are highly impedance ground plane, they must be carefully bypassed recommended and trace lengths should be kept as short to maintain minimal impedance over frequency. Although as possible. If input or output traces must be run over a crosstalk will be very dependent on the board layout, a distance of several centimeters, they should use a controlled recommended starting point for bypass capacitors would impedance with matching series and shunt resistances to be 470pF as close as possible to each input pin with one maintain signal fi delity. 4700pF capacitor in parallel. Series termination resistors should be placed as close to To maintain the LT6411’s channel isolation, it is benefi cial the output pins as possible to minimize output capacitance. to shield parallel input and output traces using a ground See the Typical Performance Characteristics section for plane or power supply traces. Vias between topside a plot of frequency response with various output capaci- and backside metal may be required to maintain a low tors—only 12pF of parasitic output capacitance causes inductance ground near the part where numerous traces 6dB of peaking in the frequency response! converge. Low ESL/ESR bypass capacitors should be placed as close ESD Protection to the positive and negative supply pins as possible. One 4700pF ceramic capacitor is recommended for both V The LT6411 has reverse-biased ESD protection diodes CC and V . Additional 470pF ceramic capacitors with minimal on all pins. If any pins are forced a diode drop above the EE trace length on each supply pin will further improve AC positive supply or a diode drop below the negative sup- and transient response as well as channel isolation. For ply, large currents may fl ow through these diodes. If the high current drive and large-signal transient applications, current is kept below 10mA, no damage to the devices additional 1µF to 10µF tantalums should be added on each will occur. TYPICAL APPLICATIONS Single-Ended to Differential Converter 5V Because the gains of each channel of the LT6411 can be confi gured independently, the LT6411 can be used to VCC LT6411 provide a gain of +2 when amplifying differential signals IN1+ + OUT1 and when converting single-ended signals to differential. OUT+ 1µF – With both channels connected to a single-ended input, INPUT IN1– 370Ω 370Ω one channel confi gured with a gain of +1 and the other IN2– 370Ω 370Ω confi gured with a gain of –1, the output will be a differential 5V version of the input with twice the peak-to-peak (differential) 10k – amplitude. Figure 8 shows the proper connections and VCM IN2+ + OUT2 OUT– Figure 9 displays the resulting performance when driv- 0.1µF 10k VEE DGND ing an LTC2249. This confi guration can preserve signal EN amplitude when converting single ended video signals to 6411 F08 differential signals when driving double terminated cables. The 10k resistors in Figure 8 set the common mode volt- Figure 8. Single-Ended to Differential Converter age at the output. with Gain of +2 and Common Mode Control 6411f 12

LT6411 TYPICAL APPLICATIONS 0 5V ––2100 3T2O7N6E8 1 P AOTIN 2T9 .F5FMTHz, –7dBFS IN+ 13 + 6,9,10 50Ω TONE 2 AT 30.5MHz, –7dBFS S) ––4300 IM3 = –90dBc 1145 LATV6 4=1 21 50Ω 100Ω RECEIVER DE (dBF –––765000 IN– 16 – 15,2,3,7 6411 F10 U 11,12 MPLIT ––9800 –5V A–100 Figure 10. Twisted-Pair Driver –110 –120 of 100Ω, the cables can be terminated with a smaller –130 series resistance or a larger shunt resistance in order to –140 0 5 10 15 20 25 30 35 40 compensate for attenuation. A typical circuit for a twisted- FREQUENCY (MHz) 6411 F09 pair driver is shown in Figure 10. Figure 9. 2-Tone Response of the LT6411 Confi gured with Single-Ended Inputs Driving the LTC2249 at 29.5MHz, 30.5MHz Single Supply Differential ADC Driver The LT6411 is well suited for driving differential analog Twisted-Pair Line Driver to digital converters. The low output impedance of the The LT6411 is ideal when used for driving inexpensive LT6411 is capable of driving a variety of fi lters as well as unshielded twisted-pair wires as often found in telephone interfacing with the typically high impedance inputs of or communications infrastructure. The input can be com- ADCs. In addition, the LT6411’s excellent distortion allows posite video, or if three parts are used, RGB or similar and the part to perform with an SFDR below the limits of many can be either single ended or differential. The LT6411 has high speed ADCs. The DC1057 demo board, shown sche- excellent performance with all formats. matically in Figure 11 and physically in Figure 12, allows Double termination of the video cable will enhance fi delity implementation and testing of the LT6411 with a variety and isolate the LT6411 from capacitive loads. Although of different Linear Technology high speed ADCs. most twisted-pair cables have a characteristic impedance 6411f 13

LT6411 TYPICAL APPLICATIONS VCC CD1 0.1µF E1 VEE + C1 VCC OPT CD2 “B” CASE E2 4700pF GND JP1 4C70Dp3F 1R01Ω 1ENABLE 0603 VCC 2 VCC 3 CD4 L2 J1 R4 C2 R2 R3 0.1µF TBD AIN+ OPT OPT 0603 0603 C3 6 9 10 11 12 R8 R9 R35 RT0B660D3 54ETC1T-11TTR123 RV3C8CRO3P7T C8R7 C5 C9 RR510 111345 IIIVNNNC112C+––VCCLTVV6CE4CE11ENDOGUNTD1 8 11R1001%ΩΩ1 C6 LT01B60D31110R%0Ω1Ω2 C4C7 11R221.3.%116ΩΩ INAPTADUOICNT+S AJIN2– OPT T0B6R0D133 C11C12 R14 16 IVNE2E+VEE VEE VEEONUCT2 5 1% TLB13D% C11%0 AIN– 1 2 3 7 4 0603 R16 0Ω VEE R17 E7 OPTVCC R1487C0DpF5 CD6 CD7 C00.6D108µ3F R01Ω9 + CO“B3P”1T CASE VOE8EPET 4700pF1µF 6411 F11 GND Figure 11. DC1057 Demo Circuit Schematic Figure 12. Layout of DC1057 Demo Circuit 6411f 14

LT6411 SIMPLIFIED SCHEMATIC VCC VCC TO OTHER AMPLIFIER BIAS IN– 370Ω VCC 46k 1k 150Ω EN IN+ 370Ω OUT VEE DGND VEE VEE 6411 SS PACKAGE DESCRIPTION UD Package 16-Lead Plastic QFN (3mm × 3mm) (Reference LTC DWG # 05-08-1691) BOTTOM VIEW—EXPOSED PAD 3.00 ± 0.10 0.75 ± 0.05 R = 0.T1Y1P5 POIRN 01. 2N5O ×T C4H5° R C =H A0M.2F0E TRYP (4 SIDES) 15 16 0.70 ±0.05 PIN 1 0.40 ± 0.10 TOP MARK (NOTE 6) 1 3.50 ± 0.05 1.45 ± 0.05 1.45 ± 0.10 2 2.10 ± 0.05 (4 SIDES) (4-SIDES) PACKAGE OUTLINE (UD16) QFN 0904 0.25 ±0.05 0.200 REF 0.25 ± 0.05 0.50 BSC 0.00 – 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6411f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 15 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LT6411 TYPICAL APPLICATION In cases where lowering the noise fl oor is paramount, or additional fi ltering. Figure 15 shows the corresponding adding higher order lowpass or bandpass fi ltering can SFDR of –75.5dBc with a 30MHz tone. Figure 16 shows signifi cantly increase signal-to-noise ratio. In Figure 13, the 2-tone response of the LT6411 with 29.5MHz and the LT6411 is shown driving an LTC2249 with a 2nd order 30.5MHz inputs. Note that 0dBFS corresponds to a 2V P-P lowpass fi lter that has been carefully chosen to ensure differential signal. optimal intermodulation distortion. The response is 9 shown in Figure 14. The fi lter improves the SNR over the unfi ltered case by 6dB to 69.5dB. With the fi lter, the SNR 6 of the ADC and the LT6411 are comparable; better SNR 3 can be achieved by using either a higher resolution ADC B) 0 d N ( 5V 80.6Ω GAI –3 IN+ 55Ω 390nH 10Ω –6 1.9VDC + AIN– IN– –– LT6411 15pF LTC2249 –9 390nH 1.9VDC + 55Ω 80.6Ω 10Ω AIN+ –121 10 100 1000 6411 F13 FREQUENCY (MHz) 6411 F14 Figure 13. Optimized 30MHz LT6411 Differential ADC Driver Figure 14. Frequency Response of the LT6411 and Filter 0 0 –10 8192 POINT FFT –10 32768 POINT FFT –20 fIN = 30MHz, –1dBFS –20 TONE 1 AT 29.5MHz, –7dBFS SNR = 69.5dB TONE 2 AT 30.5MHz, –7dBFS –30 SFDR = 75.5dB –30 IM3 = –89.7dBc –40 –40 BFS) –50 BFS) –50 E (d –60 E (d –60 D –70 D –70 U U LIT –80 LIT –80 MP –90 MP –90 A–100 A–100 –110 –110 –120 –120 –130 –130 –140 –140 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 FREQUENCY (MHz) 6411 F15 FREQUENCY (MHz) 6411 F16 Figure 15. SNR and SFDR of the LT6411 and Filter Figure 16. 2-Tone Response of the LT6411 and Filter Driving the LTC2249 Driving the LTC2249 at 29.5MHz, 30.5MHz RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1993-2 800MHz Low Distortion, Low Noise ADC Driver, A = 2 3.8nV/√Hz Total Noise, Low Distortion to 100MHz V LT1993-4 900MHz Low Distortion, Low Noise ADC Driver, A = 4 2.4nV/√Hz Total Noise, Low Distortion to 100MHz V LT1993-10 700MHz Low Distortion, Low Noise ADC Driver, A = 10 1.9nV/√Hz Total Noise, Low Distortion to 100MHz V LT1994 Low Noise, Low Distortion Fully Differential Amplfi er 70MHz Gain Bandwidth Differential In and Out LT6402-6 300MHz Low Distortion, Low Noise ADC Driver, A = 2 3.8nV/√Hz Input Referred Noise, Low Distortion to 30MHz V LT6553 650MHz Gain of 2 Triple Video Amplifi er Triple Amplifi er with Fixed Gain LT6554 650MHz Gain of 1 Triple Video Amplifi er Triple Amplifi er with Fixed Gain 6411f 16 Linear Technology Corporation LT 0606 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006