LT4430 Secondary-Side Opto-Coupler Driver FeaTures DescripTion n 600mV Reference (1.25% Over Temperature) The LT®4430 drives the opto-coupler that crosses the gal- n Wide Input Supply Range: 3V to 20V vanic barrier in an isolated power supply. The IC contains n Overshoot Control Function Prevents Output a precision-trimmed reference, a high bandwidth error Overshoot on Start-Up and Short-Circuit Recovery amplifier, an inverting gain of 6 stage to drive the opto- n High Bandwidth Error Amplifier Permits Simple Loop coupler and unique overshoot control circuitry. Frequency Compensation The LT4430’s 600mV reference provides ±0.75% initial n Ground-Referenced Opto-Coupler Drive accuracy and ±1.25% tolerance over temperature. A high n 10mA Opto-Coupler Drive with Current Limiting bandwidth 9MHz error amplifier permits simple frequency n Low Profile (1mm) ThinSOTTM Package compensation and negligible phase shift at typical loop crossover frequencies. The opto-coupler driver provides applicaTions 10mA of output current and is short-circuit protected. A unique overshoot control function prevents output n 48V Input Isolated DC/DC Converters overshoot on start-up and short-circuit recovery with a n Isolated Telecommunication Power Systems single capacitor. n Distributed Power Step-Down Converters The LT4430 is available in the low profile 6-lead TSOT-23 n Offline Isolated Power Supplies package. n Industrial Control Systems n Automotive and Heavy Equipment L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical applicaTion Simplified Isolated Synchronous Forward Converter ISOLATION BARRIER Isolated Flyback Telecom Converter VIN • • VOUT Start-Up with Overshoot Control + + (See Schematic on Back Page) VIN 50V/DIV FG CG LT1952 • SYNC VCC LTC3900 • VOUT 5V/DIV VCC OVERSHOOT CONTROL VIN OPTO IMPLEMENTED LT4430 GND COMP t = 5ms/DIV 4430 TA01b OC FB 4430 TA01 4430fd 1 For more information www.linear.com/LT4430

LT4430 absoluTe MaxiMuM raTings pin conFiguraTion (Note 1) Supply Voltage TOP VIEW V ........................................................................20V IN VIN 1 6 OPTO FB Voltage ....................................................–0.3V to 6V GND 2 5 COMP OPTO Short-Circuit Duration ............................Indefinite OC 3 4 FB Operating Junction Temperature Range (Note 2) S6 PACKAGE E-, I-Grades .......................................–40°C to 125°C 6-LEAD PLASTIC TSOT-23 H-Grade .............................................–40°C to 150°C TJMAX = 125°C, θJA = 250°C/W MP-Grade ..........................................–55°C to 150°C Storage Temperature Range ..................–65°C to 150°C Lead Temperature (Soldering, 10 sec) ...................300°C orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT4430ES6#PBF LT4430ES6#TRPBF LTBFY 6-Lead Plastic TSOT-23 –40°C to 125°C LT4430IS6#PBF LT4430IS6#TRPBF LTBFY 6-Lead Plastic TSOT-23 –40°C to 125°C LT4430HS6#PBF LT4430HS6#TRPBF LTBFY 6-Lead Plastic TSOT-23 –40°C to 150°C LT4430MPS6#PBF LT4430MPS6#TRPBF LTBFY 6-Lead Plastic TSOT-23 –55°C to 150°C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT4430ES6 LT4430ES6#TR LTBFY 6-Lead Plastic TSOT-23 –40°C to 125°C LT4430IS6 LT4430IS6#TR LTBFY 6-Lead Plastic TSOT-23 –40°C to 125°C LT4430HS6 LT4430HS6#TR LTBFY 6-Lead Plastic TSOT-23 –40°C to 150°C LT4430MPS6 LT4430MPS6#TR LTBFY 6-Lead Plastic TSOT-23 –55°C to 150°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ elecTrical characTerisTics The ● denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at T = 25°C. V = 5V, FB = V , COMP = 1V, unless otherwise noted (Note 3). A IN FB SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Voltage Range ● 3 20 V IN I Supply Current 3V ≤ V ≤ 20V (E-, I-Grades) ● 1.9 3.9 mA IN IN 3V ≤ V ≤ 20V (H-, MP-Grades) 1.9 4.3 mA IN V Undervoltage Lockout Threshold OC Held Low for V < V (E-, I-Grades) ● 1.95 2.2 2.5 V UVLO IN UVLO OC Held Low for V < V (H-Grade) ● 1.9 2.2 2.5 V IN UVLO OC Held Low for V < V (MP-Grade) ● 1.9 2.2 2.55 V IN UVLO V Feedback Reference Voltage 0.5955 0.6 0.6045 V FB 3V ≤ V ≤ 20V ● 0.5925 0.6 0.6075 V IN V Line Regulation 3V ≤ V ≤ 20V 0.02 0.1 % FB IN I FB Input Bias Current FB = V –150 –75 nA FB FB 4430fd 2 For more information www.linear.com/LT4430

LT4430 elecTrical characTerisTics The ● denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at T = 25°C. V = 5V, FB = V , COMP = 1V, unless otherwise noted (Note 3). A IN FB SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I Overshoot Control Charging Current V = 0V (E-, I-Grades) ● –15 –8.5 –5 µA OC OC V = 0V (H-Grade) ● –17 –8.5 –5 µA OC V = 0V (MP-Grade) ● –17 –8.5 –4 µA OC OC Clamp Voltage 0.93 V OC Amplifier Offset Voltage FB = 0.3V 48 mV A Error Amplifier Open-Loop DC Gain V = 0.8V to 1V (E-, I-Grades) ● 60 80 dB VOL COMP V = 0.8V to 1V (H-, MP-Grades) ● 55 80 dB COMP Error Amplifier Unity-Gain Bandwidth No Load (Note 4) 9 MHz Error Amplifier Output Swing Low FB = 1V ● 0.1 0.35 0.55 V Error Amplifier Output Swing High FB = 0V (E-, I-Grades) ● 1.2 1.33 1.5 V FB = 0V (H-Grade) ● 1.2 1.33 1.55 V FB = 0V (MP-Grade) ● 1.15 1.33 1.55 V Error Amplifier Output Source Current FB = 0V, COMP = 1V (E-, I-Grades) ● –800 –450 –225 µA FB = 0V, COMP = 1V (H-Grade) ● –825 –450 –225 µA FB = 0V, COMP = 1V (MP-Grade) ● –825 –450 –200 µA Error Amplifier Output Sink Current FB = 1V, COMP = 1V 25 mA Opto Driver Inverting DC Gain –6.4 –6 –5.6 V/V Opto Driver –3dB Bandwidth No Load (Note 4) 600 kHz Opto Driver Output Swing Low FB = 0V, COMP = Open (E-, I-Grades) ● 0.5 0.85 V FB = 0V, COMP = Open (H-, MP-Grades) ● 0.5 0.9 V Opto Driver Output Swing High V = 3V, FB = 1V, COMP = Open, ● V – 1.25 V – 1.05 V IN IN IN I = 10mA (E-, I-, H-Grades) OPTO V = 3V, FB = 1V, COMP = Open, ● V – 1.3 V – 1.05 V IN IN IN I = 10mA (MP-Grade) OPTO Opto Driver Output Swing High V = 20V, FB = 1V, COMP = Open, ● 4.2 5.6 7.5 V IN I = 10mA OPTO I Opto Driver Output FB = 1V, COMP = Open, OPTO = 0V ● 10.5 22 45 mA SC Short-Circuit Current (Sourcing) (E-, I-, H-Grades) FB = 1V, COMP = Open, OPTO = 0V ● 9.5 22 45 mA (MP-Grade) Opto Driver Output Sink Current FB = 0V, OPTO = 1.5V (E-, I-, H-Grades) ● 150 350 650 µA FB = 0V, OPTO = 1.5V (MP-Grade) ● 135 350 650 µA Note 1: Stresses beyond those listed under Absolute Maximum Ratings temperature range and the LT4430MP is tested and guaranteed over may cause permanent damage to the device. Exposure to any Absolute the –55°C to 150°C operating junction temperature range. High junction Maximum Rating condition for extended periods may affect device temperatures degrade operating lifetimes; operating lifetime is derated reliability and lifetime. for junction temperatures greater than 125°C. Note that the maximum Note 2: The LT4430 is tested under pulsed load conditions such that T ≈ T . ambient temperature consistent with these specifications is determined by J A The LT4430E is guaranteed to meet specifications from 0°C to 125°C specific operating conditions in conjunction with board layout, the rated junction temperature. Specifications over the –40°C to 125°C operating package thermal impedance and other environmental factors. junction temperature range are assured by design, characterization and Note 3: All currents into device pins are positive. All currents out of device correlation with statistical process controls. The LT4430I is guaranteed pins are negative. All voltages are referenced to GND unless otherwise over the –40°C to 125°C operating junction temperature range, the specified. LT4430H is guaranteed over the –40°C to 150°C operating junction Note 4: This parameter is guaranteed by correlation and is not tested. 4430fd 3 For more information www.linear.com/LT4430

LT4430 Typical perForMance characTerisTics Undervoltage Lockout Threshold Feedback Reference Voltage Quiescent Current vs Temperature vs Temperature vs Temperature 4.0 3.0 0.606 0.605 3.5 0.604 mA) 2.5 0.603 NT ( 3.0 0.602 ENT CURRE 2.5 VIN = 20VVIN = 3V V (V)UVLO 2.0 V (V)FB000...665009109 SC 2.0 0.598 E UI 1.5 0.597 Q 1.5 0.596 0.595 1.0 1.0 0.594 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 4430 G01 4430 G02 4430 G03 FB Input Bias Current OC Charging Current FB Voltage Line Regulation vs Temperature vs Input Voltage 0.6010 50 15 TA = 25°C 25 A) 0 A) 13 0.6005 NT (n –25 NT (µ V) URRE –50 URRE 11 V (FB0.6000 AS C –75 NG C BI –100 GI 9 T R U A P –125 H 0.5995 FB IN –150 OC C 7 –175 0.5990 –200 5 0 2 4 6 8 10 12 14 16 18 20 –75 –50 –25 0 25 50 75 100 125 150 0 5 10 15 20 VIN (V) TEMPERATURE (°C) VIN (V) 4430 G04 4430 G05 4430 G06 OC Charging Current OC Clamp Voltage OC Amplifier Offset Voltage vs Temperature vs Temperature vs Temperature 15 1.5 100 VIN = 5V 90 A) 13 1.3 80 ARGING CURRENT (µ 119 CLAMP VOLTAGE (V) 10..19 V – V (mV)OCFB 67450000 OC CH 7 OC 0.7 2300 10 5 0.5 0 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 4430 G07 4430 G08 4430 G09 4430fd 4 For more information www.linear.com/LT4430

LT4430 Typical perForMance characTerisTics Error Amplifier Open Loop Gain Error Amplifier Output Swing Low Error Amplifier Output Swing High and Phase vs Frequency vs Temperature vs Temperature 80 180 0.5 1.5 V) V) 70 W ( H ( 60 135 G LO0.4 G HIG1.4 N N 50 PHASE WI WI S S GAIN (dB) 43210000 GAIN 9405PHASE (°) PLIFIER OUTPUT 00..32 PLIFIER OUTPUT 11..32 M M 0 0 A0.1 A1.1 R R –10 RO RO R R –20 –45 E 0 E1.0 1k 10k 100k 1M 10M 50M –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 FREQUENCY (Hz) TEMPERATURE (°C) TEMPERATURE (°C) 4430 G10 4430 G11 4430 G12 Error Amplifier Output Source Error Amplifier Output Sink Current vs Temperature Current vs Temperature T (µA) 1000 mA) 50 REN 900 NT ( RCE CUR 780000 K CURRE 40 U N ERROR AMPLIFIER OUTPUT SO 6123450000000000000–75 –50 –25 0 25 50 75 100 125 150 ERROR AMPLIFIER OUTPUT SI 3120000– 75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) 4430 G13 4430 G14 Opto Driver Inverting DC Gain Opto Driver Inverting Closed Loop vs Temperature Gain and Phase vs Frequency 6.4 40 180 V/V) 6.3 35 PHASE N ( 30 135 AI 6.2 C G 25 NVERTING D 66..01 GAIN (dB) 211050 GAIN 9405 PHASE (°) R I 5.9 E 5 V RI 5.8 D 0 0 O PT 5.7 –5 O 5.6 –10 –45 –75 –50 –25 0 25 50 75 100 125 150 1k 10k 100k 1M 10M TEMPERATURE (°C) FREQUENCY (Hz) 4430 G15 4430 G16 4430fd 5 For more information www.linear.com/LT4430

LT4430 Typical perForMance characTerisTics Opto Driver Output Swing Low Opto Driver Output Swing High Opto Driver Output Swing High vs Temperature vs Temperature vs Temperature 1.0 1.5 8.0 VIN = 3V VIN = 20V W (V) 0.9 1.4 IOPTO = 10mA H (V) 7.5 IOPTO = 10mA NG LO 00..78 11..23 NG HIG 7.0 UTPUT SWI 00..65 – V (V)OPTO11..10 UTPUT SWI 66..50 R O 0.4 V IN0.9 R O 5.5 VE 0.3 0.8 VE RI RI 5.0 O D 0.2 0.7 O D OPT 0.1 0.6 OPT 4.5 0 0.5 4.0 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 4430 G17 4430 G18 4430 G19 Opto Driver Output Sink Current Opto Driver Output Short-Circuit vs Temperature Current (Sourcing) vs Temperature A) 1000 mA) 40 T (µ 900 NT ( EN 800 RE R R 30 R U U 700 C SINK C 600 RCUIT UTPUT 450000 ORT-CI 20 O H OPTO DRIVER 1230000000 OPTO DRIVER S 100 –75 –50 –25 0 25 50 75 100 125 150 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) TEMPERATURE (°C) 4430 G20 4430 G21 4430fd 6 For more information www.linear.com/LT4430

LT4430 pin FuncTions V (Pin 1): This is the input supply that powers all internal FB (Pin 4): This is the inverting input of the error ampli- IN circuitry. The input supply range is 3V minimum to 20V fier. The noninverting input is tied to the internal 0.6V maximum and the typical input quiescent current is 1.9mA. reference. Input bias current for this pin is typically 75nA Connect a 1µF bypass capacitor directly from V to GND. flowing out of the pin. This pin normally ties to a resistor IN divider network to set output voltage. Tie the top of the GND (Pin 2): Analog Ground Pin. It is also the negative external resistor divider directly to the output voltage for sense terminal for the internal 0.6V reference. Connect the best regulation performance. external feedback divider network that terminates to ground directly to this pin for best regulation and performance. COMP (Pin 5): This is the output of the error amplifier. The error amplifier is a true voltage-mode error amplifier and OC (Pin 3): Overshoot Control Pin. A typical 8.5µA current frequency compensation is performed around the amplifier. source and a capacitor placed from this pin to GND controls Typical LT4430 compensation schemes use series R-C in output voltage overshoot on start-up and recovery from parallel with C networks from the COMP pin to the FB pin. short-circuit. The typical ramp time is (C • 0.6V)/8.5µA. OC COMP also ties to the overshoot control amplifier logic If V is below V (its undervoltage lockout threshold), IN UVLO that detects if the COMP pin is at its high clamp level. The the OC pin is actively held low. The OC pin also ties to the logic activates the overshoot control amplifier if COMP is overshoot control amplifier output. This amplifier monitors at its clamp level for longer than 1µs. the FB pin voltage and the error amplifier output. If FB is low due to a short-circuit fault condition, the COMP pin OPTO (Pin 6): This is the output of the amplifier that goes high. Logic detects the error amplifier COMP pin high drives the opto-coupler. The opto driver amplifier uses an state and activates the overshoot control amplifier. The inverting gain of six configuration to drive the opto-coupler amplifier responds by discharging the OC capacitor down referenced to ground. Driving the opto-coupler referenced to the FB voltage plus a built-in offset voltage of 48mV. If to GND accommodates low output voltages and eases the short-circuit condition persists, the amplifier maintains loop frequency compensation as the secondary feedback the voltage on OC. If the short-circuit condition goes away, path with a traditional “431” topology is eliminated. The the FB pin recovers under the control of the OC pin. opto driver amplifier sources a maximum of 10mA, sinks 350µA typically and is short-circuit protected. 4430fd 7 For more information www.linear.com/LT4430

LT4430 block DiagraM VIN + I1 COMP R3 OPTO OUT 12.5µA 15k DRIVER – 1.1V + BIAS AND ERROR R4 VIN STARTUP REFERENCE 0.6V Q2 Q3 AMP 90k GENERATOR – VIN I2 12.5µA Q7 GND UVLO Q1 + V2 VIN LOGIC – 0.6V AND R1 IOC DELAY 2k Q4 8.5µA FB R2 DFB 2k – OC Q5 Q6 AMP + S1 + V1 NORMALLY – 0.2V OPEN –+ VOS 48mV OC 4430 BD01 4430fd 8 For more information www.linear.com/LT4430

LT4430 applicaTions inForMaTion Block Diagram Operation preventing overshoot. A capacitor, connected from the OC pin to GND and charged by internal 8.5µA current source A precision voltage reference, a high-bandwidth error am- I , sets the ramp rate. On start-up, Q1 actively holds plifier, an inverting opto-coupler driver and an overshoot OC the OC capacitor low until V of the LT4430 reaches its control amplifier comprise the LT4430. Referring to the IN typical undervoltage lockout threshold of 2.2V. Q1 then block diagram, a start-up circuit establishes all internal turns off and the OC capacitor charges linearly. Q2 and Q3 current and voltage biasing for the IC. A precision-trimmed OR the OC pin voltage and the 600mV reference voltage bandgap generates the 600mV reference voltage and a at the noninverting terminal of the error amplifier. The OC 1.1V bias voltage for the opto-coupler driver. Room tem- pin voltage is the reference voltage for the error amplifier perature reference voltage accuracy is specified at ±0.75% until it increases above 600mV. If the feedback loop is in and operating temperature range tolerance is specified at control, the FB pin voltage follows and regulates to the OC ±1.25%. The 600mV reference ties to the noninverting pin voltage. As the OC pin voltage increases past 600mV, input of the error amplifier. the reference voltage takes control of the error amplifier The LT4430 error amplifier senses the output voltage and the FB pin regulates to 600mV. The OC pin voltage through an external resistor divider and regulates the FB increases until it is internally clamped by R2, Q6 and V1. pin to 600mV. The FB pin ties to the inverting input of The OC pin’s typical clamp voltage of 0.93V ensures that the error amplifier. The error amplifier’s open loop DC Q3 turns off. All of I1’s current flows in Q2, matching I2’s gain is 80dB and its unity-gain crossover frequency of current in Q4. 9MHz provides negligible phase shift at typical feedback In a short-circuit condition, the output voltage decreases loop crossover frequencies. The error amplifier is a true to something well below the regulated level. The error am- voltage-mode amplifier and frequency compensation con- plifier reacts by increasing the COMP pin voltage, thereby nects around the amplifier. Typical LT4430 compensation decreasing the drive to the opto-coupler. The decreased schemes use series R-C in parallel with C networks from opto-coupler bias signals the primary-side controller to the COMP pin to the FB pin. increase the amount of power it delivers in an attempt to The opto-coupler driver amplifies the voltage difference raise the output voltage back to its regulated value. As between the COMP pin and the 1.1V bias potential applied long as the fault persists, the output voltage remains low. to its noninverting terminal with an inverting gain of 6. This The error amplifier’s COMP pin voltage increases until it signal drives the opto-coupler referenced to GND. Driving reaches a clamp level set by Q7 and V2. Q7’s resultant the opto-coupler referenced to GND accommodates low collector current drives internal logic that closes normally output voltages and simplifies loop frequency compen- open switch S1. This action activates the overshoot control sation as the secondary feedback path with a traditional amplifier which employs a unity-gain follower configura- “431” topology is eliminated. A resistor in series with the tion. The overshoot control amplifier monitors the FB pin opto-coupler sets the opto-coupler’s DC bias current. The voltage and, on S1’s closing, pulls the OC pin voltage opto driver amplifier sources a guaranteed maximum of down to the FB pin voltage plus a built-in offset voltage 10mA, sinks 350µA typically and is short-circuit protected. of typically 48mV. The built-in offset voltage serves two The opto-coupler driver amplifier’s typical –3dB band- purposes. First, the offset voltage prevents the overshoot width is 600kHz. The opto-coupler’s output crosses the control amplifier from interfering with normal transient galvanic isolation barrier and closes the feedback loop to operating conditions. Second, the offset voltage biases the primary-side controller. the feedback loop so that if the short-circuit condition ends, the feedback loop immediately starts to increase The LT4430 incorporates a unique overshoot control the output voltage to its regulated value. function that allows the user to ramp the output voltage on start-up and recovery from short-circuit conditions, 4430fd 9 For more information www.linear.com/LT4430

LT4430 applicaTions inForMaTion If the fault condition ceases, the output voltage increases. Figures 1a to 1e illustrate bias supply circuits for the In response, the error amplifier COMP pin’s voltage flyback converter. Figure 1a shows the typical flyback decreases. This action opens switch S1, deactivates the output connection. Figures 1b and 1c exhibit equivalent overshoot control amplifier and allows the OC pin capacitor circuit performance but rotate the rectifier connection to to charge. The FB pin voltage increases quickly until the the ground-referred side. This connection permits the user FB pin voltage exceeds the OC pin voltage. The feedback to take advantage of the transformer secondary’s forward loop increases the drive to the opto-coupler until the FB behavior when the primary-side switch is on. pin follows and regulates to the OC pin voltage. Again, as Figures 1d to 1e illustrate the bias generator circuit. the OC pin voltage increases past 600mV, the reference V • N volts appear across the secondary winding when IN voltage takes control of the error amplifier and the FB pin the primary-side switch is on. D2 forward biases and C1 regulates to 600mV. charges. During this time, the secondary-voltage is in series with V and C1 ultimately charges to (V • N + Generating a V Bias Supply OUT IN IN V – V ). V is the forward voltage of D2. When V OUT F F OUT Biasing an LT4430 is crucial to proper operation. If the is zero at start-up, V • N volts exists to charge C1. C1 is IN overshoot control (OC) function is not being used and the generally much smaller in value than C and the bias OUT output voltage is greater than 3.3V, the IC may be biased supply starts up ahead of V . R1 in Figures 1d and OUT from VOUT. In these cases, it is the user’s responsibility 1e limits peak charging currents, lowering D2’s current to verify large-signal start-up and fault recovery behavior. rating. R1 also filters C1 from peak-charging to the volt- age spikes induced by the secondary winding’s leakage If the overshoot control function is being used or the inductance. Between 1Ω to 10Ω is generally sufficient. R1 output voltage is below the LT4430’s minimum operat- is usually necessary if C1 is a low ESR ceramic capacitor ing voltage of 3V, employing an alternate bias method is or if the transformer has high leakage inductance. It may necessary. The LT4430’s undervoltage lockout (UVLO) be possible to eliminate R1 if C1 is a low cost, high ESR, circuitry, controlled by V , resets and holds the OC pin IN surface-mount tantalum. capacitor low for V less than 2.2V. When V increases IN IN above 2.2V, the circuit releases the OC pin capacitor. The V variation changes the bias supply in Figure 1d. Depend- IN LT4430’s supply voltage must come up faster than the ing on V , the transformer turns ratio N and V range, OUT IN output voltage to assert loop control and limit output volt- the bias supply may exceed the LT4430’s 20V V absolute IN age overshoot. In most cases, a few simple components maximum rating. If this occurs, two solutions exist. One accomplish this task. Adding a few biasing components is to tap the secondary-side inductor to create a lower to control overshoot is advantageous. Let’s examine bias voltage from which to rectify as illustrated in Figure 2a. circuits for different topologies. The bias voltage decreases to (V • N1/N + V – V ). IN OUT F This solution relies on secondary-side pins being available for the tap point. 4430fd 10 For more information www.linear.com/LT4430

LT4430 applicaTions inForMaTion T1 D1 T1 VIN • VOUT VIN • VOUT COUT COUT D1 • • 1:N 4430 F01a 1:N 4430 F01b Figure 1a. Typical Flyback Converter Connection Figure 1b. Equivalent Flyback Converter Connection Tx1 T1 VIN • VOUT VIN • VOUT COUT COUT • Q1 • D1 1:N 1:N D2 R1* SYNC LT4430 4430 F01c VBIAS C1 *OPTIONAL SEE TEXT 4430 F01d Figure 1c. Synchronous Flyback Converter Connection Figure 1d. Flyback Converter with Bias Generator T1 VIN • VOUT COUT • Q1 1:N SYNC D2 R1* LT4430 VBIAS C1 *OPTIONAL SEE TEXT 4430 F01e Figure 1e. Synchronous Flyback with Bias Generator 4430fd 11 For more information www.linear.com/LT4430

LT4430 applicaTions inForMaTion The second solution is to make a preregulator as shown MOSFETs turn on and turnoff. The gate driver circuitry in Figure 2b. In this example, the bias supply equals (V requires supply current in the range of 10mA to 100mA Z1 – V ). Select R2 to bias Zener diode Z1 and to supply depending on the gate driver supply voltage, MOSFET size BE base current to QBS. Resistor R3 (on the order of a few and switching frequency. The preregulator bias supply is hundred ohms), in series with Q5’s base, suppresses ideal for powering both the LT4430 and the gate driver possible high frequency oscillations depending on QBS’s circuitry, especially since the gate drivers typically use a selection. The preregulator circuit has additional value for supply voltage between 5V to 12V. The preregulator circuit fully synchronous converters. Fully synchronous convert- finds wide use in fully synchronous forward converters, ers require gate drivers to control the secondary-side push-pull converters and full-bridge converters. T1 VOUT N1 VIN •• • COUT N2 D1 • 1:N D2 R1* N = N1 + N2 LT4430 VBIAS C1 *OPTIONAL SEE TEXT 4430 F02a Figure 2a. Flyback Converter with Tapped Secondary Bias T1 VIN • VOUT COUT D1 • 1:N D2 R1* R2 R3* QBS C1 LT4430 VBIAS Z1 C2 *OPTIONAL SEE TEXT 4430 F02b Figure 2b. Flyback Converter with Preregulator Bias 4430fd 12 For more information www.linear.com/LT4430

LT4430 applicaTions inForMaTion Generate a bias supply for a forward converter using similar V . However, in the forward converter, L1’s presence OUT techniques to that of the flyback converter. Figure 3a to 3c decouples the bias supply from V . In Figure 3a, the OUT detail the three common bias circuits for the synchronous bias supply equals (V • N – V ). In Figure 3b, the bias IN F single-switch forward converter. In the flyback converter supply equals (V • N1/N – V ). In Figure 3c, the bias IN F of Figure 1d, the bias supply is proportional to V and supply equals (V – V ). IN Z1 F D1 R1* LT4430 VBIAS C1 T1 L1 VIN • • VOUT COUT 1:N Q1 FG Q2 CG *OPTIONAL SEE TEXT 4430 F03a Figure 3a. Typical Single-Switch Synchronous Forward Converter with Bias Generator D1 R1* D1 R1* LT4430 VBIAS C1 R2 R3* T1 L1 QBS • VOUT C1 LT4430 N2 COUT VBIAS Z1 C2 VIN •• T1 L1 • VIN • • VOUT N1 COUT 1:N Q1 FG Q2 CG 1:N Q1 FG Q2 CG N = N1 + N2 *OPTIONAL SEE TEXT *OPTIONAL SEE TEXT 4430 F03b 4430 F03c Figure 3b. Single-Switch Synchronous Forward Converter Figure 3c. Single-Switch Synchronous Forward Converter with Tapped Secondary Bias Generator with Preregulator Bias Generator 4430fd 13 For more information www.linear.com/LT4430

LT4430 applicaTions inForMaTion Figures 4a to 4d demonstrate bias supply circuits for the In general, one of the simple, low-cost biasing schemes fully-synchronous push-pull topology. Biasing for full- suffices for LT4430 applications. However, design con- bridge schemes is identical to the push-pull circuits with straints such as a very wide input voltage range may force the obvious difference in the primary-side drive. In Figure employment of other biasing circuits. Other methods of 4a, the bias supply equals (V • N – V ). In Figure 4b and generating the bias supply may include an additional IN F 4d, the bias supply equals (2 • V • N – V ). In Figure 4c transformer or output inductor winding, low-cost linear IN F and 4e, the bias supply equals (V – V ). regulators, discrete or monolithic charge pumps and buck/ Z1 F boost regulators. However, if the bias supply gets this complicated, a quick chat with your local LTC applications engineer may result in a simpler solution. T1 Q2 D1 R1* LT4430 • VBIAS C1 • ME L1 VIN VOUT • COUT • Q1 1:N *OPTIONAL SEE TEXT MF 4430 F04a Figure 4a. Typical Synchronous Push-Pull Converter with Bias Generator D1 R1* LT4430 T1 Q2 VBIAS C1 • • ME L1 VIN VOUT • COUT • Q1 1:N *OPTIONAL SEE TEXT MF 4430 F04b Figure 4b. Typical Synchronous Push-Pull Converter with 2x Bias Generator 4430fd 14 For more information www.linear.com/LT4430

LT4430 applicaTions inForMaTion D1 R1* D1 R1* LT4430 VBIAS R2 T1 L2 C1 R3* QBS • C1 LT4430 Q2 ME VBIAS • Z1 C2 VIN VOUT T1 • COUT Q2 • L1 • • ME 1:N L1 Q1 MF *OPTIONAL SEE TEXT VIN VOUT 4430 F04d • COUT Figure 4d. Typical Synchronous • Q1 Push-Pull Current-Doubler Converter with Bias Generator 1:N *OPTIONAL SEE TEXT MF 4430 F04c Figure 4c. Typical Synchronous Push-Pull Converter with Preregulator Bias D1 R1* R2 R3* QBS C1 LT4430 VBIAS Z1 C2 T1 L2 • Q2 ME • VIN VOUT • COUT L1 • 1:N Q1 MF *OPTIONAL SEE TEXT 4430 F04e Figure 4e. Typical Synchronous Push-Pull Current-Doubler Converter with Preregulator Bias 4430fd 15 For more information www.linear.com/LT4430

LT4430 applicaTions inForMaTion Setting Output Voltage circuitry resides on the primary-side. Coupling this signal requires an element that withstands the isolation potentials Figure 5 shows how to program the power supply output and still transfers the loop error signal. voltage with a resistor divider feedback network. Connect the top of R1 to V , the tap point of R1/R2 to FB and Opto-couplers remain in prevalent use because of their OUT the bottom of R2 directly to GND of the LT4430. The FB ability to couple DC signals. Opto-couplers typically con- pin regulates to 600mV and has a typical input pin bias sist of an input infrared light emitting diode (LED) and an current of 75nA flowing out of the pin. output phototransistor separated by an insulating gap. Most opto-coupler data sheets loosely specify the gain, The output voltage is set by the formula: or current transfer ratio (CTR), between the input diode V = 0.6V • (1 + R1/R2) – (75nA) • R1 OUT and the output transistor. CTR is a strong function of the input diode current, temperature and time (aging). Ag- VOUT ing degrades the LED’s brightness and accelerates with higher operating current. CTR variation directly affects the 75nA R1 overall system loop gain and the design must account for FB total variation. To make an effective optical detector, the R2 output transistor design maximizes the base area to col- 4430 F05 lect light energy. This constraint yields a transistor with a Figure 5. Setting Output Voltage large collector-to-base capacitance. This capacitance can influence the circuit’s performance based on the output Opto-Coupler Feedback and Frequency Compensation transistor’s hookup. An isolated power supply with good line and load regula- The two most common topologies for the output tran- tion generally employs the following strategy. Sense and sistor of the opto-coupler are the common-emitter and compare the output voltage with an accurate reference common-collector configurations. Figure 6a illustrates potential. Amplify and feed back the error signal to the the common-emitter design with the output transistor’s supply’s control circuitry to correct the sensed error. Have collector connected to the output of the primary-side the error signal cross the isolation barrier if the control controller’s error amplifier. ISOLATION BARRIER LT4430 VOUT + 1.1V VCC OPTO PRIMARY-SIDE OPTO R4 + 0.6V ERROR AMP DRIVER 15k – ERROR R1 C1 RC RK R5 AMP FB VREF + VC CK 90k COMP – FB R2 – CC OPTO C3 R3 C2 4430 F06a Figure 6a. Frequency Compensation with Opto-Coupler Common-Emitter Configuration 4430fd 16 For more information www.linear.com/LT4430

LT4430 applicaTions inForMaTion In this example, the error amplifier is typically a trans- where: conductance amplifier with high output impedance and A = LT4430 open loop DC Gain R dominates the impedance at the V node. Frequency C C compensation for this feedback loop is directly affected by RD = Opto-coupler diode equivalent small-signal the output transistor’s collector-to-base capacitance as it resistance introduces a pole into the feedback loop. This pole varies CTR = Opto-coupler AC current transfer ratio considerably with the transistor’s operating conditions. In C = Opto-coupler nonlinear collector-to-base many cases, this pole limits the achievable loop bandwidth. CB capacitor Cascoding the output transistor significantly reduces the effects of this capacitance and increases achievable loop C = Opto-coupler nonlinear base-to-emitter BE bandwidth. However, not all designs have the voltage capacitor headroom required for the cascode connection or can r = Opto-coupler small-signal base-to-emitter tolerate the additional circuit complexity. The open loop π resistor transfer function from the output voltage to the primary- side error amplifier’s output is: Figure 6a and its transfer function illustrate most of the possible poles and zeroes that can be set and are shown ⎛ R2 ⎞ −A•⎜ ⎟•(1+s•R1•C1)•(1+s•R3•C3) for the sake of completeness. In a practical application, the V ⎝R1+R2⎠ C = • transfer function simplifies considerably because not all V ⎛ (C2•C3)⎞ OUT [s•A•R1•(C2+C3)]•⎜1+s•R3• ⎟ the poles and zeroes are used. Also, different combinations ⎝ (C2+C3)⎠ of poles and zeroes can result in the same small signal gain-phase characteristics but demonstrate dramatically (1+s•R •C ) CTR•R 6• K K • C • different large-signal behavior. ⎛ (R •R ) ⎞ (R +R ) ⎜1+s• K D •C ⎟ K D K The common-collector configuration eliminates the miller ⎝ (R +R ) ⎠ K D effect of the output transistor’s collector-to-base capaci- 1 • tance and generally increases achievable loop bandwidth. ⎛ ⎡(CTR•R ) ⎤⎞ Figure 6b illustrates the common-collector design with the ⎝⎜1+s•rπ •⎣⎢(RK+RDC) •CCB+CBE⎦⎥⎠⎟ output transistor’s emitter connected to the inverting input of the primary-side controller’s error amplifier. 1 (1+s•R •C ) C C ISOLATION BARRIER LT4430 VOUT PRIMARY-SIDE + 1.1V ERROR AMP VCC OPTO OPTO R4 + 0.6V DRIVER 15k VC + VREF RK CK 9R05k – COMP ERAMROPR– FB R1 C1 FB – OPTO R2 C3 R3 RC RE C2 CC 4430 F06b Figure 6b. Frequency Compensation with Opto-Coupler Common-Collector Configuration 4430fd 17 For more information www.linear.com/LT4430

LT4430 applicaTions inForMaTion In this example, the error amplifier is typically a voltage This frequency compensation discussion only addresses error amplifier configured as a transimpedance amplifier. the transfer function from the output back to the control The opto-coupler transistor’s emitter provides feedback node on the primary-side. Compensation of the entire information directly to the FB pin and the resistor R from feedback loop must combine this transfer function with E FB to GND sets the DC bias condition for the opto-coupler. the transfer function of the power processing circuitry, The open loop transfer function from the output voltage commonly referred to as the modulator. In an isolated to the primary-side error amplifier’s output is: power supply, the modulator’s transfer function depends on topology (flyback, forward, push-pull, bridge), current ⎛ R2 ⎞ −A•⎜ ⎟•(1+s•R1•C1)•(1+s•R3•C3) or voltage mode control, operation in discontinuous or V ⎝R1+R2⎠ C = • continuous mode, input/output voltage, transformer turns VOUT [s•A•R1•(C2+C3)]•⎛⎜1+s•R3• (C2•C3)⎞⎟ ratio and output load current. It is beyond this data sheet’s ⎝ (C2+C3)⎠ scope to detail the transfer functions for all of the vari- ous combinations. However, the power supply designer (1+s•R •C ) CTR•R 6• K K • C • must fully characterize and understand the modulator’s ⎛ (R •R ) ⎞ (R +R ) ⎜1+s• K D •C ⎟ K D transfer function to successfully frequency compensate K ⎝ (RK+RD) ⎠ the feedback loop for all operating conditions. 1 1 • Opto-Couplers (1+s•r •C ) (1+s•R •C ) π BE C C Opto-couplers are available in a wide variety of package Figure 6b and its transfer function illustrate most of the styles and performance criteria including isolation rating, possible poles and zeroes that can be set and are shown CTR, output transistor breakdown voltage, output transistor for the sake of completeness. In a practical application, current capability, and response time. Table 1 lists several the transfer function simplifies considerably because not manufacturers of opto-coupler devices, although this is all the poles and zeroes are used. by no means a complete list. In both configurations, the terms R , CTR, r , C and C . Table 1. Opto-Coupler Vendors D π CB BE vary from part to part and also change with bias current. VENDOR PHONE URL For most opto-couplers, R is 50Ω at a DC bias of 1mA, Agilent Technologies 800-235-0312 www.agilent.com D and 25Ω at a DC bias of 2mA. CTR is the small signal AC Fairchild Semiconductor 207-775-8100 www.fairchildsemi.com current transfer ratio. As an example, the Fairchild MOC207 Isocom 214-495-0755 www.isocom.com opto-coupler has an AC CTR around 1, even though the Kodenshi Korea Corp. 82-63-839-2111 www.kodenshi.co.kr DC CTR is much lower when biased at 1mA or 2mA. Most NEC 81-44-435-1588 www.ncsd.necel.com opto-coupler data sheets do not specify the terms C , CB Sharp Microelectronics 877-343-2181 www.sharpsma.com C and r and values must be obtained from empirical BE π Toshiba 949-455-2000 www.toshiba.com measurements. Vishay 402-563-6866 www.vishay.com 4430fd 18 For more information www.linear.com/LT4430

LT4430 applicaTions inForMaTion Setting Overshoot Control Time output load characteristics heavily influence power supply behavior as it attempts to bring the output voltage into Figure 7 shows how to calculate the overshoot time by regulation. Frequency compensation values that provide connecting a capacitor from the OC pin to GND. stable response under normal operating conditions can The overshoot control time, tOC, is set by the formula: allow severe output voltage overshoot to occur during start-up and short-circuit recovery conditions. Large t = (C • 0.6V)/8.5µA OC OC overshoot often results in damage or destruction to the The OC pin requires a minimum capacitor of 100pF due to load circuitry being powered, not a desirable trait. stability requirements with the overshoot control amplifier. The LT4430’s overshoot control circuitry plus one external This yields a minimum time of 7µs which is generally on capacitor (C ) provide independent control of start-up the order of a few cycles of the switching regulator. Us- OC and short-circuit recovery response without compro- ing the minimum capacitor value results in no influence mising small-signal frequency compensation. Choosing on start-up characteristics. Larger OC capacitor values the optimum C value is a straightforward laboratory increase the overshoot control time and only increase the OC procedure. The following description and set of pictures amplifier stability. Do not modulate the overshoot control explain this procedure. time by externally increasing the OC charging current or by externally driving the OC pin. Before choosing a value for the OC pin capacitor, complete the remainder of the power supply design. This process VIN includes evaluating the chosen V bias generator topology IN IOC (please consult prior applications information section) 8.5µA and optimizing frequency compensation under all normal OC COC operating conditions. During this design phase, set COC to its minimum value of 100pF. This ensures negligible 4430 F07 interaction from the overshoot control circuitry. Once these steps are complete, construct a test setup that monitors Figure 7. Setting Overshoot Control Time start-up and short-circuit recovery waveforms. Perform this testing with the output lightly loaded. Light load, following Choosing the Overshoot Control (OC) Capacitor Value full slew operation, is the worst-case as the feedback loop As discussed in the frequency compensation section, transitions from full to minimal power delivery. the designer enjoys considerable freedom in setting the As an example, refer to the schematic on the last page feedback loop’s pole and zero locations for stability. Dif- illustrating the 5V, 2A isolated flyback converter. All of ferent pole and zero combinations can produce the same the following photos are taken with V = 48V and I = IN LD gain-phase characteristics, but result in noticeably different 20mA. Figure 8a demonstrates the power supply start-up large-signal responses. Choosing frequency compensation and short-circuit recovery behavior with no overshoot values that optimize both small-signal and large-signal control compensation (C = 100pF minimum). The 5V OC responses is difficult. Compromise values often result. output overshoots by several volts on both start-up and Power supply start-up and short-circuit recovery are the short-circuit recovery due to the conservative nature of worst-case large signal conditions. Input voltage and the small-signal frequency compensation values. 4430fd 19 For more information www.linear.com/LT4430

LT4430 applicaTions inForMaTion Next, increase C ’s value. Either use a capacitor substitu- short-circuit is therefore identical to start-up. In the flyback OC tion box or solder each new value into the circuit. Monitor example discussed, the primary-side control circuitry is the start-up and short-circuit recovery waveforms. Note always active. Switching never stops in short-circuit. The any changes. Figures 8b to 8e illustrate what happens as LT4430 error amplifier COMP pin changes from its low C increases. In general, overshoot decreases as C clamp level to its higher regulating value during start-up OC OC increases. and changes from its high clamp level to its lower regulat- ing point during short-circuit recovery. This large-signal C = 0.0168µF in Figure 8b begins to affect loop dynam- OC behavior explains the observed difference in the start-up ics, but start-up still exhibits about 1.5V of overshoot. versus short-circuit recovery waveforms. Short-circuit recovery is considerably more damped. C OC = 0.022µF in Figure 8c damps start-up overshoot to 0.5V A final point of discussion involves the chosen COC value. and short-circuit recovery remains similar to that of Figure LTC recommends that the designer use a value that con- 8b. C = 0.033µF in Figure 8d provides under 100mV trols overshoot to the acceptable level, but is not made OC of overshoot and short-circuit recovery is slightly more overly large. The temptation arises to use the overshoot damped. C = 0.047µF in Figure 8e achieves zero over- control function as a power supply “soft-start” feature. OC shoot at the expense of additional damping and delay time Larger values of COC, above what is required to control in short-circuit recovery. In this example, C = 0.033µF overshoot, do result in smaller dV/dt rates and longer OC start-up times. However, large values of C may stall the provides the best value for both start-up and short-circuit OC feedback loop during start-up or short-circuit recovery, recovery. Figure 8f provides an expanded scale of the resulting in an extended period of time that the output waveforms. After a C value is selected, check start-up OC voltage “flatspots”. This voltage shelf may occur at an and short-circuit recovery over the V supply range and IN intermediate value of output voltage, promoting anomalous with higher output load conditions. Modify the value as behavior with the powered load circuitry. If this situation necessary. occurs with the desired C value, solutions may require OC Start-up and short-circuit recovery waveforms for various circuit modifications. In particular, bias supply holdup designs will differ from the photos shown in this example. times are a prime point of concern as switching stops Factors affecting these waveforms include the isolated during these output voltage flatspots. As a reminder, topology chosen, the primary-side and secondary-side the purpose of this LT4430 circuitry is to control and bias circuitry and input/output conditions. For instance, prevent excessive output voltage overshoot that would in many isolated power supplies, a winding on the main otherwise induce damage or destruction, not to control power transformer bootstraps the supply voltage for the power supply timing, sequencing, etc. It is ultimately the primary-side control circuitry. Under short-circuit condi- user’s responsibility to define the acceptance criteria for tions, the primary-side control circuitry’s supply voltage any waveforms generated by the power supply relative to collapses, generating a restart cycle. Recovery from overall system requirements. 4430fd 20 For more information www.linear.com/LT4430

LT4430 applicaTions inForMaTion START-UP START-UP 5VV/DOUIVT VOUT 5V/DIV SHORT-CIRCUIT RECOVERY SHORT-CIRCUIT VOUT RECOVERY 5V/DIV VOUT 5V/DIV t = 5ms/DIV 4430 F08a t = 5ms/DIV 4430 F08b COC = 100pF COC = 0.0168µF = 0.01µF + 6.8nF Figure 8a. Start-Up and Short-Circuit Recovery Waveforms Figure 8b. Start-Up and Short-Circuit Recovery Waveforms START-UP START-UP VOUT VOUT 5V/DIV 5V/DIV SHORT-CIRCUIT SHORT-CIRCUIT RECOVERY RECOVERY VOUT VOUT 5V/DIV 5V/DIV t = 5ms/DIV 4430 F08c t = 5ms/DIV 4430 F08d COC = 0.022µF COC = 0.033µF Figure 8c. Start-Up and Short-Circuit Recovery Waveforms Figure 8d. Start-Up and Short-Circuit Recovery Waveforms START-UP START-UP VOUT VOUT 5V/DIV 5V/DIV SHORT-CIRCUIT SHORT-CIRCUIT RECOVERY RECOVERY VOUT 5VV/DOUIVT 5V/DIV t = 5ms/DIV 4430 F08e t = 5ms/DIV 4430 F08f COC = 0.047µF COC = 0.033µF Figure 8e. Start-Up and Short-Circuit Recovery Waveforms Figure 8f. Zoom In of Waveforms with Selected C = 0.033µF OC 4430fd 21 For more information www.linear.com/LT4430

LT4430 Typical applicaTions V 268A R24261k1% R256.04k1% Q3BCX55 VBSC101µF COUT22µF50VX7R R2015k C121nF C1610pF C15R232.2nF8.2k 4430 TA03a S B H V V L10µ R161k D78.2 1 6 5 4 R1710k R1810k R1910k OPTO 30 COMP FB 4 D6B0540W C910nF100V 5H20100 3 1 2 7 VIN1LT4 GND2 OC3 QP erter C86.8nFR15100V2.2Ω D5B0540W FGCG5+VCSCC4 LTC3900 ––GNDCSCS6 SYNCTIMER8 VBS C131µF C1433nF Base Station Conv ISOLATIONBARRIER PA0741T1•2 •47, 10 •8, 112 4Q4PH20100 C41nF VBS C111µF T2 • R21330Ω• VU1R22330Ω NECPS2701 C172200pF250V nt 6Ω 95% Efficie D3R2BAS51610 Q2PH21NQ15x2 0 R140.008Ω 020.103 200W, 26V, R247kQ1BCX55C21µFVU1 D218V 14 VU115 D4C3BAT7682.2µF 13R1239k 12 11R13680Ω C710220pF16 C = TDKOUTD1, D2, D7 = PHILIPSQ1, Q2 = PHILIPSL1 = PULSE ENGINEERING PB2T1 = PULSE ENGINEERINGT2 = COILCRAFT Q4470-B R182kC12.2µF100VD112V SSD_VSECOUT RVOSCIN BLANKGND SS_MAXDCPGND LT1952 DELAYVREF COMPOC FBISENSE SYNCSOUT 7 3 9 5 6 1 2 4 R3370k R933k NC R1022k R111.2k V N 6V TO 72VI R413.2k R633k R833k 3 F R5114k C50.47µ R733k C60.1µF 4430fd 22 For more information www.linear.com/LT4430

LT4430 Typical applicaTions 1k D710V olated 1/4 Brick (2.3" 1.45")× VF1nF100V101W T1VEVEHMIN):6T:2T:2TL6•1.25µH119•V•OUTVF7D1•1k1/4WC1, C2+•47µF16V12V/20A1µFx2100V1µFSi7370DPSi7370DPx2x2 –VOUTVVFE6.19k6.19k1k1/4W1/4W1/4W1%1%• V1k1kOUT866Ω866Ω1%1%100Ω11121415652316+–+–42.2kCSFMFMF2VCSECSECSFMEME2CC 19LTC3901EGNSYNCPVCCMMBT3904GNDPGNDGND2PGND2TIMER100Ω1µF84101371µF220pF470pF V–VOUTOUT4.7nF470pF1µF, 100V TDK C3225X7R2A105MC1, C2: SANYO 16TQC47M1C3: AVX TPSE686M020R015011.5k15nFC4: MURATA GHM3045X7R222K-GC1%1.5kD1: DIODES INC. ES1BD3-D6: BAS211D7: MMBZ5240B45VINFBCOMPL4: COILCRAFT DO1608C-105L5: COILCRAFT DO1813P-561HC2604ΩLT4430ES6L6: PULSE PA1294.132 OR 31%6PANASONIC ETQP1H1R0BFAOPTOOCGNDR1, R2: IRC LRC2512-R03G22nFT1: PULSE PA0805.0042T2: PULSE PA0785–VOUT 4430 TA03b V to 56V to 12V/20A IsININ D3 4T:6T(65µ 26 4.7Ω5Si7852DP4 30.1µF 5 Si7852DPB L4D512V1mH 1+C3D668µF20V6 T2 1(1.5mH):0.514•• 0.1µF22Ω85 ISNS31.1k SDRA 10CSMOC207 116COMP 750Ω5 C4243k22nF2.2nF330pF250V0.47µF LTC3723-1 240W 42 VIN 12V 1 VCC3ABOOSTINPLTC4440ES6Si7852DPTGTSGND 42 Si7852DP 1.5kISNSR1R20.03Ω0.03Ω1.5W1.5W B 24 RVBSDRB LTC3723EGN-1 SPRGSSRLEBDPRGVREF 16121491 33k150k270pF 10k68nF D CT 8 L50.56µH 1µF1µF12VD4100V100Vx31 VCC63BBOOSTINPLTC4440ES64.7Ω5TGTSGND 420.1µF 42VAIN 48VIN 56VIN 161820101214LOAD CURRENT (A) V12VIN A200Ω1/4W6 30kDRVA1/4W5VCC464k15UVLOGNDFB 1371.5nF 1µF 66.5k 8 V +VIN 42V TO 56–VIN 97 96 )%( YC95NEICIFFE 94 936 4430fd 23 For more information www.linear.com/LT4430

LT4430 package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. S6 Package 6-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1636) 2.90 BSC 0.62 0.95 (NOTE 4) MAX REF 1.22 REF 1.50 – 1.75 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT 0.30 – 0.45 0.95 BSC PER IPC CALCULATOR 6 PLCS (NOTE 3) 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 1.90 BSC 0.09 – 0.20 (NOTE 3) S6 TSOT-23 0302 NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 4430fd 24 For more information www.linear.com/LT4430

LT4430 revision hisTory (Revision history begins at Rev B) REV DATE DESCRIPTION PAGE NUMBER B 5/11 H-Grade and MP-Grade parts added. Reflected throughout the data sheet. 1-26 C 10/13 Corrected Q2 in Block Diagram from NPN to PNP. 8 Changed R24 from 26.1k to 261k. 22 D 7/15 Corrected typos in formulas. 17, 18 4430fd Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 25 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnecFtioorn mof oitrse c iirncfuoitrsm asa dtieosncr wibewdw h.elrineiena wr.icll onmot /inLTfr4in4g3e 0on existing patent rights.

LT4430 Typical applicaTion 5V, 2A Isolated Flyback Telecom Converter Start-Up Waveforms with Overshoot Control Implemented ISOLATION BARRIER 36V TO 72V VIN R1 R2 C11µ01F0V 2DP2D01kZ-9.1B QM2M8B.T5AV42 100k 2• CT1TX9-, 0120-15242 CO1 CO2 CO3 52VA –VIN 9.1V DBA2S516 4 •11, 12 UPDS4840 160.30VµF 160.30VµF 160.30VµF Q1 ITH/SHDN ITH/RUN NGATE FDC2512 R4 D5 220Ω MBR0530 R7 GND LTC3803 VCC 4R.73k C1530pF 111%k 200V FB SENSE C2 RCS 1µF 0.068Ω 8.5V 10V C7 BADS3516 R6.58k R68100Ω C0.8047µF 1Cµ5F VIN LT4430 OPTO R1k9 0.1µF C6 GND COMP 0.033µF MOC207 OC FB R8 1500Ω C1 = TDK, X7R R6 1% CDO1,1 D, C2,0 D2,3 C =0 3P H=I LTIDPKS, X5R 470kC4 4430 TA02 D4 = MICROSEMI 2200pF Q1 = FAIRCHILD 250V Q2 = DIODES, INC. T1 = COOPER MOC207 = FAIRCHILD relaTeD parTs PART NUMBER DESCRIPTION COMMENTS LT1952/LT1952-1 Isolated Synchronous Forward Controllers Ideal for Medium Power 24V and 48V Input Applications LTC3765/LTC3766 Isolated Synchronous No-Opto Forward Controller Chip Set Ideal for Medium Power 24V and 48V Input Applications LTC3723-1/LTC3723-2 Synchronous Push-Pull and Full-Bridge Controllers High Efficiency with On-Chip MOSFET Drivers LTC3721-1/LTC3721-2 Non-Synchronous Push-Pull and Full-Bridge Controllers Minimizes External Components, On-Chip MOSFET Drivers LTC3722/LTC3722-2 Synchronous Isolated Full Bridge Controllers Ideal for High Power 24V and 48V Input Applications LTC3900 Synchronous Rectifier Driver for Forward Converters Programmable Timeout, Synchronization Sequencer, Reverse Inductor Current Sense LTC3901 Synchronous Rectifier Driver for Push-Pull and Full-Bridge Programmable Timeout, Synchronization Sequencer, Reverse Inductor Current Sense LTC3803/LTC3803-3/ Flyback DC/DC Controller with Fixed 200kHz or 300kHz V and V Limited by External Components, 6-pin ThinSoT IN OUT LTC3803-5 Operating Frequency Package LTC3805/LTC3805-5 Adjustable Constant Frequency (70KHz to 700kHz) Frequency V and V Limited by External Components, MSOP-10E and IN OUT Flyback DC/DC Controller 3mm × 3mm DFN-10 Packages LT3748 100V No Opto Flyback Controller 5V ≤ V ≤ 100V, Boundary Mode Operation, MSOP-16 with Extra IN High Voltage Pin Spacing LT3798 Off-Line Isolated No-Opto Flyback Controller with Active PFC V and V Limited by External Components IN OUT 4430fd 26 Linear Technology Corporation LT 0715 REV D • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LT4430 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LT4430  LINEAR TECHNOLOGY CORPORATION 2004