LT4275 LTPoE++/PoE+/PoE PD Controller FeaTures DescripTion n IEEE 802.3af/at and LTPoE++™ Powered Device The LT®4275 is a pin-for-pin compatible family of IEEE (PD) Controller 802.3 and LTPoE++ powered device (PD) controllers. n LTPoE++ Supports Power Levels Up to 90W The LT4275A employs a proprietary LTPoE++ classification n LT4275A Supports All of the Following Standards: scheme, delivering 38.7W, 52.7W, 70W or 90W of power n LTPoE++ 38.7W, 52.7W, 70W and 90W at the PD RJ45 connector. The LT4275A is fully compat- n IEEE 802.3at 25.5W Compliant ible with IEEE 802.3. The LT4275B is an IEEE 802.3at n IEEE 802.3af Up to 13W Compliant compliant, Type 2 (PoE+) PD delivering up to 25.5W. The n LT4275B is IEEE 802.3at/af Compliant LT4275C is an IEEE 802.3af compliant, Type 1 (PoE) PD n LT4275C is IEEE 802.3af Compliant delivering up to 13W. n 100V Absolute Maximum Input Voltage The LT4275 internal charge pump provides an N-channel n Wide Junction Temperature Range (–40°C to 125°C) MOSFET solution, eliminating a larger and more costly n Overtemperature Protection P-channel MOSFET. A low R MOSFET also maxi- n Integrated Signature Resistor DS(ON) mizes power delivery and efficiency, reduces power and n External Hot Swap™ N-Channel MOSFET for Lowest heat dissipation, and eases thermal design. Startup inrush Power Dissipation and Highest System Efficiency current is adjustable with an external capacitor. The LT4275 n Programmable Aux Power Support as Low as 9V also includes a power good output, on-board signature n Optional Support of Non-Standard Low Voltage PoE resistor, undervoltage lockout, and thermal protection. The n Available in 10-Lead MSOP and 3mm × 3mm DFN LT4275A/LT4275B drives a single opto-coupler to indicate Packages the power level of the attached PSE. Pin-selectable sup- applicaTions port for non-standard low voltage operation is provided. Auxiliary power override is supported with the AUX pin. n High Power Wireless Data Systems The LT4275A can be configured to support all possible n Outdoor Security Camera Equipment LTPoE++, 802.3at and 802.3af power levels with external n Commercial and Public Information Displays component changes. n High Temperature Industrial Applications L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and LTPoE++ and Hot Swap are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical applicaTion LTPoE++ 90W Powered Device Interface VAUX (9V TO 60V) + LT4275 Family CPORT LT4275 GRADE FDMC86102 MAX DELIVERED ~ + DPAATIRA VPORT C0.P1DµF POWER A B C ~ – 3.3k LTPoE++ 90W l ~ + 47nF VIN LTPoE++ 70W l ISOLATED + SPPAARIRE ~ – VPORT HSGATE HSSRC SPUOPWPELRY VOUT LTPoE++ 52.7W l AUX PWRGD RUN – LTPoE++ 38.7W l LT4275A 25.5W l l RCLASS RCLS RCLS++ RCGLNADSS+I+EEEUVLO T2P OPTO P(TSOE µTPY)PE 13W l l l 4275 TA01a 4275f 1

LT4275 absoluTe MaxiMuM raTings (Notes 1, 3) VPORT, HSSRC Voltages .........................–0.3V to 100V Operating Junction Temperature Range (Note 4) HSGATE Current..................................................±20mA LT4275AI/LT4275BI/LT4275CI ..............–40°C to 85°C IEEEUVLO, RCLASS, LT4275AH/LT4275BH/LT4275CH .......–40°C to 125°C RCLASS++ Voltages .......–0.3V to 8V (and ≤ VPORT) Storage Temperature Range ..................–65°C to 150°C AUX Current ........................................................±1.4mA Lead Temperature (Soldering, 10 sec.) ..................300°C T2P, PWRGD Voltage ...............................–0.3V to 100V T2P, PWRGD Current ...............................................5mA pin conFiguraTion TOP VIEW IEEEUVLO 1 10 VPORT TOP VIEW AUX 2 9 HSGATE IEEEUVLO 1 10 VPORT 11 AUX 2 9 HSGATE RCLASS 3 8 HSSRC GND RCLASS 3 8 HSSRC RCLASS++/NC* 4 7 PWRGD RCLASS++/NC* 4 7 PWRGD GND 5 6 T2P/NC* GND 5 6 T2P/NC* MS PACKAGE DD PACKAGE 10-LEAD PLASTIC MSOP 10-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJC = 45°C/W TJMAX = 150°C, θJC = 5°C/W EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB GND * RCLASS++ is not connected in the LT4275B/C versions. T2P is not connected in the LT4275C version. orDer inForMaTion MAX PD LEAD FREE FINISH TAPE AND REEL PART MARKING* POWER PACKAGE DESCRIPTION TEMPERATURE RANGE LT4275AIDD#PBF LT4275AIDD#TRPBF LGBS 90W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LT4275AHDD#PBF LT4275AHDD#TRPBF LGBS 90W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT4275AIMS#PBF LT4275AIMS#TRPBF LTGBT 90W 10-Lead Plastic MSOP –40°C to 85°C LT4275AHMS#PBF LT4275AHMS#TRPBF LTGBT 90W 10-Lead Plastic MSOP –40°C to 125°C LT4275BIDD#PBF LT4275BIDD#TRPBF LGBV 25.5W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LT4275BHDD#PBF LT4275BHDD#TRPBF LGBV 25.5W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT4275BIMS#PBF LT4275BIMS#TRPBF LTGBW 25.5W 10-Lead Plastic MSOP –40°C to 85°C LT4275BHMS#PBF LT4275BHMS#TRPBF LTGBW 25.5W 10-Lead Plastic MSOP –40°C to 125°C LT4275CIDD#PBF LT4275CIDD#TRPBF LGBX 13W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LT4275CHDD#PBF LT4275CHDD#TRPBF LGBX 13W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT4275CIMS#PBF LT4275CIMS#TRPBF LTGBY 13W 10-Lead Plastic MSOP –40°C to 85°C LT4275CHMS#PBF LT4275CHMS#TRPBF LTGBY 13W 10-Lead Plastic MSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4275f 2

LT4275 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 3) A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VPORT Operating Input Voltage At VPORT Pin l 23 60 V V VPORT Signature Range At VPORT Pin l 1.5 10 V SIG V VPORT Classification Range At VPORT Pin l 12.5 21 V CLASS V VPORT Mark Range At VPORT Pin, Preceded by V l 5.6 10 V MARK CLASS VPORT Aux Mode Range At VPORT Pin, AUX > V l 8 60 V AUXT Signature/Class Hysteresis Window l 1.0 V V Reset Threshold l 2.6 5.6 V RESET V Hot Swap Turn-On Voltage IEEEUVLO = 0V l 35 37 V HSON IEEEUVLO Open l 27 29 V V Hot Swap Turn-Off Voltage IEEEUVLO = 0V l 30 31 V HSOFF IEEEUVLO Open l 21.5 22.5 V Hot Swap On/Off Hysteresis Window l 3 V Supply Current Supply Current VPORT = HSSRC = 57V l 2 mA Supply Current During Classification VPORT = 17.5V, RCLASS and RCLASS++ Open l 0.4 0.7 1.1 mA Supply Current During Mark Event V l 0.5 2.2 mA MARK Signature and Classification Signature Resistance V (Note 2) l 23.7 24.4 25.2 kΩ SIG Signature Resistance During Mark Event V (Note 2) l 5.8 8.3 11 kΩ MARK V RCLASS/RCLASS++ Operating Voltage –10mA ≥ I ≥ –36mA, V l 1.32 1.40 1.43 V RCLS RCLASS CLASS Classification Stability Time VPORT Step to 17.5V, RCLASS = 34.8Ω l 2 ms Analog/Digital Interface V AUX Threshold l 6.1 6.3 6.5 V AUXT I AUX Pin Hysteresis Current AUX = 6.1V l 4 5.8 8 µA AUXH T2P Output Low 1mA Load (LT4275A/LT4275B Only) l 0.8 V PWRGD Output Low 1mA Load l 0.8 V PWRGD Leakage Current PWRGD = 60V l 5 µA T2P Leakage Current T2P = 60V l 5 µA Hot Swap Control I HSGATE Pull-Up Current V – V = 5V, V > 42V, Out of Pin l 18 22 27 µA GPU HSGATE HSSRC PORT V HSGATE Open Circuit Voltage V – V , 0µA to 10µA Load with Respect l 10 18 V GOC HSGATE HSSRC to HSSRC HSGATE Pull-Down Current V – V = 5V l 200 µA HSGATE HSSRC Timing f T2P Frequency After PWRGD Valid, if LTPoE++ PSE Is Mutually l 690 840 990 Hz T2P Identified Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: All voltages with respect to GND unless otherwise noted. Positive may cause permanent damage to the device. Exposure to any Absolute currents are into pins; negative currents are out of pins unless otherwise Maximum Rating condition for extended periods may affect device noted. reliability and lifetime. Note 4: This IC includes overtemperature protection that is intended Note 2: Signature resistance specifications do not include resistance to protect the device during momentary overload conditions. Junction added by the external diode bridge which can add as much as 1.1k to the temperature will exceed 150°C when overtemperature protection is active. port resistance. Continuous operation above the specified maximum operating junction temperature may impair device reliability. 4275f 3

LT4275 Typical perForMance characTerisTics VPORT Current vs VPORT Voltage 25k Detection Range VPORT Hot Swap Thresholds Supply Current During Power-On 0.5 37 2.0 T = –40°C IEEEUVLO = 0V T = –40°C T = 25°C Hot Swap ON T = 25°C T = 75°C 36 T = 75°C 0.4 VPORT CURRENT (mA)00..23 T = 125°C VPORT VOLTAGE (V) 33332345 SUPPLY CURRENT (mA)110...055 T = 125°C 0.1 Hot Swap OFF 31 0 30 0 0 2 4 6 8 10 –50 –25 0 25 50 75 100 125 35 40 45 50 55 60 VPORT VOLTAGE (V) TEMPERATURE (°C) VPORT VOLTAGE (V) 4275 G01 4275 G02 4275 G03 Signature Resistance vs Input Voltage VPORT Hot Swap Thresholds Reset Threshold 26.25 29.0 5.6 T = –40°C IEEEUVLO = FLOAT T = 25°C Ω) 25.75 T = 75°C 27.5 Hot Swap ON 5.1 k T = 125°C ESISTANCE ( 25.25 OLTAGE (V) 26.0 OLTAGE (V) 44..16 R V V RE 24.75 RT 24.5 RT TU PO PO 3.6 A V V N G SI 24.25 23.0 Hot Swap OFF 3.1 23.75 21.5 2.6 1 3 5 7 9 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 VPORT VOLTAGE (V) TEMPERATURE (°C) TEMPERATURE (°C) 4275 G04 4275 G05 4275 G06 PWRGD, T2P Output Low Voltage vs Current VPORT Classification Thresholds T2P Frequency 4 12.5 990 T = –40°C DETECT OR MARK TO CLASS T = 25°C CLASS TO MARK T = 75°C 940 12.0 3 T = 125°C VOLTAGE (V) 2 VPORT VOLTAGE (V) 1111..05 T2P FREQUENCY (Hz) 887499000 1 10.5 740 0 10.0 690 0 1 2 3 4 5 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 CURRENT (mA) TEMPERATURE (°C) TEMPERATURE (°C) 4275 G07 4275 G08 4275 G09 4275f 4

LT4275 pin FuncTions IEEEUVLO (Pin 1): Hot Swap Turn-on Threshold Level T2P (Pin 6, LT4275A/LT4275B Only): PSE Type Indica- Control. Connect to ground for IEEE compliant turn-on tor, Open-Drain Output. T2P floats for a 13W PSE. T2P and turn-off (UVLO) voltage thresholds. Leave open for pulls down for a 25.5W PSE. T2P pulls down at f with T2P lower turn-on and turn-off voltage thresholds. a 50% (typical) duty cycle to indicate the presence of an LTPoE++ PSE. T2P is valid after PWRGD is active. This pin AUX (Pin 2): Auxiliary Sense. Assert AUX via a resistive is not connected on the LT4275C. See the Applications divider from the auxiliary power input to set the voltage Information section for behavior when using the AUX pin. at which the auxiliary supply takes over. Asserting AUX pulls down HSGATE, disconnects the signature resistor, PWRGD (Pin 7): Power Good Indicator, Open-Drain Output. disables classification and floats the PWRGD pin. The Pulls down during V and inrush. CLASS AUX pin sinks I when below its threshold voltage of AUXH HSSRC (Pin 8): External Hot Swap MOSFET Source. Con- V to provide hysteresis. Tie to GND when not used. AUXT nect to source of the external MOSFET. RCLASS (Pin 3): Programmable PoE Classification Resis- HSGATE (Pin 9): External Hot Swap MOSFET Gate Control, tor. See Table 1. Output. Connect to gate of the external MOSFET. RCLASS++ (Pin 4, LT4275A Only): Programmable VPORT (Pin 10): PD interface upper power rail and external LTPoE++ Classification Resistor. This pin is not connected Hot Swap MOSFET drain connection. on the LT4275B/LT4275C. See Table 1. Exposed Pad (Pin 11, DFN Package Only): GND. Must GND (Pin 5): Ground Pin. Must be soldered to PCB GND. be soldered to PCB GND. block DiagraM VPORT VPORT VOLTAGE AND CURRENT REFERENCES PWRGD IEEEUVLO CONTROL LOGIC HSGATE CHARGE ON PUMP VGOC HSSRC AUX + 6.3V – OVERTEMP T2P VPORT VPORT 1.4V + CLASSIFICATION + 1.4V EN LOGIC EN – – RCLASS++ RCLASS GND 4275 BD 4275f 5

LT4275 applicaTions inForMaTion OVERVIEW POWER ON Power over Ethernet (PoE) continues to gain popularity as VHSON products take advantage of DC power and high speed data VHSOFF available from a single RJ45 connector. Powered device CLASS (PD) equipment vendors are running into the 25.5W power limit established by the IEEE 802.3 standard. The LT4275A RT VCLASSMIN O P allows higher power while maintaining backwards com- V patibility with existing PSE systems. The LT4275 utilizes VSIGMAX DETECT a low R N-channel MOSFET to maximize efficiency DS(ON) and delivered power. Heat is also reduced, easing thermal VRESET design. VSIGMIN 4275 F01 MODES OF OPERATION Figure 1. Type 1 Detect/Class Signaling Waveform The LT4275 has several modes of operation depending on the input voltage sequence applied to the VPORT pin. A Type 2 PSE may declare the availability of high power These modes include 25kΩ signature detection, classifica- by performing 2-event (Physical Layer) classification tion, mark, inrush and powered on. or by communicating over the (Data Link Layer) high speed data line. A Type 2 PD must recognize both types DETECTION of communication. Since Layer 2 communications takes place directly between the PSE and the PD application, the During detection, the PSE looks for a 25kΩ signature LT4275A/LT4275B responsibility ends with supporting resistor which identifies the device as a PD. The PSE will 2-event classification. apply two voltages in the range of 2.8V to 10V and measure the corresponding currents. Figure 1 shows the detection In 2-event classification, a Type 2 PSE probes for power voltages. The PSE calculates the signature resistance using classification twice as shown in Figure 2. The LT4275A or a ∆V/∆I measurement technique. LT4275B recognizes this and pulls the T2P pin down to signal the load that Type 2 power is available. If an LT4275A The LT4275 presents its precision, temperature-compen- senses an LTPoE++ PSE it alternates between pulling T2P sated 24.4k resistor between the VPORT and GND pins, down and floating T2P at a rate of f . T2P allowing the PSE to recognize a PD is present and request- ing power to be applied. The LT4275 signature resistor is POWER ON smaller than 25k to compensate for the additional series resistance introduced by the IEEE required bridge. VHSON VHSOFF CLASSIFICATION 1ST CLASS 2ND CLASS The detection/classification process varies depending on RT VCLASSMIN O P whether the PSE is Type 1, Type 2, or LTPoE++. A Type 2 V PSE may use Type 1 classification signaling and later VSIGMAX DETECT renegotiate a higher power classification with the PD over the data layer. VRESET 1ST MARK 2ND MARK A Type 1 PSE, after a successful detection, may apply a VSIGMIN 4275 F01 classification probe voltage of 15.5V to 20.5V and mea- sure current. Figure 2. Type 2 Detect/Class Signaling Waveform 4275f 6

LT4275 applicaTions inForMaTion Table 1. Classification Codes, Power Levels and Resistor Selection PD POWER NOMINAL CLASS LT4275 GRADE CAPABILITY RESISTOR CLASS AVAILABLE PD TYPE CURRENT A B C R R ++ CLS CLS 0 13W Type 1 <0.4mA    Open Open 1 3.84W Type 1 10.5mA    140Ω Open 2 6.49W Type 1 18.5mA    76.8Ω Open 3 13W Type 1 28mA    49.9Ω Open 4 25.5W Type 2 40mA   34.8Ω Open 4* 38.7W LTPoE++ 40mA  Open 34.8Ω 4* 52.7W LTPoE++ 40mA  140Ω 46.4Ω 4* 70W LTPoE++ 40mA  76.8Ω 64.9Ω 4* 90W LTPoE++ 40mA  49.9Ω 118Ω *An LTPoE++ PD will be classified as class 4 by an IEEE 802.3 compliant PSE. LTPoE++ CLASSIFICATION power delivery and efficiency, reduces power and heat dissipation, and eases thermal design. The LT4275A allows higher power allocation while main- taining backwards compatibility with existing PSE systems The PWRGD pin is held low by its open drain output until by extending the classification signaling of IEEE 802.3. HSGATE charges up to approximately 7V above HSSRC. Linear Technology PSE controllers that are capable of The PWRGD pin is used to hold off the isolated power LTPoE++ are listed in the Related Parts section. IEEE PSEs supply until inrush is complete and the external MOSFET will classify an LTPoE++ PD as a Type 2 PD. is fully enhanced. The HSGATE pin will remain high and the PWRGD pin pulled down until the port voltage falls below V or the AUX pin is above V . SIGNATURE CORRUPT DURING MARK HSOFF AUXT During the mark state, the LT4275 presents <11kΩ to the IINRUSH port as required by the IEEE specification. VPORT + 3.3k CPORT INRUSH AND POWERED ON CGATE Once the PSE detects and optionally classifies the PD, the HSGATE PSE then powers on the PD. When the port voltage rises VPORT HSSRC above the V threshold, it begins to source I out of HSON GPU LT4275A the HSGATE pin. This current flows into an external capaci- tor (C in Figure 3) that causes a voltage to ramp up the GATE GND gate of the external MOSFET. The external MOSFET acts as 4275 F03 a source follower and ramps the voltage up on the output bulk capacitor (CPORT in Figure 3) thereby determining the Figure 3. Programming IINRUSH inrush current (I in Figure 3). INRUSH AUXILIARY SUPPLY OVERRIDE To meet IEEE requirements, design I to be approxi- INRUSH If the AUX pin is held above V , the LT4275 enters mately 100mA. See equation below: AUXT auxiliary power supply override mode. In this mode C the signature resistor is disconnected, classification is I =I • PORT INRUSH GPU C disabled, HSGATE is pulled down, and the PWRGD pin is GATE allowed to float. The T2P pin pulls down on the LT4275A/ The LT4275 internal charge pump provides an N-channel LT4275B when no R ++ resistor is present. The T2P pin CLS MOSFET solution, eliminating a larger and more costly alternates between pulling down and floating at f on the T2P P-channel FET. The low R MOSFET also maximizes LT4275A when the R ++ resistor is present. DS(ON) CLS 4275f 7

LT4275 applicaTions inForMaTion The AUX pin allows for setting the auxiliary supply turn on Transient Voltage Suppressor (V ) and turn off (V ) voltage thresholds. The AUXON AUXOFF The LT4275 specifies an absolute maximum voltage of auxiliary supply hysteresis voltage (V ) is set by AUXHYS 100V and is designed to tolerate brief overvoltage events. sinking current (I ) only when the AUX pin voltage is AUXH However, the pins that interface to the outside world can less than V . Use the following equations to set V AUXT AUXON routinely see excessive peak voltages. To protect the and V via R1 and R2 in Figure 4. AUXOFF LT4275, install a unidirectional transient voltage suppres- sor (TVS) such as an SMAJ58A between the port voltage V −V V R1= AUXON AUXOFF = AUXHYS + and GND. This TVS must be mounted near the LT4275. I I AUXH AUXH R1 R1 LT4275A For extremely high cable discharge and surge protection R2= contact Linear Technology Applications. VAUXOFF −1 VAUX AUX    VAUXT  R2 Classification Resistor (R and R ++) CLS CLS V −V GND R1≥ AUX(M1A.4Xm) A AUXT – 4275 F04 The RCLS resistors set the classification load current cor- responding to the PD power classification. Select the value Figure 4. AUX Threshold and Hysteresis Calculation of RCLS from Table 1 and connect the resistor between the RCLASS pin and GND, or float the RCLASS pin if class 0 is required. The resistor tolerance must be 1% or better to THERMAL PROTECTION avoid degrading the overall accuracy of the classification The IEEE 802.3 specification requires a PD to withstand circuit. For LTPoE++ use the LT4275A and select the value any applied voltage from 0V to 57V indefinitely. During of R ++ from Table 1 in addition to R . CLS CLS classification, however, the power dissipation in the LT4275 may be as high as 1.5W. The LT4275 can easily tolerate Power Good Interface this power for the maximum IEEE timing but will overheat The LT4275 provides a power good signal (PWRGD) to if this condition persists abnormally. simplify the isolated power supply design. The power good The LT4275 includes a thermal protection feature which signal is used to delay isolated power supply startup until protects itself from excessive heating. If the junction the C capacitor is fully charged. PORT temperature exceeds the overtemperature threshold, the LT4275 pulls down the HSGATE and PWRGD pins and Exposed Pad disables classification. The LT4275A/LT4275B/LT4275C DFN package has an exposed pad that is internally electrically connected to EXTERNAL INTERFACE AND COMPONENT SELECTION GND. The exposed pad may only be connected to GND on the printed circuit board. Input Diode Bridge The input diode bridge introduces a voltage drop that affects LAYOUT CONSIDERATIONS the voltage range for each mode of operation. The LT4275 Avoid excessive parasitic capacitance on the RCLASS is designed to tolerate these voltage drops. The voltages pin and place resistor R close to the LT4275. For the shown in the Electrical Specifications are measured at the CLS LT4275A, place R ++ nearby as well. LT4275 package pins. CLS It is strictly required for maximum protection to place the Input Capacitor input capacitor (C ) and transient voltage suppressor as PD close to the LT4275 as possible. A 0.1µF capacitor is needed from VPORT to GND to meet an input impedance requirement in IEEE 802.3. 4275f 8

LT4275 Typical applicaTions IEEE 802.3af (Type 1) 13W Powered Device FDN8601 ~ + VPORT C0.P1DµF SMAJ58A + ~ – 3.3k CPORT ETHERNET MAGNETICS 47nF VIN ~ + ISOLATED + POWER ~ – VPORT HSGATE HSSRC SUPPLY VOUT PWRGD RUN – LT4275A/LT4275B/LT4275C RCLASS RCLASS++ T2P RCLS GND IEEEUVLO AUX 4275 TA02 IEEE 802.3at (Type 2) 25.5W Powered Device FDN8601 ~ + VPORT C0.P1DµF SMAJ58A + ~ – 3.3k CPORT ETHERNET MAGNETICS 47nF VIN ~ + ISOLATED + POWER ~ – VPORT HSGATE HSSRC SUPPLY VOUT PWRGD RUN – LT4275A/LT4275B RCLASS RCLASS++ PSE TYPE T2P OPTO RCLS GND IEEEUVLO AUX (TO µP) 4275 TA03 LTPoE++ 38.7W to 90W Powered Device FDMC86102 ~ + VPORT C0.P1DµF SMAJ58A + ~ – 3.3k CPORT WÜRTH 749022016 47nF VIN ~ + ISOLATED + POWER ~ – VPORT HSGATE HSSRC SUPPLY VOUT PWRGD RUN – LT4275A RCLASS RCLASS++ PSE TYPE T2P OPTO RCLS RCLS++ GND IEEEUVLO AUX (TO µP) 4275 TA04 4275f 9

LT4275 package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DD Package DD Package 10-Lead Plastic DFN (3mm × 3mm) 10-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1699 Rev C) (Reference LTC DWG # 05-08-1699 Rev C) 0.70 ±0.05 3.55 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.125 0.40 ±0.10 TYP 6 10 3.00 ±0.10 1.65 ±0.10 (4 SIDES) (2 SIDES) PIN 1 NOTCH PIN 1 R = 0.20 OR TOP MARK 0.35 × 45° (SEE NOTE 6) CHAMFER (DD) DFN REV C 0310 5 1 0.200 REF 0.75 ±0.05 0.25 ±0.05 0.50 BSC 2.38 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4275f 10

LT4275 package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661 Rev E) 0.889 ± 0.127 (.035 ± .005) 5.23 3.20 – 3.45 (.206) (.126 – .136) MIN 3.00 ± 0.102 0.305 ± 0.038 0.50 (.118 ± .004) 0.497 ± 0.076 (.0120 ± .0015) (.0197) (NOTE 3) (.0196 ± .003) 10 9 8 76 TYP BSC REF RECOMMENDED SOLDER PAD LAYOUT 3.00 ± 0.102 4.90 ± 0.152 DETAIL “A” (.193 ± .006) (.118 ± .004) 0.254 (NOTE 4) (.010) 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.53 ± 0.152 (.021 ± .006) 1.10 0.86 (.043) (.034) DETAIL “A” MAX REF 0.18 (.007) SEATING PLANE 0.17 – 0.27 0.1016 ± 0.0508 (.007 – .011) (.004 ± .002) 0.50 TYP (.0197) MSOP (MS) 0307 REV E NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 4275f 11 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LT4275 Typical applicaTion 25W PD Solution with 12VDC and 24VAC Auxiliary Input B2100 (4plcs) VAUX ~ 9V TO 57VDC OR 24VAC ~ + TO ISOLATED MMSD4148 470µF POWER SUPPLY (2plcs) MMSD4148 158k 0.1µF FDN8601 13 WÜRTH 8.2Ω 7499511001 15 SMAJ58A 0.1µF VPORT HSGATE HSSRC 3.3k AUX 16 RCLASS 47nF 931k 34.8Ω LT4275A/LT4275B TO ISOLATED 14 IEEEUVLO PWRGD POWER SUPPLY RUN 1–12 GND T2P OPTO PSE TYPE (TO µP) B2100 4275 TA05 (8plcs) TO PHY relaTeD parTs PART NUMBER DESCRIPTION COMMENTS LTC4257-1 IEEE 802.3af PD Interface Controller Internal 100V, 400mA Switch, Dual Current Limit, Programmable Class LTC4263 Single IEEE 802.3af PSE Controller Internal FET Switch LTC4265 IEEE 802.3at PD Interface Controller Internal 100V, 1A Switch, 2-Event Classification Recognition LTC4266 Quad IEEE 802.3at PoE PSE Controller With Programmable I /I , 2-Event Classification CUT LIM LTC4266A Quad LTPoE++ PSE Controller Provides Up to 90W. Backwards Compatible with IEEE 802.3af and IEEE 802.3at PDs. With Programmable I /I , 2-Event Classification CUT LIM LTC4266C Quad IEEE 802.3af PSE Controller With Programmable I /I , 1-Event Classification CUT LIM LTC4267-3 IEEE 802.3af PD Interface with Integrated Internal 100V, 400mA Switch, Programmable Class, 300kHz Constant Frequency PWM Switching Regulator LTC4269-1 IEEE 802.3af PD Interface with Integrated 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller, Flyback Switching Regulator 50kHz to 250kHz, Aux Support LTC4269-2 IEEE 802.3af PD Interface with Integrated 2-Event Classification, Programmable Class, Synchronous Forward Controller, 100kHz Forward Switching Regulator to 500kHz, Aux Support LTC4270/LTC4271 12-Port PoE/PoE+/LTPoE++ PSE Controller Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE++ PDs LTC4274 Single IEEE 802.3at PoE PSE Controller With Programmable I /I , 2-Event Classification CUT LIM LTC4274A Single LTPoE++ PSE Controller Provides Up to 90W. Backwards Compatible with IEEE 802.3 PDs. With Programmable I /I , 2-Event Classification CUT LIM LTC4274C Single IEEE 802.3af PSE Controller With Programmable I /I , 1-Event Classification CUT LIM LTC4278 IEEE 802.3af PD Interface with Integrated 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller, Flyback Switching Regulator 50kHz to 250kHz, 12V Aux Support LTC4290/LTC4271 8-Port PoE/PoE+/LTPoE++ PSE Controller Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE++ PDs 4275f 12 Linear Technology Corporation LT 0712 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2012