LT3751 High Voltage Capacitor Charger Controller with Regulation FEATURES DESCRIPTION n Charges Any Size Capacitor The LT®3751 is a high input voltage capable flyback con- n Low Noise Output in Voltage Regulation Mode troller designed to rapidly charge a large capacitor to a n Stable Operation Under a No-Load Condition user-adjustable high target voltage set by the transformer n Integrated 2A MOSFET Gate Driver with Rail-to-Rail turns ratio and three external resistors. Optionally, a feed- Operation for V ≤ 8V back pin can be used to provide a low noise high voltage CC n Selectable 5.6V or 10.5V Internal Gate Drive regulated output. Voltage Clamp The LT3751 has an integrated rail-to-rail MOSFET gate n User-Selectable Over/Undervoltage Detect driver that allows for efficient operation down to 4.75V. n Easily Adjustable Output Voltage A low 106mV differential current sense threshold volt- n Primary or Secondary Side Output Voltage Sense age accurately limits the peak switch current. Added pro- n Wide Input V Voltage Range (5V to 24V) CC tection is provided via user-selectable overvoltage and n Available in 20-Pin QFN 4mm × 5mm and 20-Lead undervoltage lockouts for both V and V . A typical CC TRANS TSSOP Packages application can charge a 1000µF capacitor to 500V in less than one second. APPLICATIONS The CHARGE pin is used to initiate a new charge cycle and provides ON/OFF control. The DONE pin indicates n High Voltage Regulated Supply when the capacitor has reached its programmed value and n High Voltage Capacitor Charger the part has stopped charging. The FAULT pin indicates n Professional Photoflash Systems when the LT3751 has shut down due to either V or n Emergency Strobe CC V voltage exceeding the user-programmed supply n Security/Inventory Control Systems TRANS tolerances. n Detonators All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents including 6518733 and 6636021. TYPICAL APPLICATION DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY Load Regulation and Efficiency T1 D1 VTRANS 1:10 500V 500 90 24V + 0 TO 150mA 3×320µF 40.2k 1×02µF • + OFF ON CHARGREVTRANSRDCM 18.2k • 0.47µF 100µF V)498 84 2V4CVC V1T0RµAFNSMITCORO347745kk CVDFUALCOVUCALNLMOET1PLT3751HLVVRGGVCAAOSTTUPEET 40V.2CkC 6mΩ OUTPUT VOLTAGE (449946 7728 EFFICIENCY (%) 374k OVLO1 CSN 715k 492 66 VCC 475k UVLO2 FB OUTPUT VOLTAGE OVLO2 EFFICIENCY GND RBG 10nF 1.74k 490 60 0 50 100 150 732Ω LOAD CURRENT (mA) 3751 TA01b 3751 TA01a 3751fd 1 For more information www.linear.com/LT3751

LT3751 ABSOLUTE MAXIMUM RATINGS (Note 1) V , CHARGE, CLAMP ..............................................24V Current into RV Pin ........................................±10mA CC OUT DONE, FAULT ............................................................24V Current into RDCM Pin.........................................±10mA LVGATE (Note 8) .......................................................24V Current into UVLO1 Pin ..........................................±1mA V – LVGATE .............................................................8V Current into UVLO2 Pin..........................................±1mA CC HVGATE ................................................................Note 9 Current into OVLO1 Pin ..........................................±1mA RBG, CSP, CSN ...........................................................2V Current into OVLO2 Pin ..........................................±1mA FB ..............................................................................5V Maximum Junction Temperature ..........................125°C Current into DONE Pin ...........................................±1mA Operating Temperature Range (Note 2)..–40°C to 125°C Current into FAULT Pin ...........................................±1mA Storage Temperature Range ..................–65°C to 150°C Current into RV Pin.......................................±1mA TRANS PIN CONFIGURATION TOP VIEW RVTRANS 1 TOP VIEW 20 RDCM UVLO1 RVTRANS NC RDCM UVLO1 2 19 NC 20 19 18 17 OVLO1 3 18 RVOUT OVLO1 1 16 RVOUT UVLO2 4 17 NC UVLO2 2 15 NC OVLO2 5 16 RBG OVLO2 3 14 RBG 21 21 FAULT 6 15 HVGATE FAULT 4 13 HVGATE DONE 7 14 LVGATE DONE 5 12 LVGATE CHARGE 8 13 VCC CHARGE 6 11 VCC CLAMP 9 12 CSP 7 8 9 10 FB 10 11 CSN AMP FB CSN CSP FE PACKAGE CL 20-LEAD PLASTIC TSSOP UFD PACKAGE TJMAX = 125°C, θJA = 38°C/W 20-PIN (4mm × 5mm) PLASTIC QFN EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE TIED TO PCB ORDER INFORMATION http://www.linear.com/product/LT3751#orderinfo LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3751EFE#PBF LT3751EFE#TRPBF LT3751FE 20-Lead Plastic TSSOP –40°C to 125°C LT3751IFE#PBF LT3751IFE#TRPBF LT3751FE 20-Lead Plastic TSSOP –40°C to 125°C LT3751EUFD#PBF LT3751EUFD#TRPBF 3751 20-Pin (4mm × 5mm) Plastic QFN –40°C to 125°C LT3751IUFD#PBF LT3751IUFD#TRPBF 3751 20-Pin (4mm × 5mm) Plastic QFN –40°C to 125°C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3751EFE LT3751EFE#TR LT3751FE 20-Lead Plastic TSSOP –40°C to 125°C LT3751IFE LT3751IFE#TR LT3751FE 20-Lead Plastic TSSOP –40°C to 125°C LT3751EUFD LT3751EUFD#TR 3751 20-Pin (4mm × 5mm) Plastic QFN –40°C to 125°C LT3751IUFD LT3751IUFD#TR 3751 20-Pin (4mm × 5mm) Plastic QFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 3751fd 2 For more information www.linear.com/LT3751

LT3751 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C. V = CHARGE = 5V, CLAMP = 0V, unless otherwise noted. Individual A CC 25kΩ resistors tied from 5V V supply to RV , RV , RDCM, unless otherwise noted. (Note 2) TRANS TRANS OUT PARAMETER CONDITIONS MIN TYP MAX UNITS V Voltage l 4.75 24 V CC RV Voltage (Note 3) l 4.75 65 V TRANS V Quiescent Current Not Switching, CHARGE = 5V 5.5 8 mA CC Not Switching, CHARGE = 0.3V 0 1 µA RV , R Quiescent Current (Note 4) TRANS DCM Not Switching, CHARGE = 5V l 35 40 45 µA Not Switching, CHARGE = 0.3V 0 1 µA RV Quiescent Current (Note 4) OUT Not Switching, CHARGE = 5V l 42 47 52 µA Not Switching, CHARGE = 0.3V 0 1 µA UVLO1, UVLO2, OVLO1, OVLO2 Clamp Voltage Measured at 1mA into Pin, CHARGE = 0V 55 V RV , RV , R Clamp Voltage Measured at 1mA into Pin, CHARGE = 0V 60 V TRANS OUT DCM CHARGE Pin Current CHARGE = 24V 425 µA CHARGE = 5V 60 µA CHARGE = 0V 1 µA CHARGE Minimum Enable Voltage l 1.5 V CHARGE Maximum Disable Voltage I ≤ 1µA l 0.3 V VCC Minimum CHARGE Pin Low Time 20 μs One-Shot Clock Period l 32 38 44 μs V Comparator Trip Voltage Measured at RBG Pin l 0.955 0.98 1.005 V OUT V Comparator Overdrive 2µs Pulse Width, 20 40 mV OUT RV , RV = 25kΩ TRANS OUT R = 0.83kΩ BG DCM Comparator Trip Voltage Measured as V – V , R = 25kΩ, V = 4.75V 350 600 900 mV DRAIN TRANS DCM CC (Note 5) Current Limit Comparator Trip Voltage FB Pin = 0V l 100 106 112 mV FB Pin = 1.3V l 7 11 15 mV FB Pin Bias Current Current Sourced from FB Pin, Measured at FB Pin Voltage 64 300 nA FB Pin Voltage (Note 6) l 1.19 1.22 1.25 V FB Pin Charge Mode Threshold 1.12 1.16 1.2 V FB Pin Charge Mode Hysteresis (Note 7) 55 mV FB Pin Overvoltage Mode Threshold 1.29 1.34 1.38 V FB Pin Overvoltage Hysteresis 60 mV DONE Output Signal High 100kΩ to 5V 5 V DONE Output Signal Low 100kΩ to 5V 40 200 mV DONE Leakage Current DONE = 5V 5 200 nA FAULT Output Signal High 100kΩ to 5V 5 V FAULT Output Signal Low 100kΩ to 5V 40 200 mV FAULT Leakage Current FAULT = 5V 5 200 nA UVLO1 Pin Current UVLO1 Pin Voltage = 1.24V l 48.5 50 51.5 μA UVLO2 Pin Current UVLO2 Pin Voltage = 1.24V l 48.5 50 51.5 μA OVLO1 Pin Current OVLO1 Pin Voltage = 1.24V l 48.5 50 51.5 μA OVLO2 Pin Current OVLO2 Pin Voltage = 1.24V l 48.5 50 51.5 μA 3751fd 3 For more information www.linear.com/LT3751

LT3751 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C. V = CHARGE = 5V, CLAMP = 0V, unless otherwise noted. Individual A CC 25kΩ resistors tied from 5V V supply to RV , RV , RDCM, unless otherwise noted. (Note 2) TRANS TRANS OUT PARAMETER CONDITIONS MIN TYP MAX UNITS UVLO1 Threshold Measured from Pin to GND l 1.195 1.225 1.255 V UVLO2 Threshold Measured from Pin to GND l 1.195 1.225 1.255 V OVLO1 Threshold Measured from Pin to GND l 1.195 1.225 1.255 V OVLO2 Threshold Measured from Pin to GND l 1.195 1.225 1.255 V Gate Minimum High Time 0.7 μs Gate Peak Pull-Up Current V = 5V, LVGATE Active 2.0 A CC V = 12V, LVGATE Inactive 1.5 A CC Gate Peak Pull-Down Current V = 5V, LVGATE Active 1.2 A CC V = 12V, LVGATE Inactive 1.5 A CC Gate Rise Time 10% → 90%, CGATE = 3.3nF (Note 8) V = 5V, LVGATE Active 40 ns CC V = 12V, LVGATE Inactive 55 ns CC Gate Fall Time 90% → 10%, CGATE = 3.3nF (Note 8) V = 5V, LVGATE Active 30 ns CC V = 12V, LVGATE Inactive 30 ns CC Gate High Voltage (Note 8): V = 5V, LVGATE Active 4.98 5 V CC V = 12V, LVGATE Inactive 10 10.5 11.5 V CC V = 12V, LVGATE Inactive, CLAMP Pin = 5V 5 5.6 6.5 V CC V = 24V, LVGATE Inactive 10 10.5 11.5 V CC Gate Turn-Off Propagation Delay C = 3.3nF 180 ns GATE 25mV Overdrive Applied to CSP Pin Gate Voltage Overshoot 500 mV CLAMP Pin Threshold 1.6 V Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: Refer to Block Diagram for V and V definitions. TRANS DRAIN may cause permanent damage to the device. Exposure to any Absolute Note 6: Low noise regulation of the output voltage requires a resistive Maximum Rating condition for extended periods may affect device voltage divider from output voltage to FB pin. FB pin should not be reliability and lifetime. grounded in this configuration. Refer to the Typical Application diagram for Note 2: The LT3751E is guaranteed to meet performance specifications proper FB pin configuration. from 0°C to 125°C junction temperature. Specifications over the –40°C Note 7: The feedback pin has built-in hysteresis that defines the boundary to 125°C operating junction temperature range are assured by design between charge-only mode and low noise regulation mode. characterization and correlation with statistical process controls. The Note 8: LVGATE should be used in parallel with HVGATE when V is less CC LT3751I is guaranteed over the full –40°C to 125°C operating junction than or equal to 8V (LVGATE active). When not in use, LVGATE should be temperature range. tied to V (LVGATE inactive). CC Note 3: A 60V internal clamp is connected to RV , RDCM, RV , TRANS OUT Note 9: Do not apply a positive or negative voltage or current source to UVLO1, UVLO2, OVLO1 and OVLO2. Resistors should be used such that HVGATE, otherwise permanent damage may occur. the pin currents do not exceed the Absolute Maximum Ratings. Note 4: Currents will increase as pin voltages are taken higher than the internal clamp voltage. 3751fd 4 For more information www.linear.com/LT3751

LT3751 TYPICAL PERFORMANCE CHARACTERISTICS V Pin Current V Supply Current CHARGE Pin Current CC TRANS 7 150 450 RVTRANS, RVOUT, RDCM = 25k 6 145 VCC, CHARGE = 5V 400 IVTRANS = IRVTRANS + IRVOUT + IRDCM 350 PIN CURRENT (mA) 4253 I CURRENT (µA)VTRANS111113224350500 CURRENT (µA)312205050000 100 –40°C –40°C –40°C 1 25°C 115 25°C 50 25°C 125°C 125°C 125°C 0 110 0 0 4 8 12 16 20 24 0 10 20 30 40 50 60 0 4 8 12 16 20 24 PIN VOLTAGE (V) PIN VOLTAGE (V) PIN VOLTAGE (V) 3751 G01 3751 G02 3751 G03 CHARGE Pin Minimum CHARGE Pin Maximum Enable Voltage Disable Voltage DONE, FAULT Pin Voltage Low 1.3 1.2 400 VCC = 5V 1.2 1.1 VCC = 12V 350 VCC = 24V 1mA SINK E (V) 1.1 E (V) 1.0 mV)300 AG AG E (250 ARGE PIN VOLT 100...089 ARGE PIN VOLT 000...978 N LOW VOLTAG210500 CH CH PI100 0.7 VVCCCC == 51V2V 0.6 50 100µA SINK VCC = 24V 10µA SINK 0.6 0.5 0 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3751 G04 3751 G05 3751 G06 V Comparator Trip Voltage UVLO1 Trip Voltage UVLO1 Trip Current OUT 30.8 1.236 50.5 RVTRANS, RVOUT = 25.5k (RTOL = 1%) RBG = 833Ω 50.4 30.4 1.234 V) – V VOLTAGE (DRAINTRANS223990...260 UVLO1 PIN VOLTAGE (V)111...222233802 UVLO1 PIN CURRENT (µA) 4555590000.....92103 V28.8 VTRANS = 5V 1.226 VCC = 5V VCC = 5V VTRANS = 12V VTRANS = 48V VCC = 12V 49.8 VCC = 12V VTRANS = 24V VTRANS = 72V VCC = 24V VCC = 24V 28.4 1.224 49.7 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3751 G07 3751 G08 3751 G09 3751fd 5 For more information www.linear.com/LT3751

LT3751 TYPICAL PERFORMANCE CHARACTERISTICS Current Comparator Trip Voltage Current Comparator Minimum (Charge Mode) Trip Voltage (Regulation Mode) FB Pin Voltage 109.0 13.0 1.223 VTH = VCSP – VCSN VTH = VCSP – VCSN 12.8 FB = 1.3V 12.6 108.5 1.222 mV) mV) 12.4 E (V) E ( E ( 12.2 AG LTAG108.0 LTAG 12.0 VOLT1.221 V VOTH V VOTH 1111..68 FB PIN 107.5 1.220 VCC = 5V 11.4 VCC = 5V VCC = 5V VCC = 12V 11.2 VCC = 12V VCC = 12V VCC = 24V VCC = 24V VCC = 24V 107.0 11.0 1.219 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3751 G10 3751 G11 3751 G12 FB Pin Regulation FB Pin Regulation FB Pin Bias Current Mode Threshold Mode Hysteresis 100 1.168 60 MEASURED AT FB PIN VOLTAGE VCC = 5V VCC = 12V VCC = 12V A) 90 58 VCC = 24V CED PIN CURRENT (n 876000 B PIN VOLTAGE (V)11..116640 HYSTERESIS (mV) 5564 R F SOU 50 1.156 VCC = 5V 52 VCC = 12V VCC = 24V 40 1.152 50 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3751 G13 3751 G14 3751 G15 FB Pin Overvoltage Mode FB Pin Overvoltage Threshold Voltage Mode Hysteresis CLAMP Pin Threshold 1.356 61.0 1.9 VCC = 5V VCC = 12V VCC = 12V VCC = 24V 1.354 VCC = 24V 60.6 1.8 V) VOLTAGE (V)11..335520 RESIS (mV) 60.2 N VOLTAGE (1.7 FB PIN 1.348 HYSTE 59.8 LAMP PI1.6 C 1.346 59.4 VCC = 5V 1.5 VCC = 12V VCC = 24V 1.344 59.0 1.4 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 –40 0 40 80 120 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3751 G16 3751 G17 3751 G18 3751fd 6 For more information www.linear.com/LT3751

LT3751 TYPICAL PERFORMANCE CHARACTERISTICS DCM Trip Voltage (V – V ), DRAIN TRANS HVGATE Pin Clamp Voltage HVGATE Pin Clamp Voltage RV = RDCM = 25kΩ TRANS 11.0 5.70 0.64 VCC = 24V VCC = 12V VTRANS = 5V CLAMP = 0V CLAMP = 12V VTRANS = 12V 10.9 0.62 VTRANS = 24V GE (V) 10.8 GE (V) 5.65 E (V) VTRANS = 48V OLTA OLTA LTAG 0.60 ATE PIN V 1100..76 ATE PIN V 5.60 M TRIP VO 0.58 HVG HVG 5.55 DC 0.56 10.5 10.4 5.50 0.54 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 –40 0 40 80 120 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3751 G19 3751 G20 3751 G21 PIN FUNCTIONS (TSSOP/QFN) RV (Pin 1/Pin 19): Transformer Supply Sense Pin. UVLO2 (Pin 4/Pin 2): V Undervoltage Lockout Pin. TRANS CC Connect a resistor between the RV pin and the Senses when V drops below: TRANS CC V supply. Refer to Table 2 for proper sizing of the TRANS V =1.225+50µA •R RVTRANS resistor. The minimum operation voltage for UVLO2 UVLO2 V is 4.75V. TRANS and trips the FAULT latch low, disabling switching. After UVLO1 (Pin 2/Pin 20): V Undervoltage Lockout Pin. TRANS V rises above V , toggling the CHARGE pin reac- Senses when V drops below: CC UVLO2 TRANS tivates switching. VUVLO1=1.225+50µA •RUVLO1 OVLO2 (Pin 5/Pin 3): VCC Overvoltage Lockout Pin. Senses when V rises above: CC and trips the FAULT latch low, disabling switching. After V =1.225+50µA •R V rises above V , toggling the CHARGE pin OVLO2 OVLO2 TRANS UVLO1 reactivates switching. and trips the FAULT latch low, disabling switching. After OVLO1 (Pin 3/Pin 1): V Overvoltage Lockout Pin. TRANS V drops below V , toggling the CHARGE pin reac- Senses when V rises above: CC OVLO2 TRANS tivates switching. VOVLO1=1.225+50µA •ROVLO1 FAULT (Pin 6/Pin 4): Open Collector Indication Pin. When either V or V exceeds the user-selected voltage TRANS CC and trips the FAULT latch low, disabling switching. After range, or an internal UVLO condition occurs, a transistor V drops below V , toggling the CHARGE pin turns on. The part will stop switching. This pin needs a TRANS OVLO1 reactivates switching. proper pull-up resistor or current source. 3751fd 7 For more information www.linear.com/LT3751

LT3751 PIN FUNCTIONS DONE (Pin 7/ Pin 5): Open Collector Indication Pin. When LVGATE (Pin 14/Pin 12): Low Voltage Gate Pin. Connect the target output voltage (charge mode) is reached or the the NMOS gate terminal to this pin when operating V CC FAULT pin goes low, a transistor turns on. This pin needs below 8V. The internal gate driver will drive the voltage to a proper pull-up resistor or current source. the V rail. When operating V higher than 8V, tie this CC CC pin directly to V . CHARGE (Pin 8/Pin 6): Charge Pin. Initiates a new charge CC cycle (charge mode) or enables the part (regulation mode) HVGATE (Pin 15/Pin 13): High Voltage Gate Pin. Connect when driven higher than 1.5V. Bring this pin below 0.3V NMOS gate terminal to this pin for all V operating volt- CC to discontinue charging and put the part into shutdown. ages. Internal gate driver will drive the voltage to within Turn-on ramp rates should be between 10ns to 10ms. V – 2V during each switch cycle. CC CHARGE pin should not be directly ramped with V or CC RBG (Pin 16/Pin 14): Bias Generation Pin. Generates LT3751 may not properly initialize. a bias current set by 0.98V/R . Select R to achieve BG BG CLAMP (Pin 9/Pin 7): Internal Clamp Voltage Selection desired resistance for R , RV , and RV . DCM OUT TRANS Pin. Tie this pin to V to activate the internal 5.6V gate CC NC (Pins 17, 19/Pins 15, 18): No Connection. driver clamp. Tie this pin to ground to activate the internal 10.5V gate driver clamp. RVOUT (Pin 18/Pin 16): Output Voltage Sense Pin. Develops a current proportional to the output capacitor FB (Pin 10/Pin 8): Feedback Regulation Pin. Use this pin voltage. Connect a resistor between this pin and the drain to achieve low noise voltage regulation. FB is internally of NMOS such that: regulated to 1.22V when a resistive divider is tied from this pin to the output. FB pin should not float. Tie FB pin ⎛RV ⎞ V =0.98•N•⎜ OUT⎟−V OUT DIODE to either a resistor divider or ground. ⎝ RBG ⎠ CSN (Pin 11/Pin 9): Negative Current Sense Pin. Senses when RV is set equal to RV , otherwise: OUT TRANS external NMOS source current. Connect to local R SENSE ground connection for proper Kelvin sensing. The current V =N•⎡⎢0.98•RVOUT +V ⎛⎜ RVOUT −1⎞⎟⎤⎥ OUT TRANS limit is set by 106mV/RSENSE. ⎣ RBG ⎝RVTRANS ⎠⎦ CSP (Pin 12/Pin 10): Positive Current Sense Pin. Senses −V DIODE NMOS source current. Connect the NMOS source terminal where V = forward voltage drop of diode D1 (refer and the current sense resistor to this pin. The current DIODE to the Block Diagram). limit is fixed at 106mV/R in charge mode. The cur- SENSE rent limit can be reduced to a minimum 11mV/R in RDCM (Pin 20/Pin 17): Discontinuous Mode Sense Pin. SENSE regulation mode. Senses when the external NMOS drain is equal to 20µA • R + V and initiates the next switch cycle. Place V (Pin 13/Pin 11): Input Supply Pin. Must be locally DCM TRANS CC a resistor equal to 0.45 times the resistor on the RV bypassed with high grade (X5R or better) ceramic capaci- TRANS pin between this pin and V . tor. The minimum operating voltage for V is 4.75V. DRAIN CC GND (Pin 21/Pin 21): Ground. Tie directly to local ground plane. 3751fd 8 For more information www.linear.com/LT3751

LT3751 BLOCK DIAGRAM T1 D1 VTR1A2NVS +VOU4×T72µF R4R0VV.T2TRkRAANNSS 10µF PRIMARY1•:10• SECONDARY + CV4O5OU0UTVT CHARGE COMPARATOR – 0.98V OFF ON REFERENCE 60V OTLO OSNTAER-STH-UOPT RVOUT R40V.O2UkT VCC + VCC MASTER DIFF. AMP 12V LATCH COMPARATOR 60V 10µF 100k DONE DCM WITH S R COMPARATOR INTERNAL RDCM Q Q ENABLE – 60V CLAMPS RDCM 18.2k GATE DCM 100k DRIVER ONE-SHOT 60V + 1.22V FAULT REFERENCE VDRAIN QS RQ FLAAUTCLTH 26kHz ONE-SHOT VCC CLOCK HVGATE GATE DRIVE INTERNAL S Q CIRCUITRY M1 UVLO R Q 3.8V + SWITCH LATCH CLAMP VCC – VCC RUVLO1 191k UVLO1 LVGATE VTRANS – RESET VCC 55V CLK AUXILIARY COUNT + + COUNTER 162mV ROVLO1 – +– 240k OVLO1 + 26kHz 55V ONE-SHOT MAIN CSP CLOCK + – RSENSE UVLO/OVLO 106mV CSN 12mΩ RUVLO2 COMPARATORS – +– 191k UVLO2 VCC – TIMING AND PEAK 55V CURRENT CONTROL 11mV TO 106mV + TO CHARGE MODULATION ONE-SHOT 26kHz ERROR ONE-SHOT AMP + 1.22V ROVLO2 CLOCK REFERENCE 240k OVLO2 A1 + – 55V – + – RFBH 1.22V COMTOP AVROAUTTOR TDEMIEP 160ºC COMNOTDREOL FB 3.65M REFERENCE 10nF RFBL GND RBG 10k RBG 3751 BD 1.33k 3751fd 9 For more information www.linear.com/LT3751

LT3751 OPERATION The LT3751 can be used as either a fast, efficient high ILPRI voltage capacitor charger controller or as a high voltage, VTRANS – VDS(ON) low noise voltage regulator. The FB pin voltage determines IPK LPRI one of the three primary modes: charge mode, low noise regulation, or no-load operation (see Figure 1). FB PIN VOLTAGE ILSEC NO-LOAD OPERATION VOUT + VDIODE 1.34V IPNK LSEC REGULATION 1.16V CMHOADREGE VPRI VTRANS – VDS(ON) 0.0V 3751 F01 Figure 1. FB Pin Modes CHARGE MODE –(VOUT + VDIODE) N When the FB pin voltage is below 1.16V, the LT3751 acts as a rapid capacitor charger. The charging operation has VSEC VOUT + VDIODE four basic states for charge mode steady-state operation (see Figure 2). 1. Start-Up The first switching cycle is initiated approximately 2µs after the CHARGE pin is raised high. During this phase, –N (VTRANS – VDS(ON)) the start-up one-shot enables the master latch turning ocync tleh.e Aefxteterr nstaal rNt-MupO, Sth aen md absetgeirn nlaitncgh twheil lf irresmt sawini ticnh tinhge VDRAIN VTRANS +VOUT +N VDIODE switching-enable state until the target output voltage is VTRANS reached or a fault condition occurs. The LT3751 utilizes circuitry to protect against trans- VDS(ON) VDS(ON) former primary current entering a runaway condition and remains in start-up mode until the DCM comparator has 3751 F02 1. 2. 3. enough headroom. Refer to the Start-Up Protection sec- PRIMARY-SIDE SECONDARY DISCONTINUOUS CHARGING ENERGY TRANSFER MODE tion for more detail. AND OUTPUT DETECTION DETECTION 2. Primary-Side Charging When the NMOS switch latch is set, and depending on the Figure 2. Idealized Charging Waveforms use of LVGATE, the gate driver rapidly charges the gate pin to V – 2V in high voltage applications or directly to CC V in low voltage applications (refer to the Application CC 3751fd 10 For more information www.linear.com/LT3751

LT3751 OPERATION Information section for proper use of LVGATE). With the comparator sets the NMOS switch latch and a new switch gate driver output high, the external NMOS turns on, cycle begins. Steps 2-4 continue until the target output forcing V – V across the primary winding. voltage is reached. TRANS DS(ON) Consequently, current in the primary coil rises linearly at a rate (V – V )/L . The input voltage is mir- Start-Up Protection TRANS DS(ON) PRI rored on the secondary winding –N • (V – V ) TRANS DS(ON) The LT3751 at start-up, when the output voltage is very which reverse-biases the diode and prevents current flow low (or shorted), usually does not have enough V DRAIN in the secondary winding. Thus, energy is stored in the node voltage to trip the DCM comparator. The part in start- core of the transformer. up mode uses the internal 26kHz clock and an auxiliary current comparator. Figure 3 shows a simplified block 3. Secondary Energy Transfer diagram of the start-up circuitry. When current limit is reached, the current limit compara- tor resets the NMOS switch latch and the device enters the FROM AUXILIARY CURRENT INCREMENT third phase of operation, secondary energy transfer. The COMPARATOR COUNTER 1 energy stored in the transformer core forward-biases the FROM DCM – RESET diode and current flows into the output capacitor. During COMPARATOR SWITCH LATCH this time, the output voltage (neglecting the diode drop) FROM CLK INCREMENT + is reflected back to the primary coil. If the target output COUNTER 2 FROM GATE voltage is reached, the V comparator resets the master RESET OUT DRIVER ON latch and the DONE pin goes low. Otherwise, the device 3751 F03 enters the next phase of operation. Figure 3. Start-Up Protection Circuitry 4. Discontinuous Mode Detection Toggling the CHARGE pin always generates a start-up one-shot to turn on the external switch, initiating the During secondary energy transfer to the output capacitor, charging process. After the start-up one-shot, the LT3751 (V + V )/N will appear across the primary wind- OUT DIODE waits for either the DCM comparator to generate a one- ing. A transformer with no energy cannot support a DC shot or the output of the start-up protection circuitry voltage, so the voltage across the primary will decay to going high, which ever comes first. If the switch drain zero. In other words, the drain of the NMOS will ring node, V , is below the DCM comparator threshold DRAIN down from V + (V + V )/N to V . When TRANS OUT DIODE TRANS (see Entering Normal Boundary Mode), the DCM compar- the drain voltage falls to V + 20µA • R , the DCM TRANS DCM ator will never fire and the start-up circuitry is dominant. V VTH1 VTH2 VDRAIN VOUT ! DCM 1-SHOT t START-UP BOUNDARY-MODE BELOW VTH2 (DCM THRESHOLD = VTH1) (DCM THRESHOLD = VTH2) (WAIT FOR TIME-OUT) 3751 F04 Figure 4. DCM Comparator Thresholds 3751fd 11 For more information www.linear.com/LT3751

LT3751 OPERATION At very low output voltages, the boundary-mode switch- and indicates that the energy in the secondary winding ing cycle period increases significantly such that the has depleted. For this to happen, V must exceed DRAIN energy stored in the transformer core is not depleted V + ΔV prior to its negative edge; otherwise, TRANS DRAIN before the next clock cycle. In this situation, the clock the DCM comparator will not generate a one-shot to initi- may initiate another switching cycle before the secondary ate the next switching cycle. The part would remain stuck winding current reaches zero and cause the LT3751 to in this state indefinitely; however, the LT3751 uses the enter continuous-mode conduction. Normally, this is not start-up protection circuitry to jumpstart switching if the a problem; however, if the secondary energy transfer time DCM comparator does not generate a one-shot after a is much longer than the CLK period, significant primary maximum time-out of 500µs. current overshoot can occur. This is due to the non-zero Figure 4 shows a typical V node waveform with a DRAIN starting point of the primary current when the switch test circuit voltage clamp applied to the output. V is the TH1 turns on and the finite speed of the current comparator. start-up threshold and is set internally by forcing I OFFSET The LT3751 startup circuitry adds an auxiliary current to 40μA. Once the first DCM one-shot is initiated, the comparator with a trip level 50% higher than the nomi- mode latch is set to boundary-mode. The mode latch then nal trip level. Every time the auxiliary current comparator sets the clock count to maximum (500µs) and lowers the trips, the required clock count between switching cycles is DCM comparator threshold to V (I = 20μA). This TH2 OFFSET incremented by one. This allows more time for secondary provides needed hysteresis between start-up mode and energy transfer. boundary-mode operation. Counter 1 in Figure 3 is set to its maximum count when the first DCM comparator one-shot is generated. If no LOW NOISE REGULATION DCM one-shot is initiated in normal boundary-mode oper- Low noise voltage regulation can be achieved by adding ation during a maximum count of approximately 500µs, a resistive divider from the output node to the LT3751 FB the LT3751 re-enters start-up mode and the count is pin. At start-up (FB pin below 1.16V), the LT3751 enters returned to zero. the charge mode to rapidly charge the output capacitor. Note that Counter 1 is initialized to zero at start-up. Once the FB pin is within the threshold range of 1.16V Thus, the output of the startup circuitry will go high after to 1.34V, the part enters into low noise regulation. The one clock cycle. Counter 2 is reset when the gate driver switching methodology in regulation mimics that used goes high. This repeats until either the auxiliary cur- in the capacitor charging mode, but with the addition of rent comparator increments the required clock count or peak current and duty cycle control techniques. Figure 5 until V is high enough to sustain normal operation shows the steady state operation for both regulation tech- DRAIN described in steps 2 through 4 in the previous section. niques. Figure 6 shows how both techniques are com- bined to provide stable, low noise operation over a wide Entering Normal Boundary Mode load and supply range. The LT3751 has two DCM comparator thresholds that During heavy load conditions, the LT3751 sets the peak are dependent on what mode the part is in, either start- primary current to its maximum value, 106mV/R SENSE up mode or normal boundary-mode, and the state of the and sets the maximum duty cycle to approximately 95%. mode latch. For boundary-mode switching, the LT3751 This allows for maximum power delivery. At very light requires the DCM sense voltage (V ) to exceed loads, the opposite occurs, and the LT3751 reduces the DRAIN V by the ΔDCM comparator threshold, ΔV : peak primary current to approximately one tenth its maxi- TRANS DRAIN mum value while modulating the duty cycle below 10%. ΔV = (40µA + I ) • R – 40µA • RV DRAIN OFFSET DCM TRANS The LT3751 controls moderate loads with a combination where IOFFSET is mode dependent. The DCM one-shot sig- of peak current mode control and duty cycle control. nal is negative edge triggered by the switch node, V , DRAIN 3751fd 12 For more information www.linear.com/LT3751

LT3751 OPERATION CHARGE MODE LIGHT LOAD OPERATION 26kHz 26kHz ONE-SHOT ONE-SHOT CLK ... CLK ... ... SWITCH MAXIMUM ENABLE PEAK CURRENT NO BLANKING SWITCH DUTY CYCLE DUTY CYCLE ... ENABLE CONTROL CONTROL FORCED BLANKING IPRI ... IPRI ... t t tPER ≈ 38µs HEAVY LOAD OPERATION NO-LOAD OPERATION 26kHz 26kHz ONE-SHOT ONE-SHOT ... ... CLK CLK 110% SWITCH PEAK CURRENT ... VOUT, NOM ENABLE CONTROL VOUT ... FORCED 105% BLANKING VOUT, NOM IPRI ... 1/10TH IPK ... IPRI t t tPER ≈ 38µs 3751 F05 Figure 5. Modes of Operation (Steady State) ILIM( )DUTY CYCLE ( ) IMAX 95% NO-LOAD OPERATION 1/10 10% IMAX LOAD 0 LIGHT LOAD MODERATE HEAVY LOAD CHARGE CURRENT LOAD MODE 3751 F06 Figure 6. Regulation Technique 3751fd 13 For more information www.linear.com/LT3751

LT3751 OPERATION Periodic Refresh Light Load Operation When the LT3751 enters regulation, the internal circuitry The LT3751 uses duty cycle control to drastically reduce deactivates switching when the internal one-shot clock audible noise in both the transformer (mechanical) and is high. The clock operates at a 1/20th duty cycle with a the ceramic capacitors (piezoelectric effects). Internal minimum blank time of 1.5µs. This reset pulse is timed to control circuitry forces a one-shot condition at a periodic drastically reduce switching frequency content within the rate greater than 20kHz and out of the audio spectrum. audio spectrum and is active during all loading conditions. The regulation loop then determines the number of pulses Each reset pulse guarantees at least one energy cycle. A that are required to maintain the correct output voltage. minimum load is required to prevent the LT3751 from Figure 5 shows the use of duty-cycle control. entering no-load operation. No-Load Operation Heavy Load Operation The LT3751 can remain in low noise regulation at very low The LT3751 enters peak current mode control at higher loading conditions. Below a certain load current threshold output load conditions. The control loop maximizes the (Light Load Operation), the output voltage would continue number of switch cycles between each reset pulse. Since to increase and a runaway condition could occur. This is the control scheme operates in boundary mode, the reso- due to the periodic one-shot forced by the periodic refresh nant boundary-mode period changes with varying peak circuitry. By design, the LT3751 has built-in overvoltage primary current: protection associated with the FB pin. ⎡ 1 N ⎤ When the FB pin voltage exceeds 1.34V (±20mV), the Period=IPK •LPRI•⎣⎢VTRANS + VOUT⎦⎥ LT3751 enters no-load operation. No-load operation does not reset with the one-shot clock. Instead, the pulse train and the power output is proportional to the peak primary is completely load-dependent. These bursts are asynchro- current: nous and can contain long periods of inactivity. This allows 1/2•I regulation at a no-load condition but with the increase of P = PK OUT audible noise and voltage ripple. Note that when operating ⎡ 1 N ⎤ ⎢ + ⎥ with no-load, the output voltage will increase 10% above ⎣VTRANS VOUT⎦ the nominal output voltage. Noise becomes an issue at very low load currents. The LT3751 remedies this problem by setting the lower peak current limit to one tenth the maximum level and begins to employ duty-cycle control. 3751fd 14 For more information www.linear.com/LT3751

LT3751 APPLICATIONS INFORMATION The LT3751 charger controller can be optimized for either 100 P = 20 WATTS capacitor charging only or low noise regulation applica- 90 P = 50 WATTS P = 100 WATTS tions. Several equations are provided to aid in the design 80 process. 70 V) 60 Safety Warning (NS 50 A R VT 40 Large capacitors charged to high voltage can deliver a 30 lethal amount of energy if handled improperly. It is partic- 20 ularly important to observe appropriate safety measures 10 when designing the LT3751 into applications. First, cre- 0 1 10 100 ate a discharge circuit that allows the designer to safely PEAK PRIMARY CURRENT (A) discharge the output capacitor. Second, adequately space 3751 F07 high voltage nodes from adjacent traces to satisfy printed Figure 7. Maximum Power Output circuit board voltage breakdown requirements. Selecting Transformer Turns Ratio Selecting Operating Mode The transformer ratio, N, should be selected based on Tie the FB pin to GND to operate the LT3751 as a capacitor the input and output voltages. Smaller N values equate charger. In this mode, the LT3751 charges the output at to faster charge times and larger available output power. peak primary current in boundary mode operation. This Note that drastically reducing N below the V /V OUT TRANS constitutes maximum power delivery and yields the fast- ratio will increase the flyback voltage on the drain of the est charge times. Power delivery is halted once the output NMOS and increase the current through the output diode. reaches the desired output voltage set by the RVOUT and The ratio, N, should not be drastically increased either, RBG pins. due to the increased capacitance, N2 • C , reflected to SEC Tie a resistor divider from the FB pin to VOUT and GND the primary. A good choice is to select N equal to VOUT/ to operate the LT3751 as a low noise voltage regulator VTRANS. (refer to Low Noise regulation section for proper design V N≤ OUT procedures). The LT3751 operates as a voltage regulator V TRANS using both peak current and duty cycle modulation to vary output current during different loading conditions. Choosing Capacitor Charger I PK When operating the LT3751 as capacitor charger, choose Selecting Component Parameters I based on the required capacitor charge time, t , PK CHARGE Most designs start with the initial selection of VTRANS, and the initial design inputs. V , C , and either charge time, t , (capacitor OUT OUT CHARGE (2•N•V +V )•C •V charger) or P (regulator). These design inputs TRANS OUT OUT OUT OUT,MAX I = PK are then used to select the transformer ratio, N, the peak Efficiency•V •(t −t ) TRANS CHARGE d primary current, I , and the primary inductance, L . PK PRI The converter efficiency varies over the output voltage Figure 7 can be used as a rough guide for maximum range. The I equation is based on the average efficiency power output for a given V and I . PK TRANS PK over the entire charging period. Several factors can cause the charge time to increase. Efficiency is the most domi- nant factor and is mainly affected by the transformer winding resistance, core losses, leakage inductance, and transistor R . Most applications have overall efficiencies DS above 70%. 3751fd 15 For more information www.linear.com/LT3751

LT3751 APPLICATIONS INFORMATION The total propagation delay, t , is the second most domi- Transformer Design d nant factor that affects efficiency and is the summation of The transformer’s primary inductance, L , is determined PRI gate driver on-off propagation delays and the discharge by the desired V and previously calculated N and I OUT PK time associated with the secondary winding capacitance. parameters. Use the following equation to select L : PRI There are two effective methods to reduce the total propa- gation delay. First, reduce the total capacitance on the 3µs•V L = OUT secondary winding, most notably the diode capacitance. PRI I •N PK Second, reduce the total required NMOS gate charge. The previous equation guarantees that the V com- Figure 8 shows the effect of large secondary capacitance. OUT parator has enough time to sense the flyback waveform The energy stored in the secondary winding capacitance and trip the DONE pin latch. Operating V significantly OUT is ½ • C • V 2. This energy is reflected to the primary SEC OUT higher than that used to calculate L could result in a PRI when the diode stops forward conduction. If the reflected runaway condition and overcharge the output capacitor. capacitance is greater than the total NMOS drain capaci- The L equation is adequate for most regulator applica- tance, the drain of the NMOS power switch goes negative PRI tions. Note that if both I and N are increased signifi- and its intrinsic body diode conducts. It takes some time PK cantly for a given V and V , the maximum I will for this energy to be dissipated and thus adds to the total TRANS OUT PK not be reached within the refresh clock period. This will propagation delay. result in a lower than expected maximum output power. To prevent this from occurring, maintain the condition in the following equation. VDRAIN 38µs L < PRI ISEC ⎡ 1 N ⎤ NO SEC. IPK •⎢ + ⎥ CAPACITANCE ⎣VTRANS VOUT⎦ IPRI The upper constraint on L can be reduced by increas- PRI SEC. DISCHARGE ing V and starting the design process over. The best t TRANS regulation occurs when operating the boundary-mode 3751 F08 frequency above 100kHz (refer to Operation section for Figure 8. Effect of Secondary Winding Capacitance boundary-mode definition). Choosing Regulator Maximum I Figure 9 defines the maximum boundary-mode switching PK frequency when operating at a desired output power level The I parameter in regulation mode is calculated based PK and is normalized to L /P (μH/Watt). The relation- on the desired maximum output power instead of charge PRI OUT ship of output power, boundary-mode frequency, I , and time like that in a capacitor charger application. PK primary inductance can be used as a guide throughout POUT(AVG) ⎛ 1 N ⎞ the design process. I =2• •⎜ + ⎟ PK Efficiency ⎝VTRANS VOUT⎠ Note that the LT3751 regulation scheme varies the peak current based on the output load current. The maximum I is only reached during charge mode or during heavy PK load conditions where output power is maximized. 3751fd 16 For more information www.linear.com/LT3751

LT3751 APPLICATIONS INFORMATION Table 1. Recommended Transformers MANUFACTURER PART NUMBER SIZE L × W × H (mm) MAXIMUM I (A) L (µH) TURNS RATIO (PRI:SEC) PRI PRI Coilcraft DA2033-AL 17.4 × 24.1 × 10.2 5 10 1:10 www.coilcraft.com DA2034-AL 20.6 × 30 × 11.3 10 10 1:10 GA3459-BL 32.65 × 26.75 × 14 20 5 1:10 GA3460-BL 32.65 × 26.75 × 14 50 2.5 1:10 HA4060-AL 34.29 × 26.75 × 14 2 300 1:3 HA3994-AL 34.29 × 28.75 × 14 5 7.5 2:1:3:3* Würth Elektronik/Midcom 750032051 28.7 × 22 × 11.4 5 10 1:10 www.we-online.com 750032052 28.7 × 22 × 11.4 10 10 1:10 750310349 36.5 × 42 × 23 20 5 1:10 750310355 36.5 × 42 × 23 50 2.5 1:10 Sumida C8117 23 × 18.6 × 10.8 5 10 1:10 www.sumida.com C8119 32.2 × 27 × 14 10 10 1:10 PS07-299 32.5 × 26.5 × 13.5 20 5 1:10 PS07-300 32.5 × 26.5 × 13.5 50 2.5 1:10 TDK DCT15EFD-U44S003 22.5 × 16.5 × 8.5 5 10 1:10 www.tdk.com DCT20EFD-U32S003 30 × 22 × 12 10 10 1:10 DCT25EFD-U27S005 27.5 × 33 × 15.5 20 5 1:10 *Transformer has three secondaries where the ratio is designated as PRI:SEC1:SEC2:SEC3 RV , RV and R Selection TRANS OUT DCM 10.000 fMAX = 50kHz RV sets the common-mode reference voltage for fMAX = 100kHz TRANS fMAX = 200kHz both the DCM comparator and VOUT comparator. Select TT) 1.000 RVTRANS from Table 2 based on the transformer supply A W voltage range, V , and the maximum trip voltage, H/ TRANS T (µ 0.100 ΔVDRAIN (VDRAIN-VTRANS). T A W /RI The RVTRANS pin is connected to an internal 40µA current P L 0.010 source. Pin current increases as the pin voltage is taken higher than the internal 60V Zener clamp. The LT3751 can operate from V greater than the 60V internal Zener 0.001 TRANS 1 10 100 clamps by limiting the RV pin current to 250µA. TRANS PEAK PRIMARY CURRENT (A) 3751 F09 Operating V above 200V requires the use of resis- TRANS Figure 9. Maximum Switching Frequency tor dividers. Two applications are presented that operate Table 2. Suggested RV , RV , and R Values TRANS OUT DCM V Range ∆V RANGE RV RV R TRANS DRAIN TRANS OUT DCM (V) (V) (kΩ) (kΩ) (kΩ) 4.75 to 55 0 to 5 5.11 5.11 2.32 2.5 to 50 25.5 25.5 11.5 4.75 to 60 5 to 80 40.2 40.2 18.2 8 to 80 8 to 160 80.6 80.6 36.5 V −55V V −55V 80 to 200 2mA • RV TRANS TRANS 0.86 • RV OUT TRANS 0.25 0.25 >200 Resistor Divider Dependent Use Resistor Divider Use Resistor Divider Use Resistor Divider 3751fd 17 For more information www.linear.com/LT3751

LT3751 APPLICATIONS INFORMATION with V between 100V and 400V (refer to Typical RV from Table 2 meets this criterion. Use the following TRANS OUT Applications section). Consult applications engineering equation to size R (V ≤ 80V): BG TRANS for applications with V operating above 400V. TRANS ⎛ ⎞ RV RV is required for capacitor charger applications but R =0.98 •N •⎜ OUT ⎟ OUT BG ⎜ ⎟ may be removed for regulator applications. Note that the ⎝VOUT,TRIP+VDIODE⎠ V comparator can be used as secondary protection OUT for regulator applications. If the VOUT comparator is used Tie RBG pin to ground when not using the VOUT compara- for protection, design VOUT,TRIP 15% to 20% higher than tor. Consult applications engineering for calculating RBG the regulation voltage. Tie the RVOUT pin to ground when when operating VTRANS above 80V. RV resistor is removed. OUT NMOS Switch Selection R needs to be properly sized in relation to RV . DCM TRANS Choose an external NMOS power switch with minimal Improper selection of R can lead to undesired switch- DCM gate charge and on-resistance that satisfies current limit ing operation at low output voltages. Use Table 2 to size and voltage break-down requirements. The gate is nomi- R . DCM nally driven to V – 2V during each charge cycle. Ensure CC Parasitic capacitance on RV , RV , and R TRANS OUT DCM that this does not exceed the maximum gate to source should be minimized. Capacitances on these nodes slow voltage rating of the NMOS but enhances the channel down the response times of the V and DCM com- OUT enough to minimize the on-resistance. parators. Keep the distance between the resistor and Similarly, the maximum drain-source voltage rating of pin short. It is recommended to remove all ground and the NMOS must exceed V + V /N or the magni- power planes underneath these pins and their respective TRANS OUT tude of the leakage inductance spike, whichever is greater. components (refer to the recommended board layout at The maximum instantaneous drain current rating must the end of this section). exceed selected current limit. Because the switching R Selection period decreases with output voltage, the average current BG though the NMOS is greatest when the output is nearly R sets the trip current (0.98/R ) and is directly related BG BG charged and is given by: to the selection of RV . The best accuracy is achieved OUT I •V with a trip current between 100µA and 2mA. Choosing PK OUT(PK) I = AVG,M 2(V +N•V ) OUT(PK) TRANS See Table 3 for recommended external NMOS transistors. Table 3. Recommended NMOS Transistors MANUFACTURER PART NUMBER I (A) V (V) R (mΩ) Q (nC) PACKAGE D DS(MAX) DS(ON) G(TOT) Fairchild Semiconductor FDS2582 4.1 150 66 11 SO-8 www.fairchildsemi.com FQB19N20L 21 200 140 27 D2PAK FQP34N20L 31 200 75 55 TO-220 FQD12N20L 12 200 280 16 DPAK FQB4N80 3.9 800 3600 19 D2PAK On Semiconductor MTD6N15T4G 6 150 300 15 DPAK www.onsemi.com NTD12N10T4G 12 100 165 14 DPAK NTB30N20T4G 30 200 81 75 D2PAK NTB52N10T4G 52 100 30 72 D2PAK Vishay Si7820DN 2.6 200 240 12.1 1212-8 www.vishay.com Si7818DN 3.4 150 135 20 1212-8 SUP33N20-60P 33 200 60 53 TO-220 3751fd 18 For more information www.linear.com/LT3751

LT3751 APPLICATIONS INFORMATION Table 4. Recommended Output Diodes MANUFACTURER PART NUMBER I (A) V (V) T (ns) PACKAGE F(AV) RRM RR Central Semiconductor CMR1U-10M 1 1000 100 SMA www.centralsemi.com CMSH2-60M 2 60 SMA CMSH5-40 5 40 SMC Fairchild Semiconductor ES3J 3 600 35 SMC www.fairchildsemi.com ES1G 1 400 35 SMA ES1J 1 600 35 SMA On Semiconductor MURS360 3 600 75 SMC www.onsemi.com MURA260 2 600 75 SMA MURA160 1 600 75 SMA Vishay USB260 2 600 30 SMB www.vishay.com US1G 1 400 50 SMA US1M 1 1000 75 SMA GURB5H60 5 600 30 D2PAK Gate Driver Operation The average diode current is also a function of the output voltage. The LT3751 gate driver has an internal, selectable 10.5V or 5.6V clamp with up to 2A current capability (using I = IPK •VTRANS AVG LVGATE). For 10.5V operation, tie CLAMP pin to ground, 2•(V +N•V ) OUT TRANS and for 5.6V operation, tie the CLAMP pin to the V pin. CC Choose a clamp voltage that does not exceed the NMOS The highest average diode current occurs at low output manufacturer’s maximum V ratings. The 5.6V clamp voltages and decreases as the output voltage increases. GS can also be used to reduce LT3751 power dissipation Reverse recovery time, reverse bias leakage and junction and increase efficiency when using logic-level FETs. The capacitance should also be considered. All affect the over- all charging efficiency. Excessive diode reverse recovery typical gate driver overshoot voltage is 0.5V above the times can cause appreciable discharging of the output clamp voltage. capacitor, thereby increasing charge time. Choose a diode The LT3751’s gate driver also incorporates a PMOS pull- with a reverse recovery time of less than 100ns. Diode up device via the LVGATE pin. The PMOS pull-up driver leakage current under high reverse bias bleeds the output should only be used for V applications of 8V or below. CC capacitor of charge and increases charge time. Choose a Operating LVGATE with VCC above 8V will cause perma- diode that has minimal reverse bias leakage current. Diode nent damage to the part. LVGATE is active when tied to junction capacitance is reflected back to the primary, and HVGATE and allows rail-to-rail gate driver operation. This energy is lost during the NMOS intrinsic diode conduction. is especially useful for low VCC applications, allowing bet- Choose a diode with minimal junction capacitance. Table 4 ter NMOS drive capability. It also provides the fastest rise recommends several output diodes for various output times, given the larger 2A current capability verses 1.5A voltages that have adequate reverse recovery times. when using only HVGATE. Setting Current Limit Output Diode Selection Placing a sense resistor from the positive sense pin, CSP, The output diode(s) are selected based on the maximum to the negative sense pin, CSN, sets the maximum peak repetitive reverse voltage (VRRM) and the average for- switch current. The maximum current limit is nominally ward current (IF(AV)). The output diode’s VRRM should 106mV/RSENSE. The power rating of the current sense exceed VOUT + N • VTRANS. The output diode’s IF(AV) resistor must exceed: should exceed I /2N, the average short-circuit current. PK P ≥IPK2•RSENSE⎛⎜ VOUT(PK) ⎞⎟ RSENSE ⎜ ⎟ 3 ⎝VOUT(PK)+N•VTRANS⎠ 3751fd 19 For more information www.linear.com/LT3751

LT3751 APPLICATIONS INFORMATION Additionally, there is approximately a 180ns propaga- Under/Overvoltage Lockout tion delay from the time that peak current limit is The LT3751 provides user-programmable under and detected to when the gate transitions to the low state. overvoltage lockouts for both V and V . Use the CC TRANS This delay increases the peak current limit by (V ) TRANS equations in the Pin Functions section for proper selection (180ns)/L . PRI of resistor values. When under/overvoltage lockout com- Sense resistor inductance (L ) is another source of parators are tripped, the master latch is disabled, power RSENSE current limit error. L creates an input offset voltage delivery is halted, and the FAULT pin goes low. RSENSE (V ) to the current comparator and causes the current OS Adequate supply bulk capacitors should be used to reduce comparator to trip early. V can be calculated as: OS power supply voltage ripple that could cause false tripping ⎛ L ⎞ during normal switching operation. Additional filtering VOS = VTRANS •⎜ RSENSE ⎟ may be required due to the high input impedance of the ⎝LPRIMARY ⎠ under/overvoltage lockout pins to prevent false tripping. The change in current limit becomes V /R . The Individual capacitors ranging from 100pF to 1nF may be OS SENSE error is more significant for applications using large di/ placed between each of the UVLO1, UVLO2, OVLO1 and dt ratios in the transformer primary. It is recommended to OVLO2 pins and ground. Disable the undervoltage lock- outs by directly connecting the UVLO1 and UVLO2 pins use very low inductance (< 2nH) sense resistors. Several to VCC. Disable the overvoltage lockouts by directly con- resistors can be placed in parallel to help reduce the necting the OVLO1 and OVLO2 pins to ground. inductance. The LT3751 provides internal Zener clamping diodes to Care should also be taken in placement of the sense lines. protect itself in shutdown when V is operated above The negative return line, CSN, must be a dedicated trace TRANS to the low side resistor terminal. Haphazardly routing the 55V. Supply voltages should only be applied to UVLO1, CSN connection to the ground plane can cause inaccurate UVLO2, OVLO1 and OVLO2 with series resistance such current limit and can also cause an undesirable discon- that the Absolute Maximum pin currents are not exceeded. tinuous charging profile. Pin current can be calculated using: V −55V DONE and FAULT Pin Design I = APPLIED PIN R SERIES Both the DONE and FAULT pins require proper pull-up resistors or current sources. Limit pin current to 1mA Note that in shutdown, RV , RV , R , UVLO1, TRANS OUT DCM into either of these pins. 100kΩ pull-up resistors are rec- UVLO2, OVLO1 and OVLO2 currents increase significantly ommended for most applications. Both the DONE and when operating V above the Zener clamp voltages TRANS FAULT pins are latched in the low output state. Resetting and are inversely proportional to the external series pin either latch requires the CHARGE pin to be toggled. A fault resistances. condition will also cause the DONE pin to go low. A third, non-latching condition occurs during startup when the NMOS Snubber Design CHARGE pin is driven high. During this start-up condi- The transformer leakage inductance causes a parasitic tion, both the DONE and FAULT pins will go low for several voltage spike on the drain of the power NMOS switch dur- micro seconds. This indicates the internal rails are still ing the turn-off transition. Transformer leakage inductance ramping to their proper levels. External RC filters may be effects become more apparent at high peak primary cur- added to both indication pins to remove start-up indica- rents. The worst-case magnitude of the voltage spike is tion. Time constants for the RC filter should be between determined by the energy stored in the leakage inductance 5µs to 20µs. and the total capacitance on the V node. DRAIN 3751fd 20 For more information www.linear.com/LT3751

LT3751 APPLICATIONS INFORMATION LOW NOISE REGULATION 2 L •I V = LEAK PK The LT3751 has the option to provide a low noise regu- D,LEAK C VDRAIN lated output voltage when using a resistive voltage divider from the output node to the FB pin. Refer to the Selecting Two problems can arise from large V . First, the D,LEAK Component Parameters section to design the transformer, magnitude of the spike may require an NMOS with an NMOS power switch, output diode, and sense resistor. unnecessarily high V which equates to a larger (BR)DSS Use the following equations to select the feedback resis- R . Secondly, the V node will ring—possibly DS(ON) DRAIN tor values based on the power dissipation and desired below ground—causing false tripping of the DCM com- output voltage: parator or damage to the NMOS switch (see Figure 11). Both issues can be remedied using a snubber. If leakage 2 (V −1.22) inductance causes issues, it is recommended to use a RC R = OUT ; Top Feedback Resistor FBH P snubber in parallel with the primary winding, as shown D in Figure 10. Size CSNUB and RSNUB based on the desired ⎛ 1.22 ⎞ leakage spike voltage, known leakage inductance, and an RFBL =⎜ ⎟•RFBH; Bottom Feedback Resistor RC time constant less than 1µs. Otherwise, the leakage ⎝VOUT −1.22⎠ R , depending on output voltage and type used, may voltage spike can cause false tripping of the V com- FBH OUT require several smaller values placed in series. This will parator and stop charging prematurely. reduce the risk of arcing and damage to the feedback Figure 11 shows the effect of the RC snubber resulting in resistors. Consult the manufacturer’s rated voltage speci- a lower voltage spike and faster settling time. fication for safe operation of the feedback resistors. The LT3751 has a minimum periodic refresh frequency limit of 23kHz. This drastically reduces switching fre- • RSNUB LPRI quency components in the audio spectrum. The LT3751 • can operate with no-load, but the regulation scheme CSNUB switches to no-load operation and audible noise and LLEAK output voltage ripple increase. This can be avoided by operating with a minimum load current. CVDRAIN Minimum Load Current 3751 F11 Periodic refresh circuitry requires an average minimum Figure 10. RC Snubber Circuit load current to avoid entering no-load operation. Usually, the feedback resistors should be adequate to provide this minimum load current. VDRAIN (WITHOUT 2 L •I •23kHz SNUBBER) I ≥ PRI PK 0V LOAD(MIN) 100•V OUT NMOS DIODE VDRAIN CONDUCTS I is the peak primary current at maximum power deliv- (WITH PK SNUBBER) ery. The LT3751 will enter no-load operation if the mini- 0V mum load current is not met. No-load operation will pre- IPRI vent the application from entering a runaway condition; however, the output voltage will increase 10% over the 3751 F12 nominal regulated voltage. Figure 11. Effects of RC Snubber 3751fd 21 For more information www.linear.com/LT3751

LT3751 APPLICATIONS INFORMATION Large Signal Stability Small Signal Stability Large signal stability can be an issue when audible noise The LT3751’s error amplifier is internally compensated to is a concern. Figure 12 shows that the problem originates increase its operating range but requires the converter’s from the one-shot clock and the output voltage ripple. output node to be the dominant pole. Small signal stability The load must be constrained such that the output volt- constraints become more prevalent during heavy load- age ripple does not exceed the regulation range of the ing conditions where the dominant output pole moves error amplifier within one clock period (approximately to higher frequency and closer to the internal feedback 6mV referred to the FB pin). poles and zeros. The feedback loop requires the output pole frequency to remain below 200Hz to guarantee small The output capacitance should be increased if oscillations signal stability. This allows smaller R values than the occur or audible noise is present. Use Figure 13 to deter- LOAD large signal constraint. Thus, small signal issues should mine the maximum load for a given output capacitance to not arise if the large signal constraint is met. maintain low audible noise operation. A small capacitor can also be added from the FB pin to ground to lower the Board Layout ripple injected into FB pin. The high voltage operation of the LT3751 demands care- LOAD ful attention to the board layout, observing the following DROOP points: VOUT 1. Minimize the area of the high voltage end of the sec- ondary winding. IPRI 2. Provide sufficient spacing for all high voltage nodes (NMOS drain, V and secondary winding of the OUT 26kHz transformer) in order to meet the breakdown voltage ONE-SHOT CLK requirements. 3751 F13 3. Keep the electrical path formed by C , the primary VTRANS Figure 12. Voltage Ripple Stability Constraint of T1, and the drain of the NMOS as short as possible. Increasing the length of this path effectively increases the leakage inductance of T1, potentially resulting in an 30 VOUT = 150V overvoltage condition on the drain of the NMOS. VOUT = 300V 25 VOUT = 600V 4. Reduce the total node capacitance on the RV and OUT 20 RDCM pins by removing any ground or power planes F) (µN underneath the RDCM and RVOUT pads and traces. UT, MI15 Parasitic capacitance can cause unwanted behavior CO on these pins. 10 5. Thermal vias should be added underneath the Exposed 5 Pad, Pin 21, to enhance the LT3751’s thermal perfor- 0 mance. These vias should go directly to a large area of 0 50 100 150 200 OUTPUT POWER (W) ground plane. 3751 F14 6. Isolated applications require galvanic separation of the Figure 13. C vs Output Power OUT(MIN) output-side ground and primary-side ground. Adequate spacing between both ground planes is needed to meet voltage safety requirements. 3751fd 22 For more information www.linear.com/LT3751

LT3751 APPLICATIONS INFORMATION R E OWND OUT PG V OUT2 3751 F15 V C + UT1 O V C UT O V D N YRADNOCES UR • H1 e) POWERGND RET RS T11:N YR•AMIRP RFB ot to Scal REMOVE COPPERFROM ALL SUB-LAYE(SEE ITEM 4) NALOGND RSENSE RFBH2 d Board Layout (N AG M1 de n CNS3VTRANS4 RDCM RVOUT RBG VCCCVCC ANALOGGND ETD POWERGND RETURN age Recomme CVTRA SINGLPOINGN Pack 16 15 14 13 12 11 N F NS 17 10 CFB RFBL RFBH3 14. Q RVTRA 1918 LT3751 ANALOGGND VIAS 89 Figure 20 7 S2 N RA 1 2 3 4 5 6 VT C + O1 O1 ANS1 RUVL ROVL R CVT + RUVLO2 ROVLO2 RFAULT RDONE RD S E GD POWEGN VTRAN VCC CHARG ANALOGN 3751fd 23 For more information www.linear.com/LT3751

LT3751 APPLICATIONS INFORMATION UT O V H1 H2 B B RF RF 3751 F16 UT2 O CV+ VOUT UT1 D O V C YRADNOCES • T11:N YRAMIR•P ) e al c S o CVTRANS4 N out (Not t R y U a T L CVTRANS3 POWERGND RE ANALOGGND M1 ded Board n e CVTRANS2+ REMOVE COPPERFROM ALL SUB-LAYERS(SEE ITEM 4) RDCM RVOUT RBG VCC CVCC RSENSE ANALOGGND OWERND RETURN OP Package Recomm PG S S1 TS CVTRAN+ OWERND NALOGND 20 19 18 17 16375115 14 13 12 11 CFB RFBL Figure 15. PG AG LT 1 2 3 4 5 6 7 8 9 10 S RVTRAN RUVLO1 ROVLO1 RUVLO2 ROVLO2 RFAULT RDONE S C E N C G VTRA V HAR C 3751fd 24 For more information www.linear.com/LT3751

LT3751 TYPICAL APPLICATIONS 42A Capacitor Charger DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY T1** D1 D2*** VTRANS 1:10 VOUT * M1, M2 REQUIRES PROPER 12V TO 24V + C3 R6 C2 500V HEATSINK/THERMAL DISSIPATION 1000µF 40.2k 10µF • TO MEET MANUFACTURER’S SPECIFICATIONS ×3 + C4 RVTRANS • 1200µF ** TTHHEER CMHAALR GDEIS/DSIISPCAHTIAORNG OEF D TU1T YW CILYLC LLIEM OITF C4 OFF ON CHARGE R7, 18.2k CLAMP RDCM *** D2 MAY BE OMITTED FOR OUTPUT 12V TO 2V4CVC VCC LT3751 R8, 40.2k 4.7nF VOLTAGE OPERATION BELOW 300V C1 R10, 100k RVOUT Y-RATED 10µF DONE R11, 100k HVGATE M1, M2* FAULT LVGATE VCC C1: 25V X5R OR X7R CERAMIC CAPACITOR R1, 191k CSP C2: 25V X5R OR X7R CERAMIC CAPACITOR UVLO1 R5 VTRANS R2, 475k 2.5mΩ C3: 25V ELECTROLYTIC C4: HITACHI FX22L122Y 1200µF, 550V ELECTROLYTIC OVLO1 CSN OR: CORNELL DUBILIER DCMC192T550CE2B 1900µF, 550V ELECTROLYTIC R3, 191k D1, D2: VISHAY GURB5H60 600V, 5A ULTRAFAST RECTIFIER UVLO2 FB VCC R4, 475k M1, M2: 2 PARALLEL VISHAY SUP33N20-60P 200V, 33A NMOS R1 THRU R4, R6 THRU R11: USE 1% 0805 RESISTORS OVLO2 R5: USE 2 PARALLEL 5mΩ IRC LR SERIES 2512 RESISTORS GND RBG T1: COILCRAFT GA3460-BL 50A SURACE MOUNT TRANSFORMER R9 3751 TA02 787Ω FOR ANY VOUT VOLTAGE BETWEEN 50V AND 500V SELECT R9 ACCORDING TO: ⎛ 40.2kΩ ⎞ R9=0.98•N•⎜⎜ ⎟⎟ ⎝VOUT+VDIODE⎠ Efficiency Output Capacitor Charge Times Charging Waveform 85 1200 VOUT = 500V, VTRANS = 24V VOUT = 500V VOUT = 500V, VTRANS = 12V VTRANS = 24V VOUT = 300V, VTRANS = 24V C4 = 1200µF 80 VOUT = 300V, VTRANS = 12V %) ms)800 VVOTRUATN =S 1=0 204V,V FFICIENCY ( 75 ARGE TIME ( VVOTRUATN =S 1=0 102V,V 100VV/ODUIVT E H400 C 70 AVERAGE INPUT VTRANS = 12V CURRENT VTRANS = 24V 5A/DIV 65 0 50 150 250 350 450 200 400 600 800 1000 1200 100ms/DIV 3751 TA02d OUTPUT VOLTAGE (V) OUTPUT CAPACITANCE (µF) 3751 TA02b 3751 TA02c 3751fd 25 For more information www.linear.com/LT3751

LT3751 TYPICAL APPLICATIONS High Voltage Regulator DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY T1* D1 VTRANS 1:10 VOUT 5V TO 24V + 100V TO 500V C3 R6 C2 • C5 680µF 40.2k 5× 2.2µF + 0.47µF * M1 AND T1 REQUIRE PROPER RVTRANS R7, 18.2k • C1040*µ*F* HTOEA MTSEEINTK M/TAHNEURFMAACLT UDRISESRI’SPA STPIOECNI FICATIONS OFF ON CHARGE RDCM ** DEPENDING ON DESIRED OUTPUT VOLTAGES, CLAMP R10 MUST BE SPLIT INTO MULTIPLE RESISTORS, 5V TO 2V4CVC VCC LT3751RVOUT R8, 40.2k TO MEET MANUFACTURER’S VOLTAGE SPECIFICATION. C1 *** C4 MUST BE SIZED TO MEET LARGE SIGNAL 10µF TO DONE STABILITY CRITERIA DESCRIBED IN THE MICRO HVGATE M1* APPLICATIONS INFORMATION SECTION FAULT LVGATE VCC R1, 69.8k CSP UVLO1 R5 C1: 25V X5R OR X7R CERAMIC VTRANS R2, 475k 6mΩ C2: 25V X5R OR X7R CERAMIC OVLO1 CSN R10** C3: 25V ELECTROLYTIC R3, 69.8k C5: TDK CKG57NX7R2J474M UVLO2 D1: VISHAY US1M 1000V VCC R4, 475k FB M1: FAIRCHILD FQP34N20L OVLO2 C6 R1 THRU R4, R6 THRU R9, R11: USE 1% 0805 R11 GND RBG 10nF R5: IRC LR SERIES 2512 RESISTORS R10: USE 200V 1206 RESISTOR(S) 3751 TA04 T1: COILCRAFT GA3459-AL R9 Suggested Component Values Steady-State Operation with I (mA) I (mA) 1.1mA Load Current OUT(MAX) OUT(MAX) V AT V = 5V, AT V = 24V, R9 R11 R10 OUT TRANS TRANS (V) 5% V DEFLECTION 5% V DEFLECTION (kΩ) (kΩ) (kΩ) VOUT OUT OUT AC COUPLED 100 180 270 3.32 0.383 30.9 2V/DIV 200 110 315 1.65 0.768 124 VDRAIN 50V/DIV 300 75 245 1.10 1.13 274 400 55 200 0.825 1.54 499 IPRI 10A/DIV 500† 40 170 Tie to GND 1.74 715 3751 TA03b 10µs/DIV †Transformer primary inductance limits V comparator operation to V = 400V . RV OUT OUT MAX OUT and R should be tied to ground when operating V above 400V. BG OUT Steady-State Operation with Efficiency (V = 500V) Load Regulation (V = 500V) 100mA Load Current OUT OUT 90 515 VTRANS = 24V VOUT COUPLED 85 2V/DIV VTRANS = 12V 510 V) VDRAIN %) 80 E ( VTRANS = 24V 50V/DIV EFFICIENCY ( 7750 VTRANS = 5V OUTPUT VOLTAG505 VTRANS = 12V 10A/IDPIRVI 10µs/DIV 3751 TA03e 500 65 VTRANS = 5V 60 495 0 50 100 150 200 0 50 100 150 200 ILOAD (mA) ILOAD (mA) 3751 TA03c 3751 TA03d 3751fd 26 For more information www.linear.com/LT3751

LT3751 TYPICAL APPLICATIONS 1.6A High Input Voltage, Isolated Capacitor Charger DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY VTRANS F1, 1A T1* D1 D2 100V TO 1:3 VOUT * T1 REQUIRES PROPER THERMAL MANAGEMENT 400VDC + C473µF R6265k C2.22µF • + C540V TO 500V ** TMO1 ARCEHQIUEIVREE DSE PSRIROEPDE RO UHTEPAUT TS IPNOKW/TEHRE RLEMVAELLS R7, 96.2k ×5 220µF DISSIPATION TO MEET MANUFACTURER’S • SPECIFICATIONS R8 RVTRANS 417k C5 FOR ANY OUTPUT VOLTAGE BETWEEN 50V OFF ON CHARGE RDCM 0.47µF TO 500V, SET R12 GIVEN BY: CLAMP R9 10V TO 2V4CVC C1 VCC LT3751RVOUT 67.3k 2R0180k 4Y-.7RnAFTED R12= VOUT,TRI0P.9+840µA•2 10µF TO DONE R11 3•R10 MICRO FAULT 32.1k R5 C1: 25V X5R OR X7R CERAMIC R1, 1.5M 20Ω C2: 630V X5R OR X7R CERAMIC HVGATE M1** VTRANS R2, 9M UVLO1 LVGATFBE VCC CC34:: 45500VV T IOL L5I0N0OVI SE LCEACPT R47O6LCYTKIEC450MQW OVLO1 C5: TDK CKG57NX7R2J474M R3, 154k CSP D1, D2: VISHAY US1M 1000V UVLO2 R13 F1: BUSSMANN PCB-1-R VCC R4, 475k 68mΩ M1: FAIRCHILD FQB4N80 OVLO2 CSN R1, R2: 2 X 1206 RESISTORS IN SERIES, 1% R3 THRU R5, R9, R12: 0805 RESISTORS, 1% GND RBG R6, R10: 3 X 1206 RESISTORS IN SERIES, 0.1% 3751 TA04a R7, R11: 0805 RESISTORS, 0.1% R12 R8: 3 X 1206 RESISTORS IN SERIES, 1% R13: IRC LR SERIES 1206 RESISTOR, 1% T1: COILCRAFT HA4060-AL Output Trip Voltage and Charge Time (VOUT = 500V, COUT = 220µF) Efficiency Charging Waveform 530 1000 100 VOUT = 500V 95 VTRANS = 300V 520 850 VIN = 100V VOUT = 12V C 90 V (V)OUT,TRIP510 CHARGE TVIMOUET,TRIP 700HARGE TIME (ms EFFICIENCY (%) 8850 VVIINN == 245000VV A1V00EVRV/AODGUIVET ) 75 INPUT 500 550 CURRENT 70 200mA/DIV CHARGE 490 400 65 10V/DIV 100 200 300 400 50 150 250 350 450 100ms/DIV 3751 TA04d INPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 3751 TA04b 3751 TA04c 3751fd 27 For more information www.linear.com/LT3751

LT3751 TYPICAL APPLICATIONS High Input Voltage, High Output Voltage Regulator DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY 1V0T0RVA TNOS F1, 1A T11:3* D1 D2 1V0O0UVT TO 500V + * T1 REQUIRES PROPER THERMAL MANAGEMENT 400VDC C3 R6, 625k C2 • + TO ACHIEVE DESIRED OUTPUT POWER LEVELS 47µF R7, 97.6k 2.2µF C4 ×5 100µF ** M1 REQUIRES PROPER HEAT SINK/THERMAL • DISSIPATION TO MEET MANUFACTURER’S RVTRANS R8, 417k C5 SPECIFICATIONS OFF ON CHARGE RDCM 0.47µF CLAMP R9 *** DEPENDING ON DESIRED OUTPUT VOLTAGE, VCC LT3751 67.3k R10 MUST BE SPLIT INTO MULTIPLE RESISTORS 10V TO VCC RVOUT TO MEET MANUFACTURER’S VOLTAGE SPECIFICATION 24V C1 10µF TO DONE R5, 20Ω C1: 25V X5R OR X7R CERAMIC MICRO HVGATE M1** C2: 630V X5R OR X7R CERAMIC FAULT LVGATE VCC C3: 450V ILLINOIS CAP 476CKE450MQW R1, 1.5M CSP C4: 50V TO 500V ELECTROLYTIC UVLO1 R12 C5: TDK CKG57NX7R2J474M VTRANS R2, 9M 68mΩ C6: 6.3V X5R OR X7R CERAMIC OVLO1 CSN R10*** D1, D2: VISHAY US1M 1000V R3, 154k F1: BUSSMANN PCB-1-R UVLO2 M1: FAIRCHILD FQB4N80 VCC R4, 475k FB R1, R2: 2 X 1206 RESISTORS IN SERIES, 1% OVLO2 C6 R3 THRU R5, R7, R9, R11: 0805 RESISTORS, 1% R11 GND RBG 10nF R6, R8: 3 X 1206 RESISTORS IN SERIES, 1% R10: 1206 RESISTOR(S), 1% 3751 TA05a R12: IRC LR SERIES 1206 RESISTOR, 1% T1: COILCRAFT HA4060-AL Suggested Component Values I (mA) I (mA) OUT(MAX) OUT(MAX) V AT V = 100V, AT V = 400V, R10 R11 OUT TRANS TRANS (V) 1% V DEFLECTION 1% V DEFLECTION (kΩ) (kΩ) OUT OUT 100 55 130 30.9 0.383 200 110 150 124 0.768 300 95 175 274 1.13 400 80 130 499 1.54 500 65 140 715 1.74 Steady-State Operation with Efficiency Line Regulation 50mA Load Current 90 398 VIN = 100V VVIONU =T =2 0400V0V 80 VIN = 250V IOUT = 10mA V) VDRAIN %) E (397 100V/DIV CY ( 70 LTAG IOUT = 25mA N O CIE VIN = 400V T V EFFI 60 UTPU396 IOUT = 50mA O IPRI 50 2A/DIV 40 395 0 25 50 75 100 200 300 400 3751 TA05d 10µs/DIV OUTPUT CURRENT (mA) INPUT VOLTAGE (V) 3751 TA05b 3751 TA05c 3751fd 28 For more information www.linear.com/LT3751

LT3751 TYPICAL APPLICATIONS Isolated 282V Voltage Regulator DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY D2 R2, 10Ω ISOLATION BOUNDARY • T1 Npb VTRANS 1V0T0RVA TNOS F1, 2A D5 VOUT + 282V 200VDC 49.R91k M1 C2×223µF R2130k R4 C1×µ24F D3 Np •Ns C0.61µF + C4070µF 225mA RVTRANS 105k • C1 OFF ON CCHLAAMRGPE RDCM R5 R16 100pF 210k D4 249k VCC LT3751RVOUT Nsb CC12,: C168V: 1 X65VR C OORG XC7E4R CAEMRIACMIC D1 C1µ2F TO DONE HVGATE M2 • 5R.1115Ω D6 U2 R17 CCC345::, 32C55600, VVC 1EX1L5,ER CC 1OT2RR: O6XL37Y0RTV ICC XE5RRA MORIC X7R CERAMIC MRI9C, R2O.7M FAULT LVGATE VCC C0.501µF C9 VIN COMP C228nF 221k CCF179::, 23C551000VV:, 22E5ALVE F CXUT5SRREO OLRYT XIC7R CERAMIC VTRANS R10, 4.3M UOVVLLOO11 CSP 40mRΩ6 3.3µF GNLDT4430FB R3.1196k R1: 2010 RESISTOR, 1% R11, 84.5k C10 R18 R2, R3, R6, R16, R17: 1206 RESISTORS, 1% UVLO2 CSN 0.47µF 1k R4, R5: TWO 1206 RESISTORS IN SERIES, 1% VCC R12, 442k OC R7 THRU R12, R15 THRU R20: 0805 RESISTORS, 1% OVLO2 FB U1 D7 D1: 12V ZENER GND RBG R7 VCC OPTO D2: VISHAY MURS140 475Ω R20 D3: VISHAY P6KE200A R83751 TA06a 274Ω D4: VISHAY MURS160 2.49k D5: STMICROELECTRONICS STTH112A D6: VISHAY BAT54 T1: TDK SRW24LQ D7: NXP SEMICONDUCTORS BAS516 (Np:Ns:Npb:Nsb = 1:2:0.08:0.08) M1: VISHAY IRF830 U1: NEC PS2801-1 M2: STMICROELECTRONICS STB11NM60FD U2: LINEAR TECHNOLOGY LT4430 4.7nF Y RATED Steady-State Operation with Load Regulation Efficiency 7.1mA Load Current 0.50 100 63W OUTPUT 48W OUTPUT 95 25W OUTPUT R (V) 0.25 10V0DVR/DAIIVN RRO %) 90 T VOLTAGE E 0 EFFICIENCY ( 8850 IPR2IAM/ADRIVY 3751 TA06d U 20µs/DIV P T –0.25 U O 75 Steady-State Operation with –0.50 70 225mA Load Current 0 50 100 150 200 250 100 120 140 160 180 200 IOUT (mA) INPUT VOLTAGE (V) 3751 TA06c 3751 TA06b VDRAIN 100V/DIV IPRIMARY 2A/DIV 3751 TA06e 20µs/DIV 3751fd 29 For more information www.linear.com/LT3751

LT3751 TYPICAL APPLICATIONS Wide Input Voltage Range, 15 Watt, Triple Output Voltage Regulator T1 2:1:3:3 (P1:S1:S2:S3) D1 VIN VOUT3 5V TO 24V + C2 R5 C3 • C7 + C4 R12 +15V 1000µF 25.5k 10µF S3 10µF 470µF 4.99k ×2 RVTRANS OFF ON CHARGE CLAMP R6 D2 11.5k VOUT2 VCC RDCM C8 C5 R13 –15V C101µF LT3751 R7 P1 S2 10µF + 470µF 4.99k R1, 100k 25.5k • • DONE RVOUT R2, 100k D3 R3, 66.5k FAULT HVGATE M1 • C9 + C6 +V5OVUT1 CC12,: C253V: 2 S5AVN XY5OR 2 O5RM EX170R0 C0EARXAMIC R4, 464k UVLO1 LVGCASTPE VCC S1 100µF 1×020µF C4, C5: 35V SANYO 35ME470AX OVLO1 R11 C6: 10V KEMET T520D107M010ASE055 25mΩ C7, C8: 16V CERAMIC, TDK C4532X7R1E106M UVLO2 CSN R9 C9: 6.3V CERAMIC, TDK C4532X5R0J107M 309Ω D1, D2: CENTRAL SEMI CMSH2-60M OVLO2 FB D3: CENTRAL SEM1 CMSH5-40 GND RBG R10 M1: FAIRCHILD FQD12N20L 100Ω R1 THRU R10, R12, R13: 0805 RESISTOR, 1% R8 R11: 1206 RESISTOR, 1% 2.21k 3751 TA07a T1: COILCRAFT HA3994-AL, 2:1:3:3 (P1:S1:S2:S3) Maximum Output Conditions I * V P OUT(MAX) (mA) CC OUT(MAX) (V) (W) V V V OUT1 OUT2 OUT3 5 6.5 750 300 300 12 10 1750 300 300 24 13 2500 300 300 *All other output currents set to 0mA Cross Regulation Cross Regulation Efficiency (I = 100mA) (I = 500mA) (I = 500mA) VOUT1 VOUT1 VOUT1 20 26 90 VIN = 24V 24 85 VIN = 5V V (V)OUT3 18 VIN = 24V VIN = 5V V (V)OUT3 2220 VIN = 24V NCY (%) 8705 VIN = 12V –V, OUT2 16 VIN = 12V –V, OUT2 18 VIN = 12V EFFICIE 70 VIN = 5V 16 65 14 14 60 1 10 100 1000 1 10 100 1000 0 200 400 600 800 –IVOUT2, IVOUT3** (mA) 3751 TA07b –IVOUT2, IVOUT3** (mA) 3751 TA07c –IVOUT2 + IVOUT3 (mA) 3751 TA07d **SOURCE/SINK IDENTICAL CURRENTS FROM BOTH VOUT2 AND VOUT3, RESPECTIVELY 3751fd 30 For more information www.linear.com/LT3751

LT3751 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LT3751#packaging for the most recent package drawings. FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev L) Exposed Pad Variation CB 6.40 – 6.60* DETAIL A 3.86 (.252 – .260) (.152) 3.86 0.60 (.152) (.024) REF 20 1918171615141312 11 0.28 (.011) REF 6.60 ±0.10 DETAIL A IS THE PART OF 2.74 THE LEAD FRAME FEATURE 4.50 ±0.10 (.108) DETAIL A 6.40 FOR REFERENCE ONLY SEE NOTE 4 2.74 (.252) NO MEASUREMENT PURPOSE (.108) 0.45 ±0.05 BSC 1.05 ±0.10 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10 1.20 4.30 – 4.50* (.047) (.169 – .177) 0.25 MAX REF 0° – 8° 0.65 0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15 (.0035 – .0079) (.020 – .030) BSC (.002 – .006) 0.195 – 0.30 (.0077 – .0118) FE20 (CB) TSSOP REV L 0117 TYP NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE MILLIMETERS FOR EXPOSED PAD ATTACHMENT 2. DIMENSIONS ARE IN (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH 3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3751fd 31 For more information www.linear.com/LT3751

LT3751 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LT3751#packaging for the most recent package drawings. UUFFDD PPaacckkaaggee 202-L0-ePaidn PPllaassttiicc QQFFNN ((44mmmm × × 5 5mmmm)) (R(eRfeefreernecnec eL LTTCC DDWWGG ## 0055--0088--11771111 RReevv B B)) 0.70 ±0.05 2.65 ±0.05 4.50 ±0.05 1.50 REF 3.10 ±0.05 3.65 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 2.50 REF 4.10 ±0.05 5.50 ±0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 NOTCH R = 0.20 OR 4.00 ±0.10 0.75 ±0.05 R = 0.05 TYP 1.50 REF C = 0.35 (2 SIDES) 19 20 0.40 ±0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.00 ±0.10 2.50 REF (2 SIDES) 3.65 ±0.10 2.65 ±0.10 (UFD20) QFN 0506 REV B 0.200 REF R = 0.115 0.25 ±0.05 0.00 – 0.05 TYP 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3751fd 32 For more information www.linear.com/LT3751

LT3751 REVISION HISTORY (Revision history begins at Rev B) REV DATE DESCRIPTION PAGE NUMBER B 5/10 Updated FAULT (Pin 6/Pin 4) description in Pin Functions 7 Updated DONE (Pin 7/Pin 5) description in Pin Functions 8 Updated Block Diagram 9 Revised Applications Information section 17, 18 Revised Typical Applications illustration 30 C 6/12 Revised Applications Information section 20 Corrected Schematic R8 value from 3.40k to 2.21k 30 Updated FE package drawing 31 D 12/17 Revised Absolute Maximum storage temperature range upper limit from 125°C to 150°C. 2 3751fd Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog 33 Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No liceFnoser mis ogrraen tiendfo brym imatpiloicna twionw owr .olitnheearwr.icsoe mun/dLeTr 3a7ny5 1patent or patent rights of Analog Devices.

LT3751 TYPICAL APPLICATION 300V Regulated Power Supply T1 D1 VTRANS 1:10 VOUT 24V + C2 300V C3 R6 2.2µF • + 0mA TO 270mA 680µF 40.2k ×5 C4 RVTRANS R7 • 20µF OFF ON CHARGE 18.2k RDCM CLAMP RVOUT 2V4CVC VCC C1 TO DONE HVGATE M1 R8* 10µF MICRO FAULT LVGATE VCC 274k R1 CSP 432k UVLO1 R5 VTRANS R2 LT3751 6mΩ * DVOEPLTEANGDEI,N RG8 O MNU DSETS BIREE SDP OLIUTT PUT 475k OVLO1 CSN INTO MULTIPLE RESISTORS TO R3 MEET MANUFACTURER’S VOLTAGE 432k SPECIFICATION. UVLO2 FB VCC R4 C5 475k R9 10nF OVLO2 1.13k GND RBG 3751 TA08 C1: 25V X5R OR X7R CERAMIC CAPACITOR M1: FAIRCHILD FQP34N20L C2: 25V X5R OR X7R CERAMIC CAPACITOR R1 THROUGH R4: USE 1% 0805 RESISTORS C3: 25V ELECTROLYTIC R5: IRC LR SERIES 2512 RESISTOR C4: 330V RUBYCON PHOTOFLASH CAPACITOR T1: SUMIDA PS07-299, 20A TRANSFORMER D1: VISHAY US1M 1000V RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3225 150mA Supercapacitor Charger V : 2.75V to 5.5V, Charges Two Supercapacitors in Series to 4.8V or 5.3V IN LT3420/LT3420-1 1.4A/1A, Photoflash Capacitor Charger Charges 220µF to 320V in 3.7 Seconds from 5V, V : 2.2V to 16V, I < 1µA, IN SD with Automatic Top-Off 10-Lead MS Package LT3468/LT3468-1/ 1.4A, 1A, 0.7A, Photoflash Capacitor Charger V : 2.5V to 16V, Charge Time: 4.6 Seconds for LT3468 (0V to 320V, 100µF, IN LT3468-2 V = 3.6V), I < 1µA, ThinSOT Package IN SD LT3484-0/LT3484-1/ 1.4A, 0.7A, 1A Photoflash Capacitor Charger V : 1.8V to 16V, Charge Time: 4.6 Seconds for LT3484-0 (0V to 320V, 100µF, IN LT3484-2 V = 3.6V), I < 1µA, 2mm × 3mm 6-Lead DFN Package IN SD LT3485-0/LT3485-1/ 1.4A, 0.7A, 1A, 2A Photoflash Capacitor V : 1.8V to 10V, Charge Time: 3.7 Seconds for LT3485-0 (0V to 320V, 100µF, IN LT3485-2/LT3485-3 Charger with Output Voltage Monitor and V = 3.6V), I < 1µA, 3mm × 3mm 10-Lead DFN Package IN SD Integrated IGBT LT3585-0/LT3585-1/ 1.2A, 0.55A, 0.85A, 1.7A Photoflash V : 1.5V to 16V, Charge Time: 3.3 Seconds for LT3585-3 (0V to 320V, 100µF, IN LT3585-2/LT3585-3 Capacitor Charger with Adjustable Input V = 3.6V), I < 1µA, 3mm × 2mm DFN-10 Package IN SD Current and IGBT Drivers LT3750 Capacitor Charger Controller V : 3V to 24V, Charge Time: 300ms for (0V to 300V, 100µF) MSOP-10 Package IN 3751fd 34 LT 1217 REV D • PRINTED IN USA www.linear.com/LT3751 For more information www.linear.com/LT3751  ANALOG DEVICES, INC. 2017