LT3724 High Voltage, Current Mode Switching Regulator Controller FEATURES DESCRIPTION n Wide Input Range: 4V to 60V The LT®3724 is a DC/DC controller used for medium power, n Output Voltages up to 36V (Step-Down) low part count, low cost, high efficiency supplies. It of- n Burst Mode® Operation: <100µA Supply Current fers a wide 4V-60V input range (7.5V minimum startup n 10µA Shutdown Supply Current voltage) and can implement step-down, step-up, inverting n ±1.3% Reference Accuracy and SEPIC topologies. n 200kHz Fixed Frequency The LT3724 includes Burst Mode operation, which re- n Drives N-Channel MOSFET duces quiescent current below 100µA and maintains n Programmable Soft-Start high efficiency at light loads. An internal high voltage bias n Programmable Undervoltage Lockout regulator allows for simple biasing and can be back driven n Internal High Voltage Regulator for Gate Drive to increase efficiency. n Thermal Shutdown n Current Limit Unaffected by Duty Cycle Additional features include fixed frequency current mode n 16-Pin Thermally Enhanced TSSOP Package control for fast line and load transient response; a gate driver capable of driving large N-channel MOSFETs; a precision undervoltage lockout function; 10µA shutdown current; APPLICATIONS short-circuit protection; and a programmable soft-start n Industrial Power Distribution function that directly controls output voltage slew rates at n 12V and 42V Automotive and Heavy Equipment startup which limits inrush current, minimizes overshoot n High Voltage Single Board Systems and facilitates supply sequencing. n Distributed Power Systems L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Burst Mode is a trademark of Linear Technology Corporation. All other trademarks are the property n Avionics of their respective owners. Protected by U.S. Patents including 5731694, 6498466, 6611131. n Telecom Power TYPICAL APPLICATION High Voltage Step-Down Regulator Efficiency and Power Loss vs Load Current VIN 30V TO 95 12 60V CIN VIN BOOST 68µF 90 10 0.22µF 1M TG Si7852 EFFICIENCY 6280.10kk SCBHSuSrDsNt_LETN3724 VSCWC 10Ω 1µFSS3H9 47µH 0.025Ω + V27C3453OOVW0UUµTTF EFFICIENCY (%) 887505 864 POWER LOSS (W) LOSS VFB PGND 70 2 40.2k VC SENSE+ VIN = 48V 680pF 120pF 1000pF 65 0 SGND SENSE– 0.1 1 10 4.99k 93.1k LOAD CURRENT (A) 3724 TA01b 3724 TA01a 3724fd 1

LT3724 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) TOP VIEW Input Supply Voltage (V ) .........................65V to –0.3V IN Boosted Supply Voltage (BOOST) ..............80V to –0.3V VIN 1 16 BOOST Switch Voltage (SW)(Note 8) ........................65V to –1V NC 2 15 TG SHDN 3 14 SW Differential Boost Voltage (BOOST to SW) ......................................24V to –0.3V CSS 4 17 13 NC Bias Supply Voltage (V ) ..........................24V to –0.3V BURST_EN 5 12 VCC CC SENSE+ and SENSE– Voltages ...................40V to –0.3V VFB 6 11 PGND VC 7 10 SENSE+ SGND 8 9 SENSE– (SENSE+ to SENSE–) ...................................1V to –1V FE PACKAGE BURST_EN Voltage ....................................24V to –0.3V 16-LEAD PLASTIC TSSOP VC, VFB, CSS, and SHDN Voltages.................5V to –0.3V TJMAX = 125°C, θJA = 40°C/W, θJC = 10°C/W EXPOSED PAD IS SGND (PIN 17), MUST BE SOLDERED TO PCB C and SHDN Pin Currents .....................................1mA SS Operating Junction Temperature Range (Notes 2, 3) LT3724E .............................................–40°C to 125°C LT3724I ..............................................–40°C to 125°C LT3724MP..........................................–55°C to 125°C Storage Temperature ..............................–65°C to 150°C Lead Temperature (Soldering, 10 sec) ..................300°C ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LT3724EFE#PBF LT3724EFE#TRPBF 3724EFE 16-Lead Plastic TSSOP –40°C to 125°C LT3724IFE#PBF LT3724IFE#TRPBF 3724IFE 16-Lead Plastic TSSOP –40°C to 125°C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3724MPFE LT3724MPFE#TR 3724MPFE 16-Lead Plastic TSSOP –55°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 20V, V = BOOST = BURST_EN = 10V, SHDN = 2V, A IN CC SENSE– = SENSE+ = 10V, SGND = PGND = SW = 0V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Operating Voltage Range (Note 4) l 4 60 V IN Minimum Start Voltage l 7.5 V UVLO Threshold (Falling) l 3.65 3.8 3.95 V UVLO Threshold Hysteresis 670 mV I V Supply Current V > 9V 20 µA VIN IN CC V Burst Mode Current V = 0V, V = 1.35V 20 µA IN BURST_EN FB V Shutdown Current V = 0V 10 15 µA IN SHDN 3724fd 2

LT3724 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. V = 20V, V = BOOST = BURST_EN = 10V, SHDN = 2V, A IN CC SENSE– = SENSE+ = 10V, SGND = PGND = SW = 0V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Operating Voltage Range l 75 V BOOST Operating Voltage Range (Note 5) V - V l 20 V BOOST SW UVLO Threshold (Rising) V - V 5 V BOOST SW UVLO Threshold Hysteresis V - V 400 mV BOOST SW I BOOST Supply Current (Note 6) 1.4 mA BOOST BOOST Burst Mode Current V = 0V 0.1 µA BURST_EN BOOST Shutdown Current V = 0V 0.1 µA SHDN V Operating Voltage Range (Note 5) l 20 V CC Output Voltage Over Full Line and Load Range l 8 8.3 V UVLO Threshold (Rising) 6.25 V UVLO Threshold Hysteresis 500 mV I V Supply Current (Note 6) l 1.7 2.1 mA VCC CC V Burst Mode Current V = 0V 80 µA CC BURST_EN V Shutdown Current V = 0V 20 µA CC SHDN Short-Circuit Current l –30 –55 mA V Error Amp Reference Voltage Measured at V Pin 1.224 1.231 1.238 V FB FB l 1.215 1.245 V I Feedback Input Current 25 nA FB V Enable Threshold (Rising) l 1.3 1.35 1.4 V SHDN Threshold Hysteresis 120 mV V Common Mode Range l 0 36 V SENSE Current Limit Sense Voltage V + – V – l 140 150 175 mV SENSE SENSE I Input Current V = 0V 400 µA SENSE SENSE(CM) (I + + I –) V = 2.5V 2 µA SENSE SENSE SENSE(CM) V > 4V –150 µA SENSE(CM) f Operating Frequency 190 200 210 kHz SW l 175 220 kHz MP Grade l 165 200 225 kHz V Soft-Start Disable Voltage V Rising 1.185 V FB(SS) FB Soft-Start Disable Hysteresis 300 mV I Soft-Start Capacitor Control Current 2 µA SS g Error Amp Transconductance l 275 340 400 µmhos m A Error Amp DC Voltage Gain 62 dB V V Error Amp Output Range Zero Current to Current Limit 1.2 V C I Error Amp Sink/Source Current ±30 µA VC V Gate Drive Output On Voltage (Note 7) C = 3300pF 9.8 V TG LOAD Gate Drive Output Off Voltage C = 3300pF 0.1 V LOAD t Gate Drive Rise/Fall Time 10% to 90% or 90% to 10%, C = 3300pF 60 ns TG LOAD t Minimum Switch Off Time 350 ns TG(OFF) t Minimum Switch On Time l 300 500 ns TG(ON) I SW Pin Sink Current V = 2V 300 mA SW SW 3724fd 3

LT3724 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings temperature range. The LT3724MP is 100% tested and guaranteed over may cause permanent damage to the device. Exposure to any Absolute the –55°C to 125°C operating junction temperature range. Maximum Rating condition for extended periods may affect device Note 4: V voltages below the start-up threshold (7.5V) are only IN reliability and lifetime. supported when the V is externally driven above 6.5V. CC Note 2: The LT3724 includes overtemperature protection that is intended Note 5: Operating range is dictated by MOSFET absolute maximum V . GS to protect the device during momentary overload conditions. Junction Note 6: Supply current specification does not include switch drive temperature will exceed 125°C when overtemperature protection is active. currents. Actual supply currents will be higher. Continuous operation above the specified maximum operating junction Note 7: DC measurement of gate drive output “ON” voltage is typically temperature may impair device reliability. 8.6V. Internal dynamic bootstrap operation yields typical gate “ON” Note 3: The LT3724E is guaranteed to meet performance specifications voltages of 9.8V during standard switching operation. Standard operation from 0°C to 125°C junction temperature. Specifications over the –40°C gate “ON” voltage is not tested but guaranteed by design. to 125°C operating junction temperature range are assured by design, Note 8: The –1V absolute maximum on the SW pin is a transient condition. characterization and correlation with statistical process controls. The It is guaranteed by design and not subject to test. LT3724I is guaranteed over the full –40°C to 125°C operating junction TYPICAL PERFORMANCE CHARACTERISTICS Shutdown Threshold (Rising) Shutdown Threshold (Falling) vs Temperature vs Temperature V vs Temperature CC 1.38 1.26 8.2 WN THRESHOLD, RISING (V)1111....33337654 WN THRESHOLD, FALLING (V)1111....22225432 V (V)CC 88777.....10987 ICC = 20mA SHUTDO1.33 SHUTDO1.21 7.6 1.32 1.20 7.5 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3724 G01 3724 G02 3724 G03 V vs I V vs V I Current Limit vs Temperature CC CC(LOAD) CC IN CC 8.2 9 70 TA = 25°C ICC = 20mA 8.1 8 TA = 25°C 60 A) 8.0 m 7 T ( MI 50 V) 7.9 V) LI V (CC 7.8 V (CC 6 RENT 40 R U 5 C 7.7 C C I 30 7.6 4 7.5 3 20 0 5 10 15 20 25 30 35 4 5 6 7 8 9 10 11 12 –50 –25 0 25 50 75 100 125 ICC (LOAD) (mA) VIN (V) TEMPERATURE (°C) 3724 G04 3724 G05 3724 G06 3724fd 4

LT3724 TYPICAL PERFORMANCE CHARACTERISTICS V UVLO Threshold (Rising) Error Amp Transconductance CC vs Temperature I vs V (SHDN = 0V) vs Temperature CC CC 6.5 25 350 TA = 25°C os) h G (V) 6.4 20 E (µM 345 N C RISI TAN 340 D, 6.3 15 UC OL A) ND HRESH 6.2 I (µCC 10 ANSCO 335 O T TR 330 UVLCC 6.1 5 R AMP 325 V O R R E 6.0 0 320 –50 –25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 18 20 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) VCC (V) TEMPERATURE (°C) 3724 G07 3724 G08 3724 G09 I + – vs Operating Frequency Error Amp Reference (SENSE + SENSE ) V vs Temperature vs Temperature SENSE (CM) 400 230 1.234 TA = 25°C 1.233 300 Hz) 220 V) +– (µA)SE + SENSE)210000 NG FREQUENCY (k 221000 AMP REFERENCE (111...222333210 I(SEN–1000 OPERATI 119800 ERROR 11..222298 –200 170 1.227 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 VSENSE (CM) (V) TEMPERATURE (°C) TEMPERATURE (°C) 3724 G10 3724 G11 3724 G12 Maximum Current Sense V UVLO Threshold (Rising) V UVLO Threshold (Falling) IN IN Threshold vs Temperature vs Temperature vs Temperature 160 4.54 3.86 158 V) V)4.52 V) HOLD (m115564 RISING (4.50 ALLING (3.84 CURRENT SENSE THRES111111554444208642 V UVLO THRESHOLD, IN4444....44448642 V UVLO THRESHOLD, FIN333...887208 140 4.40 3.76 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3724 G13 3724 G14 3724 G15 3724fd 5

LT3724 PIN FUNCTIONS V (Pin 1): The V pin is the main supply pin and should V (Pin 7): The V pin is the output of the error amplifier IN IN C C be decoupled to SGND with a low ESR capacitor located whose voltage corresponds to the maximum (peak) switch close to the pin. current per oscillator cycle. The error amplifier is typically configured as an integrator circuit by connecting an RC NC (Pin 2): No Connection. network from the V pin to SGND. This circuit creates the C SHDN (Pin 3): The SHDN pin has a precision IC enable dominant pole for the converter regulation control loop. threshold of 1.35V (rising) with 120mV of hysteresis. It is Specific integrator characteristics can be configured to used to implement an undervoltage lockout (UVLO) circuit. optimize transient response. Connecting a 100pF or greater See Application Information section for implementing a high frequency bypass capacitor from this pin to ground UVLO function. When the SHDN pin is pulled below a is recommended. When Burst Mode operation is enabled transistor VBE (0.7V), a low current shutdown mode is (see Pin 5 description), an internal low impedance clamp entered, all internal circuitry is disabled and the VIN sup- on the VC pin is set at 100mV below the burst threshold, ply current is reduced to approximately 10µA. Typical which limits the negative excursion of the pin voltage. pin input bias current is <10µA and the pin is internally Therefore, this pin cannot be pulled low with a low imped- clamped to 6V. ance source. If the V pin must be externally manipulated, C do so through a 1kΩ series resistance. C (Pin 4): The soft-start pin is used to program the sup- SS ply soft-start function. The pin is connected to VOUT via a SGND (Pin 8, 17): The SGND pin is the low noise ground ceramic capacitor (CSS) and 200kΩ series resistor. During reference. It should be connected to the –VOUT side of the start-up, the supply output voltage slew rate is controlled output capacitors. Careful layout of the PCB is necessary to produce a 2µA average current through the soft-start to keep high currents away from this SGND connection. coupling capacitor. Use the following formula to calculate See the Application Information section for helpful hints CSS for a given output voltage slew rate: on PCB layout of grounds. CSS = 2µA(tSS/VOUT) SENSE– (Pin 9): The SENSE– pin is the negative input for the current sense amplifier and is connected to the V See the application section for more information on setting OUT side of the sense resistor for step-down applications. The the rise time of the output voltage during start-up. Shorting sensed inductor current limit is set to 150mV across the this pin to SGND disables the soft-start function. SENSE inputs. BURST_EN (Pin 5): The BURST_EN pin is used to enable SENSE+ (Pin 10): The SENSE+ pin is the positive input for or disable Burst Mode operation. Connect the BURST_EN the current sense amplifier and is connected to the induc- pin to ground to enable the burst mode function. Connect tor side of the sense resistor for step-down applications. the pin to V to disable the burst mode function. CC The sensed inductor current limit is set to 150mV across V (Pin 6): The output voltage feedback pin, V , is FB FB the SENSE inputs. externally connected to the supply output voltage via a PGND (Pin 11): The PGND pin is the high-current ground resistive divider. The V pin is internally connected to FB reference for internal low side switch and the V regulator the inverting input of the error amplifier. In regulation, CC circuit. Connect the pin directly to the negative terminal of V is 1.231V. FB the V decoupling capacitor. See the Application Informa- CC tion section for helpful hints on PCB layout of grounds. 3724fd 6

LT3724 PIN FUNCTIONS V (Pin 12): The V pin is the internal bias supply so that the BOOST pin capacitor can be charged. Give CC CC decoupling node. Use a low ESR 1µF ceramic capacitor careful consideration in choosing the Schottky diode to to decouple this node to PGND. Most internal IC func- limit the negative voltage swing on the SW pin. tions are powered from this bias supply. An external TG (Pin 15): The TG pin is the bootstrapped gate drive diode connected from V to the BOOST pin charges the CC for the top N-Channel MOSFET. Since very fast high cur- bootstrapped capacitor during the off-time of the main rents are driven from this pin, connect it to the gate of power switch. Back driving the V pin from an external CC the power MOSFET with a short and wide, typically 0.02” DC voltage source, such as the V output of the buck OUT width, PCB trace to minimize inductance. regulator supply, increases overall efficiency and reduces power dissipation in the IC. In shutdown mode this pin BOOST (Pin 16): The BOOST pin is the supply for the sinks 20µA until the pin voltage is discharged to 0V. bootstrapped gate drive and is externally connected to a low ESR ceramic boost capacitor referenced to SW pin. NC (Pin 13): No Connection. The recommended value of the BOOST capacitor, C , BOOST SW (Pin 14): In step-down applications the SW pin is is 50 times greater than the total input capacitance of the connected to the cathode of an external clamping Schottky topside MOSFET. In most applications 0.1µF is adequate. diode, the source of the power MOSFET and the induc- The maximum voltage that this pin sees is V + V , IN CC tor. The SW node voltage swing is from V during the IN ground referred. on-time of the power MOSFET, to a Schottky voltage drop Exposed Pad (SGND) (Pin 17): The exposed leadframe is below ground during the off-time of the power MOSFET. In start-up and in operating modes where there is insuf- internally connected to the SGND pin. Solder the exposed ficient inductor current to freewheel the Schottky diode, an pad to the PCB ground for electrical contact and optimal internal switch is turned on to pull the SW pin to ground thermal performance. 3724fd 7

LT3724 FUNCTIONAL DIAGRAM VIN UVLO (<4V) 8V VCC VIN VIN1 REGULATOR U(<VV6CLVCO) UBVSLTO 16BOOST CIN CBOOST 3.8V INTERNAL REGULATOR SUPPLY RAIL BOOSTED SWITCH DRIVER TG DRIVE 15 M1 RA FEEDBACK CONTROL REFERENCE – + 1.231V SW L1 RSENSE NOL 14 VOUT SHDN SLWOIGTICCH VCC D2 D1 COUT 3 + 12 RB – CVCC D3 DRIVE CONTROL (OPTIONAL) BURST_EN5 – 11PGND VFB 6 + – + R1 R2 ERgRmOR 0.5V OSCILLATOR AMP Q S – VC R SLOPE COMP 7 GENERATOR SOFT-START + CURRENT CC2 RC DISABLE/BURST SENSE ENABLE COMPARATOR + ~1V CC1 – – + BURST MODE 1.185V OPERATION CSS 2µA 4 – + SENSE+ CSS 10 SGND SENSE– 8 9 3724 FD 3724fd 8

LT3724 OPERATIONS (Refer to Functional Diagram) The LT3724 is a PWM controller with a constant frequency, V /Boosted Supply CC current mode control architecture. It is designed for low An internal V regulator provides V derived gate-drive CC IN to medium power, switching regulator applications. Its power for start-up under all operating conditions with high operating voltage capability allows it to step-up MOSFET gate charge loads up to 90nC. The regulator can or down input voltages up to 60V without the need for operate continuously in applications with V voltages a transformer. The LT3724 is used in nonsynchronous IN up to 60V, provided the V voltage and/or MOSFET gate applications, meaning that a freewheeling rectifier diode IN charge currents do not create excessive power dissipa- (D1 of Function Diagram) is used instead of a bottom tion in the IC. Safe operating conditions for continuous side MOSFET. For circuit operation, please refer to the regulator use are shown in Figure 1. In applications where Functional Diagram of the IC and Typical Application on these conditions are exceeded, V must be derived from the front page of the data sheet. The LT3800 is a similar CC an external source after start-up. The LT3724 regulator part that uses synchronous rectification, replacing the can, however, be used for “full time” use in applications diode with a MOSFET in a step-down application. where short-duration V transients exceed allowable IN Main Control Loop continuous voltages. 70 During normal operation, the external N-channel MOSFET switch is turned on at the beginning of each cycle. The 60 switch stays on until the current in the inductor exceeds a current threshold set by the DC control voltage, V , the 50 C output of the voltage control loop. The voltage control loop V) monitors the output voltage, via the VFB pin voltage, and V(IN 40 compares it to an internal 1.231V reference. It increases 30 the current threshold when the V voltage is below the SAFE FB reference voltage and decreases the current threshold 20 OPERATING AREA when the V voltage is above the reference voltage. For FB 10 instance, when an increase in the load current occurs, 0 20 40 60 80 100 MOSFET TOTAL GATE CHARGE (nC) the output voltage drops causing the V voltage to drop FB 3724 F01 relative to the 1.231V reference. The voltage control loop Figure 1. V Regulator Continuous Operating Conditions senses the drop and increases the current threshold. The CC peak inductor current is increased until the average induc- For higher converter efficiency and less power dissipa- tor current equals the new load current and the output tion in the IC, V can also be supplied from an external CC voltage returns to regulation. supply such as the converter output. When an external supply back drives the internal V regulator through an CC Current Limit/Short-Circuit external diode and the V voltage is pulled to a diode CC The inductor current is measured with a series sense above its regulation voltage, the internal regulator is dis- resistor (see the Typical Application on the front page). abled and goes into a low current mode. V is the bias CC When the voltage across the sense resistor reaches the supply for most of the internal IC functions and is also maximum current sense threshold, typically 150mV, the used to charge the bootstrapped capacitor (C ) via an BOOST TG MOSFET driver is disabled for the remainder of that external diode. The external MOSFET switch is biased from cycle. If the maximum current sense threshold is still ex- the bootstrapped capacitor. While the external MOSFET ceeded at the beginning of the next cycle, the entire cycle switch is off, an internal BJT switch, whose collector is is skipped. Cycle skipping keeps the inductor currents to connected to the SW pin and emitter is connected to the a controlled value during a short-circuit, particularly when PGND pin, is turned on to pull the SW node to PGND and VIN is high. Setting the sense resistor value is discussed recharge the bootstrap capacitor. The switch stays on until in the “Application Information” section. 3724fd 9

LT3724 OPERATIONS (Refer to Functional Diagram) either the start of the next cycle or until the bootstrapped switching resumes. An internal clamp on the V pin is set C capacitor is fully charged. at 100mV below the output disable threshold, which limits the negative excursion of the pin voltage, minimizing the MOSFET Driver converter output ripple during Burst Mode operation. The LT3724 contains a high speed boosted driver to turn During Burst Mode operation, the V pin current is 20µA IN on and off an external N-channel MOSFET switch. The and the V current is reduced to 80µA. If no external drive CC MOSFET driver derives its power from the boost capacitor is provided for V , all V bias currents originate from the CC CC which is referenced to the SW pin and the source of the V pin, giving a total V current of 100µA. Burst current IN IN MOSFET. The driver provides a large pulse of current to can be reduced further when V is driven using an output CC turn on the MOSFET fast and minimize transition times. derived source, as the V component of V current is CC IN Multiple MOSFETs can be paralleled for higher current then reduced by the converter duty cycle ratio. operation. Start-Up To eliminate the possibility of shoot through between the MOSFET and the internal SW pull-down switch, an adap- The following section describes the start-up of the supply tive nonoverlap circuit ensures that the internal pull-down and operation down to 4V once the step-down supply is switch does not turn on until the gate of the MOSFET is up and running. For the protection of the LT3724 and the below its turn on threshold. switching supply, there are internal undervoltage lockout (UVLO) circuits with hysteresis on V , V and V , IN CC BOOST Low Current Operation (Burst Mode Operation) as shown in the Electrical Characteristics table. Start-up and continuous operation require that all three of these To increase low current load efficiency, the LT3724 is undervoltage lockout conditions be satisfied because capable of operating in Linear Technology’s proprietary the TG MOSFET driver is disabled during any UVLO fault Burst Mode operation where the external MOSFET operates condition. In startup, for most applications, V is powered intermittently based on load current demand. The Burst CC from V through the high voltage linear regulator of the Mode function is disabled by connecting the BURST_EN IN LT3724. This requires V to be high enough to drive the pin to V and enabled by connecting the pin to SGND. IN CC V voltage above its undervoltage lockout threshold. CC When the required switch current, sensed via the V pin C V , in turn, has to be high enough to charge the BOOST CC voltage, is below 15% of maximum, Burst Mode operation capacitor through an external diode so that the BOOST is employed and that level of sense current is latched onto voltage is above its undervoltage lockout threshold. There the IC control path. If the output load requires less than is an NPN switch that pulls the SW node to ground each this latched current level, the converter will overdrive the cycle during the TG power MOSFET off-time, ensuring the output slightly during each switch cycle. This overdrive BOOST capacitor is kept fully charged. Once the supply condition is sensed internally and forces the voltage on the is up and running, the output voltage of the supply can V pin to continue to drop. When the voltage on V drops C C backdrive V through an external diode. Internal circuitry CC 150mV below the 15% load level, switching is disabled, disables the high voltage regulator to conserve V supply IN and the LT3724 shuts down most of its internal circuitry, current. Output voltages that are too low or too high to reducing total quiescent current to 100µA. When the backdrive V require additional circuitry such as a voltage CC converter output begins to fall, the V pin voltage begins C doubler or linear regulator. Once V is backdriven from CC to climb. When the voltage on the V pin climbs back to C a supply other than V , V can be reduced to 4V with IN IN the 15% load level, the IC returns to normal operation and normal operation maintained. 3724fd 10

LT3724 OPERATIONS (Refer to Functional Diagram) Soft-Start artificial ramp on the sensed current to increase the rising slope as duty cycle increases. The soft-start function controls the slew rate of the power supply output voltage during start-up. A controlled output Unfortunately, this additional ramp typically affects the voltage ramp minimizes output voltage overshoot, reduces sensed current value, thereby reducing the achievable inrush current from the V supply, and facilitates supply current limit value by the same amount as the added ramp IN sequencing. A capacitor, C , connected between V of represents. As such, the current limit is typically reduced SS OUT the supply and the C pin of the IC, programs the slew as the duty cycle increases. The LT3724, however, contains SS rate. The capacitor provides a current to the C pin which antislope compensation circuitry to eliminate the current SS is proportional to the dV/dt of the output voltage. The limit reduction associated with slope compensation. As the soft-start circuit overrides the control loop and adjusts the slope compensation ramp is added to the sensed current, inductor current until the output voltage slew rate yields a a similar ramp is added to the current limit threshold. The 2µA current through the soft-start capacitor. If the current is end result is that the current limit is not compromised so greater than 2µA, then the current threshold set by the DC the LT3724 can provide full power regardless of required control voltage, V , is decreased and the inductor current duty cycle. C is lowered. This in turn lowers the output current and the output voltage slew rate is decreased. If the current is less Shutdown than 2µA, then the current threshold set by the DC control The LT3724 includes a shutdown mode where all the voltage, V , is increased and the inductor current is raised. C internal IC functions are disabled and the V current is IN This in turn increases the output current and the output reduced to less than 10µA. The shutdown pin can be used voltage slew rate is increased. Once the output voltage is for undervoltage lockout with hysteresis, micropower shut- within 5% of its regulation voltage, the soft-start circuit down or as a general purpose on/off control of the converter is disabled and the main control regulates the output. The output. The shutdown function has two thresholds. The soft-start circuit is reactivated when the output voltage first threshold, a precision 1.23V threshold with 120mV drops below 70% of its regulation voltage. of hysteresis, disables the converter from switching. The second threshold, approximately a 0.7V referenced to Slope/Antislope Compensation SGND, completely disables all internal circuitry and reduces The IC incorporates slope compensation to eliminate the V current to less than 10µA. See the Application IN potential subharmonic oscillations in the current control Information section for more information. loop. The IC’s slope compensation circuit imposes an 3724fd 11

LT3724 APPLICATIONS INFORMATION The basic LT3724 step-down (buck) application, shown mode instability may occur at duty cycles greater than in the Typical Application on the front page, converts a 50%. Lower values of ∆I require larger and more costly L larger positive input voltage to a lower positive or negative magnetics. A value of ∆I = 0.3 • I produces a L OUT(MAX) output voltage. This Application Information section assists ±15% of I ripple current around the DC output OUT(MAX) selection of external components for the requirements of current of the supply. the power supply. Some magnetics vendors specify a volt-second product in their datasheet. If they do not, consult the magnetics R Selection SENSE vendor to make sure the specification is not being exceeded The current sense resistor, R , monitors the inductor SENSE by your design. The volt-second product is calculated as current of the supply (See Typical Application on front follows: page). Its value is chosen based on the maximum required output load current. The LT3724 current sense amplifier (V –V )•V IN(MAX) OUT OUT Volt-second (µsec)= has a maximum voltage threshold of, typically, 150mV. V •f Therefore, the peak inductor current is 150mV/R . IN(MAX) SW SENSE The maximum output load current, I , is the peak OUT(MAX) The magnetics vendors specify either the saturation cur- inductor current minus half the peak-to-peak ripple cur- rent, the RMS current or both. When selecting an inductor rent, ∆I . L based on inductor saturation current, use the peak cur- Allowing adequate margin for ripple current and external rent through the inductor, I + ∆I /2. The inductor OUT(MAX) L component tolerances, R can be calculated as fol- saturation current specification is the current at which SENSE lows: the inductance, measured at zero current, decreases by 100mV a specified amount, typically 30%. R = SENSE I OUT(MAX) When selecting an inductor based on RMS current rating, use the average current through the inductor, I . Typical values for R are in the range of 0.005Ω OUT(MAX) SENSE The RMS current specification is the RMS current at which to 0.05Ω. the part has a specific temperature rise, typically 40°C, Inductor Selection above 25°C ambient. The critical parameters for selection of an inductor are After calculating the minimum inductance value, the volt- minimum inductance value, volt-second product, satura- second product, the saturation current and the RMS current tion current and/or RMS current. for your design, select an off-the-shelf inductor. A list of The minimum inductance value is calculated as follows: magnetics vendors can be found at www.linear.com, or contact the Linear Technology Application Department. V –V IN(MAX) OUT L≥V • For more detailed information on selecting an inductor, OUT f •V •∆I SW IN(MAX) L please see the “Inductor Selection” section of Linear Technology Application Note 44. f is the switch frequency (200kHz). SW The typical range of values for ∆I is (0.2 • I ) to Step-Down Converter: MOSFET Selection L OUT(MAX) (0.5 • I ), where I is the maximum load OUT(MAX) OUT(MAX) The selection criteria of the external N-channel standard current of the supply. Using ∆I = 0.3 • I yields a L OUT(MAX) level power MOSFET include on resistance(R ), re- DS(ON) good design compromise between inductor performance verse transfer capacitance (C ), maximum drain source RSS versus inductor size and cost. Higher values of ∆I will L voltage (V ), total gate charge (Q ), and maximum DSS G increase the peak currents, requiring more filtering on continuous drain current. the input and output of the supply. If ∆I is too high, L the slope compensation circuit is ineffective and current 3724fd 12

LT3724 APPLICATIONS INFORMATION For maximum efficiency, minimize R and C . The internal V regulator operating range limits the maxi- DS(ON) RSS CC Low R minimizes conduction losses while low C mum total MOSFET gate charge, Q , to 90nC. The Q vs DS(ON) RSS G G minimizes transition losses. The problem is that R is V specification is typically provided in the MOSFET data DS(ON) GS inversely related to C . Balancing the transition losses sheet. Use Q at V of 8V. If V is back driven from an RSS G GS CC with the conduction losses is a good idea in sizing the external supply, the MOSFET drive current is not sourced MOSFET. Select the MOSFET to balance the two losses. from the internal regulator of the LT3724 and the Q of the G MOSFET is not limited by the IC. However, note that the Calculate the maximum conduction losses of the MOSFET: MOSFET drive current is supplied by the internal regulator  V  when the external supply back driving V is not available P =(I )2 OUT (R ) CC COND OUT(MAX)   DS(ON) such as during startup or short-circuit.  V  IN The manufacturer’s maximum continuous drain current Note that R has a large positive temperature depen- DS(ON) specification should exceed the peak switch current, dence. The MOSFET manufacturer’s data sheet contains a I + ∆I /2. OUT(MAX) L curve, R vs Temperature. DS(ON) During the supply startup, the gate drive levels are set by Calculate the maximum transition losses: the V voltage regulator, which is approximately 8V. Once CC PTRAN = (k)(VIN)2 (IOUT(MAX))(CRSS)(fSW) the supply is up and running, the VCC can be back driven by an auxiliary supply such as V . It is important not to OUT where k is a constant inversely related to the gate driver exceed the manufacturer’s maximum V specification. GS current, approximated by k = 2 for LT3724 applications. A standard level threshold MOSFET typically has a V GS The total maximum power dissipation of the MOSFET is maximum of 20V. the sum of these two loss terms: Step-Down Converter: Rectifier Selection P = P + P FET(TOTAL) COND TRAN The rectifier diode (D1 on the Functional Diagram) in a To achieve high supply efficiency, keep the P to FET(TOTAL) buck converter generates a current path for the inductor less than 3% of the total output power. Also, complete current when the main power switch is turned off. The a thermal analysis to ensure that the MOSFET junction rectifier is selected based upon the forward voltage, re- temperature is not exceeded. verse voltage and maximum current. A Schottky diode is T = T + P • θ recommended. Its low forward voltage yields the lowest J A FET(TOTAL) JA power loss and highest efficiency. The maximum reverse where θ is the package thermal resistance and T is the JA A voltage that the diode will see is V . ambient temperature. Keep the calculated T below the IN(MAX) J maximum specified junction temperature, typically 150°C. In continuous mode operation, the average diode cur- rent is calculated at maximum output load current and Note that when V is high, the transition losses may IN maximum V : dominate. A MOSFET with higher R and lower C IN DS(ON) RSS may provide higher efficiency. MOSFETs with higher volt- V −V IN(MAX) OUT I =I age VDSS specification usually have higher RDS(ON) and DIODE(AVG) OUT(MAX) V lower C . IN(MAX) RSS Choose the MOSFET V specification to exceed the To improve efficiency and to provide adequate margin for DSS maximum voltage across the drain to the source of the short-circuit operation, a diode rated at 1.5 to 2 times the MOSFET, which is V plus any additional ringing maximum average diode current, I , is recom- IN(MAX) DIODE(AVG) on the switch node. Ringing on the switch node can be mended. greatly reduced with good PCB layout and, if necessary, an RC snubber. 3724fd 13

LT3724 APPLICATIONS INFORMATION Step-Down Converter: Input Capacitor Selection Step-Down Converter: Output Capacitor Selection A local input bypass capacitor is required for buck convert- The output capacitance, C , selection is based on the OUT ers because the input current is pulsed with fast rise and design’s output voltage ripple, ∆V , and transient load OUT fall times. The input capacitor selection criteria are based requirements. ∆V is a function of ∆I and the C OUT L OUT on the bulk capacitance and RMS current capability. The ESR. It is calculated by: bulk capacitance will determine the supply input ripple  1  voltage. The RMS current capability is used to keep from ∆V =∆I • ESR+ OUT L   overheating the capacitor.  (8•f •C ) SW OUT The bulk capacitance is calculated based on maximum The maximum ESR required to meet a ∆V design OUT input ripple, ∆V : IN requirement can be calculated by: I •V OUT(MAX) OUT (∆V )(L)(f ) CIN(BULK)= ESR(MAX)= OUT SW ∆V •f •V IN SW IN(MIN)  V  V • 1– OUT OUT   V ∆V is typically chosen at a level acceptable to the user.  IN(MAX) IN 100mV-200mV is a good starting point. Aluminum elec- trolytic capacitors are a good choice for high voltage, bulk Worst-case ∆VOUT occurs at highest input voltage. Use capacitance due to their high capacitance per unit area. paralleled multiple capacitors to meet the ESR require- ments. Increasing the inductance is an option to lower the The capacitor’s RMS current is: ESR requirements. For extremely low ∆V , an additional OUT LC filter stage can be added to the output of the supply. V (V – V ) OUT IN OUT ICIN(RMS)=IOUT 2 Application Note 44 has some good tips on sizing an ad- (V ) IN ditional output filter. If applicable, calculate it at the worst case condition, Output Voltage Programming V = 2V . The RMS current rating of the capacitor IN OUT is specified by the manufacturer and should exceed the A resistive divider sets the DC output voltage according calculated I . Due to their low ESR (Equivalent to the following formula: CIN(RMS) Series Resistance), ceramic capacitors are a good choice  V  for high voltage, high RMS current handling. Note that the R2=R1 OUT –1 1.231V  ripple current ratings from aluminum electrolytic capacitor manufacturers are based on 2000 hours of life. This makes The external resistor divider is connected to the output it advisable to further derate the capacitor or to choose a of the converter as shown in Figure 2. Tolerance of the capacitor rated at a higher temperature than required. feedback resistors will add additional error to the output The combination of aluminum electrolytic capacitors and voltage. ceramic capacitors is an economical approach to meet- Example: V = 12V; R1 = 10kΩ OUT ing the input capacitor requirements. The capacitor volt- age rating must be rated greater than V . Multiple  12V  IN(MAX) R2=10kΩ −1 =87.48kΩ−use 86.6kΩ1%   capacitors may also be paralleled to meet size or height 1.231V  requirements in the design. Locate the capacitor very close to the MOSFET switch and use short, wide PCB traces to minimize parasitic inductance. 3724fd 14

LT3724 APPLICATIONS INFORMATION L1 VSUPPLY VOUT RA R2 COUT SHDN PIN VFB PIN RB R1 3724 F03 3724 F02 Figure 2. Output Voltage Feedback Divider Figure 3. Undervoltage Lockout Circuit The V pin input bias current is typically 25nA, so use If additional hysteresis is desired for the enable function, FB of extremely high value feedback resistors could cause a an external positive feedback resistor can be used from converter output that is slightly higher than expected. Bias the LT3724 regulator output. current error at the output can be estimated as: The shutdown function can be disabled by connecting the ∆V = 25nA • R2 SHDN pin to the V through a large value pull-up resistor. OUT(BIAS) IN This pin contains a low impedance clamp at 6V, so the SHDN Supply UVLO and Shutdown pin will sink current from the pull-up resistor(R ): PU The SHDN pin has a precision voltage threshold with V –6V I = IN hysteresis which can be used as an undervoltage lockout SHDN R threshold (UVLO) for the power supply. Undervoltage PU lockout keeps the LT3724 in shutdown until the supply Because this arrangement will clamp the SHDN pin to the input voltage is above a certain voltage programmed by 6V, it will violate the 5V absolute maximum voltage rating of the user. The hysteresis voltage prevents noise from falsely the pin. This is permitted, however, as long as the absolute tripping UVLO. maximum input current rating of 1mA is not exceeded. Resistors are chosen by first selecting RB. Then: Input SHDN pin currents of <100µA are recommended: a 1MΩ or greater pull-up resistor is typically used for this RA=RB•⎛ VSUPPLY(ON) –1⎞ configuration. ⎜ ⎟ ⎝ 1.35V ⎠ Soft-Start V is the input voltage at which the undervoltage SUPPLY(ON) The soft-start function forces the programmed slew rate lockout is disabled and the supply turns on. while the converter output rises to 95% of regulation, Example: Select RB = 49.9kΩ, V = 14.5V (based which corresponds to 1.185V on the V pin. Once 95% SUPPLY(ON) FB on a 15V minimum input voltage) regulation is achieved, the soft-start circuit is disabled. The soft-start circuit will re-enable when the V pin drops ⎛14.5V ⎞ FB RA=49.9kΩ• –1 below 70% of regulation, which corresponds to 300mV ⎜ ⎟ ⎝1.35V ⎠ of control hysteresis on the V pin. This allows for a FB controlled recovery from a “brown-out” condition. = 486.1kΩ (499kΩ resistor is selected) If low supply current in standby mode is required, select CSS1 LT3724 a higher value of RB. A RSS VOUT CSS The supply turn off voltage is 9% below turn on. In the example the V would be 13.2V. SUPPLY(OFF) 3724 F04 Figure 4.Soft-Start Circuit 3724fd 15

LT3724 APPLICATIONS INFORMATION The desired soft-start rise time (t ) is programmed via SS a programming capacitor CSS1, using a value that cor- VOUT responds to 2µA average current during the soft-start interval. This capacitor value follows the relation: –6 2•10 •t CSS1= SS VOUT(SS) VOUT V(VC) R is typically set to 200k for most applications. SS TIME, 250µs/DIV 3724 F05 Considerations for Low-Voltage Output Applications Figure 5. Soft-Start Characteristic Showing Excessive Ripple Component The LT3724 C pin biases to 220mV during the soft-start SS cycle, and this voltage is increased at Figure 4 node “A” by the 2µA signal current through R , so the output has to SS reach this value before the soft-start function is engaged. VOUT The value of this output soft-start startup voltage offset (V ) follows the relation: OUT(SS) V = 220mV + R • 2 • 10–6 OUT(SS) SS VOUT(SS) Which is typically 0.64V for RSS = 200k. V(VC) In some low voltage output applications, it may be desir- TIME, 250µs/DIV able to reduce the value of this soft-start startup voltage 3724F06 offset. This is possible by reducing the value of R . With SS Figure 6. Desirable Soft-Start Characteristic reduced values of R , the signal component caused by SS voltage ripple on the output must be minimized for proper This is typically accomplished by increasing output capaci- soft-start operation. tance and/or reducing output capacitor ESR. Peak-to-peak output voltage ripple (∆V ) will be imposed OUT on node “A” through the capacitor C . The value of R External Current Limit Foldback Circuit SS1 SS can be set using the following equation: An additional startup voltage offset can occur during the period before the LT3724 soft-start circuit becomes ac- ∆V RSS = OUT–6 tive. Before the soft-start circuit throttles back the VC pin 1.3•10 in response to the rising output voltage, current as high as the peak programmed current limit (I ) can flow in It is important to use low ESR output capacitors for LT3724 MAX the switched inductor. Switching will stop once the soft- voltage converter designs to minimize this ripple voltage start circuit takes hold and reduces the voltage on the component. A design with an excessive ripple component V pin, but the output voltage will continue to increase can be evidenced by observing the V pin during the start C C as the stored energy in the inductor is transferred to the cycle. output capacitor. With I in the inductor, the resulting MAX The soft-start cycle should be evaluated to verify that the leading-edge rise on V due to energy stored in the OUT reduced R value allows operation without excessive SS inductor follows the relation: modulation of the V pin before finalizing the design. C 1/2 If V pin has an excessive ripple component during the  L  C ∆V =I • OUT MAX   soft-start cycle, converter output ripple should be reduced. C  OUT 3724fd 16

LT3724 APPLICATIONS INFORMATION Inductor current typically does not reach I in the few MAX VC cycles that occur before soft-start becomes active, but can 1N4148 with high input voltages or small inductors, so the above relation is useful as a worst-case scenario. 1N4148 This energy transfer increase in output voltage is typically 39k 27k small, but for some low voltage applications with relatively small output capacitors, it can become significant. The volt- age rise can be reduced by increasing output capacitance, VOUT 3724 F07 which puts additional limitations on C for these low OUT voltage supplies. Another approach is to add an external Figure 8. Current Limit Foldback Circuit for Applications that have Soft-Start Disabled (C Pin Shorted to SGND) current limit foldback circuit which reduces the value of SS I during start-up. MAX Efficiency Considerations An external current limit foldback circuit can be easily incorporated into an LT3724 DC/DC converter application The efficiency of a switching regulator is equal to the output by placing a 1N4148 diode and a 47kΩ resistor from the power divided by the input power times 100%. Express converter output (V ) to the LT3724’s V pin. This limits percent efficiency as: OUT C the peak current to 0.25 • I when V = 0V. A cur- MAX OUT % Efficiency = 100% - (L1 + L2 + L3 + ...) rent limit foldback circuit also has the added advantage of where L1, L2, etc. are individual loss terms as a percent- providing reduced output current in the DC/DC converter age of input power. during short-circuit fault conditions, so a foldback circuit may be useful even if the soft-start function is disabled. Although all dissipative elements in the circuit produce losses, four main contributors usually account for most If the soft-start circuit is disabled by shorting the C pin SS of the losses in LT3724 circuits: to ground, the external current limit foldback circuit must be modified by adding an additional diode and resistor. 1. LT3724 V and V current loss IN CC The 2-diode, 2-resistor network shown also provides 0.25 2. I2R conduction losses • I when V = 0V. MAX OUT 3. MOSFET transition loss VC 4. Schottky diode conduction loss 1N4148 1. The V and V currents are the sum of the quiescent IN CC currents of the LT3724 and the MOSFET drive currents. The quiescent currents are in the LT3724 Electrical Char- 47k acteristics table. The MOSFET drive current is a result of charging the gate capacitance of the power MOSFET VOUT 3724 F03 each cycle with a packet of charge, Q . Q is found in G G the MOSFET data sheet. The average charging current is Figure 7. Current Limit Foldback Circuit for Applications that use Soft-Start calculated as Q • f . The power loss term due to these G SW currents can be reduced by backdriving V with a lower CC voltage than V such as V . IN OUT 3724fd 17

LT3724 APPLICATIONS INFORMATION 2. I2R losses are calculated from the DC resistances of the capacitor, and the ground return of the V capacitor. This CC MOSFET, the inductor, the sense resistor, and the input and ground has very fast high currents and is considered the output capacitors. In continuous conduction mode the aver- noisy ground. The two grounds are connected to each age output current flows through the inductor and R other only at the (–) terminal of V . SENSE OUT but is chopped between the MOSFET and the Schottky 2. Use short wide traces in the loop formed by the MOSFET, diode. The resistances of the MOSFET (R ) and the DS(ON) the Schottky diode and the input capacitor to minimize R multiplied by the duty cycle can be summed with SENSE high frequency noise and voltage stress from parasitic the resistances of the inductor and R to obtain the SENSE inductance. Surface mount components are preferred. total series resistance of the circuit. The total conduction power loss is proportional to this resistance and usually 3. Connect the VFB pin directly to the feedback resistors accounts for between 2% to 5% loss in efficiency. independent of any other nodes, such as the SENSE– pin. Connect the feedback resistors between the (+) and (–) 3. Transition losses of the MOSFET can be substantial with terminals of C . Locate the feedback resistors in close OUT input voltages greater than 20V. See MOSFET Selection proximity to the LT3724 to keep the high impedance node, section. V , as short as possible. FB 4. The Schottky diode can be a major contributor of power 4. Route the SENSE– and SENSE+ traces together and loss especially at high input to output voltage ratios (low keep as short as possible. duty cycles) where the diode conducts for the majority of the switch period. Lower Vf reduces the losses. Note 5. Locate the VCC and BOOST capacitors in close proximity that oversizing the diode does not always help because to the IC. These capacitors carry the MOSFET driver’s high as the diode heats up the V is reduced and the diode loss peak currents. Place the small signal components away f term is decreased. from high frequency switching nodes (BOOST, SW, and TG). In the layout shown in Figure 9, place all the small I2R losses and the Schottky diode loss dominate at high signal components on one side of the IC and all the power load currents. Other losses including C and C ESR IN OUT components on the other. This helps to keep the signal dissipative losses and inductor core losses generally ac- and power grounds separate. count for less than 2% total additional loss in efficiency. 6. A small decoupling capacitor (100pF) is sometimes PCB Layout Checklist useful for filtering high frequency noise on the feedback and sense nodes. If used, locate as close to the IC as When laying out the printed circuit board, the following possible. checklist should be used to ensure proper operation. These items are illustrated graphically in the layout diagram of 7. The LT3724 packaging will efficiently remove heat from Figure 9. the IC through the exposed pad on the backside of the part. The exposed pad is soldered to a copper footprint on the 1. Keep the signal and power grounds separate. The signal PCB. Make this footprint as large as possible to improve ground consists of the LT3724 SGND pin, the exposed pad the thermal resistance of the IC case to ambient air. This on the backside of the LT3724 IC and the (–) terminal of helps to keep the LT3724 at a lower temperature. V . The signal ground is the quiet ground and does not OUT contain any high, fast currents. The power ground consists 8. Make the trace connecting the gate of MOSFET M1 to of the Schottky diode anode, the (–) terminal of the input the TG pin of the LT3724 short and wide. 3724fd 18

LT3724 APPLICATIONS INFORMATION VIN+ RA 1 16 CBOOST CIN VIN BOOST 15 VIN– TG M1 RB 3 SHDNLT3724 SW 14 L1 RSENSE + 4 CSS 17 D2 CSS RCSS 5 12 6 BURST_EN VCC 11 CVCC COUT VOUT VFB PGND D3 D1 7 VC SENSE+ 10 R2 RC 8 SGND SENSE– 9 CC1 – R1 CC2 3724 F06 Figure 9. LT3724 Layout Diagram (See PCB Layout Checklist). Minimum On-Time Considerations 200kHz, therefore, the minimum duty cycle of the MOSFET (Step-Down Converters) switch is 6%. When the duty cycle needs to be less than 6% the output will stay regulated, but cycle skipping may Minimum on-time (t ) is the least amount of time TG(ON) occur. Cycle skipping results in an increase in inductor that the LT3724 is capable of turning the MOSFET on and ripple current. If it is important that cycle skipping does then off again. It is determined by internal timing delays not occur, follow this guideline which takes into account and the gate charge of the MOSFET. Applications with high worst case f and t : input to output differential voltages operate at low duty SW TG(ON) cycles and may approach this minimum on-time, typically V ≤ 9 • V IN(MAX) OUT 300nS. The LT3724 switching frequency is internally set to This is only an issue for supplies with V < 7V. OUT 3724fd 19

LT3724 TYPICAL APPLICATIONS 12V to 24V/50W Boost (Step-Up) Converter D1 RSENSE BAV99 0.015Ω 8V TO1V6IVN 1 VIN BOOST 16 32C35INµVF 1×52C010pF 02.51RVµCFSS R4.37M3 SHDNLT3724 STWG 1154 L1S10µBHMD2540 24VV AOTU T50W 200k 4 CSS R1827k 5 BURST_EN VCC 12 M1 3C3O0UµTF1 C2.O2UµTF2 x3 6 11 C4 35V 50V VFB PGND 1µF 25V 7 VC SENSE+ 10 R1 R6 10k C1220pF 40.2k 8 SGND SENSE– 9 LC1IN = = V SISAHNAYYO, ,I 2H5LSPV-5P03530MFD-011 C3 M1 = SILICONIX, Si7370DP 4700pF COUT1 = SANYO, 35CV330AXA COUT2 = TDK, C4532X7R1H225K D2 = DIODESINC., SBM540 3724 TA02 RSENSE = IRC LRF2512-01-R0I5-F Efficiency and Power Loss vs Load Current 100 3.0 LOSS VIN = 12V 98 2.5 %) 96 VIN = 16V 2.0 POW NCY ( 94 VIN = 12V 1.5 ER L E O EFFICI 92 VIN = 8V 1.0 SS (W) 90 0.5 88 0 0.1 1 10 LOAD CURRENT (A) 3724 F08 3724fd 20

LT3724 TYPICAL APPLICATIONS High Voltage LED Driver with Dimmer Control LED L1 300µH VIN 8V TO 60V C1 CIN (OPTIONAL) 22µF 1 16 D1 VIN BOOST B170 R1 15 M1 TG OPTIONAL 4.7M LT3724 ZXMN10A07F DIMMER 3 14 SHDN SW CONTROL CVCC M2 4 1µF 2N7002 CSS 16V 1kHz 5 12 BURST_EN VCC 6 11 ADJUST ILED: VFB PGND ILED = 0.15V CC1IN = = O TPDTKIO, CN4A5L3 T2OX 7RRE2DAU2C2E5 KLED RIPPLE CURRENT 7 VC SENSE+ 10 RSENSE DM11 == DZIEOTDEEXS, IZNXCM.,N B1107A007F C1 8 SGND SENSE– 9 R0.S5EΩNSE RSENSE = VISHAY, WSL2010R0150FEA 100pF L1 = COILTRONICS, CTX300-4 3724 TA03 3724fd 21

LT3724 TYPICAL APPLICATIONS 4.5V to 20V Input to 12V at 25W Output SEPIC Converter with 60V Input Transient Capability VIN 4.5V TO 20V TO 60V C22INµ1F C25INV2 D1B L1• TRANSIENT 2x 1µF RA GSD2004 20µH 1 16 25V 100k VIN BOOST C5 C7 22µF C1 3 SHDN TG 15 0.1µF M1 235xV D2 12VV AOTU T25W 390pF 49R.B9k 2R003k LT3724 SW 14 4 R6 R2 5 CBSUSRST_EN VCC 12 10Ω L1 C33O0UµTF1 130k C4 20µH 16V 6 11 1µF C6 • 7 VVFCB SEPNGSNED+ 10 25V 5R67pF R0.S0E1N0SΩE C2O2UµTF2 R141.7k 4R74k C2 R405.2k 8 SGND SENSE– 9 10Ω 25V 120pF D1A C3 GSD2004 3724 TA07a 680pF D3 C5, CIN1, COUT2 = TDKC453X7R1E226M D1N4148 COUT1 = SANYO, OS-CON 16SVP330M D2 = ON SEMI, MBRD660 L1 = COILCRAFT VERSAPAC VP5-D83 M1 = VISHAY, Si7852DP Efficiency and Power Loss vs Load Current 92 3.5 VIN = 20V 91 3.0 VIN = 15V 90 2.5 P NCY (%) 89 VIN = 10V 2.0 OWER L E O EFFICI 88 1.5 SS (W 87 LOSS 1.0 ) VIN = 15V 86 0.5 85 0 0.1 1 10 LOAD CURRENT (A) 3724 TA07b 3724fd 22

LT3724 TYPICAL APPLICATIONS 12V Step-Down with V Back Driven from V and Ceramic Capacitor in Output Filter CC OUT VIN 15V TO 60V + C6 CIN 2.2µF x2 0.1µF 100µF 100V R2 16V 100V 1 16 499k VIN BOOST R3 R7 49.9k 3 15 20Ω M1 SHDN TG Si7852DP C1 14 SW 3300pF RCSS 4 LT3724 CSS D2A VOUT 200k BAV99 12V AT 50W R1340k 5 BURST_EN VCC 12 C4 47Lµ1H 0.02R0SΩENSE 6 11 1µF 7 VVFCB SEPNGSNED+ 10 16V DBA2VB99 D1 C3136OµVUFT x3 R5 R6 8 9 14.7k C2 15k SGND SENSE– 120pF C3 680pF CIN: TDK, C4532X7R2A225MT 3724 TA04 COUT: TDK, C4532X7R1C336MT D1: DIODESINC., PDS5100H L1: COEV DU1971-470M M1: VISHAY Si7852DP 3724fd 23

LT3724 PACKAGE DESCRIPTION FE Package 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev I) Exposed Pad Variation BC 4.90 – 5.10* 3.58 (.193 – .201) 0.48 (.141) 3.58 (.019) (.141) REF 16 1514131211 109 6.60 ±0.10 2.94 0.51 4.50 ±0.10 (.116) DETAIL B (.020) 6.40 REF SEE NOTE 4 2.94 (.252) (.116) DETAIL B IS THE PART OF 0.45 ±0.05 BSC THE LEAD FRAME FEATURE FOR REFERENCE ONLY 1.05 ±0.10 NO MEASUREMENT PURPOSE 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 1.10 4.30 – 4.50* (.0433) (.169 – .177) 0.25 MAX REF 0° – 8° 0.65 0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15 (.0035 – .0079) (.020 – .030) BSC (.002 – .006) 0.195 – 0.30 (.0077 – .0118) FE16 (BC) TSSOP REV I 1210 TYP NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE MILLIMETERS FOR EXPOSED PAD ATTACHMENT 2. DIMENSIONS ARE IN (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH 3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3724fd 24 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LT3724 REVISION HISTORY (Revision history begins at Rev D) REV DATE DESCRIPTION PAGE NUMBER D 3/11 Deleted last paragraph of Description 1 Minor text edits made to SW and BOOST pin descriptions in Pin Functions section 7 Minor text edits made to Main Control Loop and Current Limit/Short Circuit sections in Operations 9 Revised High Voltage LED Driver with Dimmer Control in Typical Applications 21 Revised Typical Application drawing and Related Parts list 24 3724fd 25

LT3724 TYPICAL APPLICATION Inverting –12V 1.5A Converter VIN 18V TO 36V R2M3 1 VIN BOOST 16 01.61VµF + 2C2IN01µF 50V 0.1µF LT3724 TG 15 M1 L1 47µH 3 14 SHDN SW 4 CSS RCSS CSS 12 D1A D1B D2 1000pF 200k VCC R1 1µF 88.7k 6 11 16V VOUT R6, 40.2k 7 VFB PGND –11.52AV 10.R22k 68C0pCF2 12C0pCF1 8 VGCND SSEENNSSEE+– 190 0R.S0E4N0SΩE + C3136O0VUµTF1 D1 = BAV99 D2 = ON SEMI, MBRD350 L1 = COEV, DU1311-470M 3724 TA05 M1 = VISHAY, Si7370DP CIN1 = SANYO, 50CV220KX COUT1 = SANYO, 16SVP330M RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT3845A 60V, Low I , High Voltage Synchronous Adjustable Fixed Frequency 100kHz to 500kHz, 4V≤ V ≤ 60V, 1.23V ≤ Q IN Step-Down DC/DC Controller V ≤ 36V, I = 120µA, TSSOP-16 OUT Q LTC3891 60V, Low I , High Voltage Synchronous Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V, 0.8V Q IN Step-Down DC/DC Controller ≤ V ≤ 24V, I = 50µA OUT Q LT3844 60V, Low I , Single Output Step-Down Synchronizable Fixed Frequency 50kHz to 600kHz, 4V≤ V ≤ 60V, 1.23V Q IN DC/DC Controller ≤ V ≤ 36V, I = 120µA, TSSOP-16 OUT Q LT3741 High Power, Constant Current, Constant Voltage, Fixed 200kHz to 1MHz Operating Frequency, ±6% Current Regulation, Step-Down Controller 6V≤ V ≤ 36V, V Up to (V - 2V) IN OUT IN LTC3824 60V, Low I , Step-Down DC/DC Controller with Selectable Fixed Frequency 200kHz to 600kHz, 4V≤ V ≤ 60V, 0.8V ≤ Q IN 100% Duty Cycle V ≤ V , I = 40µA, MSOP-10E OUT IN Q LTC3834/LTC3834-1 Low I , Single Output Synchronous Step-Down Phase-Lockable Fixed Frequency 140kHz to 650kHz, 4V≤ V ≤ 36V, 0.8V Q IN LTC3835/LTC3835-1 DC/DC Controller with 99% Duty Cycle ≤ V ≤ 10V, I = 30µA/80µA OUT Q LTC3859 Low I , Triple Output Buck/Buck/Boost All Outputs Remain in Regulation Through Cold Crank 2.5V≤ V ≤ 38V, Q IN Synchronous DC/DC Controller V Up to 24V, V Up to 60V, I = 55µA OUT(BUCKS) OUT(BOOST) Q 3724fd 26 Linear Technology Corporation LT 0311 REV D • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2005