LT3055 Series 500mA, Linear Regulator with Precision Current Limit and Diagnostics FEATURES DESCRIPTION n Output Current: 500mA The LT®3055 series are micropower, low noise, low dropout n Dropout Voltage: 350mV voltage (LDO) linear regulators. The devices supply 500mA n Input Voltage Range: 1.6V to 45V of output current with a dropout voltage of 350mV. A 10nF n Programmable Precision Current Limit: ±10% bypass capacitor reduces output noise to 25μV in a RMS n Output Current Monitor: 1/500th of IOUT 10Hz to 100kHz bandwidth and soft starts the reference. n Programmable Minimum IOUT Monitor The LT3055’s ±45V input voltage rating combined with its n Temperature Monitor: 10mV/°C precision current limit and diagnostic functions make the n FAULT Indicator: Current Limit, Thermal Limit or IC an ideal choice for robust, high reliability applications. Minimum I OUT A single resistor programs the LT3055’s current limit, ac- n Low Noise: 25μV (10Hz to 100kHz) RMS curate to ±10% over a wide input voltage and temperature n Adjustable Output (V = V = 0.6V) REF OUT(MIN) range. Another resistor programs the LT3055’s minimum n Output Tolerance: ±2% Over Load, Line and Temperature output current monitor, useful for detecting open-circuit n Stable with Low ESR, Ceramic Output Capacitors conditions. The current monitor function sources a current (3.3μF Minimum) equal to 1/500th of output current. Logic fault pins assert n Shutdown Current: <1μA low if the LT3055 is in current limit (FAULT2), operating n Reverse Battery and Thermal Limit Protection below its minimum output current (FAULT1) or is in thermal n 16-Lead 4mm × 3mm DFN and MSOP Packages limit (both FAULT1 and FAULT2). PWRGD indicates output APPLICATIONS regulation. The TEMP pin indicates average die temperature. The LT3055 optimizes stability and transient response n Protected Antenna Supplies with low ESR ceramic capacitors, requiring a minimum of n Automotive Telematics 3.3μF. Internal protection circuitry includes current limit- n Industrial Applications (Trucks, Forklifts, etc.) ing, thermal limiting, reverse battery protection, reverse n High Reliability Applications current protection and reverse output protection. n Noise-Sensitive RF or DSP Supplies The LT3055 is available in fixed output voltages of 3.3V All registered trademarks and trademarks are the property of their respective owners. and 5V, and as an adjustable device with an output voltage range from 0.6V to 40V. TYPICAL APPLICATION Precision Current Limit, R = 604Ω IMAX 5V Supply with 497mA Precision Current Limit, 10mA IMIN mA)555400 VOUT(NOMINAL) = 5V V6IVN+ 10µF 200k 200k 200k ISNHDLNT3055S-E5ONUSTE 10nF 10µF 5V HRESHOLD (555132000 FFAAUULLTT12 ADJ ULT T500 VIN = 7V A 22nF 6(T0H4RΩESHOLD = 497mA) IPMWARXGD IMON 1(FAUkDLCL- SCALE = 1V) 0.1µF TµAOPDC RENT LIMIT F444978000 VIN = 5.6V TO UR460 TEMP µP C IMIN REF/BYP ADC 450–75–50–25 0 25 50 75 100125150175 0.1µF 1(T2H0RkESHOLD = 10mA) GND 10nF TEMPERATURE (°C) 3055 TA01a 3055 TA01b Rev. B 1 Document Feedback For more information www.analog.com

LT3055 Series ABSOLUTE MAXIMUM RATINGS (Note 1) IN Pin Voltage .........................................................±50V TEMP Pin Voltage ............................................–0.3V, 7V OUT Pin Voltage ...........................................+40V, –50V REF/BYP Pin Voltage ...................................................1V Input-to-Output Differential Voltage ..............+50V, –40V Output Short-Circuit Duration ..........................Indefinite ADJ Pin Voltage ......................................................±50V Operating Junction Temperature Range (Notes 2, 3) SENSE Pin Voltage ..................................................±50V E-, I-Grades .......................................–40°C to 125°C SHDN Pin Voltage ...................................................±50V MP-Grade ..........................................–55°C to 150°C FAULT1, FAULT2, PWRGD Pin Voltage ............–0.3V, 50V H-Grade .............................................–40°C to 150°C I Pin Voltage ..............................................–0.3V, 7V Storage Temperature Range ..................–65°C to 150°C MON I Pin Voltage ...............................................–0.3V, 7V Lead Temperature: (Soldering, 10 sec) MIN I Pin Voltage ..............................................–0.3V, 7V MSOP Package Only .........................................300°C MAX PIN CONFIGURATION TOP VIEW TOP VIEW IN 1 16 OUT IN 1 16 OUT IN 2 15 OUT IN 2 15 OUT SHDN 3 14 ADJ/SENSE** SHDN 3 14 ADJ/SENSE** FAULT1 4 17 13 GND/ADJ* FAULT1 4 17 13 GND/ADJ* FAULT2 5 GND 12 GND PWRGD 6 11 REF/BYP FAULT2 5 GND 12 GND TEMP 7 10 IMAX PWRGD 6 11 REF/BYP IMON 8 9 IMIN TEMP 7 10 IMAX MSE PACKAGE IMON 8 9 IMIN 16-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 37°C/W, θJC = 5°C/W TO 10°C/W DE PACKAGE TJMAX = 150°C FOR H-GRADE 16-LEAD (4mm × 3mm) PLASTIC DFN EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 38°C/W, θJC = 4.3°C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB *PIN 13 IS GND FOR LT3055; PIN 13 IS ADJ FOR LT3055-3.3 AND LT3055-5. **PIN 14 IS ADJ FOR LT3055; PIN 14 IS SENSE FOR LT3055-3.3 AND LT3055-5. Rev. B 2 For more information www.analog.com

LT3055 Series ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3055EMSE#PBF LT3055EMSE#TRPBF 3055 16-Lead Plastic MSOP –40°C to 125°C LT3055IMSE#PBF LT3055IMSE#TRPBF 3055 16-Lead Plastic MSOP –40°C to 125°C LT3055MPMSE#PBF LT3055MPMSE#TRPBF 3055 16-Lead Plastic MSOP –55°C to 150°C LT3055HMSE#PBF LT3055HMSE#TRPBF 3055 16-Lead Plastic MSOP –40°C to 150°C LT3055EMSE-3.3#PBF LT3055EMSE-3.3#TRPBF 305533 16-Lead Plastic MSOP –40°C to 125°C LT3055IMSE-3.3#PBF LT3055IMSE-3.3#TRPBF 305533 16-Lead Plastic MSOP –40°C to 125°C LT3055MPMSE-3.3#PBF LT3055MPMSE-3.3#TRPBF 305533 16-Lead Plastic MSOP –55°C to 150°C LT3055HMSE-3.3#PBF LT3055HMSE-3.3#TRPBF 305533 16-Lead Plastic MSOP –40°C to 150°C LT3055EMSE-5#PBF LT3055EMSE-5#TRPBF 30555 16-Lead Plastic MSOP –40°C to 125°C LT3055IMSE-5#PBF LT3055IMSE-5#TRPBF 30555 16-Lead Plastic MSOP –40°C to 125°C LT3055MPMSE-5#PBF LT3055MPMSE-5#TRPBF 30555 16-Lead Plastic MSOP –55°C to 150°C LT3055HMSE-5#PBF LT3055HMSE-5#TRPBF 30555 16-Lead Plastic MSOP –40°C to 150°C LT3055EDE#PBF LT3055EDE#TRPBF 3055 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C LT3055IDE#PBF LT3055IDE#TRPBF 3055 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C LT3055EDE-3.3#PBF LT3055EDE-3.3#TRPBF 05533 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C LT3055IDE-3.3#PBF LT3055IDE-3.3#TRPBF 05533 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C LT3055EDE-5#PBF LT3055EDE-5#TRPBF 30555 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C LT3055IDE-5#PBF LT3055IDE-5#TRPBF 30555 16-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix Rev. B 3 For more information www.analog.com

LT3055 Series ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 2) A PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum Input Voltage (Notes 3, 11, 17) I = 500mA l 1.6 2.2 V LOAD Regulated Output Voltage (Note 4) LT3055-3.3: V = 3.9V, I = 1mA 3.267 3.3 3.333 V IN LOAD 3.9V < V < 45V, 1mA < I < 500mA l 3.234 3.3 3.336 V IN LOAD LT3055-5: V = 3.9V, I = 1mA 4.95 5 5.05 V IN LOAD 5.6V < V < 45V, 1mA < I < 500mA l 4.9 5 5.1 V IN LOAD ADJ Pin Voltage (Notes 3, 4) LT3055: V = 2.2V, I = 1mA 594 600 606 mV IN LOAD 2.2V < V < 45V, 10mA < I < 500mA l 588 612 mV IN LOAD Line Regulation (Note 3) LT3055: ∆VIN = 2.2V to 45V, ILOAD = 1mA l 0.25 3 mV LT3055-3.3: ∆VIN = 3.9V to 45V, ILOAD = 1mA l 1.4 19.5 mV LT3055-5: ∆VIN = 5.6V to 45V, ILOAD = 1mA l 2 30 mV Load Regulation (Note 3) LT3055: V = 2.2V, I = 1mA to 500mA l 0.5 4 mV IN LOAD LT3055-3.3: V = 4.3V, I = 1mA to 500mA l 3.5 22 mV IN LOAD LT3055-5: V = 6V, I = 1mA to 500mA l 5.25 33 mV IN LOAD Dropout Voltage, V = V (Notes 5, 6) I = 10mA 140 175 mV IN OUT(NOMINAL) LOAD l 260 mV I = 50mA 200 250 mV LOAD l 370 mV I = 100mA 225 275 mV LOAD l 410 mV I = 500mA 350 400 mV LOAD l 590 mV GND Pin Current, V = V + 0.6V I = 0mA l 65 130 μA IN OUT(NOMINAL) LOAD (Notes 6, 7) I = 1mA l 100 200 μA LOAD I = 10mA l 270 550 μA LOAD I = 100mA l 1.8 4.5 mA LOAD I = 500mA l 11 25 mA LOAD Quiescent Current in Shutdown V = 45V, V = 0V 0.2 1 μA IN SHDN ADJ Pin Bias Current (Notes 3,12) V = 12V l 16 60 nA IN Output Voltage Noise C = 10µF, I = 500mA, V = 600mV, 90 μV OUT LOAD OUT RMS BW = 10Hz to 100kHz C = 10µF, C = 10nF, I = 500mA, 25 μV OUT BYP LOAD RMS V = 600mV, BW = 10Hz to 100kHz OUT Shutdown Threshold V = Off to On l 1.3 1.42 V OUT V = On to Off l 0.9 1.1 V OUT SHDN Pin Current (Note 13) V = 0V, V = 45V l 1 μA SHDN IN V = 45V, V = 45V l 0.5 3 µA SHDN IN Ripple Rejection V -V = 2V, V = 0.5V , f = 120Hz, IN OUT RIPPLE P-P RIPPLE I = 500mA LOAD LT3055, V = 0.6V 70 85 dB OUT LT3055-3.3 55 70 dB LT3055-5 51 66 dB Input Reverse Leakage Current V = –45V, V = 0 l 300 μA IN OUT Reverse Output Current (Note 14) V = 1.2V, V = 0 0 10 μA OUT IN Internal Current Limit (Note 3) V = 2.2V, V = 0, V = 0 900 mA IN OUT IMAX VIN = 2.2V, ∆VOUT = –5% l 520 mA External Programmed Current Limit, V = 5V 5.6V < V < 10V, V = 5V, R = 1.5k, l 180 200 220 mA OUT IN OUT IMAX (Notes 6, 8) FAULT2 Pin Threshold (I ) FAULT 5.6V < V < 7V, V = 5V, R = 604Ω, l 445 495 545 mA IN OUT IMAX FAULT2 Pin Threshold (I ) FAULT Rev. B 4 For more information www.analog.com

LT3055 Series ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C. (Note 2) A PARAMETER CONDITIONS MIN TYP MAX UNITS FAULT, PWRGD Pins Logic Low Voltage Pull-Up Current = 50μA l 0.14 0.25 V FAULT, PWRGD Pins Leakage Current V , V , V = 5V 0.01 1 μA FAULT1 FAULT2 PWRGD I Threshold Accuracy (Notes 6, 9) 5.6V < V < 15V, V = 5V, R = 1.2M l 0.9 1 1.1 mA MIN IN OUT IMIN 5.6V < V < 15V, V = 5V, R = 120K l 9 10 11 mA IN OUT IMIN PWRGD Trip Point % of Nominal Output Voltage, Output Rising l 86 90 94 % PWRGD Trip Point Hysteresis % of Nominal Output Voltage 1 % Current Monitor Ratio (Notes 6,10), Ratio = I /I I = 10mA, 250mA, 500mA l 450 500 550 mA/mA OUT MON LOAD TEMP Voltage (Note 16) T = 25°C 0.25 V J T = 125°C 1.25 V J TEMP Error (Note 16) l –0.08 0.08 V Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 8: Current limit varies inversely with the external resistor value tied may cause permanent damage to the device. Exposure to any Absolute from the I pin to GND. For detailed information on how to set the I MAX MAX Maximum Rating condition for extended periods may affect device pin resistor value, please see the Operation section. If a programmed reliability and lifetime. Absolute maximum input-to-output differential current limit is not needed, tie the I pin to GND and internal protection MAX voltage is not achievable with all combinations of rated IN pin and OUT pin circuitry implements short-circuit protection as specified. voltages. With the IN pin at 50V, the OUT pin may not be pulled below 0V. Note 9: The I fault condition asserts if the output current falls below the MIN The total differential voltage from IN to OUT must not exceed +50V, –40V. I threshold defined by an external resistor from the I pin to GND. MIN MIN If OUT is pulled above GND and IN, the total differential voltage from OUT For detailed information on how to set the I pin resistor value, please MIN to IN must not exceed 40V. see the Operation section. If the I fault condition is not needed, the I MIN MIN Note 2: The LT3055 is tested and specified under pulse load conditions pin must be left floating (unconnected). such that T ~ T . The LT3055E is 100% production tested at T = 25°C J A A Note 10: Current monitor ratio is tested with the I pin fixed at MON and performance is guaranteed from 0°C to 125°C. Performance at –40°C V – 0.5V and with the input range limited to V + 0.6V < V < V OUT OUT IN OUT and 125°C is assured by design, characterization and correlation with + 10V for I = 10mA; V + 0.6V < V < V + 4V for I = 250mA, OUT OUT IN OUT OUT statistical process controls. The LT3055I is guaranteed over the full –40°C and V + 0.6V < V < V + 2V for I = 500mA. Input voltage range OUT IN OUT OUT to 125°C operating junction temperature range. The LT3055MP is 100% conditions are set to limit power dissipation in the IC to 1W maximum for tested over the –55°C to 150°C operating junction temperature range. The test purposes. The current monitor ratio varies slightly when in current LT3055H is 100% tested at 150°C operating junction temperature. limit or when the I voltage exceeds V – 0.5V. Please see the MON OUT Note 3: The LT3055 adjustable version is tested and specified for these Operation section for more information. If the current monitor function is conditions with ADJ pin connected to the OUT pin. not needed, tie the IMON pin to GND. Note 4: Maximum junction temperature limits operating conditions. Note 11: To satisfy requirements for minimum input voltage, current limit Regulated output voltage specifications do not apply for all possible is tested at V = V + 1V or V = 2.2V, whichever is greater. IN OUT(NOMINAL) IN combinations of input voltage and output current. If operating at the Note 12: ADJ pin bias current flows out of the ADJ pin. maximum input voltage, limit the output current range. If operating at Note 13: SHDN pin current flows into the SHDN pin. the maximum output current, limit the input voltage range. Current limit foldback limits the maximum output current as a function of input-to- Note 14: Reverse output current is tested with the IN pin grounded and the output voltage. See Current Limit vs V -V in the Typical Performance OUT pin forced to the specified voltage. This current flows into the OUT IN OUT Characteristics section. pin and out of the GND pin. Note 5: Dropout voltage is the minimum differential IN-to-OUT voltage Note 15: 500mA of output current does not apply to the full range of input needed to maintain regulation at a specified output current. In dropout, voltage due to the internal current limit foldback. the output voltage equals (VIN – VDROPOUT). For some output voltages, Note 16: The TEMP output voltage represents the average temperature of minimum input voltage requirements limit dropout voltage. the die while dissipating quiescent power. Due to the pass device power Note 6: To satisfy minimum input voltage requirements, the LT3055 dissipation and temperature gradients across the die, the TEMP output adjustable version is tested and specified for these conditions with an voltage measurement does not guarantee that absolute maximum junction external resistor divider (60k bottom, 440k top) which sets V to 5V. The temperature is not exceeded. OUT external resistor divider adds 10μA of DC load on the output. This external Note 17: Minimum Input Voltage is the input voltage at which the output current is not factored into GND pin current. voltage is decreased 1% from nominal. At elevated temperatures, an input Note 7: GND pin current is tested with V = V + 0.6V and a voltage greater than this is necessary for correct operation of the TEMP IN OUT(NOMINAL) current source load. GND pin current increases in dropout. For the fixed pin. See Temp Pin Minimum Input Voltage in the Typical Performance output voltage versions, an internal resistor divider adds about 10µA to Characteristics section. GND pin current. See GND pin current curves in the Typical Performance Characteristics section. Rev. B 5 For more information www.analog.com

LT3055 Series TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. J Typical Dropout Voltage Guaranteed Dropout Voltage Dropout Voltage 600 700 600 = TEST POINTS 550 650 550 600 500 TJ = 150°C 500 550 mV) 450 mV)500 TJ = 150°C mV) 450 GE ( 400 TJ = 125°C GE (450 GE ( 400 IL = 500mA OLTA 330500 OLTA430500 TJ = 25°C OLTA 330500 IL = 100mA UT V 250 TJ = 25°C UT V300 UT V 250 IL = 50mA O O250 O P 200 P P 200 DRO 150 DRO210500 DRO 150 IL = 10mA 100 100 100 50 50 50 0 0 0 0 50 100150200250300350400450500 0 50 100150200250300350400450500 –75–50–25 0 25 50 75 100125150175 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) TEMPERATURE (°C) 3055 G01 3055 G02 3055 G03 Quiescent Current ADJ Pin Voltage Output Voltage–LT3055-3.3 130 612 3.366 120 610 IL = 1mA 3.355 IL = 1mA 110 608 3.344 RENT (µA) 1098000 VIN =VI LOV U=ST H1 D=0N µ5 A=V 12V GE (mV) 666000426 AGE (V)333...333213213 QUIESCENT CUR 6745300000 ADJ PIN VOLTA 655509990684 OUTPUT VOLT3333....322207860897 20 VIN = 12V 592 3.256 10 ALL OTHER PINS = 0V 590 3.245 0 588 3.234 –75–50–25 0 25 50 75 100125150175 –75–50–25 0 25 50 75 100125150175 –75–50–25 0 25 50 75 100125150175 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3055 G04 3055 G05 3055 G06 Output Voltage–LT3055-5 Quiescent Current GND Pin Current–LT3055-3.3 5.10 140 12 5.08 IL = 1mA 112300 ITLJ == 025°C 1101 RL = 6.6Ω, IL = 500mA OUTPUT VOLTAGE (V)554554......009009268046 UIESCENT CURRENT (µA)114608591700000000 LLTT33005555--35.3 GND PIN CURRENT (mA) 4683579 RL = 13.2Ω, IL = 250mA 4.94 Q 30 RL = 33Ω, IL = 100mA 2 20 4.92 10 VSHDN = 0V, RL = 0 1 RL = 330Ω, IL = 10mA 4.90 0 0 –75–50–25 0 25 50 75 100125150175 0 1 2 3 4 5 6 7 8 9 10 11 12 0 1 2 3 4 5 6 7 8 9 10 11 12 TEMPERATURE (°C) VIN (V) VIN (V) 3055 G07 3055 G08 3055 G09 Rev. B 6 For more information www.analog.com

LT3055 Series TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. J GND Pin Current–LT3055-5 GND Pin Current vs I SHDN Pin Threshold LOAD 12 20 1.5 11 RL = 10Ω, IL = 500mA 18 VVIONU =T =5 .56VV 11..43 OFF TO ON 10 16 1.2 ON TO OFF CURRENT (mA) 6879 CURRENT (mA) 111204 THRESHOLD (V) 10001.....19870 GND PIN 435 RL = 20Ω, IL = 250mA GND PIN 86 HDN PIN 000...654 2 RL = 50Ω, IL = 100mA 4 S 0.3 0.2 1 RL = 500Ω, IL = 10mA 2 0.1 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 0 50 100150200250300350400450500 –75–50–25 0 25 50 75 100125150175 VIN (V) ILOAD (mA) TEMPERATURE (°C) 3055 G10 3055 G11 3055 G12 SHDN Pin Input Current SHDN Pin Input Current ADJ Pin Bias Current 3.0 3.0 50 SHDN = 45V 45 RENT (µA) 22..05 RENT (µA) 22..05 ENT (nA) 4305 R R R 30 U U R C C U UT 1.5 UT 1.5 S C 25 P P A PIN IN 1.0 PIN IN 1.0 PIN BI 2105 SHDN 0.5 SHDN 0.5 ADJ 10 5 0 0 0 –75–50–25 0 25 50 75 100125 150175 0 5 10 15 20 25 30 35 40 45 –75–50–25 0 25 50 75 100125150175 TEMPERATURE (°C) SHDN PIN VOLTAGE (V) TEMPERATURE (°C) 3055 G13 3055 G14 3055 G15 Internal Current Limit Internal Current Limit Reverse Output Current 1.5 1.0 1.0 1.4 VIN = 6V TJ = –55°C VIN = 0 1.3 VOUT = 0V 0.9 TJ = –40°C 0.9 1.2 0.8 TJ = 25°C 0.8 MIT (A) 101...190 MIT (A) 00..76 TTJJ == 112550°°CC ENT (µA) 00..76 NT LI 00..87 NT LI 0.5 CURR 0.5 CURRE 000...654 CURRE 00..34 OUTPUT 00..34 0.3 0.2 0.2 0.2 0.1 0.1 0.1 0 0 0 –75–50–25 0 25 50 75 100125150175 0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 35 40 TEMPERATURE (°C) INPUT/OUTPUT DIFFERENTIAL (V) VOUT (V) 3055 G16 3055 G17 3055 G18 Rev. B 7 For more information www.analog.com

LT3055 Series TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. J Reverse Output Current Input Ripple Rejection Input Ripple Rejection 100 90 90 VOUT = VADJ = 1.2V CREF/BYP = 0pF COUT = 10µF 90 VIN = 0V 80 CREF/BYP = 100pF 80 COUT = 3.3µF 80 70 CREF/BYP = 10nF 70 T (µA) 70 N (dB) 60 N (dB) 60 N 60 O O URRE 50 JECTI 50 JECTI 50 UT C 40 E RE 40 E RE 40 UTP 30 PPL 30 PPL 30 O 20 IADJ RI 20 CILOOUATD == 1500µ0FmA RI 20 CILROEAFD/B =Y P5 0=0 1m0AnF 10 IOUT 10 VOUT = 3.3V 10 VOUT = 3.3V VIN = 4.3V + 50mVRMS RIPPLE VIN = 4.3V + 50mVRMS RIPPLE 0 0 0 –75–50–25 0 25 50 75 100125150175 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M TEMPERATURE (°C) FREQUENCY (Hz) FREQUENCY (Hz) 3055 G19 3055 G20 3055 G21 Input Ripple Rejection Minimum Input Voltage Load Regulation 90 2.2 16 80 2.0 ILOAD = 500mA 14 V∆IINL == 1VmOUAT T +O 1 5V0, 02m.1AV FOR LT3055 RIPPLE REJECTION (dB) 345267000000 CVILROOEUAFTD/ B ==Y 3P5. 03=0V 1m0AnF MINIMUM INPUT VOLTAGE (V) 10011011........08684462 LOAD REGULATION (mV) –11223046802 LLLTTT333000555555,-- 35V.O3UT = 0.6V 10 VIN = 4.3V + 50mVRMS RIPPLE 0.2 –4 f = 120Hz 0 0 –6 –75–50–25 0 25 50 75 100125150175 –75–50–25 0 25 50 75 100125150175 –75–50–25 0 25 50 75 100125150175 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3055 G22 3055 G23 3055 G24 Output Noise Spectral Density Output Noise Spectral Density Output Noise Spectral Density C = 0, C = 0 vs C , C = 0 vs C , C = 10nF REF/BYP FF REF/BYP FF FF REF/BYP 10 10 10 Hz) COUT = 10µF Hz) COUT = 10µF Hz) VOUT = 5V NSITY (µV/√ 1 IL = 500mA NSITY (µV/√ 1 VOUT = 5V IL = 500mA NSITY (µV/√ 1 CILO =U T5 0=0 1m0AµF DE DE DE RAL RAL VOUT = 0.6V RAL OUTPUT NOISE SPECT00.0.11 VVVVVOOOOOUUUUUTTTTT ===== 53210V....3526VVVV OUTPUT NOISE SPECT00.0.11 CCCRRREEEFFF///BBBYYYPPP === 1110n00FnpFF OUTPUT NOISE SPECT00.0.11 CCCCFFFFFFFF ==== 0111p0n0F0FnpFF 10 100 1k 10k 100k 10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) 3055 G25 3055 G26 3055 G27 Rev. B 8 For more information www.analog.com

LT3055 Series TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. J RMS Output Noise vs C , RMS Output Noise vs Load RMS Output Noise REF/BYP V = 0.6V, C = 0 Current, C = 10nF, C = 0 vs Feedforward Capacitor (C ) OUT FF REF/BYP FF FF 110 160 120 )MS19000 fC =O U1T0 H= z1 T0OµF 100kHz CREF/BYP = 0pF )MS111345000 fC =O U1T0 H= z1 T0OµF 100kHz VOUT = 5V )MS110100 VOUT = 5V CfC =RO EU1FT0/ BH=Y z1P T0 =Oµ F1 100n0FkHz GE (µVR 7800 GE (µVR111201000 VOUT = 3.3V GE (µVR 8900 VOUT = 3.3V IIFLBO-ADDIV =ID 5E0R0 =m 1A0µA LTA 60 CREF/BYP = 100pF LTA 90 LTA 70 VOUT = 2.5V SE VO 50 SE VO 7800 VOUT = 2.5V SE VO 6500 OI 40 OI 60 OI UTPUT N 2300 CREF/BYP = 1nF UTPUT N 345000 VOUT = 1.2V UTPUT N 243000 VOUT = 1.2V O 10 CREF/BYP = 10nF O 2100 VOUT = 0.6V O 10 VOUT = 0.6V 0 0 0 0.01 0.1 1 10 100 1000 0.01 0.1 1 10 100 1000 0.01 0.1 1 10 LOAD CURRENT (mA) LOAD CURRENT (mA) FEEDFORWARD CAPACITOR, CFF (nF) 3055 G28 3055 G29 3055 G30 Start-Up Time 10Hz to 100kHz Output Noise 10Hz to 100kHz Output Noise vs REF/BYP Capacitor C = 10nF, C = 0 C = 10nF, C = 10nF REF/BYP FF REF/BYP FF 60 50 s) ME (m 40 200µVV/ODUIVT 200µVV/ODUIVT P TI 30 U T- R A 20 T S 10 COUT = 10µF 1ms/DIV 3055 G32 COUT = 10µF 1ms/DIV 3055 G33 ILOAD = 500mA ILOAD = 500mA VOUT = 5V VOUT = 5V 0 0 10 20 30 40 50 60 70 80 90 100 REF/BYP CAPACITOR (nF) 3055 G31 5V Transient Response 5V Transient Response C = 0, I = 50mA to 500mA C = 10nF, I = 50mA to 500mA Transient Response (Load Dump) FF OUT FF OUT VOUT VOUT VOUT 200mV/DIV 100mV/DIV 20mV/DIV 45V VIN IOUT IOUT 10V/DIV 500mA/DIV 500mA/DIV 12V VIN = 6V 100µs/DIV 3055 G34 VIN = 6V 20µs/DIV 3055 G35 VOUT = 5V 1ms/DIV 3055 G36 COUT = 10µF COUT = 10µF IOUT = 100mA IFB-DIVIDER = 10µA IFB-DIVIDER = 10µA COUT = 10µF VOUT = 5V VOUT = 5V Rev. B 9 For more information www.analog.com

LT3055 Series TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. J SHDN Transient Response SHDN Transient Response Precision Current Limit, C = 0 C = 10nF R = 1.5k REF/BYP REF/BYP IMAX 220 mA) 216 VOUT(NOMINAL) = 5V 5V/ODUIVT 5V/ODUIVT LD ( 212 O IL=500mA IL = 500mA SH 208 E R 500RmEFV//BDYIPV 500RmEFV//BDYIPV T TH 204 VIN = 10V UL 200 A T F 196 VIN = 5.6V MI SHDN SHDN LI 192 2V/DIV 2V/DIV T EN 188 R 2ms/DIV 3055 G37 2ms/DIV 3055 G38 R U 184 C 180 –75–50–25 0 25 50 75 100125150175 TEMPERATURE (°C) 3055 G39 Precision Current Limit, R = 604Ω I /I Ratio, I = 500mA I /I Ratio, I = 500mA IMAX OUT MON OUT OUT MON OUT 550 550 550 RESHOLD (mA) 555324000 VOUT(NOMINAL) = 5V TIO (mA/mA) 555324000 VVOINU =T =5 .56VV TIO (mA/mA) 555324000 VVOINU =T =7 V5V H 510 A 510 A 510 AULT T 500 VIN = 7V RENT R 500 RENT R 500 MIT F 490 VIN = 5.6V CUR 490 CUR 490 RENT LI 447800 /I UTMON447800 TTTJJJ === 11252505°C°°CC /I UTMON447800 TTTJJJ === 11252505°C°°CC UR 460 IO460 TJ = –40°C IO460 TJ = –40°C C TJ = –55°C TJ = –55°C 450 450 450 –75–50–25 0 25 50 75 100125150175 0 1 2 3 4 5 0 1 2 3 4 5 TEMPERATURE (°C) VIMON (V) VIMON (V) 3055 G40 3055 G41 3055 G41 Minimum Output Current I /I Current Ratio I /I Current Ratio Threshold, R = 1.2M OUT MON OUT MON IMIN 550 VOUT = 5V 550 VOUT = 5V mA)1.10 A) 540 VIN = 5.6V A) 540 VIMON = 3.5V D (1.08 mA/m 530 VIMON = 3.5V mA/m 530 IIOOUUTT == 1205m0mAA a ta tV VININ = =1 59VV SHOL1.06 ON CURRENT RATIO ( 545541902800000 TJ = 150°C ON CURRENT RATIO ( 545541902800000 IOUT = 500mA at VIN = 7V TJ = 150°C TPUT CURRENT THRE10110.....0900928046 IMIIMN IRN IFSAINLLGI NTHGR TEHSRHEOSLHDOLD IOUT/IM 447600 TTTTJJJJ ==== 12––25455°05C°°°CCC IOUT/IM 447600 TTTTJJJJ ==== 12––25455°05C°°°CCC NIMUM OU00..9942 450 450 MI0.90 0 50 100150200250300350400450500 0 50 100150200250300350400450500 –75–50–25 0 25 50 75 100125150175 IOUT (mA) IOUT (mA) TEMPERATURE (°C) 3055 G43 3055 G44 3055 G45 Rev. B 10 For more information www.analog.com

LT3055 Series TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, unless otherwise noted. J Minimum Output Current TEMP Output Voltage Threshold R = 120k vs Temperature IMIN A)11.0 1.75 m D (10.8 1.50 L O H10.6 1.25 HRES10.4 E (V)1.00 T G UT CURRENT 11090...280 IIMMININ F RAILSLININGG T THHRREESSHHOOLLDD P PIN VOLTA000...725550 OUTP 9.6 TEM 0 M 9.4 –0.25 U M 9.2 –0.50 NI MI 9.0 –0.75 –75–50–25 0 25 50 75 100125150175 –75–50–25 0 25 50 75 100125150175 TEMPERATURE (°C) TEMPERATURE (°C) 3055 G46 3055 G47 TEMP Pin Error TEMP Pin Minimum Input Voltage 7 2.2 6 2.0 TEMP Pin Minimum Input Voltage 5 4 V)1.8 C) 3 GE (1.6 R (° 2 LTA1.4 ERRO 01 UT VO1.2 P PIN ––21 M INP01..80 OUT Pin Minimum Input Voltage TEM –3 NIMU0.6 VILO=U5T0 0=m 0A.6V –4 MI0.4 –5 –6 0.2 –7 0 0 25 50 75 100 125 150 –75–50–25 0 25 50 75 100125150175 TEMPERATURE (°C) TEMPERATURE (°C) 3055 G49 3055 G48 PWRGD Threshold Voltage 590 580 570 mV) 560 GE ( 550 A ADJ PIN RISING THRESHOLD T OL 540 V PIN 530 ADJ PIN FALLING THRESHOLD DJ 520 A 510 500 490 –75–50–25 0 25 50 75 100125150175 TEMPERATURE (°C) 3055 G50 Rev. B 11 For more information www.analog.com

LT3055 Series PIN FUNCTIONS IN (Pins 1, 2): Input. These pins supply power to the TEMP (Pin 7): Temperature Output. The TEMP pin outputs device. The LT3055 requires a local IN bypass capacitor a voltage proportional to the average junction temperature. if it is located more than six inches from the main input The pin voltage is 250mV for 25°C and has a slope of filter capacitor. In general, battery output impedance rises 10mV/°C. The TEMP pin output impedance is approximately with frequency, so adding a bypass capacitor in battery- 1500Ω. The TEMP pin is stable with no bypass capacitor powered circuits is advisable. A bypass capacitor in the or with a bypass capacitor with a value between 100pF range of 1µF to 10µF is sufficient. See Input Capacitance and 1nF. A 100pF capacitor is recommended to improve and Stability in the Applications Information section for TEMP pin power supply rejection. If not used, leave TEMP more information. unconnected. The LT3055 regulator withstands reverse voltages on the I (Pin 8): Output Current Monitor. This pin is the col- MON IN pins with respect to ground and the OUT pins. In the lector of a PNP current mirror that outputs 1/500th of the case of a reverse input, which can happen if a battery is power PNP current. The I pin requires a small (22nF MON plugged in backwards, the device acts as if there is a diode minimum) decoupling capacitor. In applications where the in series with its input. No reverse current flows into the I pin is used in an external feedback network (current MON regulator and no reverse voltage appears at the load. The sharing, cable drop compensation, etc.) smaller bypass device protects both itself and the load. capacitance values may be used to ensure stability of the external feedback network. If not used, tie I to GND. SHDN (Pin 3): Shutdown. Pulling the SHDN pin low puts MON the LT3055 into a low power state and turns the output off. I (Pin 9): Minimum Output Current Programming MIN Drive the SHDN pin with either logic or an open-collector/ Pin. This pin is the collector of a PNP current mirror that drain with a pull-up resistor. The resistor supplies the outputs 1/2000th of the power PNP load current. This pin pull-up current to the open-collector/drain logic, normally is also the input to the minimum output current fault com- several microamperes, and the SHDN pin current, typically parator. Connecting a resistor between I and GND sets MIN less than 2μA. If unused, connect the SHDN pin to IN. The the minimum output current fault threshold. For detailed LT3055 does not function if the SHDN pin is not connected. information on how to set the I pin resistor value, please MIN see the Operation section. A small external decoupling FAULT1 (Pin 4), FAULT2 (Pin 5): Fault Indicator Pins. capacitor (10nF minimum) is required to improve I FAULT1 and FAULT2 are open-collector logic pins. If the MIN PSRR. If minimum output current programming is not output current drops below the minimum current thresh- required, float the I pin (unconnected). old, FAULT1 asserts low. If the output current exceeds the MIN current limit threshold, FAULT2 asserts low. If the LT3055 I (Pin 10): Precision Current Limit Programming Pin. MAX enters thermal shutdown, both FAULT1 and FAULT2 assert This pin is the collector of a current mirror PNP that is low. The FAULT1 and FAULT2 pins are capable of sinking 1/500th the size of the output power PNP. This pin is also the 50μA. There is no internal pull-up resistor; an external input to the current limit amplifier. Current limit threshold pull-up resistor must be used. is set by connecting a resistor between the I pin and MAX GND. For detailed information on how to set the I pin PWRGD (Pin 6): Power Good Pin. The PWRGD pin is an MAX resistor value, please see the Operation section. The I open-collector output that actively pulls low if the output MAX pin requires a 22nF decoupling capacitor to ground. If not is less than 90% of the nominal output value. The PWRGD used, tie I to GND. pin is capable of sinking 50μA. There is no internal pull-up MAX resistor, an external pull-up resistor must be used. Rev. B 12 For more information www.analog.com

LT3055 Series PIN FUNCTIONS REF/BYP (Pin 11): Bypass/Soft-Start. Connecting a capaci- ADJ (LT3055: Pin 14): Adjust. This pin is the error amplifier’s tor from this pin to GND bypasses the LT3055’s reference inverting terminal. The typical bias current of 16nA flows noise and soft starts the reference. A 10nF bypass capaci- out of the pin (see the ADJ pin Bias Current vs Temperature tor typically reduces output voltage noise to 25μV in curve in the Typical Performance Characteristics section). RMS a 10Hz to 100kHz bandwidth. Soft-start time is directly The ADJ pin voltage is 600mV referenced to GND. proportional to BYP/SS capacitor value. If the LT3055 is Connecting a capacitor from ADJ to OUT reduces output placed in shutdown, BYP/SS is actively pulled low by an noise and improves transient response for output voltages internal device to reset soft-start. If low noise or soft-start greater than 600mV. See the Applications Information sec- performance is not required, this pin must be left floating tion for calculating the value of the feedforward capacitor. (unconnected). Do not drive this pin with any active cir- cuitry. Because the REF/BYP pin is the reference input to ADJ (LT3055-3.3, LT3055-5: Pin 13): Adjust. This pin is the error amplifier, stray capacitance at this point should the error amplifier’s inverting terminal. The typical bias be minimized. Special attention should be given to any current of 16nA flows out of the pin (see the ADJ pin Bias stray capacitances that can couple external signals onto Current vs Temperature curve in the Typical Performance the REF/BYP pin producing undesirable output transients Characteristics section). The ADJ pin voltage is 600mV or ripple. A minimum REF/BYP capacitance of 100pF is referenced to GND. recommended. Connecting a capacitor from ADJ to OUT reduces output GND (LT3055: Pin 12, Pin 13, Exposed Pad Pin 17): noise and improves transient response for output voltages Ground. The exposed pad of the DFN and MSOP pack- greater than 600mV. See the Applications Information sec- ages is an electrical connection to GND. To ensure proper tion for calculating the value of the feedforward capacitor. electrical and thermal performance, solder Pin 17 to the SENSE (LT3055-3.3, LT3055-5: Pin 14): Sense. This pin PCB ground and tie it directly to Pins 12, 13. Connect the is the top of the internal resistor divider network. SENSE bottom of the output voltage setting resistor divider directly should be connected directly to the load, as a Kelvin sense, to GND (Pin 12) for optimum load regulation. for optimum load regulation and transient performance. GND (LT3055-3.3, LT3055-5: Pin 12, Exposed Pad Connecting this pin to the output pin, rather than directly Pin 17): Ground. The exposed pad of the DFN and MSOP to the load, can result in load regulation errors due to the packages is an electrical connection to GND. To ensure current across the parasitic resistance of the PCB trace. proper electrical and thermal performance, solder Pin 17 OUT (Pins 15,16): Output. These pins supply power to to the PCB ground and tie it directly to Pin 12. Connect the load. Stability requirements demand a minimum 3.3μF the bottom of the output voltage setting resistor divider ceramic output capacitor with an ESR < 1Ω to prevent directly to GND (Pin 12) for optimum load regulation. oscillations. For output voltages less than 1.2V, a mini- mum 4.7µF ceramic output capacitor is required. Large RP IN OUT load transient applications require larger output capaci- LT3055-5 tors to limit peak voltage transients. See the Applications + + SHDN SENSE + Information section for details on output capacitance and VIN GND LOAD reverse output characteristics. Permissible output voltage range is 600mV to 40V. RP 3055 F01 Figure 1. Kelvin Sense Connection Rev. B 13 For more information www.analog.com

LT3055 Series BLOCK DIAGRAM IN R1 SENSE D1 QIMIN QIMON QIMAX 1/2000 1/500 1/500 QPOWER R5 30k THERMAL/ 1 ADJ R4 CURRENT LIMITS – R6 + Q3 CULRIMREITNT OUT Q2 ERROR AMPLIFIER 100k AMPLIFIER + R3 IMAX D2 IDEAL – IMON DIODE D3 IMIN COMPARATOR + 100k SHDN + 600mV – R2 IMIN – REFERENCE FAULT1 IMIN U1 QFAULT1 THERMAL LIMIT FAULT2 CURRENT LIMITS U2 QFAULT2 THERMAL LIMIT PWRGD – QPWRGD + + 540mV – REFERENCE REF/BYP GND 3055 F02 Figure 2. OPERATION I Pin Operation (Current Monitor) early voltage compensation circuit is active, calculate the MON output current from the simple equation: The I pin is the collector of a PNP which mirrors the MON LT3055 output PNP at a ratio of 1:500 (see Block Diagram). V IMON I =500• There is additional circuitry which compensates for early OUT R voltage variation by regulating the collector of the I IMON MON mirror PNP at the output voltage. This circuitry is active For V > (V -500mV), the I mirror PNP collec- IMON OUT MON for VIMON ≤ (VOUT – 500mV). For the range where the tor is VIMON + VDSSAT (500mV at 500mA). Early voltage effects increase the I to I ratio as V increases. OUT MON IMON Rev. B 14 For more information www.analog.com

LT3055 Series OPERATION 525 If the open-circuit detection function is not needed, the 520 I pin must be left floating (unconnected). A small de- MIN 515 EARLY VOLTAGE coupling capacitor (10nF minimum) from I to GND is mA) EFFECTS MIN mA/510 required to improve IMIN pin power supply rejection and to O (505 prevent FAULT1 pin glitches. See the Typical Performance RATI500 Characteristics section for additional information. ON495 M :IOUTI490 IMAX Pin Operation I485 VIN = 6V 480 VIMON = 2.5V The IMAX pin is the collector of a PNP which mirrors the IOUT = 500mA (IN CURRENT LIMIT) 475 LT3055 output PNP at a ratio of 1:500 (see Block Diagram). 0 1 2 3 4 5 The I pin is also the input to the precision current limit VOUT (V) MAX amplifier. If the output load increases to the point where it 3055 F03a Figure 3a. IOUT:IIMON Ratio vs VOUT causes the IMAX pin voltage to reach 0.6V, the current limit amplifier takes control of the output regulation so that the 525 VIN = 6V I pin regulates at 0.6V, regardless of the output voltage. 520 VOUT = 5V MAX 515 IOUT = 500mA The current limit threshold (ILIMIT) is set by connecting a mA) IMON MIRROR resistor (R ) from I to GND: A/510 PNP SATURATING IMAX MAX m O (505 0.6V ATI500 R =500• R IMAX MON495 EARLY VEOFLFTEACGTSE ILIMIT :IUTI490 In cases where the IN to OUT differential voltage exceeds O I485 10V, fold-back current limit lowers the internal current 480 limit level, possibly causing it to override the external 475 0 1 2 3 4 5 6 programmable current limit. See the Internal Current Limit VIMON (V) vs V -V graph in the Typical Performance Character- IN OUT 3055 F03b istics section. Figure 3. (b) I :I Ratio vs V OUT IMON IMON The I pin requires a 22nF decoupling capacitor. If the MAX external programmable current limit is not needed, the In addition, if V – V < 1V, the I mirror PNP IN IMON MON I pin must be connected to GND. The I threshold saturates at high loads, causing the I -to-I ratio MAX MAX OUT MON is affected by power dissipation in the LT3055; it increases to increase quickly. The I mirror ratio is affected by MON at a rate of approximately 0.5 percent per watt. power dissipation in the LT3055; it increases at a rate of approximately 0.5 percent per watt. FAULT Pins Operation Open-Circuit Detection (I Pin) MIN The FAULT1 and FAULT2 pins are open-drain high voltage The IMIN pin is the collector of a PNP which mirrors NMOS digital outputs. The FAULT1 pin asserts during a low the LT3055 output PNP at a ratio of 1:2000 (see Block current fault (open circuit). The FAULT2 pin asserts during Diagram). The IMIN fault comparator asserts the FAULT1 a current limit fault (internal or externally programmed). pin if the IMIN pin voltage is below 0.6V. This low output Both FAULT1 and FAULT2 assert during thermal shutdown. current fault threshold voltage (IOPEN) is set by attaching There is no internal pull-up on the FAULT pins; an external a resistor from IMIN to GND: pull-up resistor is required. The FAULT pins sink up to 50μA of pull-down current. Off state logic may be as high 0.6V R =2000• as 45V, regardless of the input voltage used. IMIN I OPEN Rev. B 15 For more information www.analog.com

LT3055 Series OPERATION value for more than 25μs, the PWRGD pin asserts low. Table 1. FAULT Pins Truth Table The PWRGD comparator has 1% hysteresis and 25μs STATUS FAULT1 FAULT2 Open Circuit Low High of deglitching. The PWRGD comparator has a dedicated Current Limit High Low reference that does not soft-start when a capacitor is Thermal Shutdown Low Low added to the REF/BYP pin. Depending on the I capacitance, BYP capacitance, The use of a feed-forward capacitor, CFF, as shown in Fig- MIN and OUT capacitance, the FAULT pins may assert during ure 5, can result in the ADJ pin being pulled artificially high start-up. Consideration should be given to masking the during start- up transients, which causes the PWRGD flag fault signals during start-up. The FAULT pin circuitry is to assert early. To avoid this problem, ensure that the REF/ inactive (not asserted) during shutdown and when the BYP capacitor is significantly larger than the feed-forward OUT pin is pulled above IN pin. capacitor, causing REF/BYP time constant to dominate over the time constant of the resistor divider network. PWRGD Pin Operation Operation in Dropout The PWRGD pin is an open-drain high voltage NMOS digital output. The PWRGD pin deasserts and becomes There may be some degradation of the current mirror ac- high impedance if the output rises above 90% of its curacy for output currents less than 50mA when operating nominal value. If the output falls below 89% of its nominal in dropout. APPLICATIONS INFORMATION The LT3055 is a micropower, low noise and low dropout volt- The LT3055 optimizes stability and transient response age, 500mA linear regulator with micropower shutdown, with low ESR, ceramic output capacitors. The regulator programmable current limit, and diagnostic functions. The does not require the addition of ESR as is common with device supplies up to 500mA at a typical dropout voltage other regulators. The LT3055 typically provides 0.1% line of 350mV and operates over a 1.6V to 45V input range. regulation and 0.1% load regulation. Internal protection circuitry includes reverse battery protection, reverse output A single external capacitor provides low noise reference protection, reverse current protection, current limit with performance and output soft-start functionality. For ex- fold-back and thermal shutdown. ample, connecting a 10nF capacitor from the REF/BYP pin to GND lowers output noise to 25μV over a 10Hz This “bullet-proof” protection set makes it ideal for use RMS to 100kHz bandwidth. This capacitor also soft starts the in battery-powered, automotive and industrial systems. reference and prevents output voltage overshoot at turn-on. In battery backup applications where the output is held The LT3055’s quiescent current is merely 65μA but provides up by a backup battery and the input is pulled to ground, fast transient response with a minimum low ESR 3.3μF the LT3055 acts like it has a diode in series with its output ceramic output capacitor. In shutdown, quiescent current is and prevents reverse current flow. less than 1μA and the reference soft-start capacitor is reset. Rev. B 16 For more information www.analog.com

LT3055 Series APPLICATIONS INFORMATION Adjustable Operation + IN OUT VOUT The adjustable LT3055 has an output voltage range of VIN LT3055 R2 0.6V to 40V. The output voltage is set by the ratio of SHDN ADJ two external resistors, as shown in Figure 4. The device GND R1 servos the output to maintain the ADJ pin voltage at 0.6V 3055 F04 referenced to ground. The current in R1 is then equal to 0.6V/R1, and the current in R2 is the current in R1 minus VOUT=0.6V1+RR21–(IADJ•R2) the ADJ pin bias current. VADJ=0.6V The ADJ pin bias current, 16nA at 25°C, flows from the IADJ=16nA AT 25°C ADJ pin through R1 to GND. Calculate the output voltage OUTPUT RANGE = 0.6V TO 40V using the formula in Figure 4. The value of R1 should be Figure 4. Adjustable Operation no greater than 62k to provide a minimum 10μA load cur- rent so that output voltage errors, caused by the ADJ pin Bypass Capacitance and Output Voltage Noise bias current, are minimized. Note that in shutdown, the The LT3055 regulator provides low output voltage output is turned off and the divider current is zero. Curves noise over a 10Hz to 100kHz bandwidth while operat- of ADJ Pin Voltage vs Temperature and ADJ Pin Bias Cur- ing at full load with the addition of a bypass capacitor rent vs Temperature appear in the Typical Performance (C ) from the REF/BYP pin to GND. A high quality REF/BYP Characteristics section. low leakage capacitor is recommended. This capacitor The LT3055 is tested and specified with the ADJ pin tied bypasses the internal reference of the regulator, provid- to the OUT pin, yielding V = 0.6V. Specifications for ing a low frequency noise pole for the internal reference. OUT output voltages greater than 0.6V are proportional to the With the use of 10nF for CREF/BYP, output voltage noise ratio of the desired output voltage to 0.6V: VOUT/0.6V. For decreases to as low as 25μVRMS when the output voltage example, load regulation for an output current change of is set for 0.6V. For higher output voltages (generated by 1mA to 500mA is 0.5mV (typical) at V = 0.6V. At V using a feedback resistor divider), the output voltage noise OUT OUT = 12V, load regulation is: gains up proportionately when using CREF/BYP. To lower the higher output voltage noise, include a feed- 12V •(0.5mV)=10mV forward capacitor (C ) from V to the ADJ pin. A high 0.6V FF OUT quality, low leakage capacitor is recommended. This Table 2 shows 1% resistor divider values for some common capacitor bypasses the error amplifier of the regulator, output voltages with a resistor divider current of 10μA. providing an additional low frequency noise pole. With the use of 10nF for both C and C , output voltage FF REF/BYP Table 2. Output Voltage Resistor Divider Values noise decreases to 25μV when the output voltage is RMS V (V) R1 (kΩ) R2 (kΩ) OUT set to 5V by a 10μA feedback resistor divider. If the cur- 1.2 60.4 60.4 rent in the feedback resistor divider is doubled, C must 1.5 59 88.7 FF also be doubled to achieve equivalent noise performance. 1.8 59 118 2.5 60.4 191 Higher values of output voltage noise can occur if care 3 59 237 is not exercised with regard to circuit layout and testing. 3.3 61.9 280 Crosstalk from nearby traces induces unwanted noise 5 59 432 onto the LT3055’s output. Power supply ripple rejection Rev. B 17 For more information www.analog.com

LT3055 Series APPLICATIONS INFORMATION must also be considered. The LT3055 regulator does not + IN OUT VOUT have unlimited power supply rejection and passes a small VIN LT3055 R2 CFF COUT portion of the input noise through to the output. SHDN ADJ R1 Using a feedforward capacitor (C ) from V to the GND REF/BYP FF OUT ADJ pin has the added benefit of improving transient CREF/BYP response for output voltages greater than 0.6V. With no 3055 F05 feedforward capacitor, the settling time increases as the CFF≥1100µnAF•(IFB_DIVIDER) output voltage increases above 0.6V. Use the equation in V Figure 5 to determine the minimum value of CFF to achieve IFB_DIVIDER=R1O+URT2 a transient response that is similar to the 0.6V output Figure 5. Feedforward Capacitor for Fast Transient Response voltage performance regardless of the chosen output volt- age (See Figure 6 and Transient Response in the Typical Performance Characteristics section). Dad iubreryicpntaglys sspt racoratpp-ouarcpti,ito otnhr aeils itnpotr eethrsneea nslt i.rz eRef eeogrfeu ntlhaceteo brs yosptfata-rssts-ta ucrpta spt iamwcheite oinsr DFORWARDACITOR, CFF 100p0F 100mV/DOUTV (See Start-Up Time vs REF/BYP Capacitor in the Typical FEECAP 1nF IV 10nF Performance Characteristics section). The reference by- LOAD CURRENT pass capacitor is actively pulled low during shutdown to 500mA/DIV reset the internal reference. VOUT = 5V 100µs/DIV 3055 F06 COUT = 10µF IFB-DIVIDER = 10µA Start-up time is also affected by the presence of a feed- Figure 6. Transient Response vs Feedforward Capacitor forward capacitor. Start-up time is directly proportional to the size of the feedforward capacitor and the output volt- capacitor in parallel with a bulk tantalum capacitor often age, and is inversely proportional to the feedback resistor provides an optimally damped response. divider current, slowing to 15ms with a 10nF feedforward capacitor and a 10μF output capacitor for an output voltage Give extra consideration to the use of ceramic capacitors. set to 5V by a 10μA feedback resistor divider. Manufacturers make ceramic capacitors with a variety of dielectrics, each with different behavior across tempera- Output Capacitance and Transient Response ture and applied voltage. The most common dielectrics are specified with EIA temperature characteristic codes The LT3055 regulator is stable with a wide range of output of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics capacitors. The ESR of the output capacitor affects stability, provide high C-V products in a small package at low cost, most notably with small capacitors. Use a minimum output but exhibit strong voltage and temperature coefficients, capacitor of 3.3μF with an ESR of 1Ω or less to prevent as shown in Figure 7 and Figure 8. When used with a 5V oscillations. If a feedforward capacitor is used with output regulator, a 16V 10μF Y5V capacitor can exhibit an effective voltages set for greater than 24V, use a minimum output value as low as 1μF to 2μF for the DC bias voltage applied, capacitor of 10μF. The LT3055 is a micropower device and and over the operating temperature range. The X5R and output load transient response is a function of output ca- X7R dielectrics yield much more stable characteristics and pacitance. Larger values of output capacitance decrease the are more suitable for use as the output capacitor. peak deviations and provide improved transient response for larger load current changes. Bypass capacitors, used to The X7R type works over a wider temperature range and decouple individual components powered by the LT3055, has better temperature stability, while the X5R is less increase the effective output capacitor value. For applica- expensive and is available in higher values. Care still must tions with large load current transients, a low ESR ceramic be exercised when using X5R and X7R capacitors; the X5R Rev. B 18 For more information www.analog.com

LT3055 Series APPLICATIONS INFORMATION 20 of noise. A ceramic capacitor produced the trace in BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10µF Figure 9 in response to light tapping from a pencil. Similar 0 vibration induced behavior can masquerade as increased %) X5R E (–20 output voltage noise. U L A V N –40 E I G N A–60 H C Y5V –80 VOUT 1mV/DIV –100 0 2 4 6 8 10 12 14 16 DC BIAS VOLTAGE (V) 3055 F07 Figure 7. Ceramic Capacitor DC Bias Characteristics 40 VOUT = 5V 10ms/DIV 3055 F09 COUT = 10µF CREF/BYP = 10nF 20 Figure 9. Noise Resulting from Tapping On a Ceramic Capacitor %) 0 X5R E ( U L –20 A N V Stability and Input Capacitance E I –40 G Y5V N Low ESR, ceramic input bypass capacitors are acceptable A H –60 C for applications without long input leads. However, appli- –80 cations connecting a power supply to an LT3055 circuit’s BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10µF IN and GND pins with long input wires combined with a –100 –50 –25 0 25 50 75 100 125 low ESR, ceramic input capacitors are prone to voltage TEMPERATURE (°C) 3055 F08 spikes, reliability concerns and application-specific board Figure 8. Ceramic Capacitor Temperature Characteristics oscillations. and X7R codes only specify operating temperature range The input wire inductance found in many battery-powered and maximum capacitance change over temperature. applications, combined with the low ESR ceramic input Capacitance change due to DC bias with X5R and X7R capacitor, forms a high QLC resonant tank circuit. In capacitors is better than Y5V and Z5U capacitors, but can some instances this resonant frequency beats against the still be significant enough to drop capacitor values below output current dependent LDO bandwidth and interferes appropriate levels. Capacitor DC bias characteristics tend with proper operation. Simple circuit modifications/solu- to improve as component case size increases, but expected tions are then required. This behavior is not indicative of capacitance at operating voltage should be verified. LT3055 instability, but is a common ceramic input bypass capacitor application issue. Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a The self-inductance, or isolated inductance, of a wire is piezoelectric response. A piezoelectric device generates directly proportional to its length. Wire diameter is not voltage across its terminals due to mechanical stress, a major factor on its self-inductance. For example, the similar to the way a piezoelectric accelerometer or micro- self-inductance of a 2-AWG isolated wire (diameter = phone works. For a ceramic capacitor, the stress is induced 0.26") is about half the self-inductance of a 30-AWG wire by vibrations in the system or thermal transients. The (diameter = 0.01"). One foot of 30-AWG wire has approxi- resulting voltages produced cause appreciable amounts mately 465nH of self-inductance. Rev. B 19 For more information www.analog.com

LT3055 Series APPLICATIONS INFORMATION Two methods can reduce wire self-inductance. One method as 0.1Ω to 0.5Ω suffices. This impedance dampens the divides the current flowing towards the LT3055 between LC tank circuit at the expense of dropout voltage. A better two parallel conductors. In this case, the farther apart the alternative is to use higher ESR tantalum or electrolytic ca- wires are from each other, the more the self-inductance is pacitors at the LT3055 input in place of ceramic capacitors. reduced; up to a 50% reduction when placed a few inches apart. Splitting the wires connects two equal inductors in Paralleling Devices parallel, but placing them in close proximity creates mutual Higher output current is obtained by paralleling multiple inductance adding to the self-inductance. The second and LT3055 together. Tie the individual OUT pins together most effective way to reduce overall inductance is to place and tie the individual IN pins together. An external NPN both forward and return current conductors (the input and or NMOS current mirror is used in combination with the GND wires) in very close proximity. Two 30-AWG wires LT3055 I pins to create a simple amplifier. This ampli- MON separated by only 0.02”, used as forward- and return- fier injects current into or out of the feedback divider of current conductors, reduce the overall self-inductance the slave LT3055 in order to ensure that the I currents MON to approximately one-fifth that of a single isolated wire. from each LT3055 are equal. If a battery, mounted in close proximity, powers the LT3055, In Figure 10, this is implemented using inexpensive 2N3904 a 10µF input capacitor suffices for stability. However, if a NPN devices. Precision 1k resistors provide 1V emitter distant supply powers the LT3055, use a larger value input degeneration at full load to guarantee good current mirror capacitor. Use a rough guideline of 1µF (in addition to the matching. The feedback resistors of the slave LT3055 are 10µF minimum) per 8 inches of wire length. The minimum split into sections to ensure adequate headroom for the input capacitance needed to stabilize the application also slave 2N3904. A 1nF capacitor added to the I pin of MON varies with power supply output impedance variations. the slave device frequency compensates the feedback loop. Placing additional capacitance on the LT3055’s output also This circuit architecture is scalable to as many LT3055s helps. However, this requires an order of magnitude more as are needed simply by extending the current mirror and capacitance in comparison with additional LT3055 input adding slave LT3055 devices. bypassing. Series resistance between the supply and the LT3055 input also helps stabilize the application; as little LT3055 (MASTER) IN 500x 1x REF + – IMON + OUT VOUT – 600mV 5V ADJ 440k 10µF 1A 60k LT3055 (SLAVE) VIN IN 5.6V 10µF REF + 500x 1x – IMON + OUT 1nF – 600mV ADJ 300k 140k 2N3904 60k 1k 1k 3055 F10 Figure 10. Parallel Devices Rev. B 20 For more information www.analog.com

LT3055 Series APPLICATIONS INFORMATION Spreading the devices on the PC board also spreads the GND pin current is determined using the GND Pin Current heat. Series input resistors can further spread the heat if curves in the Typical Performance Characteristics section. the input-to-output differential is high. Power dissipation equals the sum of the two components listed above. Overload Recovery The LT3055 regulator has internal thermal limiting that Like many IC power regulators, the LT3055 has safe oper- protects the device during overload conditions. For con- ating area protection. The safe area protection decreases tinuous normal conditions, do not exceed the maximum current limit as input-to-output voltage increases, and junction temperature of 125°C (E-, I-grades) or 150°C keeps the power transistor inside a safe operating region (MP-, H-grades). Carefully consider all sources of thermal for all values of input-to-output voltage. The LT3055 pro- resistance from junction-to-ambient including other heat vides some output current at all values of input-to-output sources mounted in proximity to the LT3055. voltage up to the device breakdown. The undersides of the LT3055 DFN and MSE packages have When power is first applied, the input voltage rises and the exposed metal from the lead frame to the die attachment. output follows the input; allowing the regulator to start-up These packages allow heat to directly transfer from the into very heavy loads. During start-up, as the input voltage die junction to the printed circuit board metal to control is rising, the input-to-output voltage differential is small, al- maximum operating junction temperature. The dual-in- lowing the regulator to supply large output currents. With a line pin arrangement allows metal to extend beyond the high input voltage, a problem can occur wherein the removal ends of the package on the topside (component side) of a of an output short will not allow the output to recover. Other PCB. Connect this metal to GND on the PCB. The multiple regulators, such as the LT1083/LT1084/ LT1085 family and IN and OUT pins of the LT3055 also assist in spreading LT1764A also exhibit this phenomenon, so it is not unique heat to the PCB. to the LT3055. The problem occurs with a heavy output load For surface mount devices, heat sinking is accomplished when the input voltage is high and the output voltage is low. by using the heat spreading capabilities of the PC board Common situations are immediately after the removal of a and its copper traces. Copper board stiffeners and plated short circuit or if the shutdown pin is pulled high after the through-holes also can spread the heat generated by input voltage is already turned on. The load line intersects power devices. the output current curve at two points. If this happens, there are two stable output operating points for the regulator. With Table 3 and Table 4 list thermal resistance as a function this double intersection, the input power supply needs to be of copper area in a fixed board size. All measurements cycled down to zero and back up again to recover the output. were taken in still air on a 4-layer FR-4 board with 1oz solid internal planes, and 2oz external trace planes with a Thermal Considerations total board thickness of 1.6mm. For further information The LT3055’s maximum rated junction temperature of on thermal resistance and using thermal information, refer 125°C (E-, I-grades) or 150°C (MP-, H-grades) limits its to JEDEC standard JESD51, notably JESD51-12. power handling capability. Two components comprise the Table 3. MSOP Measured Thermal Resistance power dissipated by the device: COPPER AREA THERMAL RESISTANCE 1. Output current multiplied by the input/output voltage TOPSIDE BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT) difference: 2500 sq mm 2500 sq mm 2500 sq mm 35°C/W IOUT • (VIN – VOUT), and 1000 sq mm 2500 sq mm 2500 sq mm 36°C/W 225 sq mm 2500 sq mm 2500 sq mm 37°C/W 2. GND pin current multiplied by the input voltage: 100 sq mm 2500 sq mm 2500 sq mm 39°C/W I • V GND IN Rev. B 21 For more information www.analog.com

LT3055 Series APPLICATIONS INFORMATION limiting, the device also protects against reverse input Table 4. DFN Measured Thermal Resistance voltages, reverse output voltages and reverse output-to- COPPER AREA THERMAL RESISTANCE TOPSIDE BOARD AREA (JUNCTION-TO-AMBIENT) input voltages. 2500 sq mm 2500 sq mm 36°C/W Current limit protection and thermal overload protection 1000 sq mm 2500 sq mm 37°C/W protect the device against current overload conditions at 225 sq mm 2500 sq mm 38°C/W the output of the device. For normal operation, do not 100 sq mm 2500 sq mm 40°C/W exceed a junction temperature of 125°C (E-, I-grades) or 150°C (MP-, H-grades). Calculating Junction Temperature The LT3055 IN pin withstands reverse voltages of 50V. The Example: Given an output voltage of 5V, an input voltage device limits current flow to less than 1μA (typically less range of 12V ±5%, a maximum output current range of than 25nA) and no negative voltage appears at OUT. The 75mA and a maximum ambient temperature of 85°C, what device protects both itself and the load against batteries is the maximum junction temperature? that are plugged in backwards. The power dissipated by the device equals: The LT3055 incurs no damage if its output is pulled below ground. If the input is left open circuit or grounded, the I • (V – V ) + I • V OUT(MAX) IN(MAX) OUT GND IN(MAX) output can be pulled below ground by 50V. No current where: flows through the pass transistor from the output. However, current flows in (but is limited by) the feedback resistor I = 75mA OUT(MAX) divider that sets the output voltage. Current flows from V = 12.6V IN(MAX) the bottom resistor in the divider and from the ADJ pin’s I at (I = 75mA, V = 12V) = 3.5mA internal clamp through the top resistor in the divider to GND OUT IN the external circuitry pulling OUT below ground. If the So: input is powered by a voltage source, the output sources P = 75mA • (12.6V – 5V) + 3.5mA • 12.6V = 0.614W current equal to its current limit capability and the LT3055 protects itself by thermal limiting. In this case, grounding Using a DFN package, the thermal resistance ranges from the SHDN pin turns off the device and stops the output 36°C/W to 40°C/W depending on the copper area. So the from sourcing current. junction temperature rise above ambient approximately equals: 1.0 0.614W • 40°C/W = 24.6°C VIN = 0 0.9 The maximum junction temperature equals the maximum 0.8 ambient temperature plus the maximum junction tempera- µA) 0.7 T ( ture rise above ambient or: EN 0.6 R UR 0.5 TJMAX = 85°C + 24.6°C = 110°C UT C 0.4 P UT 0.3 O Protection Features 0.2 0.1 The LT3055 incorporates several protection features that 0 make it ideal for use in battery-powered circuits. In ad- 0 5 10 15 20 25 30 35 40 dition to the normal protection features associated with VOUT (V) 3055 F11 monolithic regulators, such as current limiting and thermal Figure 11. Reverse Output Current Rev. B 22 For more information www.analog.com

LT3055 Series PACKAGE DESCRIPTION MSE Package 16-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1667 Rev F) BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 ±0.102 2.845 ±0.102 (.112 ±.004) 0.889 ±0.127 (.112 ±.004) (.035 ±.005) 1 8 0.35 REF 5.10 1.651 ±0.102 3.20 – 3.45 1.651 ±0.102 (.M20IN1) (.065 ±.004) (.126 – .136) (.065 ±.004) 0.12 REF DETAIL “B” CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY 16 9 0.305 ±0.038 0.50 NO MEASUREMENT PURPOSE (.0120 ±.0015) (.0197) 4.039 ±0.102 TYP BSC (.159 ±.004) (NOTE 3) 0.280 ±0.076 RECOMMENDED SOLDER PAD LAYOUT 16151413121110 9 (.011 ±.003) REF DETAIL “A” 0.254 (.010) 3.00 ±0.102 0° – 6° TYP 4.90 ±0.152 (.118 ±.004) (.193 ±.006) GAUGE PLANE (NOTE 4) 0.53 ±0.152 (.021 ±.006) 1234567 8 DETAIL “A” 1.10 0.86 0.18 (.043) (.034) (.007) MAX REF SEATING PLANE 0.17 – 0.27 0.1016 ±0.0508 (.007 – .011) (.004 ±.002) TYP 0.50 NOTE: (.0197) MSOP (MSE16) 0213 REV F 1. DIMENSIONS IN MILLIMETER/(INCH) BSC 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. Rev. B 23 For more information www.analog.com

LT3055 Series PACKAGE DESCRIPTION DE Package 16-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1732 Rev Ø) 0.70 ±0.05 3.60 ±0.05 3.30 ±0.05 2.20 ±0.05 1.70 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.45 BSC 3.15 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ±0.10 R = 0.115 0.40 ±0.10 TYP (2 SIDES) 9 16 R = 0.05 TYP 3.30 ±0.10 3.00 ±0.10 (2 SIDES) 1.70 ±0.10 PIN 1 NOTCH PIN 1 R = 0.20 OR TOP MARK 0.35 × 45° (SEE NOTE 6) CHAMFER (DE16) DFN 0806 REV Ø 8 1 0.200 REF 0.75 ±0.05 0.23 ±0.05 0.45 BSC 3.15 REF 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Rev. B 24 For more information www.analog.com

LT3055 Series REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 6/14 Modified Minimum V to 1.8V 1 IN Added 3.3V and 5V options, related specs, Typical Performance Characteristics and Pin Functions Throughout Added specification for absolute maximum SENSE pin voltage 2 Modified Pinouts to accommodate new fixed voltage options 2 Modified Note 7 5 Modified PWRGD applications section 16 B 10/18 Changed Typical Minimum Input Voltage from 1.8V to 1.6V 1, 4, 16, 26 Added Note 17 to Electrical Characteristics regarding Minimum Input Voltage 4, 5 Added new Typical Performance Curve TEMP Pin Minimum Input Voltage 11 Rev. B 25 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license Fiso gr rmanoterde biny fiomrpmlicaattiioonn owr wotwhe.arwnaisleo ugn.cdoerm any patent or patent rights of Analog Devices.

LT3055 Series TYPICAL APPLICATION Cable Drop Compensation LT3055 VIN IN 7V 10µF 1x 500x REF + – OUT RCABLE/2 + +– 600mV ADJ IMON 100nF RCABLE • 500 10µF 10µFR5CFVOA,B RCL OED/MR2 OPR–PEEN SASILSAOTTNOEGRDS RCABLE/2 440k – RCABLE • 500 10nF 2N3904 1k 1k 60k 3055 TA02FF RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1761 100mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20μV , V : 1.8V to 20V, ThinSOT™ Package RMS IN LT1762 150mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20μV , V : 1.8V to 20V, MS8 Package RMS IN LT1763 500mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20μV , V : 1.8V to 20V, SO-8 Package RMS IN LT1962 300mA, Low Noise LDO 270mV Dropout Voltage, Low Noise: 20μV , V : 1.8V to 20V, MS8 Package RMS IN LT1964 200mA, Low Noise, Negative LDO 340mV Dropout Voltage, Low Noise: 30μV , V : –1.8V to –20V, ThinSOT Package RMS IN LT1965 1.1A, Low Noise, Low Dropout Linear 290mV Dropout Voltage, Low Noise: 40μV , V : 1.8V to 20V, V : 1.2V to 19.5V, RMS IN OUT Regulator Stable with Ceramic Capacitors, TO-220, DDPak, MSOP and 3mm × 3mm DFN Packages LT3008 20mA, 45V, 3µA I Micropower LDO 300mV Dropout Voltage, Low I = 3μA, V : 2.0V to 45V, V : 0.6V to 39.5V, Q Q IN OUT ThinSOT and 2mm × 2mm DFN-6 Packages LT3009 20mA, 3µA IQ Micropower LDO 280mV Dropout Voltage, Low IQ = 3μA, VIN: 1.6V to 20V, 2mm × 2mm DFN-6 and SC-70 Packages LT3010 50mA, High Voltage, Micropower LDO V : 3V to 80V, V : 1.275V to 60V, V = 0.3V, I = 30μA, I < 1μA, IN OUT DO Q SD Low Noise: <100μV , Stable with 1μF Output Capacitor, Exposed MS8 Package RMSP-P LT3011 50mA, High Voltage, Micropower LDO with V : 3V to 80V, V : 1.275V to 60V, V = 0.3V, I = 46μA, I < 1μA, IN OUT DO Q SD PWRGD Low Noise: <100μV , PowerGood, Stable with 1μF Output Capacitor, RMS 3mm × 3mm DFN-10 and Exposed MS12E Packages LT3012 250mA, 4V to 80V, Low Dropout Micropower V : 4V to 80V, V : 1.24V to 60V, V = 0.4V, I = 40μA, I < 1μA, TSSOP-16E and IN OUT DO Q SD Linear Regulator 4mm × 3mm DFN-12 Packages LT3013 250mA, 4V to 80V, Low Dropout Micropower V : 4V to 80V, V : 1.24V to 60V, V = 0.4V, I = 65μA, I < 1μA, PowerGood IN OUT DO Q SD Linear Regulator with PWRGD Feature, TSSOP-16E and 4mm × 3mm DFN-12 Packages LT3014/LT3014HV 20mA, 3V to 80V, Low Dropout Micropower V : 3V to 80V (100V for 2ms, LT3014HV Version), V : 1.22V to 60V, V = 0.35V, IN OUT DO Linear Regulator IQ = 7μA, ISD < 1μA, ThinSOT and 3mm × 3mm DFN-8 Packages LT3080/LT3080-1 1.1A, Parallelable, Low Noise, Low Dropout 300mV Dropout Voltage (2-Supply 0peration), Low Noise: 40μV , V : 1.2V to RMS IN Linear Regulator 36V, V : 0V to 35.7V, Current-Based Reference with 1-Resistor V Set, Directly OUT OUT Parallelable (No Op Amp Required), Stable with Ceramic Capacitors, TO-220, SOT-223, MSOP and 3mm × 3mm DFN Packages, LT3080-1 Version Has Integrated Internal Ballast Resistor LT3050 100mA LDO with Diagnostics and Precision 340mV Dropout Voltage, Low Noise: 20μV , V : 1.6V to 45V, DFN and MSOP RMS IN Current Limit Packages LT3060 100mA, Low Noise LDO with Soft-Start 300mV Dropout Voltage, Low Noise: 20μV , V : 1.6V to 45V, DFN Package RMS IN Rev. B 26 10/18 www.analog.com For more information www.analog.com  ANALOG DEVICES, INC. 2013-2018