LT3030 Dual 750mA/250mA Low Dropout, Low Noise, Micropower Linear Regulator FeaTures DescripTion n Output Current: 750mA/250mA The LT®3030 is a dual, micropower, low noise, low dropout n Low Dropout Voltage: 300mV linear regulator. The device operates with either common n Low Noise: 20μV (10Hz to 100kHz) or independent input supplies for each channel, over a RMS n Low Quiescent Current: 120μA/75μA 1.7V to 20V input voltage range. Output 1/Output 2 supply n Wide Input Voltage Range: 1.7V to 20V 750mA/250mA respectively with a typical dropout voltage n Adjustable Output: 1.220V Reference Voltage of 300mV. With an external 10nF bypass capacitor, output n Shutdown Quiescent Current: <1μA noise is only 20μV over a 10Hz to 100kHz bandwidth. RMS n Stable with 10µF/3.3µF Minimum Output Capacitor Designed for use in battery-powered systems, the low n Stable with Ceramic, Tantalum or Aluminum 120μA/75μA quiescent current makes it an ideal choice. Electrolytic Capacitors In shutdown, quiescent current drops to less than 1μA. n Precision Threshold for Shutdown Logic or UVLO Function Shutdown control is independent for each channel and n PWRGD Flag for each Output its precision logic threshold allows for voltage lockout n Reverse Battery and Reverse Output-to-Input functionality. The LT3030 includes a PWRGD flag for each Protection channel to indicate output regulation. n Current Limit with Foldback and Thermal Shutdown The LT3030 optimizes stability and transient response with n Thermally Enhanced 20-Lead TSSOP and low ESR ceramic output capacitors, requiring a minimum 28-Lead (4mm × 5mm) QFN Packages of only 10μF/3.3μF. applicaTions Internal circuitry provides reverse-battery protection, n General Purpose Linear Regulator reverse-current protection, current limiting with foldback n Battery-Powered Systems and thermal shutdown with hysteresis. The adjustable n Microprocessor Core/Logic Supplies output voltage device has a 1.220V reference voltage. n Post Regulator for Switching Supplies The LT3030 is offered in the thermally enhanced 20-lead n Tracking/Sequencing Power Supplies TSSOP and 28-lead, low profile (4mm × 5mm × 0.75mm) QFN packages. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical applicaTion 2.5V to 1.8V/1.5V Application Dropout Voltage vs Load Current IN 500 2V.5IVN IN1 OUT1 1V.O8UVT1 450 TJ = 25°C 3.3µF IN2 LT3030 10nF 10µF 750mA 113k 400 SHDN1 BYP1 1% mV) 350 SHDN2 ADJ1 GE ( 300 1M 1M 213%7k OLTA 250 OUT2 V PWRGD1 UT 200 PWRGD2 OUT2 VOUT2 OPO 150 OUT1 10nF 3.3µF 12.550VmA DR 100 54.9k BYP2 1% 50 ADJ2 0 GND 237k 0 75 150225300375450525600675750 3030 TA01a 1% OUTPUT CURRENT (mA) 3030 TA01b 3030fa 1 For more information www.linear.com/LT3030

LT3030 absoluTe MaxiMuM raTings (Note 1) IN1, IN2 Pin Voltage ................................................±22V Operating Junction Temperature (Notes 2, 12) OUT1, OUT2 Pin Voltage .........................................±22V E-/I-Grade ..........................................–40°C to 125°C Input-to-Output Differential Voltage ........................±22V H-Grade .............................................–40°C to 150°C ADJ1, ADJ2 Pin Voltage ............................................±9V MP-Grade ..........................................–55°C to 150°C BYP1, BYP2 Pin Voltage ........................................±0.6V Storage Temperature Range SHDN1, SHDN2 Pin Voltage ....................................±22V QFN/TSSOP Package .............................–65°C to 150°C PWRGD1, PWRGD2 Pin Voltage ....................22V, –0.3V Lead Temperature (Soldering, 10 sec) Output Short-Circuit Duration ..........................Indefinite (TSSOP Only) ........................................................300°C pin conFiguraTion TOP VIEW 1 YP1 DJ1 ND ND ND HDN TOP VIEW B A G G G S ADJ1 1 20 SHDN1 28 27 26 25 24 23 BYP1 2 19 PWRGD1 OUT1 1 22 PWRGD1 OUT1 3 18 IN1 OUT1 2 21 IN1 GND 3 20 IN1 OUT1 4 17 IN1 GND 4 29 19 GND GND 5 21 16 GND GND 5 GND 18 GND GND 6 GND 15 GND GND 6 17 IN2 OUT2 7 14 IN2 OUT2 7 16 IN2 OUT2 8 13 IN2 OUT2 8 15 PWRGD2 BYP2 9 12 PWRGD2 9 10 11 12 13 14 ADJ2 10 11 SHDN2 2 2 D D D 2 BYP ADJ GN GN GN HDN FE PACKAGE S 20-LEAD PLASTIC TSSOP UFD PACKAGE 28-LEAD (4mm × 5mm) PLASTIC QFN EXPOSEDT JPMAADX =(P 1IN50 2°1C), IθSJ AG =N D28, °MCU/WST, ,B θEJ CS O= L1D0E°CR/EWD TO PCB TJMAX = 125°C, θJA = 33°C/W, , θJC = 3.4°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3030EUFD#PBF LT3030EUFD#TRPBF 3030 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LT3030IUFD#PBF LT3030IUFD#TRPBF 3030 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LT3030HUFD#PBF LT3030HUFD#TRPBF 3030 28-Lead (4mm × 5mm) Plastic QFN –40°C to 150°C LT3030EFE#PBF LT3030EFE#TRPBF LT3030FE 20-Lead Plastic TSSOP –40°C to 125°C LT3030IFE#PBF LT3030IFE#TRPBF LT3030FE 20-Lead Plastic TSSOP –40°C to 125°C LT3030HFE#PBF LT3030HFE#TRPBF LT3030FE 20-Lead Plastic TSSOP –40°C to 150°C LT3030MPFE#PBF LT3030MPFE#TRPBF LT3030FE 20-Lead Plastic TSSOP –55°C to 150°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3030fa 2 For more information www.linear.com/LT3030

LT3030 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C (Note 2). A PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum Input Voltage (Notes 3, 11) Output 1, I = 750mA l 1.7 2.2 V LOAD Output 2, I = 250mA l 1.7 2.2 V LOAD ADJ1, ADJ2 Pin Voltage (Notes 3, 4) V = 2V, I = 1mA 1.208 1.220 1.232 V IN LOAD Output 1, 2.2V < V < 20V, 1mA < I < 750mA l 1.196 1.220 1.244 V IN1 LOAD Output 2, 2.2V < V < 20V, 1mA < I < 250mA l 1.196 1.220 1.244 V IN2 LOAD Line Regulation (Note 3) ∆V = 2V to 20V, I = 1mA l 0.5 5 mV IN LOAD Load Regulation (Note 3) Output 1, V = 2.2V, ∆I = 1mA to 750mA 2 6 mV IN1 LOAD V = 2.2V, ∆I = 1mA to 750mA l 10 mV IN1 LOAD Output 2, V = 2.2V, ∆I = 1mA to 250mA 2 6 mV IN2 LOAD V = 2.2V, ∆I = 1mA to 250mA l 10 mV IN2 LOAD Dropout Voltage (Output 1) I = 10mA 0.13 0.20 V LOAD V = V I = 10mA l 0.28 V IN1 OUT1(NOMINAL) LOAD (Notes 5, 6, 11) I = 100mA 0.17 0.23 V LOAD I = 100mA l 0.33 V LOAD I = 500mA 0.27 0.32 V LOAD I = 500mA l 0.43 V LOAD I = 750mA 0.3 0.36 V LOAD I = 750mA l 0.48 V LOAD Dropout Voltage (Output 2) I = 10mA 0.14 0.20 V LOAD V = V I = 10mA l 0.28 V IN2 OUT2(NOMINAL) LOAD (Notes 5, 6, 11) I = 50mA 0.18 0.24 V LOAD I = 50mA l 0.32 V LOAD I = 100mA 0.22 0.28 V LOAD I = 100mA l 0.38 V LOAD I = 250mA 0.3 0.36 V LOAD I = 250mA l 0.48 V LOAD GND Pin Current (Output 1) I = 0mA l 120 300 μA LOAD V = V I = 10mA l 420 800 μA IN1 OUT1(NOMINAL) LOAD (Notes 5, 7) I = 100mA l 2 3.8 mA LOAD I = 500mA l 9 17 mA LOAD I = 750mA l 15 27 mA LOAD GND Pin Current (Output 2) I = 0mA l 75 200 μA LOAD V = V I = 10mA l 330 600 μA IN2 OUT2(NOMINAL) LOAD (Notes 5, 7) I = 50mA l 1 1.8 mA LOAD I = 100mA l 1.8 3.4 mA LOAD I = 250mA l 5 9 mA LOAD Output Voltage Noise C = 10μF, C = 10nF, I = Full Current (Note 13) 20 μV OUT BYP LOAD RMS BW = 10Hz to 100kHz ADJ1/ADJ2 Pin Bias Current (Notes 3, 8) 30 100 nA Shutdown Threshold V = Off to On l 1.09 1.21 1.33 V OUT V = On to Off l 0.5 0.83 V OUT Hysteresis (Note 2) 0.38 V SHDN1/SHDN2 Pin Current (Note 10) V , V = 0V l 0 0.5 μA SHDN1 SHDN2 V , V = 20V l 0.85 3 μA SHDN1 SHDN2 Quiescent Current in Shutdown (per Channel) V = 20V, V = 0V, V = 0V 0.3 2 μA IN SHDN1 SHDN2 PWRGD Trip Point % of Nominal Output Voltage, Output Rising l 86 90 94 % PWRGD Trip Point Hysteresis (Note 2) % of Nominal Output Voltage, Output Falling 1.6 % PWRGD Output Low Voltage I = 100μA l 15 150 mV PWRGD PWRGD Leakage Current V = 0V, V = 20V l 1 μA SHDN PWRGD 3030fa 3 For more information www.linear.com/LT3030

LT3030 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T = 25°C (Note 2). A PARAMETER CONDITIONS MIN TYP MAX UNITS Ripple Rejection V = 2.72V (Avg), V = 0.5V , 50 60 dB IN RIPPLE P-P f = 120Hz, I = Full Current (Note 13) RIPPLE LOAD V = V + 1V, V = 50mV 50 dB IN OUT(NOMINAL) RIPPLE RMS f = 1MHz, I = Full Current (Note 13) RIPPLE LOAD Current Limit (Note 9) Output 1, V = 6V, V = 0V l 1.1 1.4 1.7 A IN1 OUT1 V = 2.2V, ∆V = –0.1V l 800 mA IN1 OUT1 Output 2, V = 6V, V = 0V l 350 420 490 mA IN2 OUT2 V = 2.2V, ∆V = –0.1V l 270 mA IN2 OUT2 Input Reverse Leakage Current V = –20V, V = 0V l 1 mA IN OUT Reverse Output Current V = 1.220V, V = 0V 0.5 10 μA OUT IN Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 6: Dropout voltage is the minimum input to output voltage differential may cause permanent damage to the device. Exposure to any Absolute needed to maintain regulation at a specified output current. In dropout, the Maximum Rating condition for extended periods may affect device output voltage equals: V – V . IN DROPOUT reliability and lifetime. Note 7: GND pin current is tested with V = 2.447V and a current source IN Note 2: The LT3030 is tested and specified under pulse load conditions load. This means the device is tested while operating in its dropout region such that T ≈ T . The LT3030E is 100% tested at T = 25°C and or at the minimum input voltage specification. This is the worst-case J A A performance is guaranteed from 0°C to 125°C. Performance of the GND pin current. The GND pin current decreases slightly at higher input LT3030E over the full –40°C to 125°C operating junction temperature voltages. Total GND pin current equals the sum of output 1 and output 2 range is assured by design, characterization and correlation with statistical GND pin currents. process controls. The LT3030I is guaranteed over the full –40°C to 125°C Note 8: ADJ1/ADJ2 pin bias current flows into the pin. operating junction temperature range. The LT3030MP is 100% tested and Note 9: The LT3030 contains current limit foldback circuitry. See the guaranteed over the –55°C to 150°C operating junction temperature range. Typical Performance Characteristics section for current limit as a function The LT3030H is tested at 150°C operating junction temperature. High of the V – V differential voltage. IN OUT junction temperatures degrade operating lifetimes. Operating lifetime is Note 10: SHDN1 and SHDN2 pin current flows into the pin. derated at junction temperatures greater than 125°C. Note 11: The LT3030 minimum input voltage specification limits dropout Note 3: The LT3030 is tested and specified for these conditions with the voltage under some output voltage/load conditions. See the curve of ADJ1/ADJ2 pin connected to the corresponding OUT1/OUT2 pin. Minimum Input Voltage in the Typical Performance Characteristics section. Note 4: Maximum junction temperature limits operating conditions. The Note 12: The LT3030 includes overtemperature protection that is intended regulated output voltage specification does not apply for all possible to protect the device during momentary overload conditions. Junction combinations of input voltage and output current. When operating at temperature exceeds the maximum operating junction temperature when maximum input voltage, limit the output current range. When operating at overtemperature protection is active. Continuous operation above the maximum output current, limit the input voltage range. specified maximum operating junction temperature may impair device Note 5: To satisfy minimum input voltage requirements, the LT3030 is reliability. tested and specified for these conditions with an external resistor divider Note 13: The Full Current for I is 750mA and 250mA for Output 1 and (two 243k resistors) for an output voltage of 2.447V. The external resistor LOAD Output 2 respectively. divider adds 5μA of DC load on the output. 3030fa 4 For more information www.linear.com/LT3030

LT3030 Typical perForMance characTerisTics T = 25°C, unless otherwise noted. J OUT1 Guaranteed Dropout OUT1 Dropout Voltage OUT1 Typical Dropout Voltage Voltage vs Temperature 500 500 500 450 mV)450 = TEST POINTS 450 IILL == 755000mmAA UT VOLTAGE (mV) 433220505000000 TJ = 125°C TJT J= =1 5205°°CC DROPOUT VOLTAGE (433220505000000 TJ = 1T5J0 =° C25°C UT VOLTAGE (mV)433220505000000 IIIILLLL ==== 3111000m00mAmmAAA DROPO 150 TJ = –55°C NTEED 150 DROPO150 100 A100 100 R A 50 GU 50 50 0 0 0 0 75 150225300375450525600675750 0 75 150225300375450525600675750 –75–50–25 0 25 50 75 100125150175 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) TEMPERATURE (°C) 3030 G01 3030 G02 3030 G03 OUT2 Guaranteed Dropout OUT2 Dropout Voltage OUT2 Typical Dropout Voltage Voltage vs Temperature 500 500 500 450 mV)450 = TEST POINTS TJ = 150°C 450 IILL == 215705mmAA 400 TJ = 150°C E (400 400 IL = 100mA LTAGE (mV) 335000 TJ = 125°C TJ = 25°C OUT VOLTAG335000 TJ = 25°C LTAGE (mV)335000 IIILLL === 51100mmmAAA O 250 P250 O250 V O V T R T U 200 D200 U200 ROPO 150 TJ = –55°C TEED 150 ROPO150 D N D 100 A100 100 R A 50 GU 50 50 0 0 0 0 25 50 75 100125150175200225250 0 25 50 75 100125150175200225250 –75–50–25 0 25 50 75 100125150175 OUTPUT CURRENT (mA) OUTPUT CURRENT (mA) TEMPERATURE (°C) 3030 G04 3030 G05 3030 G06 Quiescent Current ADJ1/ADJ2 Pin Voltage Quiescent Current 300 1.244 300 VIN1 = VIN2 = 6V IL1 = IL2 = 1mA TJ = 25°C RL1 = RL2 = 243k; IL1 = IL2 = 5µA 1.238 RL1 = RL2 = 243k; IL1 = IL2 = 5µA 250 250 VOUT1 = VOUT2 = 1.220V A) 1.232 A) ENT (µ200 OUTPUT 1 GE (V)1.226 ADJ2 ENT (µ200 UIESCENT CURR115000 VSHDN1 = VINO1UTPUT 2 ADJ PIN VOLTA111...222210048 ADJ1 UIESCENT CURR115000 OOUUTTPPUUTT 12,, VVSSHHDDNN12 == VVIINN12 Q 50 VSHDN2 = VIN2 Q 50 1.202 OUTPUT 1; VSHDN1 = 0V OUTPUT 2; VSHDN2 = 0V 0 1.196 0 –75–50–25 0 25 50 75 100125150175 –75–50–25 0 25 50 75 100125150175 0 2 4 6 8 10 12 14 16 18 20 TEMPERATURE (°C) TEMPERATURE (°C) INPUT VOLTAGE (V) 3030 G07 3030 G08 3030 G09 3030fa 5 For more information www.linear.com/LT3030

LT3030 Typical perForMance characTerisTics T = 25°C, unless otherwise noted. J Quiescent Current in Shutdown (per Output) OUT1 GND Pin Current OUT1 GND Pin Current 1.0 2.4 27 TJ = 25°C TJ = 25°C TJ = 25°C 0.9 RL1 = RL2 = 243k; IL1 = IL2 = 5µA 2.1 FOR VOUT1 = 1.220V 24 FOR VOUT1 = 1.220V 0.8 VOUT1 = VOUT2 = 1.220V µA) VSHDN1 = VSHDN2 = 0V A) 1.8 A) 21 T CURRENT ( 000...576 CURRENT (m 11..52 IL1 = 100mA CURRENT (m 111528 IL1 = 750mA QUIESCEN 000...432 GND PIN 00..96 IL1 = 10mA IL1 = 1mA GND PIN 96 IILL11 == 520500mmAA 0.1 0.3 3 0 0 0 0 2 4 6 8 10 12 14 16 18 20 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V) 3030 G10 3030 G11 3030 G12 OUT1 GND Pin Current OUT2 GND Pin Current OUT2 GND Pin Current 27 1.2 9 TJ = 25°C TJ = 25°C TJ = 25°C 24 VIN1 = VOUT1(NOMINAL) + 1V FOR VOUT2 = 1.220V 8 FOR VOUT2 = 1.220V 1.0 21 7 A) A) A) m m m NT ( 18 NT ( 0.8 NT ( 6 RE 15 RE RE 5 R R 0.6 R N CU 12 N CU IL2 = 25mA N CU 4 IL2 = 250mA D PI 9 D PI 0.4 D PI 3 GN 6 GN IL2 = 10mA GN 2 IL2 = 100mA IL2 = 50mA 0.2 3 IL2 = 1mA 1 0 0 0 0 75 150225300375450525600675750 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 OUTPUT CURRENT (mA) INPUT VOLTAGE (V) INPUT VOLTAGE (V) 3030 G13 3030 G14 3030 G15 SHDN1 or SHDN2 Pin Input OUT2 GND Pin Current SHDN1 or SHDN2 Pin Threshold Current 9 1.4 2.0 8 VTJIN =2 2=5 V°COUT2(NOMINAL) + 1V 1.2 OFF TO ON 1.8 TJ = 25°C mA) 7 D (V) 1.0 NT (µA) 11..64 GND PIN CURRENT ( 64253 SHDN PIN THRESHOL 000...864 ON TO OFF HDN PIN INPUT CURRE 10001.....08642 VVIINN == 22.02VV 0.2 S 1 0.2 VIN = 2.2V 0 0 0 0 25 50 75 100125150175200225250 –75–50–25 0 25 50 75 100125150175 0 2 4 6 8 10 12 14 16 18 20 OUTPUT CURRENT (mA) TEMPERATURE (°C) SHDN PIN VOLTAGE (V) 3030 G16 3030 G17 3030 G18 3030fa 6 For more information www.linear.com/LT3030

LT3030 Typical perForMance characTerisTics T = 25°C, unless otherwise noted. J SHDN1 or SHDN2 Pin Input Current ADJ1 or ADJ2 Pin Bias Current PWRGD1 or PWRGD2 Trip Point 2.0 150 E) 94 G 1.8 135 LTA 93 CURRENT (µA) 111...642 VIN = 2.2V, URRENT (nA)11209050 OF OUTPUT VO 9912 OUTPUT RISING N INPUT 10..08 VSHDN = 20V N BIAS C 7650 OINT (% 9809 DN PI 0.6 DJ PI 45 RIP P 88 OUTPUT FALLING SH 00..42 VVISNH D= N2 0=V 2.2V A 3105 RGD T 87 W 0 0 P 86 –75–50–25 0 25 50 75 100125150175 –75–50–25 0 25 50 75 100125150175 –75–50–25 0 25 50 75 100125150175 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 3030 G19 3030 G20 3030 G21 PWRGD1 or PWRGD2 Output Low Voltage OUT1 Current Limit OUT1 Current Limit 150 2.00 2.0 IPWRGD = 100µA VOUT = 0V VOUT = 0V V)135 1.75 1.8 m GE (120 1.50 1.6 VIN = 6V LOW VOLTA1709550 T LIMIT (A) 11..2050 TTJJ == 2–55°5C°C T LIMIT (A) 111...420 OUTPUT 6405 CURREN 0.75 TJ = 150°C TJ = 125°C CURREN 00..86 D 0.50 RG 30 0.4 VIN = 18V PW 15 0.25 0.2 0 0 0 –75–50–25 0 25 50 75 100125150175 0 2 4 6 8 10 12 14 16 18 20 –75–50–25 0 25 50 75 100125150175 TEMPERATURE (°C) INPUT VOLTAGE (V) TEMPERATURE (°C) 3030 G22 3030 G23 3030 G24 OUT2 Current Limit OUT2 Current Limit Reverse Current 0.60 0.60 5.0 VOUT = 0V VOUT = 0V TJ = 25°C 0.54 0.54 4.5 VIN1 = VIN2 = 0V 0.48 0.48 4.0 VADJ1 = VOUT1 VIN = 6V A) VADJ2 = VOUT2 CURRENT LIMIT (A) 00000.....4332126048 TTTJJJ = == 1 –225555°°°CCC CURRENT LIMIT (A) 00000.....4332126048 VIN = 18V EVERSE CURRENT (m 33221.....50505 IADJ1 OR IADJ2 R 0.12 TJ = 150°C 0.12 1.0 0.06 0.06 0.5 IOUT1 OR IOUT2 0 0 0 0 2 4 6 8 10 12 14 16 18 20 –75–50–25 0 25 50 75 100125150175 0 1 2 3 4 5 6 7 8 9 INPUT VOLTAGE (V) TEMPERATURE (°C) OUTPUT VOLTAGE (V) 3030 G25 3030 G26 3030 G27 IADJ = FLOWS INTO ADJ PIN TO GND PIN IOUT = FLOWS INTO OUT PIN TO IN PIN 3030fa 7 For more information www.linear.com/LT3030

LT3030 Typical perForMance characTerisTics T = 25°C, unless otherwise noted. J Reverse Current OUT1 Input Ripple Rejection OUT1 Input Ripple Rejection 500 100 100 VIN1 = VIN2 = 0V 450 VADJ1 = VOUT1 = 1.220V 90 90 400 VADJ2 = VOUT2 = 1.220V 80 80 RENT (µA) 335000 TION (dB) 7600 COUCTO1U =T 12 2=µ 4F7µF TION (dB) 7600 CBYP1 = 10nF CBYP1 = 1000pF VERSE CUR 221505000 IADJ1 OR IADJ2 IOUT1 PPLE REJEC 543000 COUT1 = 10µF PPLE REJEC 543000 CBYP1 = 100pF RE 100 RI 20 TJ = 25°C RI 20 TJ = 25°C IL1 = 750mA, CBYP1 = 0 IL1 = 750mA, COUT1 = 22µF 50 IOUT2 10 VIN1 = VOUT1(NOMINAL) + 1V 10 VIN1 = VOUT1(NOMINAL) + 1V + 50mVRMS RIPPLE + 50mVRMS RIPPLE 0 0 0 –75 –25 0 25 50 75 100 125 150 175 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M TEMPERATURE (°C) FREQUENCY (Hz) FREQUENCY (Hz) 3030 G28 3030 G29 3030 G30 IADJ = FLOWS INTO ADJ PIN TO GND PIN IOUT = FLOWS INTO OUT PIN TO IN PIN OUT1 Input Ripple Rejection OUT2 Input Ripple Rejection OUT2 Input Ripple Rejection 100 100 100 90 90 90 dB) 8700 dB) 8700 COUT2 = 10µF dB) 8700 CBYP2 = 1000pF CBYP2 = 10nF N ( N ( COUT2 = 22µF N ( O 60 O 60 O 60 TI TI TI C C C E 50 E 50 E 50 J J J RE RE RE CBYP2 = 100pF E 40 E 40 E 40 PL PL COUT2 = 3.3µF PL P 30 P 30 P 30 RI 20 VIN1 = VOUT1(NOMINAL) + 1.5V RI 20 TJ = 25°C RI 20 TJ = 25°C + 500mVP-P RIPPLE IL2 = 250mA, CBYP2 = 0 IL2 = 250mA, COUT2 = 10µF 10 f = 120Hz 10 VIN2 = VOUT2(NOMINAL) + 1V 10 VIN2 = VOUT2(NOMINAL) + 1V IL1 = 750mA + 50mVRMS RIPPLE + 50mVRMS RIPPLE 0 0 0 –75–50–25 0 25 50 75 100125150175 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M TEMPERATURE (°C) FREQUENCY (Hz) FREQUENCY (Hz) 3030 G31 3030 G32 3030 G33 OUT2 Input Ripple Rejection Channel-to-Channel Isolation Channel-to-Channel Isolation 100 100 90 B) 90 d E REJECTION (dB) 8765400000 CHANNEL ISOLATION ( 8765400000 CCHHAANNNNEELL 12 110000mmVVVVOO//DDUUTTIIVV12 RIPPL 321000 fIV L =I2 N 12= 2 = 2 0 +5VH 05Ozm0U0TAm2(NVOPM-PI NRAILP)P +L E1.5V CHANNEL-TO- 321000 G5CDT0JHIE VmL=AEI NV2VNRN5E CM°ERCHLSIN,A SBGNIO GNFTNUEHLAL LLCIS HCO TAUNENR SONRTPEEEPLNDOST S WINITGH COUT1 = 10µF 50µs/∆DIILV1 = 50mA TO 753003m0 GA36 0 0 COUT2 = 3.3µF ∆IL2 = 50mA TO 250mA –75–50–25 0 25 50 75 100125150175 10 100 1k 10k 100k 1M 10M CBYP1 = CBYP2 = 0.01µF VIN = 6V, VOUT1 = VOUT2 = 5V TEMPERATURE (°C) FREQUENCY (Hz) 3030 G34 3030 G35 3030fa 8 For more information www.linear.com/LT3030

LT3030 Typical perForMance characTerisTics T = 25°C, unless otherwise noted. J OUT1 or OUT2 Load Regulation OUT1 or OUT2 Line Regulation Output Noise Spectral Density 10 5 10 ∆IL = 1mA TO FULL LOAD ∆VIN = 2V TO 20V Hz) TJ = 25°C AD REGULATION (mV) ––8642024 NE REGULATION (mV) ––4231021 SE SPECTRAL DENSITY (µV/√ 0.11 CICLOB =YU PTF U== L 01L0 LµOFAD VVOOUUT T= = V 5AVDJ LO –6 LI –3 T NOI U –8 –4 TP U O –10 –5 0.01 –75–50–25 0 25 50 75 100125150175 –75–50–25 0 25 50 75 100125150175 0.01 0.1 1 10 100 TEMPERATURE (°C) TEMPERATURE (°C) FREQUENCY (kHz) 3030 G37 3030 G38 3030 G39 RMS Output Noise vs Bypass OUT1 RMS Output Noise Output Noise Spectral Density Capacitor vs Output Current (10Hz to 100kHz) 10 160 160 Hz) TJ = 25°C TJ = 25°C TJ = 25°C SITY (µV/√ VOUT = 5V CILO =U TF U=L 1L0 LµOFAD )MS114200 VOUT = 5V CfILBO W=U TF= U =1L 01LH0 Lµz OFTAOD 100kHz )MS114200 COUT = 10µF VOUT1 = 5V TRAL DEN 1 CBYP = 100pF OISE (µVR10800 OUTPUT2OUTPUT1 OISE (µVR10800 CBYP1 = 0 VOUT1 = VADJ1 OISE SPEC0.1 VOUT = VADJ OUTPUT N 4600 VOUT = 1.220V OUTPUT N 4600 CBYP1 = 0 T N CBYP = 0.01µF VOUT1 = VADJ1 UTPU CBYP = 1000pF 20 OUTPUT1 OUTPUT2 20 VOUT1 = 5V CBYP1 = 10nF O0.01 0 0 0.01 0.1 1 10 100 10 100 1000 10000 0.01 0.1 1 10 100 1000 FREQUENCY (Hz) CBYP (pF) OUTPUT CURRENT (mA) 3030 G40 3030 G41 3030 G42 OUT2 RMS Output Noise Start-Up Time from Shutdown Start-Up Time from Shutdown vs Output Current (10Hz to 100kHz) C = 0pF C = 0.01µF BYP BYP 160 TJ = 25°C 140 COUT = 10µF )MS120 VOUT2 = 5V 1VV/ODUIVT VOUT µVR100 CBYP2 = 0 1V/DIV E ( OIS 80 VOUT2 = VADJ2 UT N 60 CBYP2 = 0 SHDN SHDN TP VOLTAGE VOLTAGE OU 40 2V/DIV 2V/DIV 20 VOUT2 = 5V CBYP2 = 10nF 1ms/DIV 3030 G44 1ms/DIV 3030 G45 0 VOUT2 = VADJ2 VCIINN == 21.05µVF TILJ == F2U5L°LC LOAD VCIINN == 21.05µVF TILJ == F2U5L°LC LOAD 0.01 0.1 1 10 100 1000 COUT = 10µF VOUT = 1.5V COUT = 10µF VOUT = 1.5V OUTPUT CURRENT (mA) 3030 G43 3030fa 9 For more information www.linear.com/LT3030

LT3030 Typical perForMance characTerisTics T = 25°C, unless otherwise noted. J OUT1 or OUT2 Minimum Input 10Hz to 100kHz Output Noise, 10Hz to 100kHz Output Noise, Voltage C = 0pF C = 100pF BYP BYP 2.50 VOUT1 = VOUT2 = 1.220V 2.25 V) 2.00 E ( IL = FULL LOAD G 1.75 A VOLT 1.50 IL = 1mA 100µVV/ODUIVT 100µVV/ODUIVT UT 1.25 P N M I 1.00 U M 0.75 NI MI 0.50 1ms/DIV 3030 G47 1ms/DIV 3030 G48 0.25 COUT = 10µF COUT = 10µF IL = FULL LOAD IL = FULL LOAD 0–75–50–25 0 25 50 75 100125150175 VOUT = 5V VOUT = 5V TEMPERATURE (°C) 3030 G46 10Hz to 100kHz Output Noise, 10Hz to 100kHz Output Noise, OUT1 Transient Response C = 1000pF C = 0.01µF C = 0pF BYP BYP BYP VOUT DEVIATION 200mV/DIV VOUT VOUT 100µV/DIV 100µV/DIV LOAD CURRENT DEVIATION 500mA/DIV 1ms/DIV 3030 G49 1ms/DIV 3030 G50 200µs/DIV 3030 G51 VCILOO =UU TTF U==L 15L0V LµOFAD VCILOO =UU TTF U==L 15L0V LµOFAD VCCIIONNU ==T =62 V22µ2FµF TVILJO =U= T 12 0=50 °5mCVA TO 750mA OUT1 Transient Response OUT2 Transient Response OUT2 Transient Response C = 0.01µF C = 0pF C = 0.01µF BYP BYP BYP VOUT DEVIATION VOUT DEVIATION VOUT DEVIATION 50mV/DIV 200mV/DIV 50mV/DIV LOAD CURRENT DEVIATION LOAD CURRENT DEVIATION LOAD CURRENT DEVIATION 500mA/DIV 100mA/DIV 100mA/DIV 20µs/DIV 3030 G52 200µs/DIV 3030 G53 20µs/DIV 3030 G54 VIN = 6V IL = 100mA TO 750mA VIN = 6V IL = 100mA TO 250mA VIN = 6V IL = 100mA TO 250mA CIN = 22µF TJ = 25°C CIN = 10µF TJ = 25°C CIN = 10µF TJ = 25°C COUT = 22µF VOUT = 5V COUT = 10µF VOUT = 5V COUT = 10µF VOUT = 5V 3030fa 10 For more information www.linear.com/LT3030

LT3030 pin FuncTions (QFN/TSSOP) OUT1, OUT2 (Pins 1, 2, 7, 8/Pins 3, 4, 7, 8): Output. The changes state from an open-collector pull-down to high OUT1/OUT2 pins supply power to the loads. A minimum impedance after the output increases above 90% of the 10μF/3.3μF output capacitor prevents oscillations on nominal voltage. The maximum pull-down current of the OUT1/OUT2. Applications with large output load transients PWRGD pin in the low state is 100μA. require larger values of output capacitance to limit peak SHDN1, SHDN2 (Pins 23, 14/Pins 20, 11): Shutdown. voltage transients. See the Applications Information sec- Pulling the SHDN1 or SHDN2 pin low puts its correspond- tion for more on output capacitance and on reverse output ing LT3030 channel into a low power state and turns its characteristics. output off. The SHDN1 and SHDN2 pins are completely GND (Pins 3, 4, 5, 6, 11, 12, 13, 18, 19, 24, 25, 26, independent of each other, and each SHDN pin only affects Exposed Pad Pin 29/Pins 5, 6, 15, 16, Exposed Pad Pin operation on its corresponding channel. Drive the SHDN1 21): Ground. The exposed pad (backside) of the QFN and and SHDN2 pins with either logic or an open collector/drain TSSOP packages is an electrical connection to GND. To with pull-up resistors. The resistors supply the pull-up ensure proper electrical and thermal performance, sol- current to the open collectors/drains and the SHDN1 or der the exposed pad to the PCB ground and tie directly SHDN2 current, typically less than 1μA. If unused, con- to GND pins. Connect the bottom of the output voltage nect SHDN1 and SHDN2 to their corresponding IN pins. setting resistor divider directly to GND for optimum load Each channel will be in its low power shutdown state if its regulation performance. corresponding SHDN pin is not connected. IN1, IN2 (Pins 20, 21, 16, 17/Pins 17, 18, 13, 14): In- ADJ1, ADJ2 (Pins 27, 10/Pins 1, 10): Adjust Pin. These put. The IN1/IN2 pins supply power to each channel. The are the error amplifier inputs. These pins are internally LT3030 requires a bypass capacitor at the IN1/IN2 pins clamped to ±9V. A typical input bias current of 30nA flows if located more than six inches away from the main input into the pins (see curve of ADJ1/ADJ2 Pin Bias Current vs filter capacitor. Include a bypass capacitor in battery- Temperature in the Typical Performance Characteristics powered circuits, as a battery’s output impedance rises section). The ADJ1 and ADJ2 pin voltages are 1.220V with frequency. A bypass capacitor in the range of 1μF to referenced to ground and the output voltage range is 10μF suffices. The LT3030’s design withstands reverse 1.220V to 19.5V. voltages on the IN pins with respect to ground and the BYP1, BYP2 (Pins 28, 9/Pins 2, 9): Bypass. Connecting OUT pins. In the case of a reversed input, which occurs a capacitor between OUT and BYP of a respective chan- if a battery is plugged in backwards, the LT3030 acts as nel bypasses the LT3030 reference to achieve low noise if a diode is in series with its input. No reverse current performance, improve transient response and soft-start flows into the LT3030 and no reverse voltage appears at the output. Internal circuitry clamps the BYP1/BYP2 pins the load. The device protects itself and the load. to ±0.6V (one V ) from ground. A small capacitor from BE PWRGD1, PWRGD2 (Pins 22, 15/Pins 19, 12): Power the corresponding output to this pin bypasses the refer- Good. The PWRGD flag is an open-collector flag to indicate ence to lower the output voltage noise. Using a maximum that the output voltage has increased above 90% of the value of 10nF reduces the output voltage noise to a typical nominal output voltage. There is no internal pull-up on 20μV over a 10Hz to 100kHz bandwidth. If not used, RMS this pin; a pull-up resistor must be used. The PWRGD pin this pin must be left unconnected. 3030fa 11 For more information www.linear.com/LT3030

LT3030 applicaTions inForMaTion The LT3030 is a dual 750mA/250mA low dropout regulator LT3030 wanitdh sihnudtedpoewnnd.e Tnht ein dpeuvtisc,e m suicprpolpieosw uepr tqou 7ie5s0cmenAt /c2u5r0rmenAt VIN IN1/INO2UT1/OUT2 VOUT VOUT=1.220V⎛⎝⎜1+RR21⎞⎠⎟+(IADJ)(R2) R2 COUT from the outputs of channel 1/channel 2 at a typical dropout VADJ=1.220V voltage of 300mV. The two regulators share common GND ADJ1/ADJ2 IADJ=30nA AT 25°C GND pins and are thermally coupled. However, the two inputs 3030 F01 R1 OUTPUT RANGE = 1.220V TO 19.5V and outputs of the LT3030 operate independently. Each Figure 1. Adjustable Operation channel can be shut down independently, but a thermal shutdown fault on either channel shuts off the output on For example, load regulation on OUT2 for an output cur- both channels. The addition of a 10nF reference bypass ca- rent change of 1mA to full load current is typically –2mV pacitor lowers output voltage noise to 20μV over a 10Hz at V = 1.220V. At V = 2.5V, load regulation is: RMS OUT2 OUT2 to 100kHz bandwidth. Additionally, the reference bypass (2.5V/1.220V) • (–2mV) = –4.1mV capacitor improves transient response of the regulator, lowering the settling time for transient load conditions. The Table 1 shows 1% resistor divider values for some com- low operating quiescent current (120μA/75μA for channel mon output voltages with a resistor divider current of 1/2) drops to typically less than 1μA in shutdown. In ad- approximately 5μA. dition to the low quiescent current, the LT3030 regulator Table 1. Output Voltage Resistor Divider Values incorporates several protection features that make it ideal V (V) R1 (k) R2 (k) OUT for use in battery powered systems. Most importantly, 1.5 237 54.9 the device protects itself against reverse input voltages. 1.8 237 113 2.5 243 255 Adjustable Operation 3 232 340 3.3 210 357 Each of the LT3030’s channels has an output voltage range 5 200 619 of 1.220V to 19.5V. Figure 1 illustrates that the output voltage is set by the ratio of two external resistors. The Bypass Capacitance and Low Noise Performance device regulates the output to maintain the corresponding Using a bypass capacitor connected between a channel’s ADJ pin voltage at 1.220V referenced to ground. R1’s cur- BYP pin and its corresponding OUT pin significantly low- rent equals 1.220V/R1. R2’s current equals R1’s current ers LT3030 output voltage noise, but is not required in plus the ADJ pin bias current. The ADJ pin bias current, all applications. Linear Technology recommends a good 30nA at 25°C, flows through R2 into the ADJ pin. Use quality low leakage capacitor. This capacitor bypasses the formula in Figure 1 to calculate output voltage. Linear the regulator’s reference, providing a low frequency noise Technology recommends that the value of R1 be less than pole. A 10nF bypass capacitor introduces a noise pole that 243k to minimize errors in the output voltage due to the decreases output voltage noise to as low as 20μV . Using ADJ pin bias current. In shutdown, the output turns off RMS a bypass capacitor provides the added benefit of improv- and the divider current is zero. Curves of ADJ Pin Voltage ing transient response. With no bypass capacitor and a vs Temperature and ADJ Pin Bias Current vs Temperature 10μF output capacitor, a 100mA to full load step settles to appear in the Typical Performance Characteristics section. within 1% of its final value in approximately 400μs. With Linear Technology tests and specifies each LT3030 channel the addition of a 10nF bypass capacitor and evaluating with its ADJ pin tied to the corresponding OUT pin for a the same load step, output voltage excursion stays within 1.220V output voltage. Specifications for output voltages 2% (see Transient Response in the Typical Performance greater than 1.220V are proportional to the ratio of desired Characteristics section). Using a bypass capacitor makes output voltage to 1.220V: regulator start-up time proportional to the value of the V /1.220V bypass capacitor. For example, a 10nF bypass capacitor OUT and 10μF output capacitor slow start-up time to 15ms. 3030fa 12 For more information www.linear.com/LT3030

LT3030 applicaTions inForMaTion Input Capacitance and Stability LT3030’s output also helps. However, this requires an order of magnitude more capacitance in comparison with Each LT3030 channel is stable with an input capacitor additional LT3030 input bypassing. Series resistance be- typically between 1µF and 10µF. Applications operating tween the supply and the LT3030 input also helps stabilize with smaller V to V differential voltages and that ex- IN OUT the application; as little as 0.1Ω to 0.5Ω suffices. This perience large load transients may require a higher input impedance dampens the LC tank circuit at the expense of capacitor value to prevent input voltage droop and letting dropout voltage. A better alternative is to use higher ESR the regulator enter dropout. tantalum or electrolytic capacitors at the LT3030 input in Very low ESR ceramic capacitors may be used. However, place of ceramic capacitors. in cases where long wires connect the power supply to the LT3030’s input and ground, use of low value input capaci- Output Capacitance and Transient Response tors combined with an output load current of greater than The LT3030 is stable with a wide range of output capacitors. 20mA may result in instability. The resonant LC tank circuit The ESR of the output capacitor affects stability, most nota- formed by the wire inductance and the input capacitor is bly with small capacitors. Linear Technology recommends the cause and not a result of LT3030 instability. a minimum output capacitor of 10μF/3.3μF (channel 1 The self-inductance, or isolated inductance, of a wire /channel 2) with an ESR of 3Ω, or less, to prevent oscil- is directly proportional to its length. However, the wire lations. The LT3030 is a micropower device, and output diameter has less influence on its self inductance. For transient response is a function of output capacitance. example, the self-inductance of a 2-AWG isolated wire Larger values of output capacitance decrease the peak with a diameter of 0.26" is about half the inductance of a deviations and provide improved transient response for 30-AWG wire with a diameter of 0.01". One foot of 30-AWG larger load current changes. wire has 465nH of self-inductance. Ceramic capacitors require extra consideration. Manufac- Several methods exist to reduce a wire’s self-inductance. turers make ceramic capacitors with a variety of dielectrics, One method divides the current flowing towards the LT3030 each with different behavior across temperature and applied between two parallel conductors. In this case, placing the voltage. The most common dielectrics specify the EIA wires further apart reduces the inductance; up to a 50% temperature characteristic codes of Z5U, Y5V, X5R and reduction when placed only a few inches apart. Splitting X7R. Z5U and Y5V dielectrics provide high C-V products the wires connects two equal inductors in parallel. How- in a small package at low cost, but exhibit strong voltage ever, when placed in close proximity to each other, mutual and temperature coefficients, as shown in Figure 2 and inductance adds to the overall self inductance of the wires. Figure 3. When used with a 5V regulator, a 16V 10μF Y5V The most effective technique to reducing overall inductance capacitor can exhibit an effective value as low as 1μF to is to place the forward and return current conductors (the 2μF for the applied DC bias voltage and over the operat- input wire and the ground wire) in close proximity. Two ing temperature range. X5R and X7R dielectrics result in 30-AWG wires separated by 0.02" reduce the overall self more stable characteristics and are more suitable for use inductance to about one-fifth of a single wire. as the output capacitor. The X7R type has better stability across temperature, while the X5R is less expensive and If a battery, mounted in close proximity, powers the LT3030, is available in higher values. a 1μF input capacitor suffices for stability. However, if a distantly located supply powers the LT3030, use a larger Exercise care even when using X5R and X7R capacitors; value input capacitor. Use a rough guideline of 1μF (in the X5R and X7R codes only specify operating temperature addition to the 1μF minimum) per 8 inches of wire length. range and maximum capacitance change over temperature. The minimum input capacitance needed to stabilize the Capacitance change due to DC bias (voltage coefficient) application also varies with power supply output imped- with X5R and X7R capacitors is better than with Y5V and ance variations. Placing additional capacitance on the Z5U capacitors, but can still be significant enough to drop 3030fa 13 For more information www.linear.com/LT3030

LT3030 applicaTions inForMaTion capacitor values below appropriate levels. Capacitor DC Voltage and temperature coefficients are not the only bias characteristics tend to improve as case size increases. sources of problems. Some ceramic capacitors have a Linear Technology recommends verifying expected versus piezoelectric response. A piezoelectric device generates actual capacitance values at operating voltage in situ for voltage across its terminals due to mechanical stress, an application. similar to the way a piezoelectric accelerometer or micro- phone works. For a ceramic capacitor, the stress can be 20 induced by vibrations in the system or thermal transients. BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10µF The resulting voltages produced can cause appreciable 0 amounts of noise, especially when a ceramic capacitor is %) X5R E (–20 used for noise bypassing. A ceramic capacitor produced U AL the trace's response to light tapping from a pencil, as V E IN –40 shown in Figure 4. Similar vibration induced behavior can G N masquerade as increased output voltage noise. A–60 H C Y5V –80 Shutdown/UVLO –100 The SHDN pin is used to put the LT3030 into a micropower 0 2 4 6 8 10 12 14 16 DC BIAS VOLTAGE (V) shutdown state. The LT3030 has an accurate 1.21V 3030 F02 threshold (during turn-on) on the SHDN pin. This threshold Figure 2. Ceramic Capacitor DC Bias Characteristics can be used in conjunction with a resistor divider from the system input supply to define an accurate undervoltage 40 lockout (UVLO) threshold for the regulator. The SHDN pin 20 current (at the threshold) needs to be considered when determining the resistor divider network. %) 0 X5R E ( U L –20 PWRGD Flag A V N E I –40 The PWRGD flag indicates that the ADJ pin voltage is G Y5V N HA –60 within 10% of the regulated voltage. The PWRGD pin is an C open-collector output, capable of sinking 100μA of current –80 BOTH CAPACITORS ARE 16V, when the ADJ pin voltage is below 90% of the regulated 1210 CASE SIZE, 10µF –100 voltage. There is no internal pull-up on the PWRGD pin; –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) an external pull-up resistor must be used. As the ADJ 3030 F03 pin voltage rises above 90% of its regulated voltage, the Figure 3. Ceramic Capacitor Temperature Characteristics PWRGD pin switches to a high impedance state and the external pull-up resistor pulls the PWRGD pin voltage up. COUT = 10µF During normal operation, an internal glitch filter prevents CBYP = 0.01µF the PWRGD pin from switching to a low voltage state if ILOAD = 750mA the ADJ pin voltage falls below the regulated voltage by VOUT more than 10% in a short transient (<40μs typical) event. 500µV/DIV Thermal Considerations The LT3030’s power handling capability limits the maxi- mum rated junction temperature (125°C, LT3030E/LT3030I 100ms/DIV 3030 F04 or 150°C, LT3030H/LT3030MP). Two components com- Figure 4. Noise Resulting from Tapping on a Ceramic Capacitor prise the power dissipated by each channel: 3030fa 14 For more information www.linear.com/LT3030

LT3030 applicaTions inForMaTion 1. Output current multiplied by the input/output voltage Table 3. FE Package, 20-Lead TSSOP differential: (IOUT)(VIN – VOUT), and COPPER AREA THERMAL RESISTANCE TOPSIDE* BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT) 2.GND pin current multiplied by the input voltage: 2500mm2 2500mm2 2500mm2 25°C/W (I )(V ). GND IN 1000mm2 2500mm2 2500mm2 27°C/W Ground pin current is found by examining the GND Pin 225mm2 2500mm2 2500mm2 28°C/W Current curves in the Typical Performance Characteristics 100mm2 2500mm2 2500mm2 32°C/W section. *Device is mounted on topside. Power dissipation for each channel equals the sum of the The junction-to-case thermal resistance (θ ), measured two components listed above. Total power dissipation for JC at the exposed pad on the back of the die, is 3.4°C/W for the LT3030 equals the sum of the power dissipated by the QFN package, and 10°C/W for the TSSOP package. each channel. The LT3030’s internal thermal shutdown circuitry Calculating Junction Temperature protects both channels of the device if either channel Example: Channel 1’s output voltage is set to 1.8V. experiences an overload or fault condition. Activation Channel 2’s output voltage is set to 1.5V. Each channel’s of the thermal shutdown circuitry turns both channels input voltage is 2.5V. Channel 1’s output current range off. If the overload or fault condition is removed, both is 0mA to 750mA. Channel 2’s output current range is outputs are allowed to turn back on. For continu- 0mA to 250mA. The application has a maximum ambient ous normal conditions, do not exceed the maximum temperature of 50°C. What is the LT3030’s maximum junction temperature rating of 125°C (LT3030E/LT3030I) junction temperature? or 150°C (LT3030H/LT3030MP). The power dissipated by each channel equals: Carefully consider all sources of thermal resistance from junction-to-ambient, including additional heat sources I (V – V ) + I (V ) OUT(MAX) IN OUT GND IN mounted in proximity to the LT3030. For surface mount where for output 1: devices, use the heat spreading capabilities of the PC board and its copper traces to accomplish heat sinking. Copper IOUT(MAX) = 750mA board stiffeners and plated through-holes can also spread VIN = 2.5V the heat generated by power devices. IGND at (IOUT = 750mA, VIN = 2.5V) = 13mA The following tables list thermal resistance as a function of For output 2: copper area in a fixed board size. All measurements were I = 250mA OUT(MAX) taken in still air on a four-layer FR-4 board with 1oz solid V = 2.5V IN internal planes, and 2oz external trace planes with a total I at (I = 250mA, V = 2.5V) = 4.5mA GND OUT IN board thickness of 1.6mm. For further information on ther- So, for output 1: mal resistance and using thermal information, refer to JEDEC standard JESD51, notably JESD 51-7 and JESD 51-12. P = 750mA (2.5V – 1.8V) + 13mA (2.5V) = 0.56W Table 2. UFD Package, 28-Lead QFN For output 2: COPPER AREA THERMAL RESISTANCE P = 250mA (2.5V – 1.5V) + 4.5mA (2.5V) = 0.26W TOPSIDE* BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT) 2500mm2 2500mm2 2500mm2 30°C/W The thermal resistance is in the range of 25°C/W to 35°C/W, 1000mm2 2500mm2 2500mm2 32°C/W depending on the copper area. So, the junction temperature 225mm2 2500mm2 2500mm2 33°C/W rise above ambient temperature approximately equals: 100mm2 2500mm2 2500mm2 35°C/W (0.56W + 0.26W) 30°C/W = 24.6°C *Device is mounted on topside. 3030fa 15 For more information www.linear.com/LT3030

LT3030 applicaTions inForMaTion The maximum junction temperature then equals the maxi- The LT3030 incurs no damage if either ADJ pin is pulled mum ambient temperature plus the maximum junction above or below ground by 9V. If the input is left open temperature rise above ambient temperature, or: circuit or grounded, the ADJ pins perform like an open circuit down to –1.5V, and then like a 1.2k resistor down T = 50°C + 24.6°C = 74.6°C JMAX to –9V when pulled below ground. When pulled above ground, the ADJ pins perform like an open circuit up to Protection Features 0.5V, then like a 5.7k resistor up to 3V, then like a 1.8k The LT3030 regulator incorporates several protection fea- resistor up to 9V. tures that make it ideal for use in battery-powered circuits. In situations where an ADJ pin connects to a resistor divider In addition to the normal protection features associated with that would pull the pin above its 9V clamp voltage if the monolithic regulators, such as current limiting and thermal output is pulled high, the ADJ pin input current must be limiting, the device protects itself against reverse input volt- limited to less than 5mA. For example, assume a resistor ages and reverse voltages from output to input. The two divider sets the regulated output voltage to 1.5V, and the regulators have independent inputs, a common GND pin output is forced to 20V. The top resistor of the resistor and are thermally coupled. However, the two channels of divider must be chosen to limit the current into the ADJ the LT3030 operate independently. Each channel’s output pin to less than 5mA when the ADJ pin is at 9V. The 11V can be shut down independently, and a fault condition on difference between the OUT and ADJ pins divided by the one output does not affect the other output electrically, 5mA maximum current into the ADJ pin yields a minimum unless the thermal shutdown circuitry is activated. top resistor value of 2.2k. Current limit protection and thermal overload protection In circuits where a backup battery is required, several protect the device against current overload conditions at different input/output conditions can occur. The output each output of the LT3030. For normal operation, do not voltage may be held up while the input is either pulled allow the junction temperature to exceed 125°C (LT3030E/ to ground, pulled to some intermediate voltage or is left LT3030I) or 150°C (LT3030H/LT3030MP). The typical open-circuit. Current flow back into the output follows the thermal shutdown temperature threshold is 165°C and curve shown in Figure 5. the circuitry incorporates approximately 5°C of hysteresis. If either of the LT3030’s IN pins is forced below its cor- Each channel’s input withstands reverse voltages of 22V. responding OUT pin, or the OUT pin is pulled above its Current flow into the device is limited to less than 1mA corresponding IN pin, input current for that channel typically (typically less than 100μA) and no negative voltage appears at the respective channel’s output. The device protects 5.0 both itself and the load against batteries that are plugged TJ = 25°C in backwards. 4.5 VIN1 = VIN2 = 0V 4.0 VADJ1 = VOUT1 A) VADJ2 = VOUT2 The LT3030 incurs no damage if either channel’s output m 3.5 T ( is pulled below ground. If the input is left open-circuit, EN 3.0 R or grounded, the output can be pulled below ground by UR 2.5 22V. The output acts like an open circuit, and no current SE C 2.0 IADJ1 OR IADJ2 R VE 1.5 flows from the output. However, current flows in (but is E R 1.0 limited by) the external resistor divider that sets the output 0.5 voltage. If the input is powered by a voltage source, the IOUT1 OR IOUT2 0 output sources current equal to its current limit capabil- 0 1 2 3 4 5 6 7 8 9 OUTPUT VOLTAGE (V) ity and the LT3030 protects itself by its thermal limiting 3030 F05 circuitry. In this case, grounding the relevant SHDN1 or IADJ = FLOWS INTO ADJ PIN TO GND PIN IOUT = FLOWS INTO OUT PIN TO IN PIN SHDN2 pin turns off its channel’s output and stops that Figure 5. Reverse Output Current output from sourcing current. 3030fa 16 For more information www.linear.com/LT3030

LT3030 applicaTions inForMaTion drops to less than 2μA. This occurs if the IN pin is con- When power is first applied, as input voltage rises, the nected to a discharged (low voltage) battery, and either output follows the input, allowing the regulator to start-up a backup battery or a second regulator circuit holds up into heavy loads. During start-up, as the input voltage is the output. The state of that channel’s SHDN pin has no rising, the input-to-output voltage differential is small, al- effect on the reverse output current if the output is pulled lowing the regulator to supply large output currents. With above the input. a high input voltage, an event can occur wherein removal of an output short will not allow the output to recover. The Overload Recovery event occurs with a heavy output load when the input voltage is high and the output voltage is low. Common situations Like many IC power regulators, the LT3030 has safe occur immediately after the removal of a short-circuit or if operating area (SOA) protection. The safe area protec- the shutdown pin is pulled high after the input voltage has tion decreases current limit as input-to-output voltage already been turned on. The load line intersects the output increases and keeps the power transistor inside a safe current curve at two points creating two stable output oper- operating region for all values of input-to-output voltage. ating points for the regulator. With this double intersection, The protective design provides some output current at the input power supply may need to be cycled down to zero all values of input-to-output voltage up to the specified and brought up again to make the output recover. maximum operational input voltage of 20V. 3030fa 17 For more information www.linear.com/LT3030

LT3030 Typical applicaTions Coincident Tracking Supply Application 3.3V 0.1µF CGATE VOUT1 VCC GATE 0.1µF IN1 OUT1 1.8V 750mA OFF ON ON LTC292R3AMP 1M 3.3µF 1M LT3030 10nF 111%3k 10µF PWRGD1 BYP1 RAMPBUF FB1 SHDN1 ADJ1 113k 237k 1% 1% TRACK1 SDO 90.9k 1% 54.9k 1% 2.5V IN2 OUT2 VOUT2 1.5V TRACK2 FB2 3.3µF 1M 10nF 54.9k 3.3µF 250mA 63.4k GND PWRGD2 BYP2 1% 1% SHDN2 ADJ2 GND 237k 1% 3030 TA02a VOUT1 VOUT2 500mV/DIV 3030 TA02b 20ms/DIV 3030fa 18 For more information www.linear.com/LT3030

LT3030 package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UFD Package 28-Lead (4mm × 5mm) Plastic QFN (Reference LTC DWG # 05-08-1712 Rev B) 0.70 ±0.05 4.50 ± 0.05 3.10 ± 0.05 2.50 REF 2.65 ± 0.05 3.65 ± 0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 3.50 REF 4.10 ± 0.05 5.50 ± 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 NOTCH 2.50 REF R = 0.20 OR 0.35 4.00 ± 0.10 0.75 ± 0.05 R =T Y0P.05 RTY =P 0.115 × 45° CHAMFER (2 SIDES) 27 28 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.00 ± 0.10 3.50 REF (2 SIDES) 3.65 ± 0.10 2.65 ± 0.10 (UFD28) QFN 0506 REV B 0.200 REF 0.25 ± 0.05 0.00 – 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3030fa 19 For more information www.linear.com/LT3030

LT3030 package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev J) FE Package 20-Lead Plastic TSSOP (4.4mm) Exposed Pad Variation CB (Reference LTC DWG # 05-08-1663 Rev J) Exposed Pad Variation CB 6.40 – 6.60* 3.86 (.252 – .260) (.152) 3.86 (.152) 20 1918171615141312 11 6.60 ±0.10 2.74 4.50 ±0.10 (.108) 6.40 SEE NOTE 4 2.74 (.252) (.108) 0.45 ±0.05 BSC 1.05 ±0.10 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10 1.20 4.30 – 4.50* (.047) (.169 – .177) 0.25 MAX REF 0° – 8° 0.65 0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15 (.0035 – .0079) (.020 – .030) BSC (.002 – .006) 0.195 – 0.30 (.0077 – .0118) FE20 (CB) TSSOP REV J 1012 TYP NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE MILLIMETERS FOR EXPOSED PAD ATTACHMENT 2. DIMENSIONS ARE IN (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH 3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3030fa 20 For more information www.linear.com/LT3030

LT3030 revision hisTory REV DATE DESCRIPTION PAGE NUMBER A 6/13 Lowered V minimum to 1.7V 1 IN Added H-grade in QFN package 2 Modified OUT2 GND curve pin current graph labels 6 3030fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 21 However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconneFcotior nm oof irtes cinircfouirtms aast dioensc wribwedw h.leinreeina rw.cilol nmo/t LinTf3ri0ng3e0 on existing patent rights.

LT3030 Typical applicaTion Sequencing Supply Application VIN1 IN1 OUT1 V1.O8UVT1 3.3V 750mA 1µF LT3030 10nF 22µF 1M 113k SHDN1 BYP1 1% VOUT2 1V/DIV PWRGD1 ADJ1 237k 1% 2V.I5NV2 IN2 OUT2 V1.O5UVT2 1VVO/UDTI1V 250mA 1µF 1M 10nF 10µF 54.9k VSHDN1 PWRGD2 BYP2 1% 5V/DIV SHDN2 ADJ2 10ms/DIV 3030 TA03b GND 237k 3030 TA03a 1% relaTeD parTs PART NUMBER DESCRIPTION COMMENTS LT1761 100mA, Low Noise Micropower LDO V : 1.8V to 20V, V = 1.22V, V = 0.3V, I = 20μA, I <1μA, Low Noise < 20μV , IN OUT DO Q SD RMS Stable with 1μF Ceramic Capacitors, ThinSOT™ Package LT1763 500mA, Low Noise Micropower LDO V : 1.8V to 20V, V = 1.22V, V = 0.3V, I = 30μA, I <1μA, Low Noise < 20μV , IN OUT DO Q SD RMS S8 Package LT1963/ 1.5A, Low Noise, Fast Transient Response V : 2.1V to 20V, V = 1.21V, V = 0.34V, I = 1mA, I < 1μA, IN OUT(MIN) DO Q SD LT1963A LDOs Low Noise: < 40μV , “A” Version Stable with Ceramic Capacitors, DD, TO220-5, SOT223, RMS S8 Packages LT1964 200mA, Low Noise Micropower, Negative V : –2.2V to –20V, V = 1.21V, V = 0.34V, I = 30μA, I = 3μA, IN OUT(MIN) DO Q SD LDO Low Noise: <30μV , Stable with Ceramic Capacitors, ThinSOT Package RMS LT1965 1.1A, Low Noise, Fast Transient Response V : 1.8V to 20V, V = 1.20V, V = 0.3V, I = 0.5mA, I < 1μA, IN OUT(MIN) DO Q SD LDO Low Noise: < 40μV , Stable with Ceramic Capacitors, 3mm × 3mm DFN, RMS MS8E, DD-Pak, TO-220 Packages LT3023 Dual 100mA, Low Noise, Micropower V : 1.8V to 20V, V = 1.22V, V = 0.30V, I = 40μA, I <1μA, DFN, IN OUT(MIN) DO Q SD LDO MS10 Packages LT3024 Dual 100mA/500mA, Low Noise, V : 1.8V to 20V, V = 1.22V, V = 0.30V, I = 60μA, I <1μA, DFN, IN OUT(MIN) DO Q SD Micropower LDO TSSOP-16E Packages LT3027 Dual 100mA, Low Noise, Micropower V : 1.8V to 20V, V = 1.22V, V = 0.30V, I = 40μA, I <1μA, DFN, IN OUT(MIN) DO Q SD LDO with Independent Inputs MS10E Packages LT3028 Dual 100mA/500mA, Low Noise, V : 1.8V to 20V, V = 1.22V, V = 0.30V, I = 60μA, I <1μA, DFN, IN OUT(MIN) DO Q SD Micropower LDO with Independent Inputs TSSOP-16E Packages LT3029 Dual 500mA/500mA, Low Noise, V : 1.8V to 20V, V = 1.215V, V = 0.30V, I = 55μA, I <1μA, DFN, IN OUT(MIN) DO Q SD Micropower LDO with Independent Inputs MSOP-16E Packages LT3032 Dual 150mA Positive/Negative Low V : ±2.3V to ±20V, V = ±1.22V, V = 0.30V, I = 30μA, I <1μA, IN OUT(MIN) DO Q SD Noise, Low Dropout Linear Regulator 14-Lead DFN Package LT3080/ 1.1A, Parallelable, Low Noise LDO 300mV Dropout Voltage (2-Supply Operation), Low Noise 40µV , V = 1.2V to 36V, RMS IN LT3080-1 V : 0V to 35.7V, Current-Based Reference with 1-Resistor V Set, Directly Parallelable OUT OUT (No Op Amp Required), Stable with Ceramic Capacitors, TO-220, SOT-223, MSOP and 3mm × 3mm DFN 3030fa 22 Linear Technology Corporation LT 0613 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LT3030 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LT3030  LINEAR TECHNOLOGY CORPORATION 2013