LT1994 Low Noise, Low Distortion Fully Differential Input/ Output Amplifi er/Driver FEATURES DESCRIPTION n Fully Differential Input and Output The LT®1994 is a high precision, very low noise, low distor- n Wide Supply Range: 2.375V to 12.6V tion, fully differential input/output amplifi er optimized for n Rail-to-Rail Output Swing 3V, single-supply operation. The LT1994’s output common n Low Noise: 3nV/√Hz mode voltage is independent of the input common mode n Low Distortion, 2V , 1MHz: –94dBc voltage, and is adjustable by applying a voltage on the P-P n Adjustable Output Common Mode Voltage V pin. A separate internal common mode feedback OCM n Unity-Gain Stable path provides accurate output phase balancing and reduced n Gain-Bandwidth: 70MHz even-order harmonics. This makes the LT1994 ideal for n Slew Rate: 65V/μs level shifting ground referenced signals for driving dif- n Large Output Current: 85mA ferential input, single-supply ADCs. n DC Voltage Offset <2mV Max The LT1994 output can swing rail-to-rail and is capable n Open-Loop Gain: 100V/mV of sourcing and sinking up to 85mA. In addition to the n Low Power Shutdown low distortion characteristics, the LT1994 has a low input n 8-Pin MSOP or 3mm × 3mm DFN Package referred voltage noise of 3nV/√Hz. This part maintains APPLICATIONS its performance for supply voltages as low as 2.375V. It draws only 13.3mA of supply current and has a hardware n Differential Input A/D Converter Driver shutdown feature that reduces current consumption to n Single-Ended to Differential Conversion 225μA. n Differential Amplifi cation with Common Mode The LT1994 is available in an 8-pin MSOP or 8-pin DFN Translation package. n Rail-to-Rail Differential Line Driver/Receiver L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. n Low Voltage, Low Noise, Differential Signal All other trademarks are the property of their respective owners. Processing TYPICAL APPLICATION LT1994 Driving an LTC1403A-1 1MHz A/D Preamplifi er: Single-Ended Input to Differential Output Sine Wave, 8192 Point FFT Plot with Common Mode Level Shifting 0 499Ω 499Ω 3V 10μF E (dB) ––2100 ffISINNAP M=U P1TL. 0E= 0 =21 V2MP.8H-PMz,sps 2VVPI-NP 3V 0.1μF GNITUD ––4300 SSIFNDGRL =E 9E3NdDBED A M –50 24.9Ω VDD SD0 T – + AIN+ PU –60 CONV UT –70 0.1μF V+OC–MLT1994 24.9Ω 47pF ALTINC–140G3NAD-1 VSRCEKF 50.4MHz ENTIAL O ––9800 R VOCM = 1.5V 10μF FFE–100 499Ω 499Ω 1994 TA01 DI–110 –120 0 0.35 0.70 1.05 1.40 FREQUENCY(MHz) 1994 TA01b 1994fb 1

LT1994 ABSOLUTE MAXIMUM RATINGS (Note 1) Total Supply Voltage (V+ to V–) ..............................12.6V Specifi ed Temperature Range (Note 5) Input Voltage (Note 2) ...............................................±V LT1994C ...................................................0°C to 70°C S Input Current (Note 2) ..........................................±10mA LT1994I ................................................–40°C to 85°C Input Current (V , SHDN) ................................±10mA LT1994H ............................................–40°C to 125°C OCM V , SHDN..............................................................±V LT1994MP..........................................–55°C to 125°C OCM S Output Short-Circuit Duration (Note 3) ............Indefi nite Junction Temperature ...........................................150°C Operating Temperature Range (Note 4) Storage Temperature Range ...................–65°C to 150°C LT1994C ...............................................–40°C to 85°C LT1994I ................................................–40°C to 85°C LT1994H ............................................–40°C to 125°C LT1994MP..........................................–55°C to 125°C PIN CONFIGURATION TOP VIEW IN– 1 8 IN+ TOP VIEW IN– 1 8IN+ VOCM 2 7 SHDN V+ 3 6 V– VOCVM+ 23 76SVH–DN OUT+ 4 5 OUT– OUT+ 4 5OUT– MS8 PACKAGE 8-LEAD PLASTIC MSOP DD PACKAGE 8-LEAD (3mm (cid:115) 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 140°C/W TJMAX = 150°C, θJA = 43°C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO V– ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LT1994CDD#PBF LT1994CDD#TRPBF LBQM 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C LT1994IDD#PBF LT1994IDD#TRPBF LBQM 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LT1994HDD#PBF LT1994HDD#TRPBF LBQM 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT1994MPDD#PBF LT1994MPDD#TRPBF LDXQ 8-Lead (3mm × 3mm) Plastic DFN –55°C to 125°C LT1994CMS8#PBF LT1994CMS8#TRPBF LTBQN 8-Lead Plastic MSOP 0°C to 70°C LT1994IMS8#PBF LT1994IMS8#TRPBF LTBQN 8-Lead Plastic MSOP –40°C to 85°C Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based fi nish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/ 1994fb 2

LT1994 ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V+ = 3V, V– = 0V, V = V = V = mid-supply, V = OPEN, A CM OCM ICM SHDN R = R = 499Ω, R = 800Ω to a mid-supply voltage (See Figure 1) unless otherwise noted. V is defi ned (V+ – V–). V is defi ned I F L S OUTCM as (V + + V –)/2. V is defi ned as (V + + V –)/2. V is defi ned as (V + – V –). V is defi ned as (V + – V –). OUT OUT ICM IN IN OUTDIFF OUT OUT INDIFF IN IN C/I GRADES H/MP GRADES SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS V Differential Offset Voltage V = 2.375V, V = V /4 l ±2 ±2 mV OSDIFF S ICM S (Input Referred) V = 3V l ±2 ±2 mV S V = 5V l ±2 ±2 mV S V = ±5V l ±3 ±3 mV S ΔVOSDIFF/ΔT Differential Offset Voltage Drift VS = 2.375V, VICM = VS/4 3 μV/°C (Input Referred) V = 3V 3 μV/°C S V = 5V 3 μV/°C S V = ±5V 3 μV/°C S I Input Bias Current (Note 6) V = 2.375V, V = V /4 l –45 –18 –3 –45 –18 –3 μA B S ICM S V = 3V l –45 –18 –3 –45 –18 –3 μA S V = 5V l –45 –18 –3 –45 –18 –3 μA S V = ±5V l –45 –18 –3 –45 –18 –3 μA S I Input Offset Current (Note 6) V = 2.375V, V = V /4 l ±0.2 ±2 ±0.2 ±2 μA OS S ICM S V = 3V l ±0.2 ±2 ±0.2 ±2 μA S V = 5V l ±0.2 ±3 ±0.2 ±3 μA S V = ±5V l ±0.2 ±4 ±0.2 ±4 μA S RIN Input Resistance Common Mode 700 700 kΩ Differential Mode 4.5 4.5 kΩ C Input Capacitance Differential 2 2 pF IN e Differential Input Referred Noise f = 50kHz 3 3 nV/√Hz n Voltage Density i Input Noise Current Density f = 50kHz 2.5 2.5 pA/√Hz n e Input Referred Common Mode Output f = 50kHz, V Shorted to Ground 15 15 nV/√Hz nVOCM OCM Noise Voltage Density V Input Signal Common Mode Range V = 3V l 0 1.75 0 1.75 V ICMR S (Note 7) V = ±5V l –5 3.75 –5 3.75 V S CMRRI Input Common Mode Rejection Ratio V = 3V, ΔV = 0.75V l 55 85 55 85 dB S ICM (Note 8) (Input Referred) ΔV /ΔV ICM OSDIFF CMRRIO Output Common Mode Rejection Ratio V = 5V, ΔV = 2V l 65 85 65 85 dB S OCM (Note 8) (Input Referred) ΔV /ΔV OCM OSDIFF PSRR Differential Power Supply Rejection V = 3V to ±5V l 69 105 69 105 dB S (Note 9) (ΔV /ΔV ) S OSDIFF PSRRCM Output Common Mode Power Supply V = 3V to ±5V l 45 70 45 70 dB S (Note 9) Rejection (ΔV /ΔV ) S OSCM GCM Common Mode Gain (ΔVOUTCM/ΔVOCM) VS = ±2.5V l 1 V/V Common Mode Gain Error V = ±2.5V l –0.15 ±1 % S 100 • (G – 1) CM BAL Output Balance (ΔV /ΔV ) ΔV = 2V OUTCM OUTDIFF OUTDIFF Single-Ended Input l –65 –46 –65 –46 dB Differential Input l –71 –50 –71 –50 dB V Common Mode Offset Voltage V = 2.375V, V = V /4 l ±2.5 ±25 ±2.5 ±25 mV OSCM S ICM S (V – V ) V = 3V l ±2.5 ±25 ±2.5 ±25 mV OUTCM OCM S V = 5V l ±2.5 ±30 ±2.5 ±30 mV S V = ±5V l ±2.5 ±40 ±2.5 ±40 mV S 1994fb 3

LT1994 ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V+ = 3V, V– = 0V, V = V = V = mid-supply, V = OPEN, A CM OCM ICM SHDN R = R = 499Ω, R = 800Ω to a mid-supply voltage (See Figure 1) unless otherwise noted. V is defi ned (V+ – V–). V is defi ned I F L S OUTCM as (V + + V –)/2. V is defi ned as (V + + V –)/2. V is defi ned as (V + – V –). V is defi ned as (V + – V –). OUT OUT ICM IN IN OUTDIFF OUT OUT INDIFF IN IN C/I GRADES H/MP GRADES SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS ΔVOSCM/ΔT Common Mode Offset Voltage Drift VS = 2.375V, VICM = VS/4 5 5 μV/°C V = 3V 5 5 μV/°C S V = 5V 5 5 μV/°C S V = ±5V 5 5 μV/°C S V Output Signal Common Mode Range V = 3V, ±5V l V– + V+ V– + V+ V OUTCMR S (Note 7) (Voltage Range for the V Pin) 1.1 – 0.8 1.1 – 0.8 OCM RINVOCM Input Resistance, VOCM Pin l 30 40 60 30 40 60 kΩ V Voltage at the V Pin V = 5V l 2.45 2.5 2.55 2.45 2.5 2.55 V MID OCM S V Output Voltage, High, Either Output Pin V = 3V, No Load l 70 140 70 140 mV OUT S (Note 10) V = 3V, R = 800Ω l 90 175 90 175 mV S L V = 3V, R = 100Ω l 200 400 200 400 mV S L V = ±5V, No Load l 150 325 150 325 mV S V = ±5V, R = 800Ω l 200 450 200 450 mV S L V = ±5V, R = 100Ω l 900 2400 900 2400 mV S L Output Voltage, Low, Either Output Pin V = 3V, No Load l 30 70 30 70 mV S (Note 10) V = 3V, R = 800Ω l 50 90 50 90 mV S L V = 3V, R = 100Ω l 125 250 125 250 mV S L V = ±5V, No Load l 80 180 80 180 mV S V = ±5V, R = 800Ω l 125 250 125 250 mV S L V = ±5V, R = 100Ω l 900 2400 900 2400 mV S L ISC Output Short-Circuit Current, Either VS = 2.375V, RL = 10Ω l ±25 ±35 ±10 ±35 mA Output Pin (Note 11) V = 3V, R = 10Ω l ±30 ±40 ±15 ±40 mA S L V = 5V, R = 10Ω l ±40 ±65 ±40 ±65 mA S L V = ±5V, V = 0V, R = 10Ω l ±45 ±85 ±45 ±85 mA S CM L SR Slew Rate V = 5V, ΔV + = –ΔV – = 1V l 50 65 85 50 65 85 V/μS S OUT OUT V = ±5V, V = 0V, l 50 65 85 50 65 85 V/μS S CM ΔV + = –ΔV – = 1.8V OUT OUT GBW Gain-Bandwidth Product V = 3V, T = 25°C l 58 70 58 70 MHz S A (f = 1MHz) V = ±5V, V = 0V, T = 25°C l 58 70 58 70 MHz TEST S CM A Distortion V = 3V, R = 800Ω, f = 1MHz, S L IN V + – V – = 2V OUT OUT P-P Differential Input 2nd Harmonic –99 –99 dBc 3rd Harmonic –96 –96 dBc Single-Ended Input 2nd Harmonic –94 –94 dBc 3rd Harmonic –108 –108 dBc t Settling Time V = 3V, 0.01%, 2V Step 120 120 ns S S V = 3V, 0.1%, 2V Step 90 90 ns S A Large-Signal Voltage Gain V = 3V 100 100 dB VOL S V Supply Voltage Range l 2.375 12.6 2.375 12.6 V S I Supply Current V = 3V l 13.3 18.5 13.3 20.0 mA S S V = 5V l 13.9 19.5 13.9 20.5 mA S V = ±5V l 14.8 20.5 14.8 21.5 mA S I Supply Current in Shutdown V = 3V l 0.225 0.8 0.225 0.8 mA SHDN S V = 5V l 0.375 1.75 0.375 1.75 mA S V = ±5V l 0.7 2.5 0.7 2.5 mA S 1994fb 4

LT1994 ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T = 25°C. V+ = 3V, V– = 0V, V = V = V = mid-supply, V = OPEN, A CM OCM ICM SHDN R = R = 499Ω, R = 800Ω to a mid-supply voltage (See Figure 1) unless otherwise noted. V is defi ned (V+ – V–). V is defi ned I F L S OUTCM as (V + + V –)/2. V is defi ned as (V + + V –)/2. V is defi ned as (V + – V –). V is defi ned as (V + – V –). OUT OUT ICM IN IN OUTDIFF OUT OUT INDIFF IN IN C/I GRADES H/MP GRADES SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS V SHDN Input Logic Low V = 3V to ±5V l V+ V+ V IL S – 2.1 – 2.1 V SHDN Input Logic High V = 3V to ±5V l V+ V+ V IH S – 0.6 – 0.6 RSHDN SHDN Pull-Up Resistor VS = 2.375V to ±5V 40 55 75 40 55 75 kΩ t Turn-On Time V 0.5V to 3V 1 1 μs ON SHDN t Turn-Off Time V 3V to 0.5V 1 1 μs OFF SHDN Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 7: Input Common Mode Range is tested using the Test Circuit of may cause permanent damage to the device. Exposure to any Absolute Figure 1 (R = R) by applying a single ended 2V , 1kHz signal to V F I P-P INP Maximum Rating condition for extended periods may affect device (V = 0), and measuring the output distortion (THD) at the common INM reliability and lifetime. mode Voltage Range limits listed in the Electrical Characteristics table, Note 2: The inputs are protected by a pair of back-to-back diodes. If the and confi rming the output THD is better than –40dB. The voltage range for differential input voltage exceeds 1V, the input current should be limited to the output common mode range (Pin 2) is tested using the Test Circuit of less than 10mA. Figure 1 (RF = RI) by applying a 0.5V peak, 1kHz signal to the VOCM Note 3: A heat sink may be required to keep the junction temperature Pin 2 (with VINP = VINM = 0) and measuring the output distortion (THD) below the absolute maximum rating when the output is shorted at VOUTCM with VOCM biased 0.5V from the VOCM pin range limits listed indefi nitely. in the Electrical Characteristics Table, and confi rming the THD is better Note 4: The LT1994C/LT1994I are guaranteed functional over the than –40dB. operating temperature range –40°C to 85°C. The LT1994H is guaranteed Note 8: Input CMRR is defi ned as the ratio of the change in the input functional over the operating temperature range –40°C to 125°C. The common mode voltage at the pins IN+ or IN– to the change in differential LT1994MP is guaranteed functional over the operating temperature range input referred voltage offset. Output CMRR is defi ned as the ratio of the –55°C to 125°C. change in the voltage at the VOCM pin to the change in differential input Note 5: The LT1994C is guaranteed to meet specifi ed performance from referred voltage offset. 0°C to 70°C. The LT1994C is designed, characterized, and expected to Note 9: Differential Power Supply Rejection (PSRR) is defi ned as the ratio meet specifi ed performance from –40°C to 85°C but is not tested or of the change in supply voltage to the change in differential input referred QA sampled at these temperatures. The LT1994I is guaranteed to meet voltage offset. Common Mode Power Supply Rejection (PSRRCM) is specifi ed performance from –40°C to 85°C. The LT1994H is guaranteed defi ned as the ratio of the change in supply voltage to the change in the to meet specifi ed performance from –40°C to 125°C. The LT1994MP is common mode offset, VOUTCM – VOCM. guaranteed to meet specifi ed performance from –55°C to 125°C. Note 10: Output swings are measured as differences between the output Note 6: Input bias current is defi ned as the average of the input currents and the respective power supply rail. fl owing into Pin 1 and Pin 8 (IN– and IN+). Input Offset current is defi ned Note 11: Extended operation with the output shorted may cause junction as the difference of the input currents fl owing into Pin 8 and Pin 1 temperatures to exceed the 150°C limit and is not recommended. (I = I + – I –). OS B B 1994fb 5

LT1994 TYPICAL PERFORMANCE CHARACTERISTICS Differential Input Referred Common Mode Voltage Offset vs Input Bias Current and Input Voltage Offset vs Temperature Temperature Offset Current vs Temperature 500 7.5 –10 1.0 VS = 3V VS = 3V VCM = 1.5V mV) VCM = 1.5V NTIAL V (μV)OS 2500 VFOOUCMR =T Y1P.5ICVAL UNITS VOLTAGE OFFSET ( 25..50 VFOOUCMR =T Y1P.5ICVAL UNITS S CURRENT (μA)––2105 IOS, VS = 3V IB, VIOSS =, V±S5 V= ±5V 00.5 INPUT OFFSET CU DIFFERE––520500 MON MODE 0 INPUT BIA–25 –0.5RRENT (μA) OM IB, VS = 3V C –750 –2.5 –30 –1.0 –50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) 1994 G01 1994 G02 1994 G03 Frequency Response vs Frequency Response vs Gain Bandwidth vs Temperature Supply Voltage Load Capacitance 72 2 2 RF = RI = 499Ω RF = RI = 499Ω VS = 2.5V 71 VS = 3V VS = 2.5V MHz) 70 VS = ±5V 1 VS = 5V 1 WIDTH ( 69 VS = 3V N (dB) 0 N (dB) 0 VS = 3V AND GAI VS = ±5V GAI B N 68 GAI –1 –1 5pF FROM EACH 67 OUTPUT TO GROUND 25pF FROM EACH OUTPUT TO GROUND 66 –2 –2 –50 –25 0 25 50 75 100 0.1 1 10 100 0.1 1 10 100 TEMPERATURE (°C) FREQUENCY (MHz) FREQUENCY (MHz) 1994 G04 1994 G05 1994 G06 Differential Power Supply Output Impedance vs Frequency Output Balance vs Frequency Rejection vs Frequency 100 –30 110 VS = 3V (cid:36)VOUTCM (cid:36)VS RF = RI = 499Ω (cid:36)VOUTDIFF 100 (cid:36)VOSDIFF –40 90 +–Z OUT, OUT (Ω)OUT 110 OUTPUT BALANCE (dB)–––567000 DSIIFNFGELREE-NENTIDAELD I NINPPUUTT DIFFERENTIAL PSRR (dB) 864753000000 V– SUPPLYV+ SUPPLY –80 20 10 VS = 3V VS = 3V 0.1 –90 0 0.1 1 10 100 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M 100M FREQUENCY (MHz) FREQUENCY (Hz) FREQUENCY (Hz) 1994 G07 1995 G08 1995 G09 1994fb 6

LT1994 TYPICAL PERFORMANCE CHARACTERISTICS Input Common Mode Rejection vs Common Mode Output Power Frequency Supply Rejection vs Frequency Input Noise vs Frequency 10900 VS = 3V (cid:36)(cid:36)VOVSICDMIFF 6500 V– SUPPLY (cid:36)V(cid:36)OSVOSCM TY (nV/√Hz) 100 VTAS == 235V°C 100INPUT INPUT CMRR (dB) 87650000 VS = (cid:112)5V MMON MODE PSRR (dB) 342000 V+ SUPPLY D VOLTAGE NOISE DENSI 10 en 10 CURRENT NOISE DENSIT O E Y 40 C 10 REFERR in (pA/√H VS = 3V T z) 30 0 U 1 1 P 1k 10k 100k 1M 10M 100M 0.1 1 10 100 N 10 100 1k 10k 100k 1M I FREQUENCY (Hz) FREQUENCY (MHz) FREQUENCY (Hz) 1995 G10 1995 G11 1995 G12 Differential Distortion vs Input Differential Distortion vs Input Differential Distortion vs Amplitude (Single-Ended Input) Common Mode Level Frequency –60 –40 –40 VS = 3V VS = 3V VS = 3V N HD2, HD3 (dB) ––8700 fRRVINOFL C===M R81 =0MI 0=MHΩ 4zID99-2SΩNUDP,P VLIYCM = 1.5V N HD2, HD3 (dB) –––567000 VfRRVINIOFLN C=== M= R81 2=0MIV 0=MHPΩ 4-zIPD9 9(-SSΩIUNPGPLLEY ENDED) RTION(dB) –––567000 VfRRVVINIOIFLNC C=M== M= R81 = 2=0MI V M 0=MHPΩ I4-zDIPD9- 9(-SSSΩUIUNPPGPPLLLYEY ENDE3DR)D DISTORTIO–1–0900 2ND, VCM = V– 3RD, VCM = V– DISTORTIO ––9800 2ND DISTO ––9800 2ND –100 –100 3RD, VICM = 1.5V 3RD –110 –110 –110 1 2 3 4 5 0 0.5 1.0 1.5 2.0 2.5 100k 1M 10M VIN (VP-P) INPUT COMMON MODE DC BIAS, IN– OR IN+ PINS (V) FREQUENCY (Hz) 1994 G13 1994 G14 1994 G15 Slew Rate vs Temperature 2V Step Response Settling 68 RF = RI = 499Ω S V) ET SLEW RATE (V/μs) 666246 VS = ±5VVS = 3V +– = V – V (0.5V/DIOUTOUTOUT VOUT E+R0R.1O%R E–R0R.1O%R TLE VOLTAGE ERROR (2mV/D V IV VS = 3V ) RF = RI = 499Ω 60 –50 –25 0 25 50 75 100 25ns/DIV TEMPERATURE (°C) 1994 G17 1994 G16 1994fb 7

LT1994 TYPICAL PERFORMANCE CHARACTERISTICS Small-Signal Step Response Large-Signal Step Response Output with Large Input Overdrive 25pF LOAD VS = 3V VS = 3V OUT+ RF = RI = 499Ω RF = RI = 499Ω VCM = V– 0pF LOAD OUT+ OUT+ 20mV/DIV VRVSSIIFNN == G= R3L 1VEI0 =E0 Nm49DV9EPΩD-P, 0.5V/DIV 0.5V/DIV OUT– OUT– OUT– VIN = 3VP-P SINGLE ENDED VIN = 10VP-P SINGLE ENDED 20ns/DIV 100ns/DIV 2μs/DIV 1994 G18 1994 G19 1994 G20 Supply Current vs Supply Voltage Supply Current vs SHDN Voltage Supply Current vs SHDN Voltage 20 16 16 SHDN PIN VOLTAGE = V+ VS = 3V VS = 3V RRENT (mA) 15 TA = 85°C TA = –40°C RRENT (mA) 12 TA = –40°C TA = 85°C RRENT (mA) 12 TA = –40°C TA = 85°C U U U OTAL SUPPLY C 150 TA = 70°CTA = 25°TCA = 0°C OTAL SUPPLY C 48 TTAA == 02°5C°C TA = 70°C OTAL SUPPLY C 48 TTAA == 02°5C°C TA = 70°C T T T 0 0 0 0 2.5 5.0 7.5 10.0 12.5 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 SUPPLY VOLTAGE (V) SHDNPIN VOLTAGE (V) SHDNPIN VOLTAGE (V) 1994 G21 1994 G23 1994 G23 SHDN Pin Current vs SHDN Shutdown Supply Current vs Pin Voltage Supply Voltage 0 1000 VS = 3V A) μ A) TA = –40°C NT ( 750 DNPIN CURRENT (μ––2100 TA = 0°C TA = 8T5A°C = 7T0A °=C 25°C WN SUPPLY CURRE 500 TA = –40°C TA = 25°C TA = 85°C SH DO 250 T U H S –30 0 0 0.5 1.0 1.5 2.0 2.5 3.0 0 2.5 5.0 7.5 10.0 12.5 SHDNPIN VOLTAGE (V) SUPPLY VOLTAGE (V) 1994 G24 1994 G25 1994fb 8

LT1994 PIN FUNCTIONS IN+, IN– (Pins 1, 8): Noninverting and Inverting Input V+, V– (Pins 3, 6): Power Supply Pins. For single-supply Pins of the Amplifi er, Respectively. For best performance, applications (Pin 6 grounded) it is recommended that it is highly recommended that stray capacitance be high quality 1μF and 0.1μF ceramic bypass capacitors be kept to an absolute minimum by keeping printed circuit placed from the positive supply pin (Pin 3) to the negative connections as short as possible, and if necessary, strip- supply pin (Pin 6) with minimal routing. Pin 6 should be ping back nearby surrounding ground plane away from directly tied to a low impedance ground plane. For dual these pins. power supplies, it is recommended that high quality, 0.1μF ceramic capacitors are used to bypass Pin 3 to ground V (Pin 2): Output Common Mode Reference Voltage. OCM and Pin 6 to ground. It is also highly recommended that The V pin is the midpoint of an internal resistive volt- OCM high quality 1μF and 0.1μF ceramic bypass capacitors be age divider between the supplies, developing a (default) placed across the power supply pins (Pins 3 and 6) with mid-supply voltage potential to maximize output signal minimal routing. swing. V has a Thevenin equivalent resistance of OCM approximately 40k and can be overdriven by an external OUT+, OUT– (Pins 4, 5): Output Pins. Each pin can drive voltage reference. The voltage on V sets the output approximately 100Ω to ground with a short-circuit current OCM common mode voltage level (which is defi ned as the av- limit of up to ±85mA. Each amplifi er output is designed erage of the voltages on the OUT+ and OUT– pins). V to drive a load capacitance of 25pF. This basically means OCM should be bypassed with a high quality ceramic bypass the amplifi er can drive 25pF from each output to ground capacitor of at least 0.1μF (unless connected directly to or 12.5pF differentially. Larger capacitive loads should be a low impedance, low noise ground plane) to minimize decoupled with at least 25Ω resistors from each output. common mode noise from being converted to differen- SHDN (Pin 7): When Pin 7 (SHDN) is fl oating or when tial noise by impedance mismatches both externally and Pin 7 is directly tied to V+, the LT1994 is in the normal internally to the IC. operating mode. When Pin 7 is pulled a minimum of 2.1V below V+, the LT1994 enters into a low power shutdown state. Refer to the SHDN pin section under Applications Information for a description of the LT1994 output imped- ance in the shutdown state. 1994fb 9

LT1994 APPLICATIONS INFORMATION Functional Description The outputs (OUT+ and OUT–) of the LT1994 are capable of swinging rail-to-rail. They can source or sink up to The LT1994 is a small outline, wideband, low noise and approximately 85mA of current. Each output is rated to low distortion fully-differential amplifi er with accurate drive approximately 25pF to ground (12.5pF differentially). output-phase balancing. The LT1994 is optimized to Higher load capacitances should be decoupled with at least drive low voltage, single-supply, differential input ana- 25Ω of series resistance from each output. log-to-digital converters (ADCs). The LT1994’s output is capable of swinging rail-to-rail on supplies as low as 2.5V, Input Pin Protection which makes the amplifi er ideal for converting ground referenced, single-ended signals into V referenced The LT1994’s input stage is protected against differential OCM differential signals in preparation for driving low voltage, input voltages that exceed 1V by two pairs of back-to- single-supply, differential input ADCs. Unlike traditional back diodes that protect against emitter base breakdown op amps which have a single output, the LT1994 has two of the input transistors. In addition, the input pins have outputs to process signals differentially. This allows for steering diodes to either power supply. If the input pair two times the signal swing in low voltage systems when is overdriven, the current should be limited to under compared to single-ended output amplifi ers. The balanced 10mA to prevent damage to the IC. The LT1994 also has differential nature of the amplifi er also provides even-order steering diodes to either power supply on the VOCM, and harmonic distortion cancellation, and less susceptibility SHDN pins (Pins 2 and 7) and if exposed to voltages that to common mode noise (like power supply noise). The exceed either supply, they too should be current limited LT1994 can be used as a single-ended input to differential to under 10mA. output amplifi er, or as a differential input to differential SHDN Pin output amplifi er. If the SHDN pin (Pin 7) is pulled 2.1V below the positive The LT1994’s output common mode voltage, defi ned as the supply, an internal current is generated that is used to average of the two output voltages, is independent of the power down the LT1994. The pin will have the Thevenin input common mode voltage, and is adjusted by applying equivalent impedance of approximately 55kΩ to V+. If a voltage on the V pin. If the pin is left open, there is an OCM the pin is left unconnected, an internal pull-up resistor of internal resistive voltage divider, which develops a potential halfway between the V+ and V– pins. The V pin will have 120k will keep the part in normal active operation. Care OCM should be taken to control leakage currents at this pin to an equivalent Thevenin equivalent resistance of 40k, and a under 1μA to prevent leakage currents from inadvertently Thevenin equivalent voltage of half supply. Whenever this putting the LT1994 into shutdown. In shutdown, all biasing pin is not hard tied to a low impedance ground plane, it current sources are shut off, and the output pins OUT+ and is recommended that a high quality ceramic capacitor is OUT– will each appear as open collectors with a nonlinear used to bypass the V pin to a low impedance ground OCM capacitor in parallel, and steering diodes to either supply. plane (see Layout Considerations in this document). The Because of the nonlinear capacitance, the outputs still have LT1994’s internal common mode feedback path forces the ability to sink and source small amounts of transient accurate output phase balancing to reduce even order current if exposed to signifi cant voltage transients. The harmonics, and centers each individual output about the inputs (IN+ and IN–) have anti-parallel diodes that can potential set by the V pin. OCM conduct if voltage transients at the input exceed 1V. The V = V = VOUT+ +VOUT– inputs also have steering diodes to either supply. The OUTCM OCM 2 turn-on and turn-off time between the shutdown and active states are on the order of 1μs but depends on the circuit confi guration. 1994fb 10

LT1994 APPLICATIONS INFORMATION General Amplifi er Applications Effects of Resistor Pair Mismatch As levels of integration have increased and, correspond- Figure 2 shows a circuit diagram that takes into consid- ingly, system supply voltages decreased, there has been eration that real world resistors will not perfectly match. a need for ADCs to process signals differentially in order Assuming infi nite open-loop gain, the differential output to maintain good signal-to-noise ratios. These ADCs are relationship is given by the equation: typically supplied from a single-supply voltage that can be as low as 2.5V and will have an optimal common mode V =V + –V – ≅ RF (cid:129)V + OUTDIFF OUT OUT INDIFF R input range near mid-supply. The LT1994 makes interfac- I Δβ Δβ ing to these ADCs trivial, by providing both single-ended (cid:129)V – (cid:129)V , to differential conversion as well as common mode level β ICM β OCM AVG AVG shifting. Figure 1 shows a general single-supply application with perfectly matched feedback networks from OUT+ and where: OUT–. The gain to V from V and V is: OUTDIFF INM INP R is the average of R and R , and R is the average F F1 F2 I V =V + –V – ≈ RF (cid:129)(V –V ) of RI1 and RI2. OUTDIFF OUT OUT INP INM RI βAVG is defi ned as the average feedback factor (or gain) from the outputs to their respective inputs: Note from the above equation that the differential output voltage (VOUT+ – VOUT–) is completely independent of β = 1(cid:129)⎛⎜ RI2 + RI1 ⎞⎟ input and output common mode voltages, or the voltage AVG 2 ⎝R +R R +R ⎠ I2 F2 I1 F1 at the common mode pin. This makes the LT1994 ideally suited pre-amplifi cation, level shifting, and conversion Δβ is defi ned as the difference in feedback factors: of single-ended signals to differential output signals in R R preparation for driving differential input ADCs. Δβ= I2 – I1 R +R R +R I2 F2 I1 F1 RI VIN– RF VOUT+ RL V+ RI2 VIN– RF2 VOUT+ RL 0.1μF VINM RBAL VINM VS 3 3 1 4 – + 1 4 VCM VOCM0.1μF 82 V+OCM L–T1994 0.1μF VOUTCM VOCM0.1μF 82 V+–OCM L–+T1994 0.1μF 5 SHDN 5 6 6 VINP 7 0.1μF RBAL VINP 7 VSHDN VSHDNB RI RF V– VOUT– RL RI1 RF1 VOUT– RL VIN+ 1994 F01 VIN+ 1994 F02 Figure 1. Test Circuit Figure 2. Real-World Application 1994fb 11

LT1994 APPLICATIONS INFORMATION V is defi ned as the average of the two input voltages, For single-ended inputs, because of the signal imbalance ICM V and V (also called the input common mode at the input, the input impedance actually increases over INP INM voltage): the balanced differential case. The input impedance looking into either input is: 1 ( ) V = (cid:129) V +V ICM 2 INP INM R =R = RI INP INM ⎛ 1 ⎡ R ⎤⎞ and VINDIFF is defi ned as the difference of the input ⎜1– (cid:129)⎢ F ⎥⎟ ⎝ 2 ⎣R +R ⎦⎠ voltages: I F VINDIFF = VINP – VINM Input signal sources with non-zero output impedances can When the feedback ratios mismatch (Δβ), common mode also cause feedback imbalance between the pair of feedback networks. For the best performance, it is recommended to differential conversion occurs. that the source’s output impedance be compensated for. Setting the differential input to zero (V = 0), the de- INDIFF If input impedance matching is required by the source, gree of common mode to differential conversion is given R1 should be chosen (see Figure 3): by the equation: R (cid:129)R (cid:11) – R1= INM S VOUTDIFF (cid:29)VOUT –VOUT (cid:122) R −R INM S (cid:36)(cid:66) (cid:8)V –V (cid:9)• ICM OCM According to Figure 3, the input impedance looking into (cid:66) AVG the differential amp (R ) refl ects the single-ended source INM V (cid:29)0 INDIFF case, thus: R In general, the degree of feedback pair mismatch is a source R = I of common mode to differential conversion of both signals INM ⎛ 1 ⎡ R ⎤⎞ F ⎜1– (cid:129)⎢ ⎥⎟ and noise. Using 1% resistors or better will provide about ⎝ 2 ⎣R +R ⎦⎠ I F 28dB of common mode rejection. Using 0.1% resistors will provide about 48dB of common mode rejection. A low R2 is chosen to balance R1||R : S impedance ground plane should be used as a reference R1(cid:129)R for both the input signal source and the VOCM pin. A direct R2= S R1+R short of VOCM to this ground plane or bypassing the VOCM S with a high quality 0.1μF ceramic capacitor to this ground plane will further mitigate against common mode signals RINM from being converted to differential. RS RI RF VS R1 Input Impedance and Loading Effects – + The input impedance looking into the VINP or VINM input LT1994 of Figure 1 depends on whether or not the sources V + – INP and V are fully differential. For balanced input sources INM RI RF (V = –V ), the input impedance seen at either input INP INM 1994 F03 is simply: R2 = RS || R1 R1 CHOSEN SO THAT R1 || RINM = RS R = R = R R2 CHOSEN TO BALANCE R1 || RS INP INM I Figure 3. Optimal Compensation for Signal-Source Impedance 1994fb 12

LT1994 APPLICATIONS INFORMATION Input Common Mode Voltage Range Output Common Mode Voltage Range The LT1994’s input common mode voltage (V ) is defi ned The output common mode voltage is defi ned as the aver- ICM as the average of the two input voltages, V +, and V –. age of the two outputs: IN IN It extends from V– to approximately 1.25V below V+. The V + +V – input common mode range depends on the circuit con- V = V = OUT OUT OUTCM OCM 2 fi guration (gain), V and V (refer to Figure 4). For OCM CM fully differential input applications, where VINP = –VINM, The VOCM sets this average by an internal common mode the common mode input is approximately: feedback loop which internally forces V + = –V –. The OUT OUT V + +V – ⎛ R ⎞ output common mode range extends from approximately V = IN IN ≈V (cid:129)⎜ I ⎟ + 1.1V above V– to approximately 0.8V below V+. The V ICM 2 OCM ⎝R +R ⎠ OCM I F pin sits in the middle of an 80kΩ to 80kΩ voltage divider ⎛ R ⎞ that sets the default mid-supply open-circuit potential. F V (cid:129)⎜ ⎟ CM ⎝R +R ⎠ F I In single-supply applications, where the LT1994 is used to interface to an ADC, the optimal common mode input With singled-ended inputs, there is an input signal com- range to the ADC is often determined by the ADC’s refer- ponent to the input common mode voltage. Applying only ence. If the ADC makes a reference available for setting V (setting V to zero), the input common voltage is INP INM the input common mode voltage, it can be directly tied approximately: to the V pin, but must be capable of driving a 40k OCM V + +V – ⎛ R ⎞ equivalent resistance that is tied to a mid-supply potential. V = IN IN ≈V (cid:129)⎜ I ⎟ + ICM 2 OCM ⎝R +R ⎠ If an external reference drives the VOCM pin, it should still I F be bypassed with a high quality 0.1μF capacitor to a low ⎛ R ⎞ V ⎛ R ⎞ V (cid:129)⎜ F ⎟ + INP (cid:129)⎜ F ⎟ impedance ground plane to fi lter any thermal noise and CM ⎝RF +RI⎠ 2 ⎝RF +RI⎠ to prevent common mode signals on this pin from being inadvertently converted to differential signals. RI VIN– RF VOUT+ RL Noise Considerations VS The LT1994’s input referred voltage noise is on the order VINM 3 of 3nV/√Hz. Its input referred current noise is on the 1 4 order of 2.5pA/√Hz. In addition to the noise generated – + VOCM 2 VOCM LT1994 0.1μF by the amplifi er, the surrounding feedback resistors also VCM 8 + – contribute noise. The output noise generated by both the 5 SHDN 6 amplifi er and the feedback components is given by the VINP 7 equation: VSHDNB RI VIN+ RF VOUT– 1R994L F04 ⎛⎝⎜eni(cid:129)⎡⎣⎢1+RRF⎤⎦⎥⎞⎠⎟2 +2(cid:129)(In(cid:129)RF)2 + I e = no Figure 4. Circuit for Common Mode Range 2 ⎛ ⎡R ⎤⎞ 2(cid:129)⎜enRI(cid:129)⎢ F⎥⎟ +2(cid:129)enRF2 ⎝ ⎣R ⎦⎠ I 1994fb 13

LT1994 APPLICATIONS INFORMATION A plot of this equation and a plot of the noise generated Lower resistor values always result in lower noise at the by the feedback components are shown in Figure 6. penalty of increased distortion due to increased loading of the feedback network on the output. Higher resistor values The LT1994’s input referred voltage noise contributes the will result in higher output noise, but improved distortion equivalent noise of a 560Ω resistor. When the feedback due to less loading on the output. network is comprised of resistors whose values are less than this, the LT1994’s output noise is voltage noise Figure 6 shows the noise voltage that will appear differ- dominant (See Figure 6): entially between the outputs. The common mode output noise voltage does not add to this differential noise. For ⎛ R ⎞ e ≈e (cid:129)⎜1+ F⎟ optimum noise and distortion performance, use a dif- no ni ⎝ RI⎠ ferential output confi guration. Feedback networks consisting of resistors with values Power Dissipation Considerations greater than about 10k will result in output noise which is amplifi er current noise dominant. The LT1994 is housed in either an 8-lead MSOP package (θ = 140°C/W or an 8-lead DD package (θ = 43°C/W). e ≈ 2(cid:129)I (cid:129)R JA JA no n F The LT1994 combines high speed and large output current with a small die and small package so there is a need to enRI22 RI2 RF2 enRF22 be sure the die temperature does not exceed 150°C. In the 8-lead MSOP, LT1994 has its V– lead fused to the frame so it is possible to lower the package thermal impedance in–2 VS/2 by connecting the V– pin to a large ground plane or metal 3 trace. Metal trace and plated through holes can be used to encm2 1 – + 4 spread the heat generated by the device to the backside 2 VOCM LT1994 eno2 of the PC board. For example, an 8-lead MSOP on a 3/32" 8 + – in+2 5 FR-4 board with 540mm2 of 2oz. copper on both sides 6 of the PC board tied to the V– pin can drop the θ from JA 7 –VS/2 140°C/W to 110°C/W (see Table 1). enRI12 RI1 eni2 RF1 enRF12 The underside of the DD package has exposed metal (4mm2) from the lead frame where the die is attached. 1994 F05 This provides for the direct transfer of heat from the die Figure 5. Noise Analysis junction to the printed circuit board to help control the 100 maximum operating junction temperature. The dual-in-line TOTAL (AMPLIFIER + FEEDBACK NETWORK) pin arrangement allows for extended metal beyond the OUTPUT NOISE Hz) ends of the package on the topside (component side) of a V/√ circuit board. Table 1 summarizes for the MSOP package, n E ( the thermal resistance from the die junction-to-ambient OIS 10 N that can be obtained using various amounts of topside, T U P and backside metal (2oz. copper). On multilayer boards, UT FEEDBACK NETWORK O NOISE ALONE further reductions can be obtained using additional metal on inner PCB layers connected through vias beneath the 1 package. 0.1 1 10 RF = RI (kΩ) 1994 F06 Figure 6. LT1994 Output Spot Noise vs Spot Noise Contributed by Feedback Network Alone 1994fb 14

LT1994 APPLICATIONS INFORMATION In general, the die temperature can be estimated from Table 1. LT1994 MSOP Package Thermal Resistivity the ambient temperature T , and the device power dis- A COPPER AREA COPPER AREA THERMAL RESISTANCE sipation PD: TOPSIDE (mm2) BACKSIDE (mm2) (JUNCTION-TO-AMBIENT) T = T + + P • θ 0 0 140 J A D JA 30 0 135 The power dissipation in the IC is a function of the supply 100 0 130 voltage, the output voltage, and the load resistance. For 100 100 120 fully differential output amplifi ers at a given supply voltage 540 540 110 (±V ), and a given differential load (R ), the worst- CC LOAD case power dissipation PD(MAX) occurs at the worst-case Layout Considerations quiescent current (I = 20.5mA) and when the load Q(MAX) Because the LT1994 is a high speed amplifi er, it is sensitive current is given by the expression: to both stray capacitance and stray inductance. Compo- I = VCC nents connected to the LT1994 should be connected with LOAD R as short and direct connections as possible. A low noise, LOAD low impedance ground plane is critical for the highest The worst-case power dissipation in the LT1994 at performance. In single-supply applications, high quality I = VCC is: surface mount 1μF and 0.1μF ceramic bypass capacitors LOAD R with minimum PCB trace should be used directly across LOAD the power supplies V+ to V–. In split supply applications, ( ) P ( ) =2(cid:129)V (cid:129) I +I ( ) –I 2 (cid:129) high quality surface mount 1μF and 0.1μF ceramic bypass D MAX CC LOAD Q MAX LOAD capacitors should be placed across the power supplies V 2 V+ to V–, and individual high quality surface mount 0.1μF R = CC +2(cid:129)V (cid:129)I ( ) LOAD R CC Q MAX bypass capacitors should be used from each supply to LOAD ground with direct (short) connections. Example: A LT1994 is mounted on a circuit board in a Any stray parasitic capacitance to ground at the summing MSOP-8 package (θ = 140°C/W), and is running off of JA junctions, IN+ and IN– should be kept to an absolute mini- ±5V supplies driving an equivalent load (external load plus mum even if it means stripping back the ground plane feedback network) of 75Ω. The worst-case power that away from any trace attached to this node. This becomes would be dissipated in the device occurs when: especially true when the feedback resistor network uses V 2 resistor values >500Ω in circuits with RF = RI. Excessive PD(MAX)=RCC +2(cid:129)VCC(cid:129)IQ(MAX) peaking in the frequency response can be mitigated by LOAD adding small amounts of feedback capacitance around RF 2 5V (2pF to 5pF). Always keep in mind the differential nature of = +2(cid:129)5V(cid:129)(cid:129)17.5MA=0.54W 75Ω the LT1994, and that it is critical that the output impedances seen by both outputs (stray or intended) should be as bal- The maximum ambient temperature the 8-lead MSOP is anced and symmetric as possible. This will help preserve allowed to operate under these conditions is: the natural balance of the LT1994, which minimizes the T = T – P • θ = 150°C – (0.54W) • generation of even order harmonics, and preserves the A JMAX D JA rejection of common mode signals and noise. (140°C/W) = 75°C It is highly recommended that the V pin be either hard To operate the device at higher ambient temperature, OCM connect more copper to the V– pin to reduce the thermal tied to a low impedance ground plane (in split supply applications) or bypassed to ground with a high quality resistance of the package as indicated in Table 1. 1994fb 15

LT1994 APPLICATIONS INFORMATION 0.1μF ceramic capacitor in single-supply applications. be comprised of 1% resistors (or better) to enhance the This will help prevent thermal noise from the internal output common mode rejection. This will also prevent 80kΩ-80kΩ voltage divider (25nV/√Hz) and other exter- VOCM input referred common mode noise of the common nal sources of noise from being converted to differential mode amplifi er path (which cannot be fi ltered) from being noise due to mismatches in the feedback networks. It is converted to differential noise, degrading the differential also recommended that the resistive feedback networks noise performance. SIMPLIFIED SCHEMATIC V+ 120k SHUTDOWN V+ CIRCUIT I1 I1 55k SHDN CM1 CM2 V+ V+ V– V+ V+ Q9 Q11 OUT– BIAS + BIAS + BIAS OUT+ ADJUST – – ADJUST Q10 Gm2B Gm2A Q12 V– V– V– V– V+ OUT+ +V V+ V+ V+ V+ I2 R1 V+ 4k I3 80k Q7 Q8 VOCM Q1 Q2 R2 80k IN– D1 D2 4k Q5 Q6 OUT– V– V– D3 D4 Q3 Q4 CM V– ADJUST V+ I4A I4B IN+ V– 1994 SS01 V– 1994fb 16

LT1994 TYPICAL APPLICATIONS Differential 1st Order Lowpass Filter Example: The specifi ed –3dB frequency is 1MHz Gain = 4 Maximum –3dB frequency (f ) 2MHz 1. Using f = 1000kHz, C11 = 400pF 3dB 3dB abs Stopband attenuation: –6dB at 2 • f and 14dB at 5 • f 2. Nearest standard 5% value to 400pF is 390pF and C11 3dB 3dB = C12 = 390pF C11 3. Using f = 1000kHz, C11 = 390pF and Gain = 4, R21 3dB = R22 = 412Ω and R11 = R12 = 102Ω (nearest 1% R11 R21 VIN– V+ value) 0.1μF 3 Differential 2nd Order Butterworth Lowpass Filter 1 – + 4 VOUT+ 2 LT1994 Maximum –3dB frequency (f3dB) 1MHz 0.1μF 8 + – 5 VOUT– Stopband attenuation: –12dB at 2 • f3dB and –28dB at 5 • f3dB 6 7 R12 R22 R21 VIN+ C21 C12 R11 R31 1994 TA03 VIN– V+ 0.1μF 3 Component Calculation: 1 – + 4 VOUT+ 2 R11 = R12, R21 = R22 C11 LT1994 0.1μF 8 + – 5 VOUT– f ≤2MHzandGain≤2MHz 7 6 3dB f 3dB R12 R32 VIN+ 1. Calculate an absolute value for C11 (C11abs) using a R22 C22 1994 TA04 specifi ed –3dB frequency 5 4(cid:129)10 C11 = (C11 inpF andf inkHz) Component Calculation: abs abs 3dB f 3dB R11 = R12, R21 = R22, R31 = R32, C21 = C22, C11 = 10 • C21, R1 = R11, R2 = R21, R3 = R31, 2. Select a standard 5% capacitor value nearest the absolute C2 = C21 and C1 = C11 value for C11 1. Calculate an absolute value for C2 (C2 ) using a 3. Calculate R11 and R21 using the standard 5% C11 abs specifi ed –3dB frequency value, f and desired gain 3dB 5 R11 and R21 equations (C11 in pF and f in kHz) 4(cid:129)10 3dB C2 = (C2 inpF andf inkHz)(Note22) abs abs 3dB f 159.2(cid:129)106 3dB R21= C11(cid:129)f 2. Select a standard 5% capacitor value nearest the absolute 3dB value for C2 (C1 = 10 • C2) R21 R11= Gain 1994fb 17

LT1994 TYPICAL APPLICATIONS 3. Calculate R3, R2 and R1 using the standard 5% C2 Example: The specifi ed –3dB frequency is 1MHz Gain = 1 value, the specifi ed f and the specifi ed passband 3dB 1. Using f = 1000kHz, C2 = 400pF 3dB abs gain (Gn) 2. Nearest standard 5% value to 400pF is 390pF and C21 1MHz f ≤1MHz andGain≤8.8 or Gain≤ = C22 = 390pF and C11 = 3900pF 3dB f 3dB 3. Using f = 1000kHz, C2 = 390pF and Gain = 1, R1 3dB = 549Ω, R2 = 549Ω and R3 = 15.4Ω (nearest 1% R1, R2 and R3 equations (C2 in pF and f in kHz) 3dB values). R11 = R21 = 549Ω, R21 = R22 = 549Ω and ( ) ( ) 8 R31 = R32 = 15.4Ω. 1.121– 1.131–0.127(cid:129)Gn (cid:129)10 R3= ( ) (Note1) Note 1: The equations for R1, R2, R3 are ideal and do Gn+1 (cid:129)C2(cid:129)f 3ddB not account for the fi nite gain bandwidth product (GBW) 15 1.266(cid:129)10 of the LT1994 (70MHz). The maximum gain is set by R2= 2 2 the C1/C2 ratio (which for convenience is set equal to R3(cid:129)C2 (cid:129)f 3dB ten). R2 R1= Note 2: The calculated value of a capacitor is chosen Gn to produce input resistors less than 600Ω. If a higher value input resistance is required then multiply all resis- tor values and divide all capacitor values by the same number. A Single-Ended to Differential Voltage Conversion with Source Impedance Matching and Level Shifting RS 50Ω 50Ω 374Ω 402Ω V+ VIN 0.1μF V 54.9Ω 3 V 12 – + 4 VOUT– VOCM + 0.25V VOUT+ VOCMLT1994 VOCM 1 VIN 0.1μF 8 + – 5 VOUT+ VOCM – 0.25V VOUT– 6 0 t 0 t 7 402Ω 402Ω –1 1994 TA05 1994fb 18

LT1994 PACKAGE DESCRIPTION DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) R = 0.115 0.38(cid:112) 0.10 TYP 5 8 0.675(cid:112)0.05 3.5(cid:112)0.05 1.65(cid:112)0.05 3.00(cid:112)0.10 1.65(cid:112) 0.10 2.15(cid:112)0.05 (2 SIDES) (4 SIDES) (2 SIDES) PIN 1 PACKAGE TOP MARK OUTLINE (NOTE 6) (DD) DFN 1203 4 1 0.25(cid:112) 0.05 0.200 REF 0.75(cid:112)0.05 0.25(cid:112) 0.05 0.50 0.50 BSC BSC 2.38(cid:112)0.10 2.38(cid:112)0.05 0.00 – 0.05 (2 SIDES) (2 SIDES) BOTTOM VIEW—EXPOSED PAD RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev F) 3.00(cid:112) 0.102 (.118(cid:112) .004) 0.52 (NOTE 3) 8 7 6 5 (.0205) REF 3.00(cid:112) 0.102 4.90(cid:112) 0.152 DETAIL “A” (.118(cid:112) .004) 0.889(cid:112) 0.127 0.254 (.193(cid:112) .006) (NOTE 4) (.035(cid:112) .005) (.010) 0(cid:111) – 6(cid:111) TYP GAUGE PLANE 1 2 3 4 5.23 (.206) 3.20 – 3.45 0.53(cid:112) 0.152 MIN (.126 – .136) (.021(cid:112) .006) 1.10 0.86 (.043) (.034) DETAIL “A” MAX REF 0.18 0.42(cid:112) 0.038 0.65 (.007) (.0165(cid:112) .0015) (.0256) SEATING TYP BSC PLANE 0.22 – 0.38 0.1016(cid:112) 0.0508 RECOMMENDED SOLDER PAD LAYOUT (.009 – .015) (.004(cid:112) .002) NOTE: TYP (.00.26556) MSOP (MS8) 0307 REV F 1. DIMENSIONS IN MILLIMETER/(INCH) BSC 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 1994fb 19

LT1994 TYPICAL APPLICATION RFID Receiver Front-End, 1kHz < –3dB BW < 2MHz (Baseband Gain = 5) 82pF 1μF 140Ω 1k 5V 0.1μF 120pF 3 1 4 7 5V 2 LT1994 IOUT 10pF 0.1μF 8 LT5575 RF AMP I MIXER LPF IOUT+ 270μH* 6 5 1μF RF IOUT– 270μH* 140Ω 1k 82pF 120pF 10pF LO 0°/90° LO BUFFERS 5V 82pF 10pF 1μF RF AMP LPF QOUT+ 270μH* 140Ω 1k QOUT– 270μH* 5V 0.1μF 120pF Q MIXER 3 10pF 1 4 120pF 7 5V 2 LT1994 QOUT 0.1μF 8 5 6 1μF 140Ω 1k 82pF *COILCRAFT 0603HP 1994 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT®1167 Precision, Instrumentation Amp Single Gain Set Resistor: G = 1 to 10,000 LT1806/LT1807 Single/Dual Low Distortion Rail-to-Rail Amp 325MHz, 140V/μs Slew Rate, 3.5nV/√Hz Noise LT1809/LT1810 Single/Dual Low Distortion Rail-to-Rail Amp 180MHz, 350V/μs Slew Rate, Shutdown LT1990 High Voltage Gain Selectable Differential Amp ±250V Common Mode, Micropower, Gain = 1, 10 LT1991 Precision Gain Selectable Differential Amp Micropower, Pin Selectable Gain = –13 to 14 LTC1992/LTC1992-x Fully Differential Input/Output Amplifi ers Programmable Gain or Fixed Gain (G = 1, 2, 5, 10) LT1993-2/-4/-10 Low Distortion and Noise, Differential In/Out Fixed Gain (G = 2, 4, 10) LT1995 High Speed Gain Selectable Differential Amp 30MHz, 1000V/μs, Pin Selectable Gain = –7 to 8 LT1996 Precision, 100μA, Gain Selectable Differential Amp Pin Selectable Gain = 9 to 117 LTC6403 Low Noise, Low Power Fully Differential Amp 11mA Supply Current LTC6404-1/LTC6404-2 600MHz AC Precision Fully Differential Amp Available H-Grade (–40°C to 125°C) LTC6404-4 LT6600-2.5/-5/-10/-15/-20 Differential Amp and Lowpass, Chebyshev Filter Filter Cutoff = 2.5MHz, 5MHz, 10MHz, 15MHz or 20MHz 1994fb 20 Linear Technology Corporation LT 0309 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005

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