LT1956/LT1956-5 High Voltage, 1.5A, 500kHz Step-Down Switching Regulators FEATURES DESCRIPTIOU n Wide Input Range: 5.5V to 60V The LT®1956/LT1956-5 are 500kHz monolithic buck n 1.5A Peak Switch Current switching regulators with an input voltage capability up to n Small 16-Pin SSOP or Thermally Enhanced 60V. A high efficiency 1.5A, 0.2W switch is included on the TSSOP Package die along with all the necessary oscillator, control and logic n Saturating Switch Design: 0.2W circuitry. A current mode architecture provides fast tran- n Peak Switch Current Maintained Over sient response and good loop stability. Full Duty Cycle Range Special design techniques and a new high voltage process n Constant 500kHz Switching Frequency achieve high efficiency over a wide input range. Efficiency n Effective Supply Current: 2.5mA is maintained over a wide output current range by using the n Shutdown Current: 25m A output to bias the circuitry and by utilizing a supply boost n 1.2V Feedback Reference (LT1956) capacitor to saturate the power switch. Patented circuitry n 5V Fixed Output (LT1956-5) maintains peak switch current over the full duty cycle n Easily Synchronizable range*. A shutdown pin reduces supply current to 25m A and n Cycle-by-Cycle Current Limiting the device can be externally synchronized from 580kHz to APPLICATIOU S 700kHz with a logic level input. The LT1956/LT1956-5 are available in fused-lead 16-pin n High Voltage, Industrial and Automotive SSOP and thermally enhanced TSSOP packages. n Portable Computers , LTC and LT are registered trademarks of Linear Technology Corporation. n *U.S. PATENT NO. 6,498,466 n Battery Chargers n Distributed Power Systems TYPICAL APPLICATIOU 5V Buck Converter Efficiency vs Load Current MMSD914TI 100 VIN = 12V 6 L = 18µH 1V2IVN 4 BOOST 2 0.1µF 10µH VOUT 90 VOUT = 5V (TRANTSOIE 6N0TVS) 21C.0E20RµVAFM†IC VINLT1956-5SW 10MQ060N 2512VAµF CY (%) 80 VOUT = 3.3V 15 SHDN BIAS 10 6C.E3RVAMIC EFFICIEN 70 14 12 SYNC FB 60 GND VC 1, 8, 9, 16 11 50 220pF 0 0.25 0.50 0.75 1.00 1.25 4.7k LOAD CURRENT (A) 1956 TA02 4700pF †UNITED CHEMI-CON THCS50EZA225ZT 1956 TA01 1956f 1

LT1956/LT1956-5 ABSOLUTE W AXIW UW RATIU GS (Note 1) Input Voltage (V ) ................................................. 60V Operating Junction Temperature Range IN BOOST Pin Above SW ............................................ 35V LT1956EFE/LT1956EFE-5/LT1956EGN/LT1956EGN-5 BOOST Pin Voltage................................................. 68V (Notes 8, 10)..................................... –40(cid:176) C to 125(cid:176) C SYNC, SENSE Voltage (LT1956-5) ........................... 7V LT1956IFE/LT1956IFE-5/LT1956IGN/LT1956IGN-5 SHDN Voltage........................................................... 6V (Notes 8, 10)..................................... –40(cid:176) C to 125(cid:176) C BIAS Pin Voltage .................................................... 30V Storage Temperature Range................ –65(cid:176) C to 150(cid:176) C FB Pin Voltage/Current (LT1956)................... 3.5V/2mA Lead Temperature (Soldering, 10 sec)................. 300(cid:176) C PACKAGE/ORDER IU FORW ATIOU TOP VIEW ORDER PART TOP VIEW ORDER PART NUMBER NUMBER GND 1 16 GND GND 1 16 GND SW 2 15 SHDN SW 2 15 SHDN LT1956EFE LT1956EGN NC 3 14 SYNC NC 3 14 SYNC LT1956IFE LT1956IGN VIN 4 13 NC LT1956EFE-5 VIN 4 13 NC LT1956EGN-5 NC 5 12 FB/SENSE NC 5 12 FB/SENSE LT1956IFE-5 LT1956IGN-5 BOOST 6 11 VC BOOST 6 11 VC NC 7 10 BIAS FE PART MARKING NC 7 10 BIAS GN PART MARKING GND 8 9 GND GND 8 9 GND 1956EFE 1956 FE PACKAGE GN PACKAGE 16-LEAD PLASTIC TSSOP 1956IFE 16-LEAD PLASTIC SSOP 1956I TJMAX = 125(cid:176)C, q JA = 45(cid:176)C/W, q JC (PAD) = 10(cid:176)C/W 1956EFE-5 TJMAX = 125(cid:176)C, q JA = 85(cid:176)C/W, q JC (PIN 8) = 25(cid:176)C/W 19565 EXPOSED BACKSIDE MUST BE SOLDERED 1956IFE-5 FOUR CORNER PINS SOLDERED 1956I5 TO GROUND PLANE TO GROUND PLANE Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25(cid:176) C. J V = 15V, V = 1.5V, SHDN = 1V, Boost o/c, SW o/c, unless otherwise noted. IN C PARAMETER CONDITIONS MIN TYP MAX UNITS Reference Voltage (LT1956) 5.5V £ V £ 60V 1.204 1.219 1.234 V IN V + 0.2 £ V £ V – 0.2 l 1.195 1.243 V OL C OH SENSE Voltage (LT1956-5) 5.5V £ V £ 60V 4.94 5 5.06 V IN V + 0.2 £ V £ V – 0.2 l 4.90 5.10 V OL C OH SENSE Pin Resistance (LT1956-5) 9.5 13.8 19 kW FB Input Bias Current (LT1956) l 0.5 1.5 m A Error Amp Voltage Gain (Notes 2, 9) 200 400 V/V Error Amp g dl (V ) = – 10m A (Note 9) 1500 2000 3000 m Mho m C l 1000 3200 m Mho V to Switch g 1.7 A/V C m EA Source Current FB = 1V or V = 4.1V l 125 225 400 m A SENSE EA Sink Current FB = 1.4V or V = 5.7V l 100 225 450 m A SENSE V Switching Threshold Duty Cycle = 0 0.9 V C V High Clamp SHDN = 1V 2.1 V C 1956f 2

LT1956/LT1956-5 ELECTRICAL CHARACTERISTICS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at T = 25(cid:176) C. J V = 15V, V = 1.5V, SHDN = 1V, Boost o/c, SW o/c, unless otherwise noted. IN C PARAMETER CONDITIONS MIN TYP MAX UNITS Switch Current Limit V Open, Boost = V + 5V, FB = 1V or V = 4.1V l 1.5 2 3 A C IN SENSE Switch On Resistance I = 1.5A, Boost = V + 5V (Note 7) 0.2 0.3 W SW IN l 0.4 W Maximum Switch Duty Cycle FB = 1V or V = 4.1V 82 90 % SENSE l 75 90 % Switch Frequency V Set to Give DC = 50% 460 500 540 kHz C l 430 570 kHz f Line Regulation 5.5V £ V £ 60V l 0.05 0.15 %/V SW IN f Shifting Threshold Df = 10kHz 0.8 V SW Minimum Input Voltage (Note 3) l 4.6 5.5 V Minimum Boost Voltage (Note 4) I £ 1.5A l 2 3 V SW Boost Current (Note 5) Boost = V + 5V, I = 0.5A l 12 25 mA IN SW Boost = V + 5V, I = 1.5A l 42 70 mA IN SW Input Supply Current (I ) (Note 6) V = 5V 1.4 2.2 mA VIN BIAS Output Supply Current (I ) (Note 6) V = 5V 2.9 4.2 mA BIAS BIAS Shutdown Supply Current SHDN = 0V, V £ 60V, SW = 0V, V Open 25 75 m A IN C l 200 m A Lockout Threshold V Open l 2.30 2.42 2.53 V C Shutdown Thresholds V Open, Shutting Down l 0.15 0.37 0.6 V C V Open, Starting Up l 0.25 0.45 0.6 V C Minimum SYNC Amplitude l 1.5 2.2 V SYNC Frequency Range 580 700 kHz SYNC Input Resistance 20 kW Note 1: Absolute Maximum Ratings are those values beyond which the life Note 7: Switch on resistance is calculated by dividing V to SW voltage by IN of a device may be impaired. the forced current (1.5A). See Typical Performance Characteristics for the Note 2: Gain is measured with a V swing equal to 200mV above the low graph of switch voltage at other currents. C clamp level to 200mV below the upper clamp level. Note 8: The LT1956EFE/LT1956EFE-5/LT1956EGN/LT1956EGN-5 are Note 3: Minimum input voltage is not measured directly, but is guaranteed guaranteed to meet performance specifications from 0(cid:176) C to 125(cid:176) C by other tests. It is defined as the voltage where internal bias lines are still junction temperature. Specifications over the –40(cid:176) C to 125(cid:176) C operating regulated so that the reference voltage and oscillator remain constant. junction temperature range are assured by design, characterization and Actual minimum input voltage to maintain a regulated output will depend correlation with statistical process controls. The LT1956IFE/LT1956IFE-5/ upon output voltage and load current. See Applications Information. LT1956IGN/LT1956IGN-5 are guaranteed over the full –40(cid:176) C to 125(cid:176) C operating junction temperature range. Note 4: This is the minimum voltage across the boost capacitor needed to guarantee full saturation of the internal power switch. Note 9: Transconductance and voltage gain refer to the internal amplifier exclusive of the voltage divider. To calculate gain and transconductance, Note 5: Boost current is the current flowing into the BOOST pin with the refer to the SENSE pin on fixed voltage parts. Divide values shown by the pin held 5V above input voltage. It flows only during switch on time. ratio V /1.219. Note 6: Input supply current is the quiescent current drawn by the input OUT Note 10: This IC includes overtemperature protection that is intended to pin when the BIAS pin is held at 5V with switching disabled. Bias supply protect the device during momentary overload conditions. Junction current is the current drawn by the BIAS pin when the BIAS pin is held at 5V. Total input referred supply current is calculated by summing input temperature will exceed 125(cid:176) C when overtemperature protection is active. supply current (I ) with a fraction of supply current (I ): Continuous operation above the specified maximum operating junction VIN BIAS temperature may impair device reliability. I = I + (I )(V /V ) TOTAL VIN BIAS OUT IN with V = 15V, V = 5V, I = 1.4mA, I = 2.9mA, I = 2.4mA. IN OUT VIN BIAS TOTAL 1956f 3

LT1956/LT1956-5 TYPICAL PERFORW AU CE CHARACTERISTICS Switch Peak Current Limit FB Pin Voltage and Current SHDN Pin Bias Current 2.5 1.234 2.0 250 CURRENT REQUIRED TO FORCE SHUTDOWN 1.229 200 (FLOWS OUT OF PIN). AFTER SHUTDOWN, CH PEAK CURRENT (A) 12..50 GUARANTTYEPEIDC AMLINIMUM DBACK VOLTAGE (V) 111...222112494 CVUORLTRAEGNET 11..50 CURRENT (A)µ mCURRENT (A) 11501002 CURRENT DROPS TO A FEW m A WIT FEE 0.5 AT 2.38V STANDBY THRESHOLD S (CURRENT FLOWS OUT OF PIN) 1.209 6 1.0 1.204 0 0 0 20 40 60 80 100 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 DUTY CYCLE (%) JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) 1956 G01 1956 G02 1956 G03 Lockout and Shutdown Thresholds Shutdown Supply Current Shutdown Supply Current 2.4 40 300 VSHDN = 0V LOCKOUT 35 VOLTAGE (V) 211...062 µY CURRENT (A) 322050 µY CURRENT (A)122505000 VIN = 60V VIN = 15V SHDN PIN 00..84 START-UP INPUT SUPPL 1150 INPUT SUPPL15000 5 SHUTDOWN 0 0 0 –50 –25 0 25 50 75 100 125 0 10 20 30 40 50 60 0 0.1 0.2 0.3 0.4 0.5 JUNCTION TEMPERATURE (°C) INPUT VOLTAGE (V) SHUTDOWN VOLTAGE (V) 1956 G04 1956 G05 1956 G06 Error Amplifier Transconductance Error Amplifier Transconductance Frequency Foldback 2500 3000 200 625 SWITCHING PHASE FREQUENCY µmho) 2000 2500 150 Y (kHz)A)500 TRANSCONDUCTANCE ( 11505000000 mGAIN (Mho)211050000000 EVRFRB (O 2R • 1A0M–3PG)LAIFINIER EQUI2RV0OA0ULkTENT CIR1CC2OUpUIVTFTC 150000PHASE (DEG) SWITICHING FREQUENCµOR FB CURRENT (123257505 RLOAD = 50W CUFBR RPEINNT 0 500 –50 0 –50 –25 0 25 50 75 100 125 100 1k 10k 100k 1M 10M 0 0.2 0.4 0.6 0.8 1.0 1.2 JUNCTION TEMPERATURE FREQUENCY (Hz) VFB (V) 1956 G08 1956 G07 1956 G09 1956f 4

LT1956/LT1956-5 TYPICAL PERFORW AU CE CHARACTERISTICS Minimum Input Voltage with 5V Switching Frequency Output BOOST Pin Current 575 7.5 45 VOUT = 5V L = 18µH 40 550 7.0 A) 35 m FREQUENCY (kHz) 554207505 NPUT VOLTAGE (V) 66..50 VOMLITNAIMMGIEUN MTIMO IU NSMPTUA ITRNTPUT ST PIN CURRENT ( 32210505 I VOLTAGE TO RUN O O 5.5 B 10 450 5 425 5.0 0 –50 –25 0 25 50 75 100 125 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.5 1 1.5 JUNCTION TEMPERATURE (°C) LOAD CURRENT (A) SWITCH CURRENT (A) 1956 G10 1956 G11 1956 G12 Switch Minimum ON Time V Pin Shutdown Threshold Switch Voltage Drop vs Temperature C 2.1 450 600 400 1.9 TJ = 125°C s) 500 OLD VOLTAGE (V) 111...537 H VOLTAGE (mV) 332250500000 TJ = 25°C NIMUM ON TIME (n 430000 HRESH 1.1 SWITC 150 TJ = –40°C TCH MI 200 T 100 WI 0.9 S 100 50 0.7 0 0 –50 –25 0 25 50 75 100 125 0 0.5 1 1.5 –50 –25 0 25 50 75 100 125 JUNCTION TEMPERATURE (°C) SWITCH CURRENT (A) JUNCTION TEMPERATURE (°C) 1956 G13 1766 G14 1956 G15 1956f 5

LT1956/LT1956-5 PIU FUU CTIOU S GND (Pins 1, 8, 9, 16): The GND pin connections act as V (Pin 11) The V pin is the output of the error amplifier C C the reference for the regulated output, so load regulation and the input of the peak switch current comparator. It is will suffer if the “ground” end of the load is not at the same normally used for frequency compensation, but can also voltage as the GND pins of the IC. This condition will occur serve as a current clamp or control loop override. V sits C when load current or other currents flow through metal at about 1V for light loads and 2V at maximum load. It can paths between the GND pins and the load ground. Keep the be driven to ground to shut off the regulator, but if driven paths between the GND pins and the load ground short high, current must be limited to 4mA. and use a ground plane when possible. For the FE package, FB/SENSE (Pin 12): The feedback pin is used to set the the exposed pad should be soldered to the copper GND output voltage using an external voltage divider that gen- plane underneath the device. (See Applications Informa- erates 1.22V at the pin for the desired output voltage. The tion—Layout Considerations.) 5V fixed output voltage parts have the divider included on SW (Pin 2): The switch pin is the emitter of the on-chip the chip and the FB pin is used as a SENSE pin, connected power NPN switch. This pin is driven up to the input pin directly to the 5V output. Three additional functions are voltage during switch on time. Inductor current drives the performed by the FB pin. When the pin voltage drops switch pin negative during switch off time. Negative volt- below 0.6V, switch current limit is reduced and the exter- age is clamped with the external catch diode. Maximum nal SYNC function is disabled. Below 0.8V, switching negative switch voltage allowed is –0.8V. frequency is also reduced. See Feedback Pin Functions in Applications Information for details. NC (Pins 3, 5, 7, 13): No Connection. SYNC (Pin 14): The SYNC pin is used to synchronize the V (Pin 4): This is the collector of the on-chip power NPN IN internal oscillator to an external signal. It is directly logic switch. V powers the internal control circuitry when a IN compatible and can be driven with any signal between voltage on the BIAS pin is not present. High dI/dt edges 10% and 90% duty cycle. The synchronizing range is occur on this pin during switch turn on and off. Keep the equal to initial operating frequency up to 700kHz. See path short from the V pin through the input bypass IN Synchronizing in Applications Information for details. If capacitor, through the catch diode back to SW. All trace unused, this pin should be tied to ground. inductance on this path will create a voltage spike at switch off, adding to the V voltage across the internal NPN. SHDN (Pin 15): The SHDN pin is used to turn off the CE regulator and to reduce input current to a few microam- BOOST (Pin 6): The BOOST pin is used to provide a drive peres. This pin has two thresholds: one at 2.38V to disable voltage, higher than the input voltage, to the internal switching and a second at 0.4V to force complete mi- bipolar NPN power switch. Without this added voltage, the cropower shutdown. The 2.38V threshold functions as an typical switch voltage loss would be about 1.5V. The accurate undervoltage lockout (UVLO); sometimes used additional BOOST voltage allows the switch to saturate to prevent the regulator from delivering power until the and voltage loss approximates that of a 0.2W FET struc- input voltage has reached a predetermined level. ture, but with much smaller die area. If the SHDN pin functions are not required, the pin can BIAS (Pin 10): The BIAS pin is used to improve efficiency either be left open (to allow an internal bias current to lift when operating at higher input voltages and light load the pin to a default high state) or be forced high to a level current. Connecting this pin to the regulated output volt- not to exceed 6V. age forces most of the internal circuitry to draw its oper- ating current from the output voltage rather than the input supply. This architecture increases efficiency especially when the input voltage is much higher than the output. Minimum output voltage setting for this mode of operation is 3V. 1956f 6

LT1956/LT1956-5 BLOCK DIAGRAW The LT1956 is a constant frequency, current mode buck it much easier to frequency compensate the feedback loop converter. This means that there is an internal clock and and also gives much quicker transient response. two feedback loops that control the duty cycle of the power Most of the circuitry of the LT1956 operates from an switch. In addition to the normal error amplifier, there is a internal 2.9V bias line. The bias regulator normally draws current sense amplifier that monitors switch current on a power from the regulator input pin, but if the BIAS pin is cycle-by-cycle basis. A switch cycle starts with an oscilla- connected to an external voltage higher than 3V, bias tor pulse which sets the R flip-flop to turn the switch on. S power will be drawn from the external source (typically the When switch current reaches a level set by the inverting regulated output voltage). This will improve efficiency if input of the comparator, the flip-flop is reset and the the BIAS pin voltage is lower than regulator input voltage. switch turns off. Output voltage control is obtained by using the output of the error amplifier to set the switch High switch efficiency is attained by using the BOOST pin current trip point. This technique means that the error to provide a voltage to the switch driver which is higher amplifier commands current to be delivered to the output than the input voltage, allowing switch to be saturated. rather than voltage. A voltage fed system will have low This boosted voltage is generated with an external capaci- phase shift up to the resonant frequency of the inductor tor and diode. Two comparators are connected to the and output capacitor, then an abrupt 180(cid:176) shift will occur. shutdown pin. One has a 2.38V threshold for undervoltage The current fed system will have 90(cid:176) phase shift at a much lockout and the second has a 0.4V threshold for complete lower frequency, but will not have the additional 90(cid:176) shift shutdown. until well beyond the LC resonant frequency. This makes VIN 4 RLIMIT RSENSE BIAS 10 R2E.G9UVL BAITAOSR IVNCTCERNAL + – CURRENT S COMPARATOR SLOPE COMP SYNC 14 ANTISLOPE COMP BOOST 6 SHUTDOWN COMPARATOR 500kHz + – OSCILLATOR S RS DRIVER QPO1WER FLIP-FLOP CIRCUITRY SWITCH R 0.4V 5.5µA 2 SW SHDN 15 + FREQUENCY – FOLDBACK LOCKOUT COMPARATOR · 1 Q2 VCCL(AMMAXP) Q3 FCOULDRBRAECNKT LIMIT ERROR CLAMP AMPLIFIER gm = 2000m Mho – 12 FB 11 + 2.38V 1.22V VC GND 1, 8, 9, 16 1956 F01 Figure 1. LT1956 Block Diagram 1956f 7

LT1956/LT1956-5 APPLICATIOU S IU FORW ATIOU FEEDBACK PIN FUNCTIONS current through the diode and inductor is equal to the short-circuit current limit of the switch (typically 2A for The feedback (FB) pin on the LT1956 is used to set output the LT1956, folding back to less than 1A). Minimum voltage and provide several overload protection features. switch on time limitations would prevent the switcher The first part of this section deals with selecting resistors from attaining a sufficiently low duty cycle if switching to set output voltage and the remaining part talks about frequency were maintained at 500kHz, so frequency is foldback frequency and current limiting created by the FB reduced by about 5:1 when the feedback pin voltage drops pin. Please read both parts before committing to a final below 0.8V (see Frequency Foldback graph). This does design. The 5V fixed output voltage part (LT1956-5) has not affect operation with normal load conditions; one internal divider resistors and the FB pin is renamed SENSE, simply sees a shift in switching frequency during start-up connected directly to the output. as the output voltage rises. The suggested value for the output divider resistor (see In addition to lower switching frequency, the LT1956 also Figure 2) from FB to ground (R2) is 5k or less, and a operates at lower switch current limit when the feedback formula for R1 is shown below. The output voltage error pin voltage drops below 0.6V. Q2 in Figure 2 performs this caused by ignoring the input bias current on the FB pin is function by clamping the V pin to a voltage less than its less than 0.25% with R2 = 5k. A table of standard 1% C normal 2.1V upper clamp level. This foldback current limit values is shown in Table 1 for common output voltages. greatly reduces power dissipation in the IC, diode and in- Please read the following section if divider resistors are ductor during short-circuit conditions. External synchro- increased above the suggested values. nization is also disabled to prevent interference with fold- R2(V - 1.22) back operation. Again, it is nearly transparent to the user R1= OUT under normal load conditions. The only loads that may be 1.22 affected are current source loads which maintain full load Table 1 current with output voltage less than 50% of final value. In OUTPUT R1 % ERROR AT OUTPUT these rare situations the feedback pin can be clamped above VOLTAGE R2 (NEAREST 1%) DUE TO DISCRETE 1% 0.6V with an external diode to defeat foldback current limit. (V) (kW ) (kW ) RESISTOR STEPS Caution: clamping the feedback pin means that frequency 3 4.99 7.32 +0.32 shifting will also be defeated, so a combination of high in- 3.3 4.99 8.45 –0.43 put voltage and dead shorted output may cause the LT1956 5 4.99 15.4 –0.30 to lose control of current limit. 6 4.75 18.7 +0.38 The internal circuitry which forces reduced switching 8 4.47 24.9 +0.20 frequency also causes current to flow out of the feedback 10 4.32 30.9 –0.54 pin when output voltage is low. The equivalent circuitry is 12 4.12 36.5 +0.24 shown in Figure 2. Q1 is completely off during normal 15 4.12 46.4 –0.27 operation. If the FB pin falls below 0.8V, Q1 begins to conduct current and reduces frequency at the rate of More Than Just Voltage Feedback approximately 3.5kHz/m A. To ensure adequate frequency The feedback pin is used for more than just output voltage foldback (under worst-case short-circuit conditions), the sensing. It also reduces switching frequency and current external divider Thevinin resistance must be low enough limit when output voltage is very low (see the Frequency to pull 115m A out of the FB pin with 0.44V on the pin (RDIV Foldback graph in Typical Performance Characteristics). £ 3.8k). The net result is that reductions in frequency and This is done to control power dissipation in both the IC current limit are affected by output voltage divider imped- and in the external diode and inductor during short-circuit ance. Although divider impedance is not critical, caution conditions. A shorted output requires the switching regu- should be used if resistors are increased beyond the lator to operate at very low duty cycles, and the average suggested values and short-circuit conditions will occur 1956f 8

LT1956/LT1956-5 APPLICATIOU S IU FORW ATIOU LT1956 TO FREQUENCY VSW L1 SHIFTING OUTPUT 5V 1.4V Q1 ERROR AMPLIFIER + 1.2V R1 R3 R4 1k 2k FB + – C1 BUFFER R2 Q2 TO SYNC CIRCUIT VC GND 1956 F02 Figure 2. Frequency and Current Limit Foldback with high input voltage. High frequency pickup will in- VOUT USING crease and the protection accorded by frequency and 10mV/DIV 22µF CERAMIC OUTPUT current foldback will decrease. CAPACITOR CHOOSING THE INDUCTOR VOUT USING 100µF, 0.08Ω 10mV/DIV TANTALUM For most applications, the output inductor will fall into the OUTPUT range of 5m H to 30m H. Lower values are chosen to reduce CAPACITOR physical size of the inductor. Higher values allow more VIN = 12V 1µs/DIV 1956 F03 output current because they reduce peak current seen by VOUT = 5V L = 15µH the LT1956 switch, which has a 1.5A limit. Higher values Figure 3. LT1956 Output Ripple Voltage Waveforms. also reduce output ripple voltage. Ceramic vs Tantalum Output Capacitors When choosing an inductor you will need to consider Output ripple voltage is determined by ripple current output ripple voltage, maximum load current, peak induc- (I ) through the inductor and the high frequency LP-P tor current and fault current in the inductor. In addition, impedance of the output capacitor. At high frequencies, other factors such as core and copper losses, allowable the impedance of the tantalum capacitor is dominated by component height, EMI, saturation and cost should also its effective series resistance (ESR). be considered. The following procedure is suggested as a way of handling these somewhat complicated and con- Tantalum Output Capacitor flicting requirements. The typical method for reducing output ripple voltage when using a tantalum output capacitor is to increase the Output Ripple Voltage inductor value (to reduce the ripple current in the induc- Figure 3 shows a comparison of output ripple voltage for tor). The following equations will help in choosing the the LT1956 using either a tantalum or ceramic output required inductor value to achieve a desirable output ripple capacitor. It can be seen from Figure 3 that output ripple voltage level. If output ripple voltage is of less importance, voltage can be significantly reduced by using the ceramic the subsequent suggestions in Peak Inductor and Fault output capacitor; the significant decrease in output ripple Current and EMI will additionally help in the selection of voltage is due to the very low ESR of ceramic capacitors. the inductor value. 1956f 9

LT1956/LT1956-5 APPLICATIOU S IU FORW ATIOU Peak-to-peak output ripple voltage is the sum of a triwave ceramic capacitor. Although this reduction of ESR re- (created by peak-to-peak ripple current (I ) times ESR) moves a useful zero in the overall loop response, this zero LP-P and a square wave (created by parasitic inductance (ESL) can be replaced by inserting a resistor (R ) in series with C and ripple current slew rate). Capacitive reactance is the V pin and the compensation capacitor C . (See C C assumed to be small compared to ESR or ESL. Ceramic Capacitors in Applications Information.) Peak Inductor Current and Fault Current ( )( ) ( ) dI V = I ESR + ESL S RIPPLE LP-P dt To ensure that the inductor will not saturate, the peak in- ductor current should be calculated knowing the maximum where: load current. An appropriate inductor should then be cho- ESR = equivalent series resistance of the output sen. In addition, a decision should be made whether or not capacitor the inductor must withstand continuous fault conditions. ESL = equivalent series inductance of the output If maximum load current is 0.5A, for instance, a 0.5A capacitor inductor may not survive a continuous 2A overload condi- dI/dt = slew rate of inductor ripple current = V /L tion. Dead shorts will actually be more gentle on the IN inductor because the LT1956 has frequency and current Peak-to-peak ripple current (I ) through the inductor LP-P limit foldback. and into the output capacitor is typically chosen to be between 20% and 40% of the maximum load current. It is Peak inductor and switch current can be significantly approximated by: higher than output current, especially with smaller induc- tors and lighter loads, so don’t omit this step. Powdered ( )( ) V V –V ILP-P = OU(T )I(N)( )OUT Table 2 V f L IN VENDOR/ VALUE I DCR HEIGHT DC(MAX) Example: with V = 12V, V = 5V, L = 15m H, ESR = PART NO. (m H) (Amps) (Ohms) (mm) IN OUT 0.080W and ESL = 10nH, output ripple voltage can be Coiltronics approximated as follows: UP1B-100 10 1.9 0.111 5.0 UP1B-220 22 1.2 0.254 5.0 ( )( ) 5 12- 5 UP2B-220 22 2.0 0.062 6.0 I = ( )( ) =0.389A LP-P (12) 15•10–6 500•10–6 UP2B-330 33 1.7 0.092 6.0 UP1B-150 15 1.5 0.175 5.0 dI 12 S = =106 •0.8 Coilcraft dt 15•10- 6 D01813P-153HC 15 1.5 0.170 5.0 ( )( ) V =(0.389)(0.08)+ 10•10- 9 106 (0.8) D01813P-103HC 10 1.9 0.111 5.0 RIPPLE D53316P-223 22 1.6 0.207 5.1 =0.031+0.008=39mV P-P D53316P-333 33 1.4 0.334 5.1 LP025060B-682 6.8 1.3 0.165 1.65 To reduce output ripple voltage further requires an in- Sumida crease in the inductor value with the trade-off being a CDRH4D28-4R7 4.7 1.32 0.072 3.0 physically larger inductor with the possibility of increased CDRH5D28-100 10 1.30 0.065 3.0 component height and cost. CDRH6D28-150 15 1.40 0.084 3.0 Ceramic Output Capacitor CDRH6D28-180 18 1.32 0.095 3.0 An alternative way to further reduce output ripple voltage CDRH6D28-220 22 1.20 0.128 3.0 is to reduce the ESR of the output capacitor by using a CDRH6D38-220 22 1.30 0.096 4.0 1956f 10

LT1956/LT1956-5 APPLICATIOU S IU FORW ATIOU iron cores are forgiving because they saturate softly, current without affecting the frequency compensation it whereas ferrite cores saturate abruptly. Other core mate- provides. rials fall somewhere in between. The following formula Maximum load current would be equal to maximum assumes continuous mode of operation, but errs only switch current for an infinitely large inductor, but with slightly on the high side for discontinuous mode, so it can finite inductor size, maximum load current is reduced by be used for all conditions. one half of peak-to-peak inductor current (I ). The LP-P ( ) following formula assumes continuous mode operation, I V V –V I =I + LP-P =I + OUT IN OUT implying that the term on the right is less than one half PEAK OUT OUT 2 2•VIN•f•L of␣IP. EMI I ContinuousMode OUT(MAX) Decide if the design can tolerate an “open” core geometry I (V +V )(V –V –V ) like a rod or barrel, which have high magnetic field =IP – LP-P =IP – OUT ( F)( IN)( )(O)UT F 2 2 V f L radiation, or whether it needs a closed core like a toroid to IN prevent EMI problems. This is a tough decision because For V = 5V, V = 8V, V = 0.63V, f = 500kHz OUT IN(MAX) F(DI) the rods or barrels are temptingly cheap and small and and L = 10m H: there are no helpful guidelines to calculate when the magnetic field radiation will be a problem. ( )( ) 5+0.63 8–5–0.63 I =1.5– ( )( ) OUT(MAX) ( )( ) Additional Considerations 2 8 500•103 10•10–6 After making an initial choice, consider additional factors =1.5–0.17=1.33A such as core losses and second sourcing, etc. Use the Note that there is less load current available at the higher experts in Linear Technology’s Applications department if input voltage because inductor ripple current increases. At you feel uncertain about the final choice. They have V = 15V and using the same set of conditions: experience with a wide range of inductor types and can tell IN you about the latest developments in low profile, surface ( )( ) 5+0.63 15–5–0.63 mounting, etc. I =1.5– ( )( ) OUT(MAX) ( )( ) 2 15 500•103 10•10–6 MAXIMUM OUTPUT LOAD CURRENT =1.5–0.35=1.15A Maximum load current for a buck converter is limited by To calculate peak switch current with a given set of the maximum switch current rating (I ). The current rating P conditions, use: for the LT1956 is 1.5A. Unlike most current mode convert- ers, the LT1956 maximum switch current limit does not I I =I + LP-P fall off at high duty cycles. Most current mode converters SW(PEAK) OUT 2 suffer a drop off of peak switch current for duty cycles (V +V )(V –V –V ) above 50%. This is due to the effects of slope compensa- =IOUT + OUT ( F)( IN)( )(O)UT F 2 V f L tion required to prevent subharmonic oscillations in cur- IN rent mode converters. (For detailed analysis, see Applica- tion Note 19.) Reduced Inductor Value and Discontinuous Mode The LT1956 is able to maintain peak switch current limit If the smallest inductor value is of the most importance to over the full duty cycle range by using patented circuitry to a converter design, in order to reduce inductor size/cost, cancel the effects of slope compensation on peak switch discontinuous mode may yield the smallest inductor 1956f 11

LT1956/LT1956-5 APPLICATIOU S IU FORW ATIOU solution. The maximum output load current in discontinu- load current is required, the inductor value must be ous mode, however, must be calculated and is defined increased. If I no longer meets the discontinuous OUT(MAX) later in this section. mode criteria, use the I equation for continuous OUT(MAX) mode; the LT1956 is designed to operate well in both Discontinuous mode is entered when the output load modes of operation, allowing a large range of inductor current is less than one-half of the inductor ripple current values to be used. (I ). In this mode, inductor current falls to zero before LP-P the next switch turn-on (see Figure 8). Buck converters will be in discontinuous mode for output load current SHORT-CIRCUIT CONSIDERATIONS given by: For a ground short-circuit fault on the regulated output, the maximum input voltage for the LT1956 is typically I DiscontinousMode OUT limited to 25V. If a greater input voltage is required, (V +V )(V –V –V ) increasing the resistance in series with the inductor may < OUT F IN OUT F (2)(V )(f)(L) suffice (see short-circuit calculations at the end of this IN section). Alternatively, the 1.5A LT1766 can be used since The inductor value in a buck converter is usually chosen it is identical to the LT1956 but runs at a lower frequency large enough to keep inductor ripple current (I ) low; of 200kHz, allowing higher sustained input voltage capa- LP-P this is done to minimize output ripple voltage and maxi- bility during output short circuit. mize output load current. In the case of large inductor The LT1956 is a current mode controller. It uses the V C values, as seen in the equation above, discontinuous node voltage as an input to a current comparator which mode will be associated with “light loads.” turns off the output switch on a cycle-by-cycle basis as When choosing small inductor values, however, discon- peak switch current is reached. The internal clamp on the tinuous mode will occur at much higher output load VC node, nominally 2V, then acts as an output switch peak currents. The limit to the smallest inductor value that can current limit. This action becomes the switch current limit be chosen is set by the LT1956 peak switch current (I ) specification. The maximum available output power is P then determined by the switch current limit. and the maximum output load current required given by: A potential controllability problem could occur under I DiscontinuousMode OUT(MAX) short-circuit conditions. If the power supply output is 2 2 short circuited, the feedback amplifier responds to the low I I (f)(L)(V ) = P = P IN output voltage by raising the control voltage, V , to its 2(I ) 2(V +V )(V –V - V ) C LP-P OUT F IN OUT F peak current limit value. Ideally, the output switch would be turned on, and then turned off as its current exceeded Example: For V = 15V, V = 5V, V = 0.63V, f = 500kHz IN OUT F and L = 4m H the value indicated by VC. However, there is finite response time involved in both the current comparator and turnoff of the output switch. These result in a minimum on time I DiscontinuousMode OUT(MAX) t . When combined with the large ratio of V to 1.52(500•103)(4•10- 6)(15) ON(MIN) IN = (VF + I • R), the diode forward voltage plus inductor I • R 2(5+0.63)(15–5–0.63) voltage drop, the potential exists for a loss of control. Expressed mathematically the requirement to maintain I Discontinuous Mode = 0.639A OUT(MAX) control is: What has been shown here is that if high inductor ripple V +I•R current and discontinuous mode operation can be toler- f•t £ F ON V ated, small inductor values can be used. If a higher output IN 1956f 12

LT1956/LT1956-5 APPLICATIOU S IU FORW ATIOU where: capacitor may potentially be starting from 0V. This re- quires that the part obey the overall duty cycle demanded f = switching frequency by the loop, related to V and V , as the output voltage t = switch minimum on time IN OUT ON rises to its target value. It is recommended that for [V / V = diode forward voltage IN F (V + V )] ratios > 4, a soft-start circuit should be used V = input voltage OUT F IN to control the output capacitor charge rate during start-up I • R = inductor I • R voltage drop or during recovery from an output short circuit, thereby If this condition is not observed, the current will not be adding additional control over peak inductor current. See limited at IPK, but will cycle-by-cycle ratchet up to some Buck Converter with Adjustable Soft-Start later in this higher value. Using the nominal LT1956 clock frequency data sheet. of 500KHz, a V of 12V and a (V + I • R) of say 0.7V, the IN F maximum t to maintain control would be approximately ON OUTPUT CAPACITOR 116ns, an unacceptably short time. The LT1956 will operate with either ceramic or tantalum The solution to this dilemma is to slow down the oscillator output capacitors. The output capacitor is normally cho- when the FB pin voltage is abnormally low thereby indicat- sen by its effective series resistance (ESR), because this ing some sort of short-circuit condition. Oscillator fre- is what determines output ripple voltage. The ESR range quency is unaffected until FB voltage drops to about 2/3 of for typical LT1956 applications using a tantalum output its normal value. Below this point the oscillator frequency capacitor is 0.05W to 0.2W . A typical output capacitor is an decreases roughly linearly down to a limit of about 100kHz. AVX type TPS, 100m F at 10V, with a guaranteed ESR less This lower oscillator frequency during short-circuit condi- than 0.1W . This is a “D” size surface mount solid tantalum tions can then maintain control with the effective mini- capacitor. TPS capacitors are specially constructed and mum on time. Even with frequency foldback, however, the tested for low ESR, so they give the lowest ESR for a given LT1956 will not survive a permanent output short at the volume. The value in microfarads is not particularly criti- absolute maximum voltage rating of V = 60V; this is IN cal, and values from 22m F to greater than 500m F work well, defined solely by internal semiconductor junction break- but you cannot cheat mother nature on ESR. If you find a down effects. tiny 22m F solid tantalum capacitor, it will have high ESR, For the maximum input voltage allowed during an output and output ripple voltage will be terrible. Table 3 shows short to ground, the previous equation defining minimum some typical solid tantalum surface mount capacitors. on-time can be used. Assuming V (D1 catch diode) = F Table 3. Surface Mount Solid Tantalum Capacitor ESR 0.63V at 1A (short-circuit current is folded back to typical and Ripple Current switch current limit • 0.5), I (inductor) • DCR = 1A • 0.128 E CASE SIZE ESR (MAX, W ) RIPPLE CURRENT (A) = 0.128V (L␣=␣CDRH6D28-22), typical f = 100kHz (folded AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1 back) and typical minimum on-time = 300ns, the maxi- D CASE SIZE mum allowable input voltage during an output short to AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1 ground is typically: C CASE SIZE V = (0.63V + 0.128V)/(100kHz • 300ns) AVX TPS 0.2 (typ) 0.5 (typ) IN V = 25V IN(MAX) Unlike the input capacitor, RMS ripple current in the Increasing the DCR of the inductor will increase the maxi- output capacitor is normally low enough that ripple cur- mum V allowed during an output short to ground but will rent rating is not an issue. The current waveform is IN also drop overall efficiency during normal operation. triangular with a typical value of 125mA . The formula RMS to calculate this is: Every time the converter wakes up from shutdown or undervoltage lockout to begin switching, the output 1956f 13

LT1956/LT1956-5 APPLICATIOU S IU FORW ATIOU Output capacitor ripple current (RMS): is to prevent excessive ripple causing dips below the mini- mum operating voltage resulting in erratic operation. ( )( ) 0.29 V V –V IRIPPLE(RMS) = O(U)T( )(IN ) OUT Depending on how the LT1956 circuit is powered up you L f V IN may need to check for input voltage transients. Ceramic Capacitors The input voltage transients may be caused by input voltage steps or by connecting the LT1956 converter to an Ceramic capacitors are generally chosen for their good already powered up source such as a wall adapter. The high frequency operation, small size and very low ESR sudden application of input voltage will cause a large (effective series resistance). Their low ESR reduces surge of current in the input leads that will store energy in output ripple voltage but also removes a useful zero in the the parasitic inductance of the leads. This energy will loop frequency response, common to tantalum capaci- cause the input voltage to swing above the DC level of input tors. To compensate for this, a resistor R can be placed C power source and it may exceed the maximum voltage in series with the V compensation capacitor C . Care C C rating of input capacitor and LT1956. must be taken however, since this resistor sets the high frequency gain of the error amplifier, including the gain The easiest way to suppress input voltage transients is to at the switching frequency. If the gain of the error add a small aluminum electrolytic capacitor in parallel with amplifier is high enough at the switching frequency, the low ESR input capacitor. The selected capacitor needs output ripple voltage (although smaller for a ceramic to have the right amount of ESR in order to critically output capacitor) may still affect the proper operation of dampen the resonant circuit formed by the input lead the regulator. A filter capacitor C in parallel with the inductance and the input capacitor. The typical values of F R /C network is suggested to control possible ripple at ESR will fall in the range of 0.5W to 2W and capacitance will C C the V pin. The LT1956 can be stabilized for V = 5V at fall in the range of 5m F to 50m F. C OUT 1A using a 22m F ceramic output capacitor and VC com- If tantalum capacitors are used, values in the 22m F to ponent values of CC = 4700pF, RC␣=␣4.7k and CF = 220pF. 470m F range are generally needed to minimize ESR and meet ripple current and surge ratings. Care should be INPUT CAPACITOR taken to ensure the ripple and surge ratings are not exceeded. The AVX TPS and Kemet T495 series are surge Step-down regulators draw current from the input supply rated. AVX recommends derating capacitor operating in pulses. The rise and fall times of these pulses are very voltage by 2 for high surge applications. fast. The input capacitor is required to reduce the voltage ripple this causes at the input of LT1956 and force the switching current into a tight local loop, thereby minimiz- CATCH DIODE ing EMI. The RMS ripple current can be calculated from: Highest efficiency operation requires the use of a Schottky type diode. DC switching losses are minimized due to its ( ) V V –V I C =I OUT IN OUT low forward voltage drop, and AC behavior is benign due RIPPLE(RMS) IN OUT V 2 to its lack of a significant reverse recovery time. Schottky IN diodes are generally available with reverse voltage ratings Ceramic capacitors are ideal for input bypassing. At 500kHz of up to 60V and even 100V, and are price competitive with switching frequency, the energy storage requirement of other types. the input capacitor suggests that values in the range of The use of so-called “ultrafast” recovery diodes is gener- 2.2m F to 10m F are suitable for most applications. If opera- ally not recommended. When operating in continuous tion is required close to the minimum input required by the mode, the reverse recovery time exhibited by “ultrafast” output of the LT1956, a larger value may be required. This diodes will result in a slingshot type effect. The power 1956f 14

LT1956/LT1956-5 APPLICATIOU S IU FORW ATIOU internal switch will ramp up V current into the diode in an A 0.1m F boost capacitor is recommended for most appli- IN attempt to get it to recover. Then, when the diode has cations. Almost any type of film or ceramic capacitor is finally turned off, some tens of nanoseconds later, the V suitable, but the ESR should be <1W to ensure it can be SW node voltage ramps up at an extremely high dV/dt, per- fully recharged during the off time of the switch. The haps 5 to even 10V/ns! With real world lead inductances, capacitor value is derived from worst-case conditions of the V node can easily overshoot the V rail. This can 1800ns on time, 42mA boost current and 0.7V discharge SW IN result in poor RFI behavior and if the overshoot is severe ripple. The boost capacitor value could be reduced under enough, damage the IC itself. less demanding conditions, but this will not improve circuit operation or efficiency. Under low input voltage and The suggested catch diode (D1) is an International Recti- low load conditions, a higher value capacitor will reduce fier 10MQ060N Schottky. It is rated at 1.5A average discharge ripple and improve start-up operation. forward current and 60V reverse voltage. Typical forward voltage is 0.63V at 1A. The diode conducts current only during switch off time. Peak reverse voltage is equal to SHUTDOWN FUNCTION AND UNDERVOLTAGE regulator input voltage. Average forward current in normal LOCKOUT operation can be calculated from: Figure 4 shows how to add undervoltage lockout (UVLO) I = I (1 – DC) to the LT1956. Typically, UVLO is used in situations where D(AVG) OUT the input supply is current limited, or has a relatively high This formula will not yield values higher than 1.5A with source resistance. A switching regulator draws constant maximum load current of 1.5A. The only reason to power from the source, so source current increases as consider a larger diode is the worst-case condition of a source voltage drops. This looks like a negative resistance high input voltage and shorted output. With a shorted load to the source and can cause the source to current limit condition, diode current will increase to a typical value of or latch low under low source voltage conditions. UVLO 2A, determined by peak switch current limit. This is safe prevents the regulator from operating at source voltages for short periods of time, but it would be prudent to check where these problems might occur. with the diode manufacturer if continuous operation under these conditions must be tolerated. Threshold voltage for lockout is about 2.38V. A 5.5m A bias current flows out of the pin at this threshold. The internally generated current is used to force a default high state on BOOST␣PIN␣ the shutdown pin if the pin is left open. When low shut- For most applications, the boost components are a 0.1m F down current is not an issue, the error due to this current capacitor and an MMSD914TI diode. The anode is typi- can be minimized by making R 10k or less. If shutdown LO cally connected to the regulated output voltage to generate current is an issue, R can be raised to 100k, but the error LO a voltage approximately VOUT above VIN to drive the output due to initial bias current and changes with temperature stage. However, the output stage discharges the boost should be considered. capacitor during the on time of the switch. The output ( ) driver requires at least 3V of headroom throughout this R =10k to 100k 25k suggested LO period to keep the switch fully saturated. If the output ( ) R V - 2.38V vboolotasgt seu isp lpelsys i sth uasne 3dV. T, hite is b roeocsotm dimodeen dceadn tbhea ct oannn aeltcetrenda ttoe RHI= 2.3L8OV- INRLO(5.5m A) the input, although, care must be taken to prevent the 2· V = minimum input voltage IN V boost voltage from exceeding the BOOST pin absolute IN maximum rating. The additional voltage across the switch Keep the connections from the resistors to the shutdown driver also increases power loss, reducing efficiency. If pin short and make sure that interplane or surface capaci- available, an independent supply can be used with a local tance to the switching nodes are minimized. If high bypass capacitor. resistor values are used, the shutdown pin should be 1956f 15

LT1956/LT1956-5 APPLICATIOU S IU FORW ATIOU RFB LT1956 L1 INPUT IN 2.38V + VSW OUTPUT STANDBY RHI 5.5m A – + SHDN C1 + TOTAL SHUTDOWN C2 RLO 0.4V – GND 1956 F04 Figure 4. Undervoltage Lockout bypassed with a 1000pF capacitor to prevent coupling SYNCHRONIZING problems from the switch node. If hysteresis is desired in The SYNC input must pass from a logic level low, through the undervoltage lockout point, a resistor R can be FB the maximum synchronization threshold with a duty cycle added to the output node. Resistor values can be calcu- between 10% and 90%. The input can be driven directly lated from: from a logic level output. The synchronizing range is equal [ ( ) ] R V - 2.38 D V/V + 1 +D V to initial operating frequency up to 700kHz. This means LO IN OUT RHI = 2.38- R (5.5m A) that minimum practical sync frequency is equal to the LO worst-case high self-oscillating frequency (570kHz), not ( )( ) R = R V /D V the typical operating frequency of 500kHz. Caution should FB HI OUT be used when synchronizing above 662kHz because at 25k suggested for R LO higher sync frequencies the amplitude of the internal slope V = Input voltage at which switching stops as input IN compensation used to prevent subharmonic switching is voltage descends to trip level reduced. This type of subharmonic switching only occurs D V = Hysteresis in input voltage level at input voltages less than twice output voltage. Higher Example: output voltage is 5V, switching is to stop if input inductor values will tend to eliminate this problem. See voltage drops below 12V and should not restart unless Frequency Compensation section for a discussion of an input rises back to 13.5V. D V is therefore 1.5V and entirely different cause of subharmonic switching before V ␣=␣12V. Let R = 25k. assuming that the cause is insufficient slope compensa- IN LO tion. Application Note 19 has more details on the theory [ ( ) ] 25k 12- 2.38 1.5/5+ 1 +1.5 of slope compensation. RHI = 2.38–25k(5.5m A) At power-up, when VC is being clamped by the FB pin (see Figure 2, Q2), the sync function is disabled. This allows the ( ) frequency foldback to operate in the shorted output con- 25k 10.41 = =116k dition. During normal operation, switching frequency is 2.24 ( ) controlled by the internal oscillator until the FB pin reaches RFB=116k 5/1.5 =387k 0.8V, after which the SYNC pin becomes operational. If no synchronization is required, this pin should be connected to ground. 1956f 16

LT1956/LT1956-5 APPLICATIOU S IU FORW ATIOU LAYOUT CONSIDERATIONS LT1956 L1 As with all high frequency switchers, when considering 5V layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. For maximum HIGH FREQUENCY efficiency, switch rise and fall times are typically in the VIN C3 CIRCULATING D1 C1 LOAD PATH nanosecond range. To prevent noise both radiated and conducted, the high speed switching current path, shown in Figure 5, must be kept as short as possible. This is 1956 F05 implemented in the suggested layout of Figure 6. Shorten- ing this path will also reduce the parasitic trace inductance Figure 5. High Speed Switching Path of approximately 25nH/inch. At switch off, this parasitic The V and FB components should be kept as far away as C inductance produces a flyback spike across the LT1956 possible from the switch and boost nodes. The LT1956 switch. When operating at higher currents and input pinout has been designed to aid in this. The ground for voltages, with poor layout, this spike can generate volt- these components should be separated from the switch ages across the LT1956 that may exceed its absolute current path. Failure to do so will result in poor stability or maximum rating. A ground plane should always be used subharmonic like oscillation. under the switcher circuitry to prevent interplane coupling and overall noise. CONNECT TO GROUND PLANE GND L1 FOR THE FE PACKAGE, C1 SOLDER THE EXPOSED MINIMIZE LT1956 PAD TO THE COPPER C3-D1 LOOP D2 GROUND PLANE UNDERNEATH THE DEVICE VOUT GND D1 C2 GND GND SHDN KELVIN SENSE SW VOUT VIN SYNC LT1956 C3 FB R2 BOOST VC R1 CFB BIAS CF VIN GND GND RC KEEP FB AND VC COMPONENTS PLACE FEEDTHROUGH AROUND CC AHWIGAHY C FURRORME NHTIG CHO MFRPEOQNUEENNTCSY, GROUND PINS (4 CORNERS) FOR GOOD THERMAL CONDUCTIVITY 1956 F06 Figure 6. Suggested Layout 1956f 17

LT1956/LT1956-5 APPLICATIOU S IU FORW ATIOU Board layout also has a significant effect on thermal resis- a >100MHz oscilloscope must be used, and waveforms tance. For the GN package, Pins 1, 8, 9 and 16, GND, are should be observed on the leads of the package. This a continuous copper plate that runs under the LT1956 die. switch off spike will also cause the SW node to go below This is the best thermal path for heat out of the package. ground. The LT1956 has special circuitry inside which Reducing the thermal resistance from Pins 1, 8, 9 and 16 mitigates this problem, but negative voltages over 0.8V onto the board will reduce die temperature and increase lasting longer than 10ns should be avoided. Note that the power capability of the LT1956. This is achieved by 100MHz oscilloscopes are barely fast enough to see the providing as much copper area as possible around these details of the falling edge overshoot in Figure 7. pins. Adding multiple solder filled feedthroughs under and A second, much lower frequency ringing is seen during around these four corner pins to the ground plane will also switch off time if load current is low enough to allow the help. Similar treatment to the catch diode and coil termi- inductor current to fall to zero during part of the switch off nations will reduce any additional heating effects. For the time (see Figure 8). Switch and diode capacitance resonate FE package, the exposed pad should be soldered to the with the inductor to form damped ringing at 1MHz to 10 copper ground plane underneath the device. MHz. This ringing is not harmful to the regulator and it has not been shown to contribute significantly to EMI. Any PARASITIC RESONANCE attempt to damp it with a resistive snubber will degrade efficiency. Resonance or “ringing” may sometimes be seen on the switch node (see Figure 7). Very high frequency ringing following switch rise time is caused by switch/diode/input THERMAL CALCULATIONS capacitor lead inductance and diode capacitance. Schot- Power dissipation in the LT1956 chip comes from four tky diodes have very high “Q” junction capacitance that sources: switch DC loss, switch AC loss, boost circuit can ring for many cycles when excited at high frequency. current, and input quiescent current. The following formu- If total lead length for the input capacitor, diode and switch las show how to calculate each of these losses. These path is 1 inch, the inductance will be approximately 25nH. formulas assume continuous mode operation, so they At switch off, this will produce a spike across the NPN should not be used for calculating efficiency at light load output device in addition to the input voltage. At higher currents. currents this spike can be in the order of 10V to 20V or higher with a poor layout, potentially exceeding the abso- Switch loss: lute max switch voltage. The path around switch, catch ( )2( ) diode and input capacitor must be kept as short as P =RSW IOUT VOUT +t (1/2)(I )(V )(f) SW EFF OUT IN possible to ensure reliable operation. When looking at this, VIN SW RISE SW FALL 10V/DIV SVWOLITTCAHG ENODE 2V/DIV INDUCTOR 0.2A/DIV CURRENT AT IOUT = 0.1A VIN = 25V 500ns/DIV 1956 F08 50ns/DIV 1956 F07 VL O=U 1T 5=m 5HV Figure 7. Switch Node Resonance Figure 8. Discontinuous Mode Ringing 1956f 18

LT1956/LT1956-5 APPLICATIOU S IU FORW ATIOU Boost current loss: (V )(V –V )(I ) P = F IN OUT LOAD DIODE V 2(I /36) VIN P = OUT OUT BOOST V V = Forward voltage of diode (assume 0.63V at 1A) IN F Quiescent current loss: (0.63)(12 –5)(1) P = =0.37W P =V (0.0015)+V (0.003) DIODE 12 Q IN OUT Notice that the catch diode’s forward voltage contributes R = switch resistance (» 0.3) hot SW a significant loss in the overall system efficiency. A larger, t = effective switch current/voltage overlap time EFF low V diode can improve efficiency by several percent. = (t + t + t + t ) F r f Ir If t = (V /1.2)ns P = (I )(L ) r IN INDUCTOR LOAD DCR t = (V /1.7)ns L = inductor DC resistance (assume 0.1W ) f IN DCR t = t = (I /0.05)ns P = (1)(0.1) = 0.1W Ir If OUT INDUCTOR f = switch frequency Typical thermal resistance of the board is 10(cid:176) C/W. Taking Example: with V = 12V, V = 5V and I = 1A: the catch diode and inductor power dissipation into ac- IN OUT OUT count and using the example calculations for LT1956 dis- P = (0.3)(1)2(5)+(57•10- 9)(1/2)(1)(12)(500•103) sipation, the LT1956 die temperature will be estimated as: SW 12 T = T + (q • P ) + (10 • [P + P ]) J A JA TOT DIODE INDUCTOR =0.125+0.171=0.296W With the GN16 package (q = 85(cid:176) C/W), at an ambient JA ( )2( ) temperature of 70(cid:176) C: 5 1/36 P = =0.058W BOOST 12 T = 70 + (85 • 0.39) + (10 • 0.47) = 108(cid:176) C J ( ) ( ) PQ =12 0.0015 +5 0.003 =0.033W With the TSSOP package (q = 45(cid:176) C/W) at an ambient JA temperature of 70(cid:176) C: Total power dissipation in the IC is given by: T = 70 + (45 • 0.37) + (10 • 0.47) = 91(cid:176) C J P = P + P + P TOT SW BOOST Q = 0.296W + 0.058W + 0.033W = 0.39W Die temperature can peak for certain combinations of V , V and load current. While higher V gives greater IN OUT IN Thermal resistance for the LT1956 packages is influenced switch AC losses, quiescent and catch diode losses, a by the presence of internal or backside planes. lower V may generate greater losses due to switch DC IN SSOP (GN16) Package: With a full plane under the GN16 losses. In general, the maximum and minimum V levels IN package, thermal resistance will be about 85(cid:176) C/W. should be checked with maximum typical load current for calculation of the LT1956 die temperature. If a more TSSOP (Exposed Pad) Package: With a full plane under the accurate die temperature is required, a measurement of TSSOP package, thermal resistance (q ) will be about JA the SYNC pin resistance (to GND) can be used. The SYNC 45(cid:176) C/W. pin resistance can be measured by forcing a voltage no To calculate die temperature, use the proper thermal greater than 0.5V at the pin and monitoring the pin resistance (q ) number for the desired package an add in current over temperature in a oven. This should be done JA worst-case ambient temperature: with minimal device power (low V and no switching IN T = T + (q • P ) [VC = 0V]) in order to calibrate SYNC pin resistance with J A JA TOT ambient (oven) temperature. When estimating ambient, remember the nearby catch diode and inductor will also be dissipating power. 1956f 19

LT1956/LT1956-5 APPLICATIOU S IU FORW ATIOU Note: Some of the internal power dissipation in the IC, due A zener, D4, placed in series with D2 (see Figure 9), drops to BOOST pin voltage, can be transferred outside of the IC voltage to C2. to reduce junction temperature by increasing the voltage Example: drop in the path of the boost diode D2 (see Figure 9). This reduction of junction temperature inside the IC will allow The BOOST pin power dissipation for a 20V input to 12V higher ambient temperature operation for a given set of output conversion at 1A is given by: conditions. BOOST pin circuitry dissipates power given by: ( ) 12• 1/36 •12 ( ) P = =0.2W BOOST P (BOOST Pin)= VOUT • ISW /36 •VC2 20 DISS V IN If a 7V zener is placed in series with D2, then power dissipation becomes: Typically, V (the boost voltage across the capacitor C2) C2 equals VOUT. This is because diodes D1 and D2 can be ( ) 12• 1/36 •5 considered almost equal, where: P = =0.084W BOOST 20 V = V – V (D2) – [–V (D1)] = V . C2 OUT F F OUT For an FE package with thermal resistance of 45(cid:176) C/W, Hence, the equation for boost circuitry power dissipation ambient temperature savings would be: given in the previous Thermal Calculations section, is stated as: T (ambient) savings = 0.116W • 45(cid:176) C/W = 5(cid:176) C ( ) For a GN package with thermal resistance of 85(cid:176) C/W, V • I /36 •V P = OUT SW OUT ambient temperature savings would be: DISS(BOOST) V IN T (ambient) savings = 0.116W • 85(cid:176) C/W = 10(cid:176) C Here it can be seen that boost power dissipation increases The 7V zener should be sized for excess of 0.116W as the square of V . It is possible, however, to reduce OUT operation. The tolerances of the zener should be consid- V below V to save power dissipation by increasing C2 OUT ered to ensure minimum V exceeds 3.3V + V . BOOST DROOP the voltage drop in the path of D2. Care should be taken that V does not fall below the minimum 3.3V boost C2 D2 D4 voltage required for full saturation of the internal power switch. For output voltages of 5V, V is approximately 5V. C2 During switch turn on, VC2 will fall as the boost capacitor D2 C2 is discharged by the BOOST pin. In the previous BOOST Pin section, the value of C2 was designed for a 0.7V droop BOOST C2 L1 in VC2 (= VDROOP). Hence, an output voltage as low as 4V VIN VIN LT1956 SW VOUT would still allow the minimum 3.3V for the boost function C3 SHDN BIAS + using the C2 capacitor calculated. R1 C1 SYNC FB If a target output voltage of 12V is required, however, an GND VC D1 R2 excess of 8V is placed across the boost capacitor which is not required for the boost function but still dissipates RC CF additional power. CC What is required is a voltage drop in the path of D2 to achieve minimal power dissipation while still maintaining 1956 F09 minimum boost voltage across C2. Figure 9. BOOST Pin, Diode Selection 1956f 20

LT1956/LT1956-5 APPLICATIOU S IU FORW ATIOU Input Voltage vs Operating Frequency Considerations circuits, read the Layout Considerations section first. Common layout errors that appear as stability problems The absolute maximum input supply voltage for the LT1956 are distant placement of input decoupling capacitor and/ is specified at 60V. This is based on internal semiconduc- or catch diode, and connecting the V compensation to a tor junction breakdown effects. The practical maximum C ground track carrying significant switch current. In addi- input supply voltage for the LT1956 may be less than 60V tion, the theoretical analysis considers only first order due to internal power dissipation or switch minimum on non-ideal component behavior. For these reasons, it is time considerations. important that a final stability check is made with produc- For the extreme case of an output short-circuit fault to tion layout and components. ground, see the section Short-Circuit Considerations. The LT1956 uses current mode control. This alleviates A detailed theoretical basis for estimating internal power many of the phase shift problems associated with the dissipation is given in the Thermal Calculations section. inductor. The basic regulator loop is shown in Figure 10. This will allow a first pass check of whether an application’s The LT1956 can be considered as two g blocks, the error m maximum input voltage requirement is suitable for the amplifier and the power stage. LT1956. Be aware that these calculations are for DC input Figure 11 shows the overall loop response. At the V pin, voltages and that input voltage transients as high as 60V C the frequency compensation components used are: are possible if the resulting increase in internal power R = 2.2k, C = 0.022m F and C = 220pF. The output dissipation is of insufficient time duration to raise die C C F capacitor used is a 100m F, 10V tantalum capacitor with temperature significantly. For the FE package, this means typical ESR of 100mW . high voltage transients on the order of hundreds of milli- seconds are possible. If LT1956 (FE package) thermal The ESR of the tantalum output capacitor provides a useful calculations show power dissipation is not suitable for the zero in the loop frequency response for maintaining stabil- given application, the LT1766 (FE package) is a recom- ity. This ESR, however, contributes significantly to the mended alternative since it is identical to the LT1956 but ripple voltage at the output (see Output Ripple Voltage in runs cooler at 200kHz. the Applications Information section). It is possible to reduce capacitor size and output ripple voltage by replac- Switch minimum on time is the other factor that may limit ing the tantalum output capacitor with a ceramic output the maximum operational input voltage for the LT1956 if capacitor because of its very low ESR. The zero provided pulse-skipping behavior is not allowed. For the LT1956, by the tantalum output capacitor must now be reinserted pulse-skipping may occur for V /(V + V ) ratios > 4. IN OUT F back into the loop. Alternatively, there may be cases (V = Schottky diode D1 forward voltage drop, Figure 5.) F where, even with the tantalum output capacitor, an addi- If the LT1766 is used, the ratio increases to 10. Pulse- tional zero is required in the loop to increase phase margin skipping is the regulator’s way of missing switch pulses to for improved transient response. maintain output voltage regulation. Although an increase in output ripple voltage can occur during pulse-skipping, A zero can be added into the loop by placing a resistor (R ) C a ceramic output capacitor can be used to keep ripple at the V pin in series with the compensation capacitor, C , C C voltage to a minimum (see output ripple voltage compari- or by placing a capacitor (C ) between the output and the FB son for tantalum vs ceramic output capacitors, Figure 3). FB pin. When using R , the maximum value has two limitations. C FREQUENCY COMPENSATION First, the combination of output capacitor ESR and R may C Before starting on the theoretical analysis of frequency stop the loop rolling off altogether. Second, if the loop gain response, the following should be remembered—the worse is not rolled off sufficiently at the switching frequency, the board layout, the more difficult the circuit will be to output ripple will perturb the VC pin enough to cause stabilize. This is true of almost all high frequency analog unstable duty cycle switching similar to subharmonic 1956f 21

LT1956/LT1956-5 APPLICATIOU S IU FORW ATIOU 80 180 LT1956 CURRENT MODE SW 60 150 POWER STAGE OUTPUT GAIN gm = 2mho AMERPRLIOFRIER CFB R1 40 120P 2R00Ok200g0mµ m=h–+o 1.22FVB RLOAD + TEASNRTALUM CERAEMSILC GAIN (dB) 200 PHASE 9600 HASE (DEG) C1 C1 GND VC –20 30 R2 –40 0 RC CF 10 100 1k 10k 100k 1M CC VIN = 12V FREQUENCY (HRz)C = 2.2k 1956 F11 1956 F10 VOUT = 5V CC = 22nF ILOAD = 500mA CF = 220pF COUT = 100µF, 10V, 0.1Ω Figure 10. Model for Loop Response Figure 11. Overall Loop Response oscillations. If needed, an additional capacitor (C ) can be CONVERTER WITH BACKUP OUTPUT REGULATOR F added across the R /C network from the V pin to ground C C C In systems with a primary and backup supply, for ex- to further suppress V ripple voltage. C ample, a battery powered device with a wall adapter input, With a tantalum output capacitor, the LT1956 already the output of the LT1956 can be held up by the backup includes a resistor (R ) and filter capacitor (C ) at the V supply with the LT1956 input disconnected. In this condi- C F C pin (see Figures 10 and 11) to compensate the loop over tion, the SW pin will source current into the V pin. If the IN the entire V range (to allow for stable pulse skipping for SHDN pin is held at ground, only the shut down current of IN high V -to-V ratios ‡ 4). A ceramic output capacitor 25m A will be pulled via the SW pin from the second supply. IN OUT can still be used with a simple adjustment to the resistor With the SHDN pin floating, the LT1956 will consume its R for stable operation (see Ceramic Capacitors section quiescent operating current of 1.5mA. The V pin will also C IN for stabilizing LT1956). If additional phase margin is source current to any other components connected to the required, a capacitor (C ) can be inserted between the input line. If this load is greater than 10mA or the input FB output and FB pin but care must be taken for high output could be shorted to ground, a series Schottky diode must voltage applications. Sudden shorts to the output can be added, as shown in Figure 12. With these safeguards, create unacceptably large negative transients on the FB the output can be held at voltages up to the V absolute IN pin. maximum rating. For V -to-V ratios < 4, higher loop bandwidths are IN OUT possible by readjusting the frequency compensation com- BUCK CONVERTER WITH ADJUSTABLE SOFT-START ponents at the V pin. C Large capacitive loads or high input voltages can cause When checking loop stability, the circuit should be oper- high input currents at start-up. Figure 13 shows a circuit ated over the application’s full voltage, current and tem- that limits the dv/dt of the output at start-up, controlling perature range. Proper loop compensation may be obtained the capacitor charge rate. The buck converter is a typical by empirical methods as described in Application Notes 19 configuration with the addition of R3, R4, CSS and Q1. and 76. As the output starts to rise, Q1 turns on, regulating switch 1956f 22

LT1956/LT1956-5 APPLICATIOU S IU FORW ATIOU MMSD914TI C2 D3 0.1m F L1 10MQ060N BOOST 18m H REMOVABLE INPUT VIN LT1956 SW R3 5V, 1A ALTERNATE BIAS 54k SUPPLY R1 SHDN 15.4k R4 SGYNNDC VCFB D101MQ060N R4.299k + C110010VµF 25k C2.32m F RC CF 2.2k 220pF CC 0.022µF 1956 F12 Figure 12. Dual Source Supply with 25m A Reverse Leakage D2 MMSD914TI C2 0.1m F L1 BOOST BIAS 18m H OUTPUT INPUT 12V C3 VIN SW + 51VA 2.2m F D1 C1 R1 CERAMIC LT1956 100m F 15.4k SHDN FB SYNC GND VC R2 4.99k CSS R3 15nF Q1 2k RC CF 2.2k 220pF 1766 F13 CC R4 0.022µF 47k Figure 13. Buck Converter with Adjustable Soft-Start current via the V pin to maintain a constant dv/dt at the The ramp is linear and rise times in the order of 100ms are C output. Output rise time is controlled by the current possible. Since the circuit is voltage controlled, the ramp through C defined by R4 and Q1’s V . Once the output rate is unaffected by load characteristics and maximum SS BE is in regulation, Q1 turns off and the circuit operates output current is unchanged. Variants of this circuit can be normally. R3 is transient protection for the base of Q1. used for sequencing multiple regulator outputs. ( )( )( ) R4 C V SS OUT RiseTime= DUAL POLARITY OUTPUT CONVERTER V BE The circuit in Figure 14a generates both positive and Using the values shown in Figure 10, negative 5V outputs with all components under 3mm ( )( ) height. The topology for the 5V output is a standard buck ( ) 47•103 15•10–9 5 converter. The –5V output uses a second inductor L2, RiseTime = =5ms 0.7 diode D3 and output capacitor C6. The capacitor C4 1956f 23

LT1956/LT1956-5 APPLICATIOU S IU FORW ATIOU D2 MMSD914TI C2 0.1m F L1* VIN BOOST 15m H (TR9AVN STIOE N12TVS VIN SW V5VOUT1** LT1956 TO 36V) SHDN R1 C3 15.4k + C5 2.2m F SYNC FB 10m F 50V 6.3V CERAMIC GND VC R2 CER 4.99k D1 RC CF B0540W 2.2k 220pF CC 3300pF GND 10Cµ4F + C6 + *SUMIDA CDRH4D28-150 6.3V L2* 10m F **SEE FIGURE 14c FOR VOUT1, VOUT2 CER 6.3V CER LOAD CURRENT RELATIONSHIP VOUT2**† † IF LOAD CAN GO TO ZERO, AN OPTIONAL –5V PRELOAD OF 500Ω CAN BE D3 USED TO IMPROVE REGULATION B0540W 1956 F14a Figure 14a. Dual Polarity Output Converter 500 5.30 100 A)450 5.25 90 VOUT1 LOAD CURRENT T (m400 5.20 V75O0UmT1A LOAD CURRENT 80 750mA N MUM LOAD CURRE322300550000 |V| (V)OUT245555.....9010155500 V50O0UmT1A LOAV2D5O0U CmTU1A RLROEANDT CURRENT FFICIENCY (%) 64570000 VOUT1 L2O5A0Dm CAURRENT AXI150 4.90 E 30 M UT2100 4.85 20 VO 50 4.80 10 0 4.75 0 0 200 400 600 800 0 100 200 300 400 500 600 0 100 200 300 400 500 VOUT1 LOAD CURRENT (mA) VOUT2 LOAD CURRENT (mA) VOUT2 LOAD CURRENT (mA) 1956 F15b 1956 F14c 1956 F14d Figure 14b. V (–5V) Maximum Figure 14c. V (–5V) Output Figure 14d. Dual Polarity Output OUT2 OUT2 Allowable Load Current vs V Voltage vs Load Current Converter Efficiency OUT1 (5V) Load Current couples energy to L2 and ensures equal voltages across transformer becomes available to provide a better height/ L2 and L1 during steady state. Instead of using a trans- cost solution, refer to the dual output SEPIC circuit de- former for L1 and L2, uncoupled inductors were used scription in Design Note 100 for correct transformer because they require less height than a single transformer, connection. can be placed separately in the circuit layout for optimized During switch on-time, in steady state, the voltage across space savings and reduce overall cost. This is true even both L1 and L2 is positive and equal; with energy (and when the uncoupled inductors are sized (twice the value of current) ramping up in each inductor. The current in L2 is inductance of the transformer) in order to keep ripple provided by the coupling capacitor C4. During switch off- current comparable to the transformer solution. If a single time, current ramps downward in each inductor. The 1956f 24

LT1956/LT1956-5 APPLICATIOU S IU FORW ATIOU current in L2 and C4 flows via the catch diode D3, charging Ø (V )(V ) ø IN OUT the negative output capacitor C6. If the negative output is ºŒ IP – 2(V +V )(f)(L)ßœ (VOUT)(VIN –0.3) not loaded enough, it can go severely unregulated (be- I = OUT IN MAX (V +V –0.3)(V +V ) come more negative). Figure 14b shows the maximum OUT IN OUT F allowable –5V output load current (vs load current on the I = maximum rated switch current P 5V output) that will maintain the –5V output within 3% V = minimum input voltage IN tolerance. Figure 14c shows the –5V output voltage regu- V = output voltage OUT lation vs its own load current when plotted for three V = catch diode forward voltage F separate load currents on the 5V output. The efficiency of 0.3 = switch voltage drop at 1.5A the dual output converter circuit shown in Figure 14a is given in Figure 14d. Example: with VIN(MIN) = 5.5V, VOUT = 12V, L = 15m H, V = 0.63V, I = 1.5A: I = 0.36A. F P MAX POSITIVE-TO-NEGATIVE CONVERTER INDUCTOR VALUE The circuit in Figure 15 is a positive-to-negative topology using a grounded inductor. It differs from the standard The criteria for choosing the inductor is typically based on approach in the way the IC chip derives its feedback signal ensuring that peak switch current rating is not exceeded. because the LT1956 accepts only positive feedback sig- This gives the lowest value of inductance that can be used, nals. The ground pin must be tied to the regulated negative but in some cases (lower output load currents) it may give output. A resistor divider to the FB pin, then provides the a value that creates unnecessarily high output ripple proper feedback voltage for the chip. voltage. The following equation can be used to calculate maximum The difficulty in calculating the minimum inductor size load current for the positive-to-negative converter: needed is that you must first decide whether the switcher will be in continuous or discontinuous mode at the critical D2 point where switch current reaches 1.5A. The first step is MMSD914TI to use the following formula to calculate the load current C2 above which the switcher must use continuous mode. If 0.1m F L1* BOOST 7m H your load current is less than this, use the discontinuous 1V2IVN VIN SW mode formula to calculate minimum inductor needed. If LT1956 R1 C3 36.5k load current is higher, use the continuous mode formula. 2.2µF FB 25V GND VC Output current where continuous mode is needed: + C1 D1 CC 10MQO60N 100m F CF RC R4.212k 20OV UTTAPNUTT** ICONT > 4(V +V (VIN)()V2(IP+)2V +V ) IN OUT IN OUT F –12V, 0.25A *INCREASE L1 TO 10m H OR 18m H FOR HIGHER CURRENT APPLICATIONS. 1956 F15 Minimum inductor discontinuous mode: SEE APPLICATIONS INFORMATION **MAXIMUM LOAD CURRENT DEPENDS ON MINIMUM INPUT VOLTAGE AND INDUCTOR SIZE. SEE APPLICATIONS INFORMATION 2(V )(I ) L = OUT OUT MIN Figure 15. Positive-to-Negative Converter (f)(I )2 P 1956f 25

LT1956/LT1956-5 PACKAGE DESCRIPTIOU Minimum inductor continuous mode: The output capacitor ripple current for the positive-to- negative converter is similar to that for a typical buck (V )(V ) L = IN OUT regulator—it is a triangular waveform with peak-to-peak MIN Ø (cid:230) (V +V )(cid:246) ø value equal to the peak-to-peak triangular waveform of the 2(f)(V +V )Œ I –I (cid:231) 1+ OUT F (cid:247) œ IN OUT º P OUTŁ V ł ß inductor. The low output ripple design in Figure 14 places IN the input capacitor between V and the regulated negative IN For a 12V to –12V converter using the LT1956 with peak output. This placement of the input capacitor significantly switch current of 1.5A and a catch diode of 0.63V: reduces the size required for the output capacitor (versus placing the input capacitor between V and ground). IN (12)2(1.5)2 I > =0.370A The peak-to-peak ripple current in both the inductor and CONT 4(12+12)(12+12+0.63) output capacitor (assuming continuous mode) is: For a load current of 0.25A, this says that discontinuous DC•V mode can be used and the minimum inductor needed is I = IN P-P found from: f•L V +V 2(12)(0.25) DC=DutyCycle= OUT F L = =5.3m H V +V +V MIN (500•103)(1.5)2 OUT IN F I I (RMS)= P-P In practice, the inductor should be increased by about COUT 12 30% over the calculated minimum to handle losses and variations in value. This suggests a minimum inductor of The output ripple voltage for this configuration is as low as 7m H for this application. the typical buck regulator based predominantly on the inductor’s triangular peak-to-peak ripple current and the Ripple Current in the Input and Output Capacitors ESR of the chosen capacitor (see Output Ripple Voltage in Positive-to-negative converters have high ripple current Applications Information). in the input capacitor. For long capacitor lifetime, the RMS value of this current must be less than the high Diode Current frequency ripple current rating of the capacitor. The Average diode current is equal to load current. Peak diode following formula will give an approximate value for RMS current will be considerably higher. ripple current. This formula assumes continuous mode Peak diode current: and large inductor value. Small inductors will give some- what higher ripple current, especially in discontinuous ContinuousMode= mode. The exact formulas are very complex and appear (V +V ) (V )(V ) in Application Note 44, pages 29 and 30. For our pur- I IN OUT + IN OUT poses here I have simply added a fudge factor (ff). The OUT V 2(L)(f)(V +V ) IN IN OUT value for ff is about 1.2 for higher load currents and L 2(I )(V ) ‡ 15m H. It increases to about 2.0 for smaller inductors at DiscontinuousMode= OUT OUT (L)(f) lower load currents. Keep in mind that during start-up and output overloads, V CapacitorIRMS =(ff)(IOUT) OUT average diode current may be much higher than with V IN normal loads. Care should be used if diodes rated less than ff = 1.2 to 2.0 1A are used, especially if continuous overload conditions must be tolerated. 1956f 26

LT1956/LT1956-5 PACKAGE DESCRIPTIOU FE Package 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation BB 4.90 – 5.10* 3.58 (.193 – .201) (.141) 3.58 (.141) 16 151413121110 9 6.60 – 0.10 2.94 4.50 – 0.10 (.116) SEE NOTE 4 2.94 6.40 0.45 – 0.05 (.116) BSC 1.05 – 0.10 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 1.10 4.30 – 4.50* (.0433) (.169 – .177) MAX 0° – 8° 0.45 – 0.75 0.65 0.09 – 0.20 (.018 – .030) (.0256) 0.05 – 0.15 (.0036 – .0079) BSC (.002 – .006) 0.195 – 0.30 (.0077 – .0118) FE16 (BB) TSSOP 0203 NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE MILLIMETERS FOR EXPOSED PAD ATTACHMENT 2. DIMENSIONS ARE IN (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH 3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE 1956f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. 27 However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LT1956/LT1956-5 PACKAGE DESCRIPTIOU GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .045 – .005 .189 – .196* (4.801 – 4.978) .009 (0.229) 16 15 14 13 12 11 109 REF .254 MIN .150 – .165 .229 – .244 .150 – .157** (5.817 – 6.198) (3.810 – 3.988) .0165 – .0015 .0250 TYP RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 .015 – .004 · 45(cid:176) .053 – .068 .004 – .0098 (0.38 – 0.10) (1.351 – 1.727) (0.102 – 0.249) .007 – .0098 0° – 8° TYP (0.178 – 0.249) .016 – .050 .008 – .012 .0250 (0.406 – 1.270) (0.203 – 0.305) (0.635) NOTE: BSC 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE GN16 (SSOP) 0502 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1074/LT1076/ Step-Down Switching Regulators Up to 64V Input, 100kHz, 5A and 2A LT1076HV LT1082 1A High Voltage/Efficiency Switching Voltage Regulator Up to 75V Input, 60kHz Operation LT1370 High Efficiency DC/DC Converter Up to 42V, 6A, 500kHz Switch LT1371 High Efficiency DC/DC Converter Up to 35V, 3A, 500kHz Switch LT1375/LT1376 1.5A, 500kHz Step-Down Switching Regulators Operation Up to 25V Input, Synchronizable (LT1375), N8, S8, S16 LT1616 600mA, 1.4MHz Step-Down Switching Regulator 3.6V to 25V V , 6-Lead ThinSOTTM IN LT1676 Wide Input Range, High Efficiency, Step-Down Switching Regulator 7.4V to 60V V , 100kHz Operation, 700mA Internal Switch, S8 IN LT1765 Monolithic 3A, 1.25MHz Step-Down Regulator V : 3V to 25V; V = 1.2V; S8, TSSOP-16E IN REF Exposed Pad LT1766 Wide Input Range, High Efficiency, Step-Down Switching Regulator 5.5V to 60V Input, 200kHz Operation, 1.5A Internal Switch, TSSOP-16E LT1767 Monolithic 1.5A, 1.25MHz Step-Down Regulator V : 3V to 25V; V = 1.2V; MS8 IN REF LT1776 Wide Input Range, High Efficiency, Step-Down Switching Regulator Up to 7.4V to 60V, 200kHz Operation, 700mA Internal Switch, TSSOP-16E LT1777 Low Noise Buck Regulator Operation Up to 48V, Controlled Voltage and Current Slew Rates, S16 ThinSOT is a trademark of Linear Technology Corporation. 1956f 28 Linear Technology Corporation LT/TP 0303 2K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 l FAX: (408) 434-0507 l www.linear.com ª LINEAR TECHNOLOGY CORPORATION 2001