LT1218/LT1219 Precision Rail-to-Rail Input and Output Op Amps FEATURES DESCRIPTIOUN n Rail-to-Rail Input and Output The LT®1218/LT1219 are bipolar op amps which combine n 90m V V for V = V– to V+ rail-to-rail input and output operation with precision speci- OS(MAX) CM n High Common Mode Rejection Ratio: 97dB Min fications. Unlike other rail-to-rail amplifiers, the LT1218/ n C-LoadTM Stable Version (LT1219) LT1219’s input offset voltage is a low 90m V across the n High A : 500V/mV Minimum Driving 10kW Load entire rail-to-rail input range, not just a portion of it. Using VOL n Wide Supply Range: a patented technique, both input stages of the LT1218/ 2V to – 15V (LT1218/LT1219) LT1219 are trimmed: one at the negative supply and the 2V to – 5V (LT1218L/LT1219L) other at the positive supply. The resulting common mode n Shutdown Mode: I < 30m A rejection of 97dB minimum is much better than other rail- S n Low Supply Current: 420m A Max to-rail input op amps. A minimum open-loop gain of 500V/mV into a 10k load virtually eliminates all gain error. n Low Input Bias Current: 18nA Typical n 300kHz Gain-Bandwidth Product (LT1218) The LT1218 has conventional compensation which n Slew Rate: 0.10V/m s (LT1218) assures stability for capacitive loads of 1000pF or less. The LT1219 has compensation that requires the use of a APPLICATIOUNS 0.1m F output capacitor, which improves the amplifier’s supply rejection and reduces output impedance at high frequencies. The output capacitor’s filtering action also n Driving A/D Converters reduces high frequency noise, which is beneficial when n Test Equipment Amplifiers driving A/D converters. n MUX Amplifiers High and low voltage versions of the devices are offered. Operation is specified for 3V, 5V and – 5V supplies for the LT1218L/LT1219L and 3V, 5V and – 15V for the LT1218/ , LTC and LT are registered trademarks of Linear Technology Corporation. LT1219. C-Load is a trademark of Linear Technology Corporation. TYPICAL APPLICATIONU MUX Amplifier Voltage Follower Input to Output Error 5V (cid:13) 10 VS = 5V(cid:13) VIN1 + ANVO =L O1(cid:13)AD LT1218L VOUT – SHDN mV) 1.0 ( ‰R O R 5V ‰ER 0.1 M0A.0X5 EVR ≤R OVIRN =≤ 141.80VµV(cid:13) VIN2 + LT1218L – MAXIMUM IN (cid:13) SHDN TO OUT ERROR(cid:13) 0.01 = 110µV FOR (cid:13) 0 1 2 3 4 5 0.05V ≤ VIN ≤ 4.8V(cid:13) 0.05 4.95 INPUT(cid:13) RL = 10k INPUT VOLTAGE (V) LT1218/19 • TA02 SELECT 74HCO4 1218/19 • TA01 1

LT1218/LT1219 ABSOLUTE WMAXIWMUWM RATINUGS PACKAGE/ORDER IUNFORWMATIOUN Supply Voltage ORDER PART LT1218/LT1219.................................................– 18V NUMBER LT1218L/LT1219L...............................................– 8V TOP VIEW Input Current......................................................– 15mA LT1218CN8 Output Short-Circuit Duration (Note 1).........Continuous VOS TRIM(cid:13) 1(cid:13) 8(cid:13) VOS TRIM(cid:13) LT1218CS8 –IN(cid:13) 2(cid:13) 7(cid:13) V+(cid:13) LT1218LCN8 Operating Temperature Range................ –40(cid:176) C to 85(cid:176) C +IN(cid:13) 3(cid:13) 6(cid:13) OUT(cid:13) LT1218LCS8 Specified Temperature Range (Note 3)... –40(cid:176) C to 85(cid:176) C V– 4 5(cid:13) SHDN LT1219CN8 Storage Temperature Range................. –65(cid:176) C to 150(cid:176) C (cid:13) LT1219CS8 Junction Temperature...........................................150(cid:176) C N8 PACKAGE(cid:13) S8 PACKAGE(cid:13) 8-LEAD PDIP 8-LEAD PLASTIC SO LT1219LCN8 Lead Temperature (Soldering, 10 sec)..................300(cid:176) C LT1219LCS8 TJMAX = 150(cid:176)C, q JA = 130(cid:176)C/W (N8) TJMAX = 150(cid:176)C, q JA = 190(cid:176)C/W (S8) S8 PART MARKING 1218 1219 1218L 1219L Consult factory for Industrial and Military grades. ELECTRICAL CHARACTERISTICS T = 25(cid:176) C, V = 5V, 0V; V = 3V, 0V; V = V = half supply, V = V+, unless otherwise noted. A S S CM O SHDN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Offset Voltage V = V+ 25 90 m V OS CM V = V– 25 90 m V CM D V Input Offset Voltage Shift V = V– to V+ 15 70 m V OS CM I Input Bias Current V = V+ 30 70 nA B CM V = V– –70 –18 nA CM D I Input Bias Current Shift V = V– to V+ 50 140 nA B CM I Input Offset Current V = V+ 5 18 nA OS CM V = V– 2 18 nA CM D I Input Offset Current Shift V = V– to V+ 5 18 nA OS CM e Input Noise Voltage Density f = 1kHz 33 nV/(cid:214) Hz n i Input Noise Current Density f = 1kHz 0.09 pA/(cid:214) Hz n A Large-Signal Voltage Gain V = 5V, V = 50mV to 4.8V, R = 10k 250 1000 V/mV VOL S O L V = 3V, V = 50mV to 2.8V, R = 10k 200 750 V/mV S O L CMRR Common Mode Rejection Ratio V = 5V, V = V– to V+ 97 110 dB S CM V = 3V, V = V– to V+ 92 106 dB S CM PSRR Power Supply Rejection Ratio V = 2.3V to 12V, V = 0V, V = 0.5V 90 100 dB S CM O V Output Voltage Swing LOW No Load 4 12 mV OL I = 0.5mA 45 90 mV SINK I = 2.5mA 120 240 mV SINK V Output Voltage Swing HIGH No Load V+ – 0.012 V+ – 0.003 V OH I = 0.5mA V+ – 0.130 V+ – 0.065 V SOURCE I = 2.5mA V+ – 0.400 V+ – 0.210 V SOURCE I Short-Circuit Current V = 5V 5 10 mA SC S V = 3V 4 7 mA S I Supply Current V = 5V 370 420 m A S S V = 3V 370 410 m A S Positive Supply Current, SHDN V = 5V, V = 0V 9 30 m A S SHDN V = 3V, V = 0V 6 20 m A S SHDN 2

LT1218/LT1219 ELECTRICAL CHARACTERISTICS T = 25(cid:176) C, V = 5V, 0V; V = 3V, 0V; V = V = half supply, V = V+, unless otherwise noted. A S S CM O SHDN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SR Slew Rate (LT1218/LT1218L) A = –1 0.10 V/m s V (LT1219/LT1219L) A = –1 0.05 V/m s V GBW Gain Bandwidth Product (LT1218/LT1218L) A = 1000 0.30 MHz V (LT1219/LT1219L) A = 1000 0.15 MHz V 0(cid:176) C £ T £ 70(cid:176) C, V = 5V, 0V; V = 3V, 0V; V = V = half supply, V = V+, unless otherwise noted. A S S CM O SHDN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Offset Voltage V = V+ l 75 200 m V OS CM V = V– l 75 200 m V CM V TC Input Offset Drift (Note 2) l 1 3 m V/(cid:176) C OS D V Input Offset Voltage Shift V = V– to V+ l 25 80 m V OS CM I Input Bias Current V = V+ l 30 75 nA B CM V = V– l –75 –18 nA CM D I Input Bias Current Shift V = V– to V+ l 50 150 nA B CM I Input Offset Current V = V+ l 5 25 nA OS CM V = V– l 3 25 nA CM D I Input Offset Current Shift V = V– to V+ l 5 25 nA OS CM A Large-Signal Voltage Gain V = 5V, V = 50mV to 4.8V, R = 10k l 250 1000 V/mV VOL S O L V = 3V, V = 50mV to 2.8V, R = 10k l 150 750 V/mV S O L CMRR Common Mode Rejection Ratio V = 5V, V = V– to V+ l 96 104 dB S CM V = 3V, V = V– to V+ l 91 106 dB S CM PSRR Power Supply Rejection Ratio V = 2.3V to 12V, V = 0V, V = 0.5V l 88 100 dB S CM O V Output Voltage Swing LOW No Load l 4 14 mV OL I = 0.5mA l 45 100 mV SINK I = 2.5mA l 130 290 mV SINK V Output Voltage Swing HIGH No Load l V+ – 0.014 V+ – 0.004 V OH I = 0.5mA l V+ – 0.150 V+ – 0.075 V SOURCE I = 2.5mA l V+ – 0.480 V+ – 0.240 V SOURCE I Short-Circuit Current V = 5V l 4 7 mA SC S V = 3V l 3 6 mA S I Supply Current V = 5V l 370 485 m A S S V = 3V l 370 475 m A S Positive Supply Current, SHDN V = 5V, V = 0V l 9 36 m A S SHDN V = 3V, V = 0V l 6 26 m A S SHDN –40(cid:176) C £ T £ 85(cid:176) C, V = 5V, 0V; V = 3V, 0V; V = V = half supply, V = V+, unless otherwise noted. (Note 3) A S S CM O SHDN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Offset Voltage V = V+ – 0.15 l 400 m V OS CM V = V– + 0.15 l 400 m V CM V TC Input Offset Drift (Note 2) l 1 4 m V/(cid:176) C OS D V Input Offset Voltage Shift V = V+ – 0.15 to V– + 0.15 l 30 105 m V OS CM I Input Bias Current V = V+ – 0.15 l 80 nA B CM V = V– + 0.15 l –80 nA CM D I Input Bias Current Shift V = V+ – 0.15 to V– + 0.15 l 160 nA B CM I Input Offset Current V = V+ – 0.15 l 40 nA OS CM V = V– + 0.15 l 40 nA CM D I Input Offset Current Shift V = V+ – 0.15 to V– + 0.15 l 40 nA OS CM 3

LT1218/LT1219 ELECTRICAL CHARACTERISTICS –40(cid:176) C £ T £ 85(cid:176) C, V = 5V, 0V; V = 3V, 0V; V = V = half supply, V = V+, unless otherwise noted. (Note 3) A S S CM O SHDN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS A Large-Signal Voltage Gain V = 5V, V = 50mV to 4.8V, R = 10k l 150 500 V/mV VOL S O L V = 3V, V = 50mV to 2.8V, R = 10k l 100 500 V/mV S O L CMRR Common Mode Rejection Ratio V = 5V, V = V+ – 0.15 to V– + 0.15 l 93 102 dB S CM V = 3V, V = V+ – 0.15 to V– + 0.15 l 88 100 dB S CM PSRR Power Supply Rejection Ratio V = 2.3V to 12V, V = 0V, V = 0.5V l 86 100 dB S CM O V Output Voltage Swing LOW No Load l 5 15 mV OL I = 0.5mA l 50 105 mV SINK I = 2.5mA l 130 300 mV SINK V Output Voltage Swing HIGH No Load l V+ – 0.015 V+ – 0.004 mV OH I = 0.5mA l V+ – 0.160 V+ – 0.070 mV SOURCE I = 2.5mA l V+ – 0.500 V+ – 0.250 mV SOURCE I Short-Circuit Current V = 5V l 4 7 mA SC S V = 3V l 3 7 mA S I Supply Current V = 5V l 410 505 m A S S V = 3V l 400 495 m A S Positive Supply Current, SHDN V = 5V, V = 0V l 15 50 m A S SHDN V = 3V, V = 0V l 13 40 m A S SHDN LT1218L/LT1219L only; T = 25(cid:176) C, V = – 5V, V = 0V, V = 0V, V = 5V, unless otherwise noted. A S CM O SHDN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Offset Voltage V = V+ 35 140 m V OS CM V = V– 35 140 m V CM D V Input Offset Voltage Shift V = V– to V+ 20 70 m V OS CM I Input Bias Current V = V+ 30 70 nA B CM V = V– –70 –18 nA CM D I Input Bias Current Shift V = V– to V+ 50 140 nA B CM I Input Offset Current V = V+ 5 18 nA OS CM V = V– 2 18 nA CM D I Input Offset Current Shift V = V– to V+ 5 18 nA OS CM A Large-Signal Voltage Gain V = –4.7V to 4.7V, R = 10k 500 2800 V/mV VOL O L V = –4.5V to 4.5V, R = 2k 300 1300 V/mV O L CMRR Common Mode Rejection Ratio V = V– to V+ 103 114 dB CM V Output Voltage Swing LOW No Load V– + 0.004 V– + 0.012 V OL I = 0.5mA V– + 0.045 V– + 0.090 V SINK I = 5mA V– + 0.180 V– + 0.525 V SINK V Output Voltage Swing HIGH No Load V+ – 0.012 V+ – 0.003 V OH I = 0.5mA V+ – 0.130 V+ – 0.065 V SOURCE I = 5mA V+ – 0.800 V+ – 0.350 V SOURCE I Short-Circuit Current 6 12 mA SC I Supply Current 400 430 m A S Positive Supply Current, SHDN V = 0V 10 40 m A SHDN SR Slew Rate (LT1218/LT1218L) A = –1, R = Open, V = – 3.5V 0.06 0.10 V/m s V L O (LT1219/LT1219L) A = –1, R = Open, V = – 3.5V 0.03 0.05 V/m s V L O GBW Gain-Bandwidth Product (LT1218/LT1218L) A = 1000 0.2 0.30 MHz V (LT1219/LT1219L) A = 1000 0.1 0.15 MHz V 4

LT1218/LT1219 ELECTRICAL CHARACTERISTICS LT1218L/LT1219L only; 0(cid:176) C £ T £ 70(cid:176) C, V = – 5V, V = 0V, V = 0V, V = 5V, unless otherwise noted. A S CM O SHDN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Offset Voltage V = V+ l 100 250 m V OS CM V = V– l 100 250 m V CM D V Input Offset Voltage Shift V = V– to V+ l 30 90 m V OS CM I Input Bias Current V = V+ l 30 75 nA B CM V = V– l –75 –18 nA CM D I Input Bias Current V = V– to V+ l 50 150 nA B CM I Input Offset Current V = V+ l 5 25 nA OS CM V = V– l 3 25 nA CM D I Input Offset Current Shift V = V– to V+ l 5 20 nA OS CM A Large-Signal Voltage Gain V = –4.7V to 4.7V, R = 10k l 375 2800 V/mV VOL O L V = –4.5V to 4.5V, R = 2k l 275 1300 V/mV O L CMRR Common Mode Rejection Ratio V = V– to V+ l 100 110 dB CM V Output Voltage Swing LOW No Load l V– + 0.004 V– + 0.014 V OL I = 0.5mA l V– + 0.045 V– + 0.100 V SINK I = 5mA l V– + 0.200 V– + 0.580 V SINK V Output Voltage Swing HIGH No Load l V+ – 0.014 V+ – 0.004 V OH I = 0.5mA l V+ – 0.150 V+ – 0.075 V SOURCE I = 5mA l V+ – 0.920 V+ – 0.450 V SOURCE I Short-Circuit Current l 5 10 mA SC I Supply Current l 400 495 m A S Positive Supply Current, SHDN V = 0V l 11 54 m A SHDN LT1218L, LT1219L only; –40(cid:176) C £ T £ 85(cid:176) C, V = – 5V; V = 0V, V = 0V, V = 5V, unless otherwise noted. (Note 3) A S CM O SHDN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Offset Voltage V = V+ – 0.15 l 125 500 m V OS CM V = V– + 0.15 l 125 500 m V CM D V Input Offset Voltage Shift V = V+ – 0.15 to V– + 0.15 l 35 120 m V OS CM I Input Bias Current V = V+ – 0.15 l 80 nA B CM V = V– + 0.15 l –80 nA CM D I Input Bias Current V = V+ – 0.15 to V– + 0.15 l 160 nA B CM I Input Offset Current Shift V = V+ – 0.15 l 40 nA OS CM V = V– + 0.15 l 40 nA CM D I Input Offset Current Shift V = V+ – 0.15 to V– + 0.15 l 40 nA OS CM A Large-Signal Voltage Gain V = –4.7V to 4.7V, R = 10k l 300 2000 V/mV VOL O L V = –4.5V to 4.5V, R = 2k l 200 600 V/mV O L CMRR Common Mode Rejection Ratio V = V+ – 0.15 to V– + 0.15 l 98 109 dB CM V Output Voltage Swing LOW No Load l V– + 0.005 V– + 0.015 V OL I = 0.5mA l V– + 0.050 V– + 0.105 V SINK I = 2.5mA l V– + 0.200 V– + 0.620 V SINK V Output Voltage Swing HIGH No Load l V+ – 0.015 V+ – 0.004 V OH I = 0.5mA l V+ – 0.160 V+ – 0.070 V SOURCE I = 2.5mA l V+ – 1.000 V+ – 0.400 V SOURCE I Short-Circuit Current l 5 10 mA SC I Supply Current l 420 525 m A S Positive Supply Current, SHDN V = 0V l 18 60 m A SHDN 5

LT1218/LT1219 ELECTRICAL CHARACTERISTICS LT1218/LT1219 only; T = 25(cid:176) C, V = – 15V, V = 0V, V = 0V, V = 15V, unless otherwise noted. A S CM O SHDN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Offset Voltage V = V+ 85 200 m V OS CM V = V– 85 200 m V CM D V Input Offset Voltage Shift V = V– to V+ 30 70 m V OS CM I Input Bias Current V = V+ 30 70 nA B CM V = V– –70 –18 nA CM D I Input Bias Current V = V– to V+ 50 140 nA B CM I Input Offset Current V = V+ 5 18 nA OS CM V = V– 2 18 nA CM D I Input Offset Current Shift V = V– to V+ 5 18 nA OS CM A Large-Signal Voltage Gain V = –14.7V to 14.7V, R = 10k 1000 4000 V/mV VOL O L V = –10V to 10V, R = 2k 500 2000 V/mV O L CMRR Common Mode Rejection Ratio V = V– to V+ 113 120 dB CM PSRR Power Supply Rejection Ratio V = – 5V to – 15V 100 110 dB S V Output Voltage Swing LOW No Load V– + 0.004 V– + 0.012 V OL I = 0.5mA V– + 0.045 V– + 0.090 V SINK I = 5mA V– + 0.270 V– + 0.525 V SINK V Output Voltage Swing HIGH No Load V+ – 0.012 V+ – 0.003 V OH I = 0.5mA V+ – 0.130 V+ – 0.065 V SOURCE I = 5mA V+ – 0.800 V+ – 0.580 V SOURCE I Short-Circuit Current 10 20 mA SC I Supply Current 425 550 m A S Positive Supply Current, SHDN V = 0V 15 40 m A SHDN SR Slew Rate (LT1218/LT1218L) A = –1 0.10 V/m s V (LT1219/LT1219L A = –1 0.05 V/m s V GBW Gain Bandwidth Product (LT1218/LT1218L) A = 1000 0.28 MHz V (LT1219/LT1219L) A = 1000 0.15 MHz V LT1218/LT1219 only; 0(cid:176) C £ T £ 70(cid:176) C, V = – 15V, V = 0V, V = 0V, V = 15V, unless otherwise noted. A S CM O SHDN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Offset Voltage V = V+ l 120 300 m V OS CM V = V– l 120 300 m V CM D V Input Offset Voltage Shift V = V– to V+ l 50 105 m V OS CM I Input Bias Current V = V+ l 30 75 nA B CM V = V– l –75 –18 nA CM D I Input Bias Current V = V– to V+ l 50 150 nA B CM I Input Offset Current V = V+ l 5 25 nA OS CM V = V– l 3 25 nA CM D I Input Offset Current Shift V = V– to V+ l 5 20 nA OS CM A Large-Signal Voltage Gain V = –14.7V to 14.7V, R = 10k l 750 3000 V/mV VOL O L V = –10V to 10V, R = 2k l 500 1500 V/mV O L CMRR Common Mode Rejection Ratio V = V– to V+ l 109 114 dB CM PSRR Power Supply Rejection Ratio V = – 5V to – 15V l 97 110 dB S V Output Voltage Swing LOW No Load l V– + 0.004 V– + 0.014 V OL I = 0.5mA l V– + 0.045 V– + 0.100 V SINK I = 5mA l V– + 0.310 V– + 0.580 V SINK V Output Voltage Swing HIGH No Load l V+ – 0.014 V+ – 0.003 V OH I = 0.5mA l V+ – 0.150 V+ – 0.075 V SOURCE I = 5mA l V+ – 0.920 V+ – 0.700 V SOURCE 6

LT1218/LT1219 ELECTRICAL CHARACTERISTICS LT1218/LT1219 only; 0(cid:176) C £ T £ 70(cid:176) C, V = – 15V, V = 0V, V = 0V, V = 15V, unless otherwise noted. A S CM O SHDN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I Short-Circuit Current l 8 17 mA SC I Supply Current l 450 600 m A S Positive Supply Current, SHDN V = 0V l 20 54 m A SHDN LT1218, LT1219 only; –40(cid:176) C £ T £ 85(cid:176) C, V = – 15V; V = 0V = V = 0V, V = 15V, unless otherwise noted. (Note 3) A S CM O SHDN SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V Input Offset Voltage V = V+ – 0.15 l 150 600 m V OS CM V = V– + 0.15 l 150 600 m V CM D V Input Offset Voltage Shift V = V+ – 0.15 to V– + 0.15 l 50 165 m V OS CM I Input Bias Current V = V+ – 0.15 l 80 nA B CM V = V– + 0.15 l –80 nA CM D I Input Bias Current V = V+ – 0.15 to V– + 0.15 l 160 nA B CM I Input Offset Current V = V+ – 0.15 l 40 nA OS CM V = V– + 0.15 l 40 nA CM D I Input Offset Current Shift V = V+ – 0.15 to V– + 0.15 l 40 nA OS CM A Large-Signal Voltage Gain V = –14.7V to 14.7V, R = 10k l 500 3000 V/mV VOL O L V = –10V to 10V, R = 2k l 400 1000 V/mV O L CMRR Common Mode Rejection Ratio V = V+ – 0.15 to V– + 0.15 l 105 114 dB CM PSRR Power Supply Rejection Ratio V = – 5V to – 15V l 96 110 dB S V Output Voltage Swing LOW No Load l V– + 0.005 V– + 0.015 V OL I = 0.5mA l V– + 0.050 V– + 0.105 V SINK I = 2.5mA l V– + 0.200 V– + 0.620 V SINK V Output Voltage Swing HIGH No Load l V+ – 0.015 V+ – 0.004 V OH I = 0.5mA l V+ – 0.160 V+ – 0.070 V SOURCE I = 2.5mA l V+ – 1.000 V+ – 0.400 V SOURCE I Short-Circuit Current l 5 14 mA SC I Supply Current l 650 m A S Positive Supply Current, SHDN V = 0V l 60 m A SHDN The l denotes specifications which apply over the full operating Note 2: This parameter is not 100% tested. temperature range. Note 3: The LT1218/LT1219 are designed, characterized and expected to Note 1: A heat sink may be required to keep the junction temperature meet these extended temperature limits, but are not tested at –40(cid:176) C and below the Absolute Maximum Rating when the output is shorted 85(cid:176) C. Guaranteed I grade part are available: consult factory. indefinitely. 7

LT1218/LT1219 TYPICAL PERFORWMANUCE CHARACTERISTICS V Distribution, V = 0V V Shift, V = 0V to 5V V Distribution, V = 5V OS CM OS CM OS CM 30(cid:13) 40(cid:13) 30(cid:13) VS = 5V, 0V(cid:13) VS = 5V, 0V(cid:13) VS = 5V, 0V(cid:13) 25(cid:13) VCM = 0V 35(cid:13) VCM = 0V TO 5V 25(cid:13) VCM = 5V %) %) 30(cid:13) %) NITS ( 20(cid:13) NITS ( 25(cid:13) NITS ( 20(cid:13) U U U OF 15(cid:13) OF 20(cid:13) OF 15(cid:13) RCENT 10(cid:13) RCENT 15(cid:13) RCENT 10(cid:13) PE PE 10(cid:13) PE 5(cid:13) 5(cid:13) 5(cid:13) 0 0 0 –100 (cid:13) –60 (cid:13) –20 (cid:13) 20 (cid:13) 60 (cid:13) 100 –100 (cid:13) –60 (cid:13) –20 (cid:13) 20 (cid:13) 60 (cid:13) 10(cid:13)0 –100 (cid:13) –60 (cid:13) –20 (cid:13) 20 (cid:13) 60 (cid:13) 100 INPUT OFFSET VOLTAGE (µV) INPUT OFFSET VOLTAGE (µV) INPUT OFFSET VOLTAGE (µV) LT1218/19 • TPC01 LT1218/19 • TPC02 LT1218/19 • TPC03 Input Bias Current vs Supply Current vs Temperature Minimum Supply Voltage Common Mode Voltage 500(cid:13) 200(cid:13) 50(cid:13) VS = – 15V V) TA = –40°C (cid:13) VS = 5V, 0V(cid:13)(cid:13) µSUPPLY CURRENT (A)432100000000(cid:13)(cid:13)(cid:13)(cid:13) VS = – 2.5V µHANGE IN OFFSET VOLTAGE (115050000(cid:13)(cid:13)(cid:13)(cid:13) TTAA == 2855°°CC INPUT BIAS CURRENT (nA)–22055(cid:13)(cid:13)(cid:13)(cid:13)(cid:13) TA T=A 2 T=5A ° 2=C5 –°C40°C TA = 85°C C (cid:13) 0 –50 –50 –40 –20 0 20 40 60 80 100 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –1 0 1 2 3 4 5 6 7 TEMPERATURE (°C) TOTAL SUPPLY VOLTAGE (V) COMMON MODE VOLTAGE (V) LT1218/19 • TPC04 LT1218/19 • TPC05 LT1218/19 • TPC06 Output Saturation Voltage vs Output Saturation Voltage vs 0.1Hz to 10Hz Output Load Current (Output Low) Load Current (Output High) Voltage Noise 10(cid:13) 10(cid:13) (cid:13) VS = 5V, 0V(cid:13) VS = 5V, 0V(cid:13) VS = – 2.5V(cid:13) (cid:13) (cid:13) (cid:13) (cid:13) VCM = 0V V) E (V) 1 E (V) 1 nV/DI G G 0 RATION VOLTA 0.1 TA = 25°C RATION VOLTA 0.1 TA = 25°C TA = 85T°AC = –40°C T VOLTAGE (40 SATU0.01 TA = 85°C TA = –40°C SATU0.01 OUTPU 0.001 0.001 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 TIME (1s/DIV) LOAD CURRENT (mA) LOAD CURRENT (mA) LT1218/19 • TPC07 LT1218/19 • TPC08 LT1218/19 • TPC09 8

LT1218/LT1219 TYPICAL PERFORWMANUCE CHARACTERISTICS Noise Voltage Spectrum Noise Current Spectrum 100(cid:13) 2.5(cid:13) 90(cid:13) (cid:13)VS = 5V, 0V(cid:13) (cid:13) (cid:13)VS = 5V, 0V(cid:13) 80(cid:13) 2.0(cid:13) Hz) 70(cid:13) Hz) (cid:13) (cid:214)V/ (cid:214)A/ AGE (n 6500(cid:13)(cid:13) OISE (p 1.5(cid:13)(cid:13) OISE VOLT 4300(cid:13)(cid:13) VVCCMM == 42V.5V URRENT N 1.0(cid:13)(cid:13) VCM = 2.5V N 20(cid:13) C 0.5(cid:13) 10(cid:13) (cid:13) VCM = 4V 0 0(cid:13) 1 10 100 1000 1 10 100 1000 (cid:13) FREQUENCY (Hz) FREQUENCY (Hz) LT1218/19 • TPC10 LT1218/19 • TPC11 LT1218 Gain and Phase LT1219 Gain and Phase Shift vs Frequency Shift vs Frequency 70(cid:13) 140(cid:13) 70(cid:13) 140(cid:13) 60(cid:13) VS = – 2.5V 120(cid:13) 60(cid:13) CVSL == 0– .21.µ5FV(cid:13) 120(cid:13) 50(cid:13) 100(cid:13) 50(cid:13) 100(cid:13) PHASE GE GAIN (dB) 432000(cid:13)(cid:13)(cid:13) GAIN 864000(cid:13)(cid:13)(cid:13) PHASE SHIFT GE GAIN (dB) 432000(cid:13)(cid:13)(cid:13) PHASE 864000(cid:13)(cid:13)(cid:13) PHASE SHIFT VOLTA 100(cid:13)(cid:13) 200(cid:13) (cid:13) (DEG) VOLTA 100(cid:13)(cid:13) 200(cid:13) (cid:13) (DEG) –10(cid:13) –20(cid:13) –10(cid:13) –20(cid:13) –20(cid:13) –40(cid:13) –20(cid:13) GAIN –40(cid:13) –30 –60 –30 –60 1 10 100 1000 10000 1 10 100 1000 10000 FREQUENCY (kHz) FREQUENCY (kHz) LT1218/19 • TPC12 LT1218/19 • TPC13 LT1218 Gain Bandwidth and LT1218 Common Mode Rejection LT1219 Power Supply Rejection Phase Margin vs Supply Voltage Ratio vs Frequency Ratio vs Frequency 400(cid:13) 80(cid:13) 100(cid:13) 100(cid:13) B) 90(cid:13) VS = – 2.5V B) 90(cid:13) VS = – 2.5V 350(cid:13) 70(cid:13) d d PHASE MARGIN O ( 80(cid:13) O ( 80(cid:13) Y (kHz) 320500(cid:13)(cid:13) GBW 6500(cid:13)(cid:13) PHASE M CTION RATI 7600(cid:13)(cid:13) CTION RATI 7600(cid:13)(cid:13) POSITIVE SUPPLY REQUENC 210500(cid:13)(cid:13) 4300(cid:13)(cid:13) ARGIN (D ODE REJE 5400(cid:13)(cid:13) PLY REJE 5400(cid:13)(cid:13) F 100(cid:13) 20(cid:13) EG) N M 30(cid:13) SUP 30(cid:13) NEGATIVE SUPPLY MO 20(cid:13) ER 20(cid:13) M W 50(cid:13) 10(cid:13) O 10(cid:13) O 10(cid:13) C P 0 0 0 0 0 5 10 15 20 25 30 1 10 100 1000 1 10 100 1000 SUPPLY VOLTAGE (V) FREQUENCY (kHz) FREQUENCY (kHz) LT1218/19 • TPC15 LT1218/19 • TPC16 LT1218/19 • TPC 9

LT1218/LT1219 TYPICAL PERFORWMANUCE CHARACTERISTICS LT1218 Power Supply Rejection LT1218 Closed Loop Output LT1219 Closed Loop Output Ratio vs Frequency Impedance vs Frequency Impedance vs Frequency 100(cid:13) 1000(cid:13) 1000(cid:13) dB) 90(cid:13) VS = – 2.5V (cid:13)(cid:13) VS = – 2.5V (cid:13)(cid:13) CVSL == 0– .21.µ5FV(cid:13) O ( 80(cid:13) REJECTION RATI 765000(cid:13)(cid:13)(cid:13) POSITIVE SUPPLY ΩMPEDANCE () 11000 AV = 10 AV = 1 ΩMPEDANCE () 11000 AV = 10 AV = 1 R SUPPLY 432000(cid:13)(cid:13)(cid:13) OUTPUT I 1.0 OUTPUT I 1.0 WE NEGATIVE SUPPLY O 10(cid:13) P 0 0.1 0.1 1 10 100 1000 0.1 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY (kHz) FREQUENCY (kHz) FREQUENCY (kHz) LT1218/19 • TPC17 LT1218/19 • TPC18 LT1218/19 • TPC19 LT1219 Overshoot vs Load LT1219 Overshoot vs Load LT1218 Capacitive Load Handling Current, V = – 2.5V Current, V = – 15V S S 80(cid:13) 70(cid:13) 70(cid:13) VS = – 2.5V VS = – 2.5V(cid:13) VS = – 15V(cid:13) 70(cid:13) 60(cid:13) AV = 1 60(cid:13) AV = 1 60(cid:13) CL = 0.22µF 50(cid:13) 50(cid:13) %) 50(cid:13) %) CL = 0.22µF %) RSHOOT ( 40(cid:13) AV = 1 RSHOOT ( 4300(cid:13)(cid:13) CL = 0.047µF RSHOOT ( 4300(cid:13)(cid:13) CL = 0.047µF OVE 30(cid:13) AV = 5 OVE OVE 20(cid:13) 20(cid:13) 20(cid:13) 10(cid:13) AV = 10 10(cid:13) CL = 0.1µF 10(cid:13) CL = 0.1µF 0 0 0 10 100 1000 10000 100000 –10 –5 0 5 10 –10 –5 0 5 10 CAPACITIVE LOAD (pF) LOAD CURRENT (mA) LOAD CURRENT (mA) LT1218/19 • TPC20 LT1218/19 • TPC21 LT1218/19 • TPC22 Open-Loop Gain, V = – 15V Input Offset Drift vs Time THD + Noise vs Frequency S 40(cid:13) 40(cid:13) 1 µOFFSET VOLTAGE CHANGE (V)––32112000000(cid:13)(cid:13)(cid:13)(cid:13)(cid:13)(cid:13) RL = 2kRL V=S 1 =0 k– 15V µHANGE IN OFFSET VOLTAGE (V)––32112000000(cid:13)(cid:13)(cid:13)(cid:13)(cid:13)(cid:13) VVSS == –– 21.55VV THD + NOISE (%)0.00.11 VRVSILN == = –1 201Vk.5PV-P(cid:13)(cid:13) AV = 1 AV = –1 –30(cid:13) C–30(cid:13) –40 –40 0.001 –20 –15 –10 –5 0 5 10 15 20 0 20 40 60 80 100 120140 160180200 0.01 0.1 1 10 OUTPUT VOLTAGE (V) TIME AFTER POWER-UP (SEC) FREQUENCY (kHz) LT1218/19 • TPC23 LT1218/19 • TPC24 LT1218/19 • TPC25 10

LT1218/LT1219 TYPICAL PERFORWMANUCE CHARACTERISTICS THD + Noise vs Small-Signal Response Large-Signal Response Peak-to-Peak Voltage V = – 15V V = – 15V S S 10(cid:13) f = 1kHz(cid:13) RL = 10k(cid:13) (ALL CURVES)(cid:13) 1(cid:13) (cid:13) %) NOISE ( 0.1(cid:13) AVSV == ––11.5V(cid:13) AVSV == –11.5V(cid:13) + THD VS = – 2.5V(cid:13) AV = 1 0.01(cid:13) VS = – 2.5V(cid:13) AV = 1 AV = 1 AV = –1 VS = – 15V VS = – 15V 0.001 LT1218/18 • TPC27 LT1218/18 • TPC28 0 1 2 3 4 5 INPUT VOLTAGE (PEAK-TO-PEAK) LT1218/19 • TPC26 APPLICATIOUNS INUFORWMATIOUN Rail-to-Rail Operation Q1/Q2 and an NPN stage Q3/Q4, which are active over different portions of the input common mode range. The LT1218/LT1219 differ from conventional op amps in Lateral devices are used in both input stages, eliminating the design of both the input and output stages. Figure 1 the need for clamps across the input pins. Each input stage shows a simplified schematic of the amplifier. The input is trimmed for offset voltage. A complementary output stage consists of two differential amplifiers, a PNP stage configuration (Q23 through Q26) is employed to create an TRIM V+ D6 D7 D4 D5 BIAS(cid:13) CONTROL I1 Q10 Q17 Q21 Q24 Q11 Q23 SHDN Q5 V– Q16 V– V– C1 OUT V– V+ V+ IN+ Q1 Q2 C2 D1 V+ CC V+ IN– Q3 Q4 D2 Q7 Q14 Q15 Q20 Q25 Q8 Q9 Q22 Q26 Q12 V+(cid:13) – 300mV Q6 Q13 Q18 Q19 D8 D3 D7 V– LT1218/19 • F01 Figure 1. LT1218 Simplified Schematic Diagram 11

LT1218/LT1219 APPLICATIOUNS INUFORWMATIOUN output stage with rail-to-rail swing. The amplifier is fabri- ure 1) turns on, pulling the output of the second stage low, cated on Linear Technology’s proprietary complementary which forces the output high. For input below the negative bipolar process, which ensures very similar DC and AC supply, diodes D1 and D2 turn on, overcoming the satu- characteristics for the output devices Q24 and Q26. ration of the input pair Q1/Q2. A simple comparator Q5 steers current from current When overdriven, the amplifier draws input current that source I between the two input stages. When the input exceeds the normal input bias current. Figures 2 and 3 1 common mode voltage V is near the negative supply, show typical input current as a function of input voltage. CM Q5 is reverse biased, and I becomes the tail current for the The input current must be less than 10mA for the phase 1 PNP differential pair Q1/Q2. At the other extreme, when reversal protection to work properly. When the amplifier is V is within about 1.3V from the positive supply, Q5 severely overdriven, an external resistor should be used to CM diverts I to the current mirror D3/Q6, which furnishes the limit the overdrive current. 1 tail current for the NPN differential pair Q3/Q4. 110 The collector currents of the two input pairs are combined 100 MEASURED AS A (cid:13) in the second stage, consisting of Q7 through Q11. Most 90 FOLLOWER A) + of the voltage gain in the amplifier is contained in this n 80 T ( – stage. Differential amplifier Q14/Q15 buffers the output of REN 70 T = 25°C R 60 the second stage, converting the output voltage to differ- U C ential currents. The differential currents pass through AS 50 T = 85°C T = –55°C BI 40 current mirrors D4/Q17 and D5/Q16, and are converted to PUT 30 T = 70°C N differential voltages by Q18 and Q19. These voltages are I 20 also buffered and applied to the output Darlington pairs 10 Q23/Q24 and Q25/Q26. Capacitors C1 and C2 form local 0 –500 –300 –100 VS 100 300 500 feedback loops around the output devices, lowering the COMMON MODE VOLTAGE RELATIVE TO(cid:13) POSITIVE SUPPLY (mV) output impedance at high frequencies. LT1218/19 • F02 Input Offset Voltage Figure 2. Input Bias Current vs Common Mode Voltage Since the amplifier has two input stages, the input offset 0 MEASURED AS A FOLLOWER voltage changes depending upon which stage is active. –10 + –20 The input offsets are random, but bounded voltages. A) – n–30 When the amplifier switches between stages, offset volt- T ( N–40 ages may go up, down or remain flat; but will not exceed RE T = –55°C T = 25°C T = 70°C R–50 U the guaranteed limits. This behavior is illustrated in three AS C–60 T = 85°C distribution plots of input offset voltage in the Typical BI–70 T Performance Characteristics section. PU–80 N I–90 –100 Overdrive Protection –110 Two circuits prevent the output from reversing polarity –800 –600 –400 (cid:13) –200 VS 200 COMMON MODE VOLTAGE RELATIVE TO(cid:13) when the input voltage exceeds the common mode range. NEGATIVE SUPPLY (mV) When the noninverting input exceeds the positive supply LT1218/19 • F03 by approximately 300mV, the clamp transistor Q12 (Fig- Figure 3. Input Bias Current vs Common Mode Voltage 12

LT1218/LT1219 APPLICATIOUNS INUFORWMATIOUN Shutdown The SHDN pin can be driven directly from CMOS logic if the logic and the LT1218/LT1219 are operated from the same The biasing of the LT1218/LT1219 is controlled by the supplies. For higher supply operation, an interface is SHDN pin. When the SHDN pin is low, the part is shut required. An easy way to interface between supplies is to down. In the shutdown mode, the output looks like a 40pF use open-drain logic, an example is shown in Figure 5. capacitor and the supply current is less than 30m A. The Because the SHDN pin is referenced to the positive supply, SHDN pin is referenced to the positive supply through an the logic used should have a breakdown voltage greater internal bias circuit (see Figure 1). The SHDN pin current than the positive supply. with the pin low is typically 3m A. 15V The switching time between the shutdown and active states is about 20m s, however, the total time to settle will LT1218/(cid:13) + LT1219 be greater by the slew time of the amplifier. For example, SHDN if the DC voltage at the amplifier output is 0V in shutdown – and –2V in the active mode, an additional 20m s is required. Figures 4a and 4b show the switching waveforms for a –15V sinusoidal and a –2V DC input to the LT1218. 5V SHDN 74C906 0V LT1218/19 • F05 VOUT Figure 5. Shutdown Interface Trim Pins Trim pins are provided for compatibility with other single SHDN op amps. Input offset voltage can be adjusted over a 0V – 2.3mV range with a 10k potentiometer. RL = 10V V+ VS = – 2.5V LT1218/19 • F04a Figure 4a 10k 1 2 – 8 7 0V LT1218/(cid:13) OUT LT1219 3 VOUT + 4 V– LT1218/19 • F06 Figure 6. Optional Offset Nulling SHDN Improved Supply Rejection in the LT1219 0V The LT1219 is a variation of the LT1218 offering greater RL = 10V supply rejection and lower high frequency output imped- VS = – 2.5V LT1218/19 • F04a Figure 4b ance. The LT1219 requires a 0.1m F load capacitance for 13

LT1218/LT1219 APPLICATIOUNS INUFORWMATIOUN compensation. The output capacitance forms a filter, positive supply. The LT1219 power supply rejection is which reduces pickup from the supply and lowers the about ten times greater than that of the LT1218 at 50kHz. output impedance. This additional filtering is helpful in Note the 5-to-1 scale change in the output voltage traces. mixed analog/digital systems with common supplies or The tolerance of the external compensation capacitor is systems employing switching supplies. Filtering also not critical. The plots of Overshoot vs Load Current in the reduces high frequency noise, which may be beneficial Typical Performance Characteristics section illustrate the when driving A/D converters. effect of a capacitive load. Figures 7a and 7b show the outputs of the LT1218/LT1219 perturbed by a 200mV 50kHz square wave added to the P-P V+ V+ (AC) (AC) VOUT VOUT LT1218/19 • F07a LT1218/19 • F07b Figure 7a. LT1218 Power Supply Rejection Test Figure 7b. LT1219 Power Supply Rejection Test TYPICAL APPLICATIONUS Buffer for 12-Bit A/D Converter High-Side Current Source 3V VCC RSENSE(cid:13) 0.2W 0.1m F 1m F 1k VIN + 0.0033m F LT1219 LT1004-1.2 – 1(cid:13) 8(cid:13) 100W Q1(cid:13) – 0.1m F VREF(cid:13) VCC(cid:13) RP(cid:13) LT1218 MTP23P06 2(cid:13) 7(cid:13) 10k + +IN(cid:13) CLK(cid:13) 3(cid:13) LTC1285 6(cid:13) ILOAD –IN(cid:13) DOUT(cid:13) TO m P 4 5 40k GND CS/SHDN 5V < VCC < 30V(cid:13) 0A < ILOAD < 1A AT VCC = 5V(cid:13) LT1218/19 • TA03 0mA < ILOAD < 160mA AT VCC = 30V(cid:13) Q2(cid:13) (cid:13) 2N4340 LT1218/19 • TA04 14

LT1218/LT1219 TYPICAL APPLICATIONUS Positive Supply Current Sense VCC R1(cid:13) 200Ω – RS(cid:13) 0.2Ω Q1(cid:13) LT1218 TP0610L + ILOAD VO ( ) R2(cid:13) LOAD VO = (ILOAD)(RS) R1 R202k(cid:13) = (ILOAD)(20Ω) 1218/19 • TA06 PACKAGE DESCRIPTIOUN Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510) 0.300 – 0.325(cid:13) 0.045 – 0.065(cid:13) 0.130 – 0.005(cid:13) 0.400*(cid:13) (7.620 – 8.255) (1.143 – 1.651) (3.302 – 0.127) (10.160)(cid:13) MAX 8 7 6 5 0.065(cid:13) (1.651)(cid:13) 0.009 – 0.015(cid:13) TYP (0.229 – 0.381) 0.005(cid:13) 0.125(cid:13) 0.255 – 0.015*(cid:13) (3.175)(cid:13) 0.015(cid:13) (6.477 – 0.381)(cid:13) (0.127)(cid:13) (0.325–+00..002155)(cid:13) MIN MI(cid:13)N(cid:13) (0M.3I8N0)(cid:13) (cid:13) +0.635(cid:13) 8.255–0.381 0.100 – 0.010(cid:13) 0.018 – 0.003(cid:13) 1 2 3 4 (2.540 – 0.254) (0.457 – 0.076) N8 0695 *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.(cid:13) MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197*(cid:13) (4.801 – 5.004) 8 7 6 5 0.010 – 0.020(cid:13) · 45(cid:176) 0.053 – 0.069(cid:13) 0.228 – 0.244(cid:13) (0.254 – 0.508) (5.791 – 6.197) (1.346 – 1.752) 0.008 – 0.010(cid:13) 0.004 – 0.010(cid:13) 0.150 – 0.157**(cid:13) (0.203 – 0.254) 0°– 8° TYP (0.101 – 0.254) (3.810 – 3.988) 0.016 – 0.050(cid:13) 0.014 – 0.019(cid:13) 0.050(cid:13) 0.406 – 1.270 (0.355 – 0.483) (1.270)(cid:13) *(cid:13)DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH (cid:13) TYP 1 2 3 4 SO8 0996 (cid:13)SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE(cid:13) **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD (cid:13) FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE(cid:13) (cid:13) (cid:13) 15 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LT1218/LT1219 TYPICAL APPLICATIONU 8-Channel, 12-Bit Data Acquisition System with Programmable Gain 5V 1m F 5V 1(cid:13) 16(cid:13) CH0(cid:13) V+(cid:13) 1m F 2(cid:13) CH1(cid:13) D(cid:13) 15(cid:13) + 3(cid:13) 14(cid:13) CH2(cid:13) V–(cid:13) LT1219L 5V 4(cid:13) 13(cid:13) INPUTS 5(cid:13) CH3(cid:13) DOUT(cid:13) 12(cid:13) – 0.1m F 6(cid:13) CH4(cid:13) DIN(cid:13) 11(cid:13) 17 16 15, 19 1m F 7(cid:13) CH5(cid:13) CS(cid:13) 10(cid:13) ADCIN VREF VCC CH6(cid:13) CLK(cid:13) 64R(cid:13) 20(cid:13) CH0(cid:13) 8 9 CH7 GND 32R(cid:13) 21(cid:13) CH1(cid:13) 10(cid:13) CSADC(cid:13) 16R(cid:13) 22(cid:13) CH2(cid:13) 6(cid:13) LTC1391(cid:13) CSMUX(cid:13) 8-CHANNEL(cid:13) 8R(cid:13) 23(cid:13) CH3(cid:13) 8-CHANNEL(cid:13) 12-BIT(cid:13) 5, 14(cid:13) + CLK(cid:13) MUX 4R(cid:13) 24(cid:13) CH4(cid:13) MUX SAMPLING(cid:13) 11(cid:13) m P/m C ADC DOUT(cid:13) 2R(cid:13) 1(cid:13) CH5(cid:13) 7 – DIN R(cid:13) 2(cid:13) CH6(cid:13) (cid:9)(cid:9) GAIN(cid:13) R 3 CH7 (cid:9) MUX (cid:13) LTC1598 C(cid:9) HANNEL(cid:9) GAIN(cid:13) 12(cid:13) 18 MUXOUT NC(cid:13) (cid:9)(cid:9) 01(cid:9)(cid:9)(cid:9)(cid:9) 12(cid:13)(cid:13) 8 COM GND NC 13 (cid:9) 2(cid:9)(cid:9) 4(cid:13) 4, 9 (cid:9) 3(cid:9)(cid:9) 8(cid:13) (cid:9) 4(cid:9)(cid:9) 16(cid:13) (cid:9) 5(cid:9)(cid:9) 32(cid:13) (cid:9) 6(cid:9)(cid:9) 64(cid:13) (cid:9) 7(cid:9)(cid:9) 128 1218/19 • TA05 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC®1152 Rail-to-Rail Input and Output, Zero-Drift Op Amp High DC Accuracy, 10m V V , 100nV/(cid:176) C Drift, 0.7MHz GBW, 0.5V/m s OS(MAX) Slew Rate, Maximum Supply Current 3mA LT1366/LT1367 Dual/Quad Precision, Rail-to-Rail Input and Output 475m V V , 400kHz GBW, 0.13V/m s Slew Rate, OS(MAX) Op Amps Maximum Supply Current 520m A per Op Amp LT1466/LT1467 Dual/Quad Micropower, Rail-to-Rail Input and Output Maximum Supply Current 75m A per Op Amp, 390m V V , OS(MAX) Op Amps 120kHz Gain Bandwidth 16 Linear Technology Corporation 12189f LT/TP 0697 7K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 l (408) 432-1900 FAX: (408) 434-0507 l TELEX: 499-3977 l www.linear-tech.com ª LINEAR TECHNOLOGY CORPORATION 1997