LSM2 Series www.murata-ps.com Single Output, Non-Isolated Selectable-Output POL DC/DC Converters Typical Unit Murata Power Solutions’ miniature POL switching DC/DC converters are ideal regulation and supply elements for mixed voltage systems. FEATURES PRODUCT OVERVIEW „„Point-of-load (POL) converters for They are fully compatible with the Distributed- in the central supply, leaving lower cost POL mixed voltage systems power Open Standards Alliance specification regulation right at the load. Unlike linear regula- „„5V & 12V wide input ranges (www.dosapower.com). LSM2s can power CPU’s, tors, the LSM2’s can deliver very high power (up to programmable logic and mixed voltage systems 52 Watts) in a tiny area with no heat sinking and no „„6, 10 or 16 Amp maximum outputs with little heat and low noise. A typical applica- external components needed. They feature quick „„DOSA compatible SMT package tion uses a master isolated 12 or 5 Volt DC supply transient response (to 25µsec) and very fast current „„Meets RoHS-6 compliance and individual LSM2 converters for local 1.8 and slew rates (to 20A/µsec). 3.3 Volt DC supplies. All system isolation resides „„Phased start up sequencing and tracking „„Extensive self-protection „„Starts up into pre-biased loads CONNECTION DIAGRAM +INPUT +OUTPUT +SENSE COMMON COMMON VCC CURRENT POWER ON/OFF CONPTWROMLLER SENSE GOOD CONTROL VTRACK/ REFERENCE & VOUT SEQUENCE ERROR AMP TRIM INPUT Typical topology is shown For full details go to www.murata-ps.com/rohs www.murata-ps.com/support MDC_LSM2 Series.D02∆ Page 1 of 17

LSM2 Series Single Output, Non-Isolated Selectable-Output POL DC/DC Converters PERFORMANCE SPECIFICATIONS AND ORDERING GUIDE  Output Input VOUT IOUT Power R/N (mVp-p)  Regulation  VIN Nom. Range  IIN  Efficiency Package Root Model (Volts) (Amps) (Watts) Typ. Max. Line Load (Volts) (Volts) (mA/A) Min. Typ. (Case/Pinout) LSM2-T/6-W3-C 0.75-3.3 6 19.8 20 40 ±0.11% ±0.075% 5 2.4-5.5 50/4.15 93% 95.5% C63, P67 LSM2-T/6-D12-C 0.75-5 6 30.0 30 90 ±0.075% ±0.15% 12 8.3-13.2 70/2.68 91.9% 93.4% C63, P67 LSM2-T/10-W3-C 0.75-3.3 10 33.0 58 79 ±0.15% ±0.075% 5 2.4-5.5 75/6.91 94% 95.5% C62, P66 LSM2-T/10-D12-C 0.75-5 10 50.0 62 80 ±0.07% ±0.15% 12 8.3-13.2 100/4.368 93.5% 95.4% C62, P66 LSM2-T/16-W3-C 0.75-3.3 16 52.8 83 110 ±0.1% ±0.075% 5 2.4-5.5 70/11.15 92.8% 94.7% C62, P66 LSM2-T/16-D12-C 0.75-5 16 80.0 90 125 ±0.1% ±0.21% 12 8.3-13.2 100/7.1 93% 94% C62, P66  Typical at TA = +25°C under nominal line voltage and full-load conditions, unless noted.  Nominal line voltage, no-load/full-load conditions.  Ripple/Noise (R/N) is tested/specified over a 20MHz bandwidth and may be reduced  LSM2-T16-D12 efficiencies are shown at 5VOUT. with external filtering. See I/O Filtering and Noise Reduction for details.  VIN must be ≥0.5V greater than VOUT.  These devices have no minimum-load requirements and will regulate under no-load „These are not complete model numbers. Please refer to the Part Number Structure conditions. Regulation specifications describe the output-voltage deviation as the line when ordering. voltage or load is varied from its nominal/midpoint value to either extreme. ➇ RoHS-6 compliance does not claim EU RoHS exemption 7b (lead in solder). PART NUMBER STRUCTURE L SM2 - T / 16 - D12 N G -C Note: Not all model number combinations Output Configuration: RoHS6 compliant* are available. Contact MPS. L = Unipolar (see note 8) Low Voltage Power Good Output: ** Blank = Omitted * Contact MPS (DATEL) for availability. G = Installed Non-Isolated SMT On/Off Polarity: ** The Power Good option is not available for Nominal Output Voltage: Blank = Positive polarity LSM2-T/10-D12 and LSM2-T/16-D12. Models 0.75-3.3 Volts (W3) N = Negative polarity without Power Good do not install pad 8 (10/16 0.75-5 Volts (D12) Amp). For 6 Amp models, pad 7 is only installed for “G” models. Input Voltage Range: Maximum Rated Output D12 = 8.3-14 Volts (12V nominal) Current in Amps W3 = 2.4-5.5 Volts (5V nominal) www.murata-ps.com/support MDC_LSM2 Series.D02∆ Page 2 of 17

LSM2 Series Single Output, Non-Isolated Selectable-Output POL DC/DC Converters Performance/Functional Specifications (1) INPUT Pre-bias Startup (15) Converter will start up if the external output voltage is less than VNOM Input Voltage Range See Ordering Guide Sequencing Isolation Not isolated, input and output use the same Slew Rate 2V max. per millisecond common return. Startup delay until sequence start 10 milliseconds Start-Up Threshold Tracking accuracy, rising input VOUT = ±100mV of Sequence In W3 Models 2.2 Volts Tracking accuracy, falling input VOUT = ±200mV of Sequence In 12V Models 8 Volts Sequence pin input impedance 400kW to 1MW Undervoltage Shutdown Remote Sense to VOUT 0.5V max. (7) W3 Models 2.0 Volts Power Good Output (17) TRUE (OK) = open drain 12V Models 7.5 Volts (“G” suffix) FALSE (not OK) = Signal Ground to 0.4V Overvoltage Shutdown None Power_Good Configuration MOSFET to ground with external user Reflected (Back) Ripple Current (2) 20-70mAp-p (model dependent) pullup, 10mA max. sink Internal Input Filter Type Capacitive DYNAMIC CHARACTERISTICS Reverse Polarity Protection See fuse information Dynamic Load Response 25µsec to ±2% of final value Input Current: (50-100-50% load step, di/dt = 20A/µsec) Full Load Conditions See Ordering Guide Start-Up Time 7msec for VOUT = nominal Inrush Transient 0.1-0.4A2sec (model dependent) (VIN on to VOUT regulated or On/Off to VOUT) Shutdown Mode (Off, UV, OT) 5mA Switching Frequency Output Short Circuit 60mA LSM2-T/6 models 315kHz Low Line (VIN = VMIN) LSM2-T/10 and -T/16 models 230kHz LSM2-T/6-W3 5.54 Amps LSM2-T/6-D12 3.79 Amps ENVIRONMENTAL LSM2-T/10-W3 9.14 Amps Calculated MTBF (4) TBC Hours LSM2-T/10-D12 6.375 Amps LSM2-T/16-W3 14.63 Amps Operating Temperature Range (Ambient) –40 to +85°C with derating (9) See Derating Curves LSM2-T/16-D12 10.2 Amps Remote On/Off Control: (5) Operating PC Board TemUperature –40 to +100°C max. (12) Positive Logic (no model suffix) OFF = ground pin to +0.3V max. Storage Temperature Range –55 to +125°C ON = open pin or +VIN max. Thermal Protection/Shutdown +115°C Negative Logic (“N” model suffix) ON = Open pin or 0 to +0.3V max. Relative Humidity to 85% / +85°C, non-condensing OFF = +2.5V to +VIN max. Current 1mA max. PHYSICAL OUTPUT Outline Dimensions See Mechanical Specifications Voltage Output Range See Ordering Guide Removable Heat Shield Nylon 46 Minimum Loading No minimum load Weight 0.28 ounces (7.8 grams) Accuracy (50% load) ±2% of VNOM Lead Material Tin-plated copper alloy Voltage Adjustment Range (13) See Ordering Guide Electromagnetic Interference Designed to meet FCC part 15, class B, EN55022 Temperature Coefficient ±0.02% of VOUT range per °C (conducted and radiated) (may need external filter) Ripple/Noise (20 MHz bandwidth) See Ordering Guide and (8) Safety Designed to meet UL/cUL 60950-1 CSA- Line/Load Regulation (See Tech Notes) See Ordering Guide and (10) C22.2 No.234 IEC/EN Efficiency See Ordering Guide 60950-1 Maximum Capacitive Loading: (14) Flammability UL94V-0 LSM2-T/6 models: Cap-ESR = 0.001 to 0.01W 3000µF ABSOLUTE MAXIMUM RATINGS Cap-ESR >0.01W 5000µF Input Voltage (Continuous or transient) LSM2-T/10 and -T/16 models: W3 models +7 Volts Cap-ESR = 0.001 to 0.01W 5000µF 12V models +15 Volts Cap-ESR >0.01W 10,000µF Current Limit Inception: (98% of VOUT) On/Off Control –0.3V min. to +VIN max. LSM2-T/6 models 10 Amps (after warm up) Input Reverse Polarity Protection See Fuse section LSM2-T/10 models 16.75 Amps (after warm startup) Output Current (7) Current-limited. Devices can LSM2-T/16 models 21–31 Amps (after warm up) withstand sustained short circuit Short Circuit Mode (6) without damage. Short Circuit Current Output 600mA Storage Temperature –55 to +125°C Protection Method (16) Hiccup autorecovery on overload removal Short Circuit Duration Continuous, no damage (output shorted to Lead Temperature (soldering 10 sec. max.) +280°C ground) These are stress ratings. Exposure of devices to greater than any of these conditions may adversely affect long-term reliability. Proper operation under conditions other than those listed in the Performance/Functional Specifications Table is not implied. www.murata-ps.com/support MDC_LSM2 Series.D02∆ Page 3 of 17

LSM2 Series Single Output, Non-Isolated Selectable-Output POL DC/DC Converters Performance/Functional Specification Notes: (7) If Sense is connected remotely at the load, up to 0.5 Volts difference is allowed (1) All models are tested and specified with external 1 || 10µF ceramic/tantalum output between the Sense and +Vout pins to compensate for ohmic voltage drop in the power capacitors and a 22µF external input capacitor. All capacitors are low ESR types. These lines. A larger voltage drop may cause the converter to exceed maximum power dis- capacitors are necessary to accommodate our test equipment and may not be required sipation. Connect sense to +Vout if not used. to achieve specified performance in your applications. All models are stable and (8) Output noise may be further reduced by adding an external filter. See I/O Filtering and regulate within spec under no-load conditions. Noise Reduction. General conditions for Specifications are +25°C, Vin = nominal, Vout = nominal, full (9) All models are fully operational and meet published specifications, including “cold load. “Nominal” output voltage is +5V for D12 models and +3.3V for W3 models. start” at –40°C. (2) Input Back Ripple Current is tested and specified over a 5-20MHz bandwidth. Input (10) Regulation specifications describe the deviation as the line input voltage or output load filtering is Cin = 2 × 100µF tantalum, Cbus = 1000µF electrolytic, Lbus = 1µH. current is varied from a nominal midpoint value to either extreme. (3) Note that Maximum Power Derating curves indicate an average current at nominal (11) Other input or output voltage ranges are available under scheduled quantity special order. input voltage. At higher temperatures and/or lower airflow, the DC/DC converter will (12) Maximum PC board temperature is measured with the sensor in the center. tolerate brief full current outputs if the total RMS current over time does not exceed the (13) Do not exceed maximum power specifications when adjusting the output trim. derating curve. (14) The maximum output capacitive loads depend on the the Equivalent Series Resistance (4) Mean Time Before Failure is calculated using the Telcordia (Belcore) SR-332 Method 1, (ESR) of the external output capacitor. Case 3, ground fixed conditions, Tpcboard = +25°C, full output load, natural air convec- (15) Do not use Pre-bias startup and sequencing together. See Technical Notes below. tion. (16) After short circuit shutdown, if the load is partially removed such that the load still ex- (5) The On/Off Control may be driven with external logic or by applying appropriate exter- ceeds the overcurrent (OC) detection, the converter will remain in hiccup restart mode. nal voltages which are referenced to –Input Common. The On/Off Control Input should (17) When Sequencing is not used, the Power Good output is TRUE at any time the output use either an open collector/open drain transistor or logic gate which does not exceed is within approximately ±10% of the voltage set point. Power Good basically indicates +Vin. A 68KΩ external pullup resistor to +Vin will cause the “ON” state for negative if the converter is in regulation. Power Good detects Over Temperature if the PWM has logic models. shut down due to OT. Power Good does not directly detect Over Current. (6) Short circuit shutdown begins when the output voltage degrades approximately 2% If Sequencing is in progress, Power Good will falsely indicate TRUE (valid) before the from the selected setting. output reaches its setpoint. Ignore Power Good if Sequencing is in transition. at the DC/DC output pins with scope probe ground less than 0.5" in length. TECHNICAL NOTES All external capacitors should have appropriate voltage ratings and be located I/O Filtering and Noise Reduction as close to the converters as possible. Temperature variations for all relevant All models in the LSM2 Series are tested and specified with external 1 || 10µF parameters should be taken into consideration. ceramic/tantalum output capacitors and a 22µF tantalum input capacitor. These capacitors are necessary to accommodate our test equipment and may not be The most effective combination of external I/O capacitors will be a function required to achieve desired performance in your application. The LSM2s are of your line voltage and source impedance, as well as your particular load and designed with high-quality, high-performance internal I/O caps, and will oper- layout conditions. ate within spec in most applications with no additional external components. Input Fusing In particular, the LSM2’s input capacitors are specified for low ESR and Most applications and or safety agencies require the installation of fuses at the are fully rated to handle the units' input ripple currents. Similarly, the internal inputs of power conversion components. The LSM2 Series are not internally output capacitors are specified for low ESR and full-range frequency response. fused. Therefore, if input fusing is mandatory, either a normal-blow or a fast-blow fuse with a value no greater than twice the maximum input current In critical applications, input/output ripple/noise may be further reduced using should be installed within the ungrounded input path to the converter. filtering techniques, the simplest being the installation of external I/O caps. Safety Considerations External input capacitors serve primarily as energy-storage devices. They minimize high-frequency variations in input voltage (usually caused by IR drops LSM2 SMTs are non-isolated DC/DC converters. In general, all DC/DCs must in conductors leading to the DC/DC) as the switching converter draws pulses of be installed, including considerations for I/O voltages and spacing/separation current. Input capacitors should be selected for bulk capacitance (at appropri- requirements, in compliance with relevant safety-agency specifications (usually ate frequencies), low ESR, and high rms-ripple-current ratings. The switching UL/IEC/EN60950-1). nature of modern DC/DCs requires that the dc input voltage source have low ac In particular, for a non-isolated converter’s output voltage to meet SELV impedance at the frequencies of interest. Highly inductive source impedances (safety extra low voltage) requirements, its input must be SELV compliant. If the can greatly affect system stability. Your specific system configuration may output needs to be ELV (extra low voltage), the input must be ELV. necessitate additional considerations. Input Overvoltage and Reverse-Polarity Protection Output ripple/noise (also referred to as periodic and random deviations or LSM2 SMT Series DC/DCs do not incorporate either input overvoltage or input PARD) may be reduced below specified limits with the installation of additional reverse-polarity protection. Input voltages in excess of the specified absolute external output capacitors. Output capacitors function as true filter elements maximum ratings and input polarity reversals of longer than "instantaneous" and should be selected for bulk capacitance, low ESR, and appropriate fre- duration can cause permanent damage to these devices. quency response. Any scope measurements of PARD should be made directly www.murata-ps.com/support MDC_LSM2 Series.D02∆ Page 4 of 17

LSM2 Series Single Output, Non-Isolated Selectable-Output POL DC/DC Converters The remote sense line is part of the feedback control loop regulating the DC/ TO DC converter’s output. The sense line carries very little current and conse- OSCILLOSCOPE CURRENT PROBE quently requires a minimal cross-sectional-area conductor. As such, it is not 2 +INPUT a low-impedance point and must be treated with care in layout and cabling. + LBUS Sense lines should be run adjacent to signals (preferably ground), and in cable and/or discrete-wiring applications, twisted-pair or similar techniques VIN CBUS CIN – should be used. To prevent high frequency voltage differences between VOUT 3 and Sense, we recommend installation of a 1000pF capacitor close to the COMMON converter. CIN = 2 x 100µF, ESR < 700mΩ @ 100kHz The sense function is capable of compensating for voltage drops between CBUS = 1000µF, ESR < 100mΩ @ 100kHz LBUS = 1µH the +Output and +Sense pins that do not exceed 10% of VOUT. [VOUT(+) – Common] – [Sense(+) – Common] ≤ 10%VOUT Figure 2. Measuring Input Ripple Current Power derating (output current limiting) is based upon maximum output cur- rent and voltage at the converter’s output pins. Use of trim and sense functions Start-Up Time can cause the output voltage to increase, thereby increasing output power The VIN to VOUT Start-Up Time is the interval between the time at which a ramp- beyond the LSM2's specified rating. Therefore: ing input voltage crosses the lower limit of the specified input voltage range and the fully loaded output voltage enters and remains within its specified (VOUT at pins) x (IOUT) ≤ rated output power accuracy band. Actual measured times will vary with input source impedance, The internal 10.5W resistor between +Sense and +Output (see Figure 1) external input capacitance, and the slew rate and final value of the input volt- serves to protect the sense function by limiting the output current flowing age as it appears to the converter. through the sense line if the main output is disconnected. It also prevents output voltage runaway if the sense connection is disconnected. Note: If the sense function is not used for remote regulation, +Sense must +SENSE 6 COPPER STRIP be tied to +Output at the DC/DC converter pins. 4 +OUTPUT Sense Input Use the Sense input with caution. Many applications do not need the Sense connection. Sense is intended to correct small output accuracy errors caused C1 C2 SCOPE RLOAD by the resistive ohmic drop in output wiring as output current increases. This output drop (the difference between Sense and VOUT when measured at the 3 converter) should not be allowed to exceed 0.5V. Consider using heavier wire if COMMON COPPER STRIP this drop is excessive. Sense is connected at the load and corrects for resistive errors only. Be C1 = NA careful where it is connected. Any long, distributed wiring and/or significant C2 = 22µF TANTALUM inductance introduced into the Sense control loop can adversely affect overall LOAD 2-3 INCHES (51-76mm) FROM MODULE system stability. If in doubt, test the application, and observe the DC/DC's output transient response during step loads. There should be no appreciable ringing or Figure 3. Measuring Output Ripple/Noise (PARD) oscillation. You may also adjust the output trim slightly to compensate for voltage loss in any external filter elements. Do not exceed maximum power ratings. The On/Off to VOUT Start-Up Time assumes the converter is turned off via the On/Off Control with the nominal input voltage already applied to the converter. On/Off Control The specification defines the interval between the time at which the converter The On/Off Control pin may be used for remote on/off operation. LSM2 Series is turned on and the fully loaded output voltage enters and remains within its DC/DC converters are designed so that they are enabled when the control pin specified accuracy band. See Typical Performance Curves. is left open (open collector). Remote Sense Dynamic control of the on/off function is best accomplished with a me- chanical relay or open-collector/open-drain drive circuit (optically isolated if LSM2 Series offer an output sense function. The sense function enables appropriate). The drive circuit should be able to sink appropriate current when point-of-use regulation for overcoming moderate IR drops in conductors and/or activated and withstand appropriate voltage when deactivated. cabling. Since these are non-isolated devices whose inputs and outputs usually share the same ground plane, sense is provided only for the +Output. www.murata-ps.com/support MDC_LSM2 Series.D02∆ Page 5 of 17

LSM2 Series Single Output, Non-Isolated Selectable-Output POL DC/DC Converters Output Reverse Conduction Many DC/DCs using synchronous rectification suffer from Output Reverse +INPUT Conduction. If those devices have a voltage applied across their output before a voltage is applied to their input (this typically occurs when another power sup- ply starts before them in a power-sequenced application), they will either fail to +V start or self destruct. In both cases, the cause is the "freewheeling" or "catch" ON/OFF SMALL CONTROL FET biasing itself on and effectively becoming a short circuit. SIGNAL SHUTDOWN TRANSISTOR SIGNAL LSM2 SMT DC/DC converters do not suffer from Output Reverse Conduc- HLOI = = O OFNF GROUND CONTROLLER tion. They employ proprietary gate drive circuitry that makes them immune to moderate applied output overvoltages. COMMON Thermal Considerations and Thermal Protection The typical output-current thermal-derating curves shown below enable Figure 4. On/Off Control Using An External Open Collector Driver designers to determine how much current they can reliably derive from each model of the LSM2 SMT's under known ambient-temperature and air-flow Applying an external voltage to the On/Off Control pin when no input power conditions. Similarly, the curves indicate how much air flow is required to reli- is applied to the converter can cause permanent damage to the converter. The ably deliver a specific output current at known temperatures. on/off control function, however, is designed such that the converter can be disabled (control pin pulled low) while input voltage is ramping up and then "released" once the input has stabilized (see also power-up sequencing). +INPUT Power-up sequencing If a controlled start-up of one or more LSM2 Series DC/DC converters is 10kΩ +V required, or if several output voltages need to be powered-up in a given ON/OFF sequence, the On/Off control pin can be driven with an external open collector EXTERNAL CONTROL SHUTDOWN OPEN device as per Figure 4. COLLECTOR SIGNAL INPUT GROUND CONTROLLER Leaving the input of the on/off circuit closed during power-up will have the output of the DC/DC converter disabled. When the input to the external open COMMON collector is pulled high, the DC/DC converter’s output will be enabled. Output Overvoltage Protection Figure 5. Inverting On/Off Control LSM2 SMT Series DC/DC converters do not incorporate output overvoltage protection. In the extremely rare situation in which the device’s feedback loop The highest temperatures in LSM2 SMT's occur at their output inductor, is broken, the output voltage may run to excessively high levels (VOUT = VIN). If it whose heat is generated primarily by I2R losses. The derating curves were de- is absolutely imperative that you protect your load against any and all possible veloped using thermocouples to monitor the inductor temperature and varying overvoltage situations, voltage limiting circuitry must be provided external to the load to keep that temperature below +110°C under the assorted condi- the power converter. tions of air flow and air temperature. Once the temperature exceeds +115°C (approx.), the thermal protection will disable the converter. Automatic restart Output Overcurrent Detection occurs after the temperature has dropped below +110°C. Overloading the power converter's output for an extended time will invariably cause internal component temperatures to exceed their maximum ratings and As you may deduce from the derating curves and observe in the efficiency eventually lead to component failure. High-current-carrying components such curves on the following pages, LSM2 SMT's maintain virtually constant as inductors, FET's and diodes are at the highest risk. LSM2 SMT Series DC/DC efficiency from half to full load, and consequently deliver very impressive converters incorporate an output overcurrent detection and shutdown function temperature performance even if operating at full load. that serves to protect both the power converter and its load. Lastly, when LSM2 SMT's are installed in system boards, they are obviously If the output current exceeds it maximum rating by typically 50% or if the subject to numerous factors and tolerances not taken into account here. If you output voltage drops to less than 98% of it original value, the LSM2's internal are attempting to extract the most current out of these units under demanding overcurrent-detection circuitry immediately turns off the converter, which then temperature conditions, we advise you to monitor the output-inductor tempera- goes into a "hiccup" mode. While hiccupping, the converter will continuously ture to ensure it remains below +110°C at all times. attempt to restart itself, go into overcurrent, and then shut down. Once the output short is removed, the converter will automatically restart itself. www.murata-ps.com/support MDC_LSM2 Series.D02∆ Page 6 of 17

LSM2 Series Single Output, Non-Isolated Selectable-Output POL DC/DC Converters Start Up Considerations Increase the input start up voltage if possible to raise the downward voltage When power is first applied to the DC/DC converter, operation is different than spike. Also, make sure that the input voltage ramps up in a reasonably short when the converter is running and stabilized. There is some risk of start up time (less than a few milliseconds). If possible, move the input source closer to difficulties if you do not observe several application features. Lower output the converter to reduce ohmic losses in the input wiring. Remember that the voltage converters may have more problems here since they tend to have input current is carried both by the wiring and the ground plane return. Make higher output currents. Operation is most critical with any combination of the sure the ground plane uses adequate thickness copper. Run additional bus wire following external factors: if necessary. 1 – Low initial input line voltage and/or poor regulation of the input source. Any added output capacitor should use just enough capacitance (and no 2 – Full output load current on lower output voltage converters. more) to reduce output noise at the load and to avoid marginal threshold noise problems with external logic. An output cap will also “decouple” inductive re- 3 – Slow slew rate of input voltage. actance in the load. Certain kinds of electronic loads include “constant current” 4 – Longer distance to input voltage source and/or higher external input characteristics which destabilize the output with insufficient capacitance. If the source impedance. wiring to the eventual load is long, consider placing this decoupling cap at the 5 – Limited or insufficient ground plane. External wiring that is too small. load. Use the Remote Sense input to avoid ohmic voltage drop errors. 6 – Too small external input capacitance. Too high ESR. An elegant solution to start up problems is to apply the input voltage with 7 – High output capacitance causing a start up charge overcurrent surge. the Remote On/Off control first in the off setting (for those converters with an 8 – Output loads with excessive inductive reactance or constant current On/Off Control). After the specified start-up delay (usually under 20 mSec), turn characteristics. on the converter. The controller will have already been stabilized. The short delay will not be noticed in most applications. Be aware of applications which If the input voltage is already at the low limit before power is applied, the need “power management” (phased start up). start up surge current may instantaneously reduce the voltage at the input terminals to below the specified minimum voltage. Even if this voltage depres- Finally, it is challenging to model some application circuits with absolute fidel- sion is very brief, this may interfere with the on-board controller and possibly ity. How low is the resistance of your ground plane? What is the inductance (and cause a failed start. Or the converter may start but the input current load will distributed capacitance) of external wiring? Even a detailed mathematical model now drive the input voltage below its running low limit and the converter will may not get all aspects of your circuit. Therefore it is difficult to give cap values shut down. which serve all applications. Some experimentation may be required. If you measure the input voltage before start up with a Digital Voltmeter (DVM), Pre-Biased Startup the voltage may appear to be adequate. Limited external capacitance and/or Newer systems with multiple power voltages have an additional problem too high a source impedance may cause a short downward spike at power up, besides startup sequencing. Some sections have power already partially ap- causing an instantaneous voltage drop. Use an oscilloscope not a DVM to observe plied (possibly because of earlier power sequencing) or have leakage power this spike. The converter’s soft-start controller is sensitive to input voltage. What present so that the DC/DC converter must power up into an existing voltage. matters here is the actual voltage at the input terminals at all times. This power may either be stored in an external bypass capacitor or supplied by an active source. Symptoms of start-up difficulties may include failed started, output oscilla- tion or brief start up then overcurrent shutdown. Since the input voltage is never This “pre-biased” condition can also occur with some types of program- absolutely constant, the converter may start up at some times and not at others. mable logic or because of blocking diode leakage or small currents passed through forward biased ESD diodes. Conventional DC/DCs may fail to start up Solutions correctly if there is output voltage already present. And some external circuits To improve start up, review the conditions above. One of the better solutions is are adversely affected when the low side MOSFET in a synchronous rectifier to place a moderate size capacitor very close to the input terminals. You may converter sinks current at start up. need two parallel capacitors. A larger electrolytic or tantalum cap supplies the surge current and a smaller parallel low-ESR ceramic cap gives low AC imped- The LSM2 series includes a pre-bias startup mode to prevent these initializa- ance. Too large an electrolytic capacitor may have higher internal impedance tion problems. Essentially, the converter acts as a simple buck converter until the (ESR) and/or lower the start up slew rate enough to upset the DC/DC’s control- output reaches its set point voltage at which time it converts to a synchronous ler. Make sure the capacitors can tolerate reflected switching current pulses rectifier design. This feature is variously called “monotonic” because the voltage from the converter. does not decay (from low side MOSFET shorting) or produce a negative transient once the input power is applied and the startup sequence begins. The capacitors will not help if the input source has poor regulation. A converter which starts successfully at 3.3 Volts will turn off if the input voltage decays to below the input voltage theshold, regardless of external capacitance. www.murata-ps.com/support MDC_LSM2 Series.D02∆ Page 7 of 17

LSM2 Series Single Output, Non-Isolated Selectable-Output POL DC/DC Converters Don’t Use Pre-Biasing and Sequencing Together D12 Models Resistor Trim Equation: Normally, you would use startup sequencing on multiple DC/DC’s to solve the Pre-Bias problem. By causing all power sources to ramp up together, no one RTRIM (W) = _____ _ 1_0_5_0_0___ –1000 source can dominate and force the others to fail to start. For most applica- VO – 0.7525 tions, do not use startup sequencing in a Pre-Bias application, especially with an external active power source. If you have active source pre-biasing, leave Vout (Typ.) 0.7525V 1.0V 1.2V 1.5V 1.8V 2.5V 3.3V 5V the Sequence input open so that the output will step up quickly and safely. A Rtrim (kW) Open 41.424 22.46 13.05 9.024 5.009 3.122 1.472 symptom of this condition is repeated failed starts. You can further verify this by removing the existing load and testing it with a separate passive resistive Voltage Trim load which does not exceed full current. If the resistive load starts successfully, The LSM2 Series may also be trimmed using an external voltage applied you may be trying to drive an external pre-biased active source. between the Trim input and Output Common. Be aware that the internal “load” It may also be possible to use pre-bias and sequencing together if the Pre- impedance looking into trim pin is approximately 5 Kilohms. Therefore, you Bias source is in fact only a small external bypass capacitor slowly charged by may have to compensate for this in the source resistance of your external volt- leakage currents. Test your application to be sure. age reference. Output Adjustments Use a low noise DC reference and short leads. Mount the leads close to the The LSM2 series includes a special output voltage trimming feature which converter. is fully compatible with competitive units. The output voltage may be varied Two different trim equations are used for the W3 and D12 models. using a single trim resistor from the Trim input to Power Common (pin 4) or an external DC trim voltage applied between the Trim input and Power Common. W3 Models Voltage Trim Equation: The output voltage range for W3 models is 0.75 to 3.3 Volts. For D12 models, the output range is 0.75 to 5 Volts. VTRIM (in Volts) = 0.7 – (0.1698 x (VO – 0.7525)) IMPORTANT: On W3 models only, for outputs greater than 3 Volts up to The LSM2 W3 fixed trim voltages to set the output voltage are: 3.3 Volts maximum, the input supply must be 4.5 Volts minimum. To retain proper regulation, do not exceed the 3.3V output. Vout (Typ.) 0.7525V 1.0V 1.2V 1.5V 1.8V 2.5V 3.3V As with other trim adjustments, be sure to use a precision low-tempco Vtrim Open 0.6928V 0.624V 0.5731V 0.5221V 0.4033V 0.267V resistor (±100 ppm/°C) mounted close to the converter with short leads. Also be aware that the output voltage accuracy is ±2% (typical) therefore you may D12 Models Voltage Trim Equation: need to vary this resistance slightly to achieve your desired output setting. Two different trim equations are used for the W3 and D12 models. VTRIM (in Volts) = 0.7 – (0.0667 x (VO – 0.7525)) W3 Models Resistor Trim Equation: The LSM2 D12 fixed trim voltages to set the output voltage are: RTRIM (W) = ___ V_O_ _– 2_ 01_.0_77_50_2_5_ – 5110 Vout (Typ.) 0.7525V 1.0V 1.2V 1.5V 1.8V 2.5V 3.3V 5V Vtrim Open 0.6835 0.670 0.650 0.630 0.583 0.530 0.4166 The W3 models fixed trim resistors to set the output voltage are: Vout (Typ.) 0.7525V 1.0V 1.2V 1.5V 1.8V 2.5V 3.3V Rtrim (kW) Open 80.021 41.973 23.077 15.004 6.947 3.16 www.murata-ps.com/support MDC_LSM2 Series.D02∆ Page 8 of 17

LSM2 Series Single Output, Non-Isolated Selectable-Output POL DC/DC Converters Typical Performance Curves LSM2-T/6-D12 LSM2-T/6-D12 Maximum Current Temperature Derating Efficiency vs. Line Voltage and Load Current @ 25°C (VOUT = 5V) VOUT = 5V (air flow from input to output) 95 6.5 94 6 93 s) p m 92 A nt ( 5.5 %Efficiency () 998109 VIN = 8.3V Output Curre 5 Natural Convection 100 lfm 200 lfm 4.5 88 400 lfm VIN = 12V 87 86 VIN = 14V 4–40 25 30 35 40 45 50 55 60 65 70 75 80 85 Ambient Temperature (°C) 85 1 2 3 4 5 6 Load Current (Amps) LSM2-T/6-D12 Efficiency vs. Line Voltage and Load Current @ 25°C (VOUT = 0.75V) LSM2-T/6-D12 Maximum Current Temperature Derating VOUT = 0.75V (air flow from input to output) 84 6.5 82 6 80 ps) m VIN = 8.3V A %cy () 78 urrent ( 5.5 Natural Convection n C Efficie 76 Output 5 100 lfm 74 VIN = 12V 4.5 72 VIN = 14V 4 –40 25 30 35 40 45 50 55 60 65 70 75 80 85 70 Ambient Temperature (°C) 1 2 3 4 5 6 Load Current (Amps) www.murata-ps.com/support MDC_LSM2 Series.D02∆ Page 9 of 17

LSM2 Series Single Output, Non-Isolated Selectable-Output POL DC/DC Converters Tape & Reel Surface Mount Package MPS is not exempted from the Laws of Physics, and we do not have MPS’s LSM2 series DC/DC converters are the only higher-current (16A) SMT magic solders no one else has. Nevertheless, we have a simple and practical, DC/DC's that can be automatically “pick-and-placed” using standard vacuum- straightforward approach that works. We assemble our LSM2 SMT DC/DC's pickup equipment (nozzle size and style, vacuum pressure and placement using a high-temperature (+216°C), lead-free alloy (Sn96.2%, Ag2.5%, Cu0.8%, speed may need to be optimized for automated pick and place) and subse- Sb0.5%). The LSM2 design ensures co-planarity to within 0.004 inches quently reflowed using high-temperature, lead-free solder. (100µ1m) of the unit's tin-plated (150 micro-inches) copper leads. See Me- chanical Data for additional information. Virtually all SMT DC/DCs today are unprotected "open-frame" devices as- sembled by their vendors with high-temperature solder (usually Sn96.5/Ag3.5 The disposable heat shield (patent pending), which has a cutaway expos- with a melting point +221°C) so that you may attach them to your board using ing the package leads, provides thermal insulation to internal components low-temperature solder (usually Sn63/Pb37 with a melting point of +183°C). during reflow and its smooth surface ideally doubles as the vacuum pick-up Conceptually straightforward, this "stepped" solder approach has its limita- location also. The insulation properties of the heat shield are so effective tions, and it is clearly out of step with an industry trending toward the broad that temperature differentials as high as 50°C develop inside-to-outside the use of lead-free solders. Are you to experiment and develop reflow profiles shield. Oven temperature profiles with peaks of 250-260°C and dwell times from other vendors that ensure the components on those DC/DC never exceed exceeding 2 minutes above 221°C (the melting point of Sn96.5/Ag3.5) are 215-216°C? If those components get too hot, "double-reflow" could compro- easily achieved. mise the reliability of their solder joints. Virtually all these devices demand you "cool down" the Sn63 profile you are likely using today. HEAT SHIELD OUTSIDE TEMPERATURE 250 Sn96.5/Ag3.5 Melting Point 221 C) 200 Sn63/Pb37 Melting Point e (˚183 r u at 150 r pe PCB TEMPERATURE INSIDE THE HEAT SHIELD m Te 100 50 0 50 100 150 200 250 300 350 400 Time (Seconds) Figure 6. Reflow Solder Profile www.murata-ps.com/support MDC_LSM2 Series.D02∆ Page 10 of 17

LSM2 Series Single Output, Non-Isolated Selectable-Output POL DC/DC Converters LSM2 TAPE AND REEL SPECIFICATIONS DATEL's new-generation LSM2 SMT DC/DC converters are shipped in quantities of 150 modules per tape and reel. 0.158 1.102 (4) (28) CENTERED PICK UP LOCATION NOTCH IN SHELL CAUTION INDICATES PRESS TO REMOVE PIN ONE. THE HEAT SHIELD 1.370 2.205 2.063 AFTER THE SOLDER (34.8) (56) (52.4) PROCESS. 1 1 1 FEED DIRECTION TAPE DIMENSIONS IN INCHES (mm) 0.590 0.605 Removable Heat Shield (14.97) (15.36) Figure 7. Tape Dimensions 2.44 (62.0) 13.0 (330.2) 7.38 (187.5) 0.51(13.0) Figure 8. Reel Dimensions www.murata-ps.com/support MDC_LSM2 Series.D02∆ Page 11 of 17

LSM2 Series Single Output, Non-Isolated Selectable-Output POL DC/DC Converters LSM2 Power Sequencing Whereas in the old days, one master switch simultaneously turned on the +12Vdc power for all parts of a system, many modern systems require multiple supply voltages for different on-board sections. Typically the CPU or microcontroller “ALL ON” needs 1.8 Volts or lower. Memory (particularly DDR) may use 1.8 to 2.5 Volts. +VIN POL +5V Interface “glue” and “chipset” logic might use +3.3Vdc power while Input/Out- A LOADS put subsystems may need +5V. Finally, peripherals use 5V and/or 12V. ENABLE Timing is Everything SEQUENCING CPU CONTROLLER +VIN This mix of system voltages is being distributed by several local power solu- POL +3.3V B LOADS tions including Point-of-load (POL) DC/DC converters and sometimes a linear ENABLE regulator, all sourced from a master AC power supply. While this mix of volt- ages is challenging enough, a further difficulty is the start-up and shutdown timing relationship between these power sources and relative voltage differ- TO OTHER POLs ences between them. STARTUP SEQUENCE: For many systems, the CPU and memory must be powered up, boot-strap ENABLE loaded and stabilized before the I/O section is turned on. This avoids uncom- manded data bytes being transferred, compromising an active external network ON or placing the I/O section in an undefined mode. Or it keeps bad commands out of disk and peripheral controllers until they are ready to go to work. OFF POL A Settling Another goal for staggered power-up is to avoid an oversize load applied to Delay ON the master source all at once. A more serious reason to manage the timing and OFF voltage differences is to avoid either a latchup condition in programmable logic POL B (a latchup might ignore commands or would respond improperly to them) or a TIME high current startup situation (which may damage on-board circuits). And on the power down phase, inappropriate timing or voltages can cause interface Figure 9. Power Up/Down Sequencing Controller logic to send a wrong “epitaph” command. Two Approaches If the power up/down timing needs to be closely controlled, each POL must There are two ways to manage these timing and voltage differences. Either the be characterized for start-up and down times. These often vary—one POL may power up/down sequence can be controlled by discrete On/Off logic controls stabilize in 15 milliseconds whereas another takes 50 milliseconds. Another for each power supply (see Figure 9). Or the power up/down cycle is set by problem is that the sequencing controller itself must be “already running” and Sequencing or Tracking circuits. Some systems combine both methods. stabilized before starting up other circuits. If there is a glitch in the system, the power up/down sequencer could get out of step with possible disastrous The first system (discrete On/Off controls) applies signals from an already- results. Lastly, changing the timing may require reprogramming the logic powered logic sequencer or dedicated microcontroller which turns on each sequencer or rewriting software. downstream power section in cascaded series. This of course assumes all POL’s have On/Off controls. A distinct advantage of the sequencing controller Sequence/Track Input is that it can produce an “All On” output signal to state that the full system is A different power sequencing solution is employed on MPS’s LSM2 DC/DC con- stable and ready to go to work. For additional safety, the sequencer can moni- verter. After external input power is applied and the converter stabilizes, a high tor the output voltages of all downstream POL’s with an A/D converter system. impedance Sequence/Track input pin accepts an external analog voltage. The output power voltage will then track this Sequence/Track input at a one-to-one However the sequencer controller has some obvious difficulties besides ratio up to the nominal set point voltage for that converter. This Sequencing extra cost, wiring and programming complexity. First, power is applied as a input may be ramped, delayed, stepped or otherwise phased as needed for fast-rising, all-or-nothing step which may be unacceptable to certain circuits, the output power, all fully controlled by the user’s simple external circuits. As a especially large output bypass capacitors. These could force POL’s into over- direct input to the converter’s feedback loop, response to the Sequence/Track current shutdown. And some circuits (such as many linear regulators and some input is very fast (milliseconds). POL’s) may not have convenient start-up controls. This requires designing and fabricating external power controls such as high-current MOSFET’s. By properly controlling this Sequence pin, most operations of the discrete On/Off logic sequencer may be duplicated. The Sequence pin system does not use the converter’s Enable On/Off control (unless it is a master emergency shut down system). www.murata-ps.com/support MDC_LSM2 Series.D02∆ Page 12 of 17

LSM2 Series Single Output, Non-Isolated Selectable-Output POL DC/DC Converters Power Phasing Architectures Observe the simplified timing diagrams below. There are many possible power OUTPUT VOLTAGE phasing architectures and these are just some examples to help you analyze your system. Each application will be different. Multiple output voltages may require more complex timing than that shown here. POL A VOUT These diagrams illustrate the time and slew rate relationship between two typical power output voltages. Generally the Master will be a primary power POL B VOUT voltage in the system which must be present first or coincident with any Slave power voltages. The Master output voltage is connected to the Slave’s Sequence input, either by a voltage divider, divider-plus-capacitor or some Coincident VOUT Times other method. Several standard sequencing architectures are prevalent. They are concerned with three factors: TIME „ The time relationship between the Master and Slave voltages Figure 11. Proportional or Ratiometric Phasing (Identical VOUT Time) „ The voltage difference relationship between the Master and Slave Figures 12 and 13 show both delayed start up and delayed final voltages „ The voltage slew rate (ramp slope) of each converter’s output. for two converters. Figure 12 is called “Inclusive” because the later starting For most systems, the time relationship is the dominant factor. The voltage POL finishes inside the earlier POL. The timing in Figure 12 is more easily built difference relationship is important for systems very concerned about possible using a combined digital sequence controller and the Sequence/Track pin. latchup of programmable devices or overdriving ESD diodes. Lower slew rates Figure 13 is the same strategy as Figure 12 but with an “exclusive” timing avoid overcurrent shutdown during bypass cap charge-up. relationship staggered approximately the same at power-up and power-down. In Figure 10, two POL’s ramp up at the same rate until they reach their different respective final set point voltages. During the ramp, their voltages are nearly identical. This avoids problems with large currents flowing between OUTPUT VOLTAGE logic systems which are not initialized yet. Since both end voltages are differ- ent, each converter reaches it’s setpoint voltage at a different time. OUTPUT POL A VOUT VOLTAGE POL B VOUT Delayed POL A VOUT VOUT Times POL B VOUT TIME Figure 12. Staggered or Sequential Phasing—Inclusive (Fixed Delays) Staggered +VOUT Times OUTPUT VOLTAGE TIME Not Drawn To Scale Figure 10. Coincident or Simultaneous Phasing (Identical Slew Rates) Figure 11 shows two POL’s with different slew rates in order to reach differ- POL A VOUT ing final voltages at about the same time. POL B VOUT Delayed VOUT Times TIME Figure 13. Staggered or Sequential Phasing—Exclusive (Fixed Cascaded Delays) www.murata-ps.com/support MDC_LSM2 Series.D02∆ Page 13 of 17

LSM2 Series Single Output, Non-Isolated Selectable-Output POL DC/DC Converters Operation Figure 15 shows a single POL and the same RC network. However, we have To use the Sequence pin after power start-up stabilizes, apply a rising external added a FET at Q1 as an up/down control. When VIN power is applied to the voltage to the Sequence input. As the voltage rises, the output voltage will POL, Q1 is biased on, shorting out the Sequence pin. When Q1’s gate is biased track the Sequence input (gain = 1). The output voltage will stop rising when it off, R1 charges C1 and the POL’s output ramps up at the R1-C1 slew rate. Note: reaches the normal set point for the converter. The Sequence input may option- Q1’s gate would typically be controlled from some external digital logic. ally continue to rise without any effect on the output. Keep the Sequence input voltage below the converter’s input supply voltage. Use a similar strategy on power down. The output voltage will stay constant +VIN until the Sequence input falls below the set point. R1 Any strategy may be used to deliver the power up/down ramps. The circuits SEQ/TRK POL A +VOUT = 5V Q1 below show simple RC networks but you may also use operational amplifiers, D/A converters, etc. UP/DN C1 –VIN Circuits The circuits shown in Figures 14 through 16 introduce several concepts when using these Sequencing controls on Point-of-Load (POL) converters. These Figure 15. Self-Ramping Power Up circuits are only for reference and are not intended as final designs ready for your application. Also, numerous connections are omitted for clarity. If you wish to have a ramped power down (rather than a step down), add a small resistor in series with Q1’s drain. +VIN Figure 16 shows both a RC ramp on Master POL A and a proportional track- ing divider (R2 and R3) on POL B. We have also added an optional very small R1 noise filter cap at C2. Figure 16’s circuit corresponds roughly to Figure 11’s SEQ/TRK POL A +VOUT = 5V timing for power up. C1 +VIN –VIN R1 MAIN RAMP SEQ/TRK POL A +VOUT = 5V RATE C1 POL B +VOUT = 3.3V –VIN SEQ/TRK R2 Figure 14. Wiring for Simultaneous Phasing SEQ/TRK POL B +VOUT = 3.3V Figure 14 shows a basic Master (POL A) and Slave (POL B) connected so the R3 C2 POL B ramps up identically to POL A as shown in timing diagram, Figure 10. RC network R1 and C1 charge up at a rate set by the R1-C1 time constant, giving –VIN a roughly linear ramp. As POL A reaches 3.3VOUT (the setpoint of POL B), POL ANTI-NOISE FILTER, 1000pF TYP. B will stop rising. POL A then continues rising until it reaches 5V. R1 should be significantly smaller than the internal bias current resistor from the Sequence Figure 16. Proportional Phasing pin. Start with a 20kW value. We assume that the critical phase is only on power up therefore there is no provision for ramped power down. www.murata-ps.com/support MDC_LSM2 Series.D02∆ Page 14 of 17

LSM2 Series Single Output, Non-Isolated Selectable-Output POL DC/DC Converters Guidelines for Sequence/Track Applications [8] If one converter is slaving to another master converter, there will be a very [1] Leave the converter’s On/Off Enable control (if installed) in the On setting. short phase lag between the two converters. This can usually be ignored. Normally, you should just leave the On/Off pin open. [9] You may connect two or more Sequence inputs in parallel from two con- [2] Allow the converter to stabilize (typically less than 20 mS after +VIN power verters. Be aware of the increasing pull-up bias current and reduced input on) before raising the Sequence input. Also, if you wish to have a ramped impedance. power down, leave +VIN powered all during the down ramp. Do not simply [10] Any external capacitance added to the converter’s output may affect ramp shut off power. up/down times and ramp tracking accuracy. [3] If you do not use the Sequence/Track pin, leave it open or tied to +VIN. Power Good Output [4] Observe the Output slew rate relative to the Sequence input. A rough The Power Good Output consists of an unterminated BSS138 small signal guide is 2 Volts per millisecond maximum slew rate. If you exceed this field effect transistor and a dual window comparator input circuit driving the slew rate on the Sequence pin, the converter will simply ramp up at gate of the FET. Power Good is TRUE (open drain, high impedance state) if the it’s maximum output slew rate (and will not necessarily track the faster converter’s power output voltage is within about ±10% of the setpoint. Thus, Sequence input). The reason to carefully consider the slew rate limitation the PG TRUE condition indicates that the converter is approximately within is in case you want two different POL’s to precisely track each other. regulation. Since an overcurrent condition occurs at about 2% output voltage reduction, the Power Good does not directly measure an output overcurrent [5] Be aware of the input characteristics of the Sequence pin. The high input condition at rated maximum output current. However, gross overcurrent or an impedance affects the time constant of any small external ramp capacitor. output short circuit will set Power Good to FALSE (+0.2V saturation, low imped- And the bias current will slowly charge up any external caps over time ance condition). if they are not grounded. The internal pull-up resistor to +VIN is typically 400kW to 1MW. +LOGIC Notice in the simplified Sequence/Track equivalent circuit (Figure 17) that External Pullup SUPPLY Resistor a blocking diode effectively disconnects this circuit when the Sequence/ Track pin is pulled up to +VIN or left open. POWER User’s External Logic GOOD HI BSS138 Window Comparator +VIN PWM COMMON LOGIC CONTROLLER +VOUT LO 1M0AmXA. POWER GROUND FEEDBACK OUTPUT 1MΩ +VIN HI (Open Drain) = Power OK TRIM LO (+0.2V Saturation) = Power not OK Figure 18. Equivalent Power Good Circuit SEQ/ – TRK IN Using a simple connection to external logic (and returned to the converter’s + Common connection), the Power Good output is unterminated so that the user may adapt the output to a variety of logic families. The PG pin may therefore Figure 17. Sequence/Track Simplified Equivalent Schematic be used with logic voltages which are not necessarily the same as the input or output power voltages. Install an external pullup resistor to the logic supply voltage which is compatible with your logic system. When the Power Good is [6] Allow the converter to eventually achieve its full-rated setpoint output out of limit, the FET is at saturation, approximately +0.2V output. Keep this voltage. Do not remain in ramp up/down mode indefinitely. The converter LOW (FALSE) pulldown current to less than 10mA. is characterized and meets all its specifications only at the setpoint volt- age (plus or minus any trim voltage). During the ramp-up phase, the con- Please note that Power Good is briefly false during Sequence ramp-up. verter is not considered fully in regulation. This may affect performance Ignore Power Good while in transition. with excessive high current loads at turn-on. [7] The Sequence is a sensitive input into the feedback control loop of the converter. Avoid noise and long leads on this input. Keep all wiring very short. Use shielding if necessary. Consider adding a small parallel ceramic capacitor across the Sequence/Track input (see Figure 16) to block any external high frequency noise. www.murata-ps.com/support MDC_LSM2 Series.D02∆ Page 15 of 17

LSM2 Series Single Output, Non-Isolated Selectable-Output POL DC/DC Converters MECHANICAL SPECIFICATIONS Case C62 10/16 Amp Models I/O CONNECTIONS Pin Function P66 1 On/Off Control 1.30 2 +Input (33.02) 3 Seq./Track 4 Common 0.34 5 +Output (8.64) 6 Trim 7 Sense 8 Power Good* SMT COPPER LEADS 0.085 * Power Good is only installed for 10 and 16 Amp COPLANAR 0.004 (2.16) “G” W3 models, otherwise pad 8 is not installed. Dimensions are in inches (mm) shown for ref. only. 0.950 (24.13) 0.120 5 EQ. SP. @ Third Angle Projection (30.48) 0.190 (4.83) 3 4 5 6 7 8 0.53 0.48 (12.19)(13.46) Tolerances (unless otherwise specified): .XX ± 0.02 (0.5) 2 1 .XXX ± 0.010 (0.25) Angles ± 2˚ 0.430 BOTTOM VIEW 0.075 (10.92) Components are shown for reference only. 0.062 (1.91) 0.112 (2.84) TYP. (1.57) TYP. 1.177 0.048 0.297 0.190 0.190 0.190 0.190 (29.90) (1.22) (7.54) (4.83) (4.83) (4.83) (4.83) 0.190 (4.83) Dimensions are in inches (mm) Drawing not to scale 8 7 6 5 4 3 0.405 0.430 (10.29) (10.92) 1 2 1.177 (29.90) RECOMMENDED PAD LAYOUT Recommended Pad Size: 0.15 x 0.10 (3.81 x 2.54) RECOMMENDED PAD LAYOUT Recommended Pad Size: 0.15 x 0.10 (3.81 x 2.54) www.murata-ps.com/support MDC_LSM2 Series.D02∆ Page 16 of 17

LSM2 Series Single Output, Non-Isolated Selectable-Output POL DC/DC Converters MECHANICAL SPECIFICATIONS (continued) I/O CONNECTIONS Case C63 6 Amp Models Pin Function P67 1 On/Off Control 2 +Input 1.10 3 Seq./Track (27.94) 4 Common 5 Trim 6 +Output 0.30 7 Power Good* (7.62) * Power Good is only included for 6 Amp “G” models. Otherwise pad 7 is not installed. SMT COPPER LEADS 0.160 (4.06) COPLANAR 0.004 0.160 (4.06) 0.020 (0.51) 0.160 (4.06) 0.190 (4.43) 0.480 (12.19) 0.190 7 6 5 4 3 3 EQ. SP. @ (4.43) 0.45 0.350 0.160 (4.06) (11.43) (8.89) 3 4 5 6 7 1 2 0.45 0.062 0.06 (1.52) 0.15 (1.57) 0.090 0.05 (11.43) (3.81) (2.29) (1.27) 2 1 1.10 (27.94) 0.350 RECOMMENDED PAD LAYOUT (8.89) 0.09 0.06 (1.52) Recommended Pad Size: 0.15 x 0.10 (3.81 x 2.54) 0.05 (2.29) (1.27) 0.062(1.58) TYP. Drawing not to scale TYP. 0.15 (3.81) BOTTOM VIEW 0.690 (17.53) Dimensions are in inches (mm) Drawing not to scale This product is subject to the following operating requirements Murata Power Solutions, Inc. and the Life and Safety Critical Application Sales Policy: 129 Flanders Road, Westborough, MA 01581 U.S.A. Refer to: http://www.murata-ps.com/requirements/ ISO 9001 and 14001 REGISTERED Murata Power Solutions, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change witho ut n oti ce. © 2018 Murata Power Solutions, Inc. www.murata-ps.com/support MDC_LSM2 Series.D02∆ Page 17 of 17