LPC2290 16/32-bit ARM microcontroller with CAN, 10-bit ADC and external memory interface Rev. 03 — 16 November 2006 Product data sheet 1. General description The LPC2290 microcontroller is based on a 16/32-bit ARM7TDMI-S CPU with real-time emulationandembeddedtracesupport.Forcriticalcodesizeapplications,thealternative 16-bit Thumb mode reduces code by more than 30% with minimal performance penalty. With its 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC,twoadvancedCANchannels,PWMchannelsanduptonineexternalinterruptpins this microcontroller is particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The LPC2290providesupto76GPIOsdependingonbusconfiguration.Withawiderangeof additional serial communications interfaces, it is also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark:Throughout the data sheet, the term ‘LPC2290’ will apply to devices with and without the /01 suffix. New devices will use the /01 suffix to differentiate from the original devices only when necessary. 2. Features 2.1 Enhancements introduced with LPC2290/01 device n CPU clock up to 72MHz and 64kB of on-chip static RAM. n Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original LPC2290. A port pin can be read at any time regardless of its function. n Dedicated result registers for ADC reduce interrupt overhead. n UART0/1 include fractional baud rate generator, auto-bauding capabilities and handshake flow-control fully implemented in hardware. n SSP serial controller supporting SPI, 4-wire SSI, and Microwire buses. 2.2 Key features common for LPC2290 and LPC2290/01 n 16/32-bit ARM7TDMI-S microcontroller in a LQFP144 package. n 16/64kB on-chip static RAM. n Serial bootloader using UART0 provides in-system download and programming capabilities. n EmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with the on-chip RealMonitor software as well as high-speed real-time tracing of instruction execution. n TwointerconnectedCANinterfaceswithadvancedacceptancefilters.Additionalserial interfaces include two UARTs (16C550), Fast I2C-bus (400kbit/s) and two SPIs.

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface n Eight channel 10-bit ADC with conversion time as low as 2.44m s. n Two 32-bit timers (with four capture and four compare channels), PWM unit (six outputs), Real-Time Clock (RTC) and watchdog. n Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses. n Configurable external memory interface with up to four banks, each up to 16MB and 8/16/32-bit data width. n Up to 76 general purpose I/O pins (5V tolerant). Up to nine edge/level sensitive external interrupt pins available. n 60/72MHz maximum CPU clock available from programmable on-chip PLL with settling time of 100m s. n On-chip crystal oscillator with an operating range of 1MHz to 30MHz. n Power saving modes include Idle and Power-down. n Processor wake-up from Power-down mode via external interrupt. n Individual enable/disable of peripheral functions for power optimization. n Dual power supply: u CPU operating voltage range of 1.65V to 1.95V (1.8V– 0.15V). u I/O power supply range of 3.0V to 3.6V (3.3V– 10%) with 5V tolerant I/O pads. 3. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC2290FBD144 LQFP144 plastic low profile quad flat package; SOT486-1 144leads; body 20· 20· 1.4mm LPC2290FBD144/01 LQFP144 plastic low profile quad flat package; SOT486-1 144leads; body 20· 20· 1.4mm 3.1 Ordering options Table 2. Ordering options Type number RAM CAN Enhancements Temperature range LPC2290FBD144 16kB 2 channels None - 40(cid:176) C to +85(cid:176) C LPC2290FBD144/01 64kB 2 channels Higher CPU clock, more - 40(cid:176) C to +85(cid:176) C on-chip SRAM, Fast I/Os, improved UARTs, added SSP, upgraded ADC LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 2 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface 4. Block diagram TMS(1) TDI(1) XTAL2 TRST(1) TCK(1) TDO(1) XTAL1 RST LPC2290 TEST/DEBUG CE LPC2290/01 INTERFACE N TRAULE PLL FUSNYCSTTIEOMNS ARM7TDMI-S TIOOD P1[31:16]P, P0[13[11::00]] FPAUSRTP GOESNEE I/ROA(3L) AHB BRIDGE EMULAM scylsotcekm IVNETCETRORRUEPDT CONTROLLER ARM7 local bus AMBA Advanced High-performance Bus(AHB) INTERNAL SRAM CONTROLLER AHB DECODER 16/64 kB AHB TO APB APB CS3 to CS0(2) SRAM BRIDGE DIVIDER A23 to A0(2) EXTERNAL MEMORY BLS3 to BLS0(2) CONTROLLER Advanced OE, WE(2) Peripheral Bus D31 to D0(2) (APB) SCL EINT3 to EINT0 EXTERNAL I2C-BUS SERIAL INTERRUPTS INTERFACE SDA 4 · CAP0 SCK0, SCK1 4 · CAP1 CAPTURE/ SPI AND SSP(3) MOSI0, MOSI1 4 · MAT0 COMPARE SERIAL INTERFACES MISO0, MISO1 TIMER 0/TIMER 1 0 AND 1 4 · MAT1 SSEL0, SSEL1 AIN3 to AIN0 TXD0, TXD1 A/D CONVERTER UART0/UART1 RXD0, RXD1 AIN7 to AIN4 DSR1, CTS1, DCD1, RI1 P0[30:0] TD2, TD1 P1[31:16], P1[1:0] GENERAL CAN P2[31:0] PURPOSE I/O RD2, RD1 P3[31:0] WATCHDOG PWM6 to PWM1 PWM0 TIMER SYSTEM REAL-TIME CLOCK CONTROL 002aaa796 (1) When test/debug interface is used, GPIO/other functions sharing these pins are not available. (2) Pins shared with GPIO. (3) Available in LPC2290/01 only. Fig 1. Block diagram LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 3 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface 5. Pinning information 5.1 Pinning 4 9 4 0 1 1 1 108 LPC2290 36 73 7 2 3 7 002aaa797 Fig 2. LQFP144 pinning LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 4 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface 5.2 Pin description Table 3. Pin description Symbol Pin Type Description P0.0 to P0.31 I/O Port0:Port0isa32-bitbidirectionalI/Oportwithindividualdirectioncontrols for each bit. The operation of port 0 pins depends upon the pin function selected via the Pin Connect Block. Pins 26 and 31 of port 0 are not available. P0.0/TXD0/ 42[1] I/O P0.0 —General purpose digital input/output pin. PWM1 O TXD0 —Transmitter output for UART0. O PWM1 —Pulse Width Modulator output 1. P0.1/RXD0/ 49[2] I/O P0.1 —General purpose digital input/output pin. PWM3/EINT0 I RXD0 —Receiver input for UART0. O PWM3 —Pulse Width Modulator output 3. I EINT0 —External interrupt 0 input P0.2/SCL/ 50[3] I/O P0.2 —General purpose digital input/output pin. CAP0.0 I/O SCL —I2C-bus clock input/output. Open-drain output (for I2C-bus compliance). I CAP0.0 —Capture input for Timer0, channel 0. P0.3/SDA/ 58[3] I/O P0.3 —General purpose digital input/output pin. MAT0.0/EINT1 I/O SDA —I2C-bus data input/output. Open-drain output (for I2C-bus compliance). O MAT0.0 —Match output for Timer0, channel 0. I EINT1 —External interrupt 1 input. P0.4/SCK0/ 59[1] I/O P0.4 —General purpose digital input/output pin. CAP0.1 I/O SCK0 —SerialclockforSPI0.SPIclockoutputfrommasterorinputtoslave. I CAP0.1 —Capture input for Timer0, channel 1. P0.5/MISO0/ 61[1] I/O P0.5 —General purpose digital input/output pin. MAT0.1 I/O MISO0 —Master In Slave OUT for SPI0. Data input to SPI master or data output from SPI slave. O MAT0.1 —Match output for Timer0, channel 1. P0.6/MOSI0/ 68[1] I/O P0.6 —General purpose digital input/output pin. CAP0.2 I/O MOSI0 —MasterOutSlaveInforSPI0.DataoutputfromSPImasterordata input to SPI slave. I CAP0.2 —Capture input for Timer0, channel 2. P0.7/SSEL0/ 69[2] I/O P0.7 —General purpose digital input/output pin. PWM2/EINT2 I SSEL0 —Slave Select for SPI0. Selects the SPI interface as a slave. O PWM2 —Pulse Width Modulator output 2. I EINT2 —External interrupt 2 input. P0.8/TXD1/ 75[1] I/O P0.8 —General purpose digital input/output pin. PWM4 O TXD1 —Transmitter output for UART1. O PWM4 —Pulse Width Modulator output 4. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 5 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface Table 3. Pin description …continued Symbol Pin Type Description P0.9/RXD1/ 76[2] I/O P0.9 —General purpose digital input/output pin. PWM6/EINT3 I RXD1 —Receiver input for UART1. O PWM6 —Pulse Width Modulator output 6. I EINT3 —External interrupt 3 input. P0.10/RTS1/ 78[1] I/O P0.10 —General purpose digital input/output pin. CAP1.0 O RTS1 —Request to Send output for UART1. I CAP1.0 —Capture input for Timer1, channel 0. P0.11/CTS1/ 83[1] I/O P0.11 —General purpose digital input/output pin. CAP1.1 I CTS1 —Clear to Send input for UART1. I CAP1.1 —Capture input for Timer1, channel 1. P0.12/DSR1/ 84[1] I/O P0.12 —General purpose digital input/output pin. MAT1.0 I DSR1 —Data Set Ready input for UART1. O MAT1.0 —Match output for Timer1, channel 0. P0.13/DTR1/ 85[1] I/O P0.13 —General purpose digital input/output pin. MAT1.1 O DTR1 —Data Terminal Ready output for UART1. O MAT1.1 —Match output for Timer1, channel 1. P0.14/DCD1/ 92[2] I/O P0.14 —General purpose digital input/output pin. EINT1 I DCD1 —Data Carrier Detect input for UART1. I EINT1 —External interrupt 1 input. Note:LOWonthispinwhileRESETisLOWforceson-chipbootloadertotake over control of the part after reset. P0.15/RI1/ 99[2] I/O P0.15 —General purpose digital input/output pin. EINT2 I RI1 —Ring Indicator input for UART1. I EINT2 —External interrupt 2 input. P0.16/EINT0/ 100[2] I/O P0.16 —General purpose digital input/output pin. MAT0.2/CAP0.2 I EINT0 —External interrupt 0 input. O MAT0.2 —Match output for Timer0, channel 2. I CAP0.2 —Capture input for Timer0, channel 2. P0.17/CAP1.2/ 101[1] I/O P0.17 —General purpose digital input/output pin. SCK1/MAT1.2 I CAP1.2 —Capture input for Timer1, channel 2. I/O SCK1 —Serial Clock for SPI1/SSP. SPI clock output from master or input to slave (SSP is available in LPC2290/01 only). O MAT1.2 —Match output for Timer1, channel 2. P0.18/CAP1.3/ 121[1] I/O P0.18 —General purpose digital input/output pin. MISO1/MAT1.3 I CAP1.3 —Capture input for Timer1, channel 3. I/O MISO1 —MasterInSlaveOutforSPI1/SSP.DatainputtoSPImasterordata output from SPI slave (SSP is available in LPC2290/01 only). O MAT1.3 —Match output for Timer1, channel 3. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 6 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface Table 3. Pin description …continued Symbol Pin Type Description P0.19/MAT1.2/ 122[1] I/O P0.19 —General purpose digital input/output pin. MOSI1/CAP1.2 O MAT1.2 —Match output for Timer1, channel 2. I/O MOSI1 —MasterOutSlaveInforSPI1/SSP.DataoutputfromSPImasteror data input to SPI slave (SSP is available in LPC2290/01 only). I CAP1.2 —Capture input for Timer1, channel 2. P0.20/MAT1.3/ 123[2] I/O P0.20 —General purpose digital input/output pin. SSEL1/EINT3 O MAT1.3 —Match output for Timer1, channel 3. I SSEL1 —Slave Select for SPI1/SSP. Selects the SPI interface as a slave (SSP is available in LPC2290/01 only). I EINT3 —External interrupt 3 input. P0.21/PWM5/ 4[1] I/O P0.21 —General purpose digital input/output pin. CAP1.3 O PWM5 —Pulse Width Modulator output 5. I CAP1.3 —Capture input for Timer1, channel 3. P0.22/CAP0.0/ 5[1] I/O P0.22 —General purpose digital input/output pin. MAT0.0 I CAP0.0 —Capture input for Timer0, channel 0. O MAT0.0 —Match output for Timer0, channel 0. P0.23/RD2 6[1] I/O P0.23 —General purpose digital input/output pin. I RD2 —CAN2 receiver input. P0.24/TD2 8[1] I/O P0.24 —General purpose digital input/output pin. O TD2 —CAN2 transmitter output. P0.25 21[1] I/O P0.25 —General purpose digital input/output pin. I RD1 —CAN1 receiver input. P0.27/AIN0/ 23[4] I/O P0.27 —General purpose digital input/output pin. CAP0.1/MAT0.1 I AIN0 —ADC, input 0. This analog input is always connected to its pin. I CAP0.1 —Capture input for Timer0, channel 1. O MAT0.1 —Match output for Timer0, channel 1. P0.28/AIN1/ 25[4] I/O P0.28 —General purpose digital input/output pin. CAP0.2/MAT0.2 I AIN1 —ADC, input 1. This analog input is always connected to its pin. I CAP0.2 —Capture input for Timer0, channel 2. O MAT0.2 —Match output for Timer0, channel 2. P0.29/AIN2/ 32[4] I/O P0.29 —General purpose digital input/output pin. CAP0.3/MAT0.3 I AIN2 —ADC, input 2. This analog input is always connected to its pin. I CAP0.3 —Capture input for Timer0, Channel 3. O MAT0.3 —Match output for Timer0, channel 3. P0.30/AIN3/ 33[4] I/O P0.30 —General purpose digital input/output pin. EINT3/CAP0.0 I AIN3 —ADC, input 3. This analog input is always connected to its pin. I EINT3 —External interrupt 3 input. I CAP0.0 —Capture input for Timer0, channel 0. P1.0 to P1.31 I/O Port1:Port1isa32-bitbidirectionalI/Oportwithindividualdirectioncontrols for each bit. The operation of port 1 pins depends upon the pin function selected via the Pin Connect Block. Pins 2 through 15 of port1 are not available. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 7 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface Table 3. Pin description …continued Symbol Pin Type Description P1.0/CS0 91[5] I/O P1.0 —General purpose digital input/output pin. O CS0 —LOW-active Chip Select 0 signal. (Bank 0 addresses range 0x8000 0000 to 0x80FF FFFF) P1.1/OE 90[5] I/O P1.1 —General purpose digital input/output pin. O OE —LOW-active Output Enable signal. P1.16/ 34[5] I/O P1.16 —General purpose digital input/output pin. TRACEPKT0 O TRACEPKT0 —Trace Packet, bit 0. Standard I/O port with internal pull-up. P1.17/ 24[5] I/O P1.17 —General purpose digital input/output pin. TRACEPKT1 O TRACEPKT1 —Trace Packet, bit 1. Standard I/O port with internal pull-up. P1.18/ 15[5] I/O P1.18 —General purpose digital input/output pin. TRACEPKT2 O TRACEPKT2 —Trace Packet, bit 2. Standard I/O port with internal pull-up. P1.19/ 7[5] I/O P1.19 —General purpose digital input/output pin. TRACEPKT3 O TRACEPKT3 —Trace Packet, bit 3. Standard I/O port with internal pull-up. P1.20/ 102[5] I/O P1.20 —General purpose digital input/output pin. TRACESYNC O TRACESYNC —Trace Synchronization. Standard I/O port with internal pull-up. Note: LOW on this pin whileRESET is LOW, enables pins P1[25:16] to operate as Trace port after reset. P1.21/ 95[5] I/O P1.21 —General purpose digital input/output pin. PIPESTAT0 O PIPESTAT0 —Pipeline Status, bit 0. Standard I/O port with internal pull-up. P1.22/ 86[5] I/O P1.22 —General purpose digital input/output pin. PIPESTAT1 O PIPESTAT1 —Pipeline Status, bit 1. Standard I/O port with internal pull-up. P1.23/ 82[5] I/O P1.23 —General purpose digital input/output pin. PIPESTAT2 O PIPESTAT2 —Pipeline Status, bit 2. Standard I/O port with internal pull-up. P1.24/ 70[5] I/O P1.24 —General purpose digital input/output pin. TRACECLK O TRACECLK —Trace Clock. Standard I/O port with internal pull-up. P1.25/EXTIN0 60[5] I/O P1.25 —General purpose digital input/output pin. I EXTIN0 —External Trigger Input. Standard I/O with internal pull-up. P1.26/RTCK 52[5] I/O P1.26 —General purpose digital input/output pin. I/O RTCK —Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional pin with internal pull-up. Note: LOW on this pin whileRESET is LOW, enables pins P1[31:26] to operate as Debug port after reset. P1.27/TDO 144[5] I/O P1.27 —General purpose digital input/output pin. O TDO —Test Data out for JTAG interface. P1.28/TDI 140[5] I/O P1.28 —General purpose digital input/output pin. I TDI —Test Data in for JTAG interface. P1.29/TCK 126[5] I/O P1.29 —General purpose digital input/output pin. I TCK —Test Clock for JTAG interface. P1.30/TMS 113[5] I/O P1.30 —General purpose digital input/output pin. I TMS —Test Mode Select for JTAG interface. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 8 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface Table 3. Pin description …continued Symbol Pin Type Description P1.31/TRST 43[5] I/O P1.31 —General purpose digital input/output pin. I TRST —Test Reset for JTAG interface. P2.0 to P2.31 I/O Port 2 —Port 2 is a 32-bit bidirectional I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the Pin Connect Block. P2.0/D0 98[5] I/O P2.0 —General purpose digital input/output pin. I/O D0 —External memory data line 0. P2.1/D1 105[5] I/O P2.1 —General purpose digital input/output pin. I/O D1 —External memory data line 1. P2.2/D2 106[5] I/O P2.2 —General purpose digital input/output pin. I/O D2 —External memory data line 2. P2.3/D3 108[5] I/O P2.3 —General purpose digital input/output pin. I/O D3 —External memory data line 3. P2.4/D4 109[5] I/O P2.4 —General purpose digital input/output pin. I/O D4 —External memory data line 4. P2.5/D5 114[5] I/O P2.5 —General purpose digital input/output pin. I/O D5 —External memory data line 5. P2.6/D6 115[5] I/O P2.6 —General purpose digital input/output pin. I/O D6 —External memory data line 6. P2.7/D7 116[5] I/O P2.7 —General purpose digital input/output pin. I/O D7 —External memory data line 7. P2.8/D8 117[5] I/O P2.8 —General purpose digital input/output pin. I/O D8 —External memory data line 8. P2.9/D9 118[5] I/O P2.9 —General purpose digital input/output pin. I/O D9 —External memory data line 9. P2.10/D10 120[5] I/O P2.10 —General purpose digital input/output pin. I/O D10 —External memory data line 10. P2.11/D11 124[5] I/O P2.11 —General purpose digital input/output pin. I/O D11 —External memory data line 11. P2.12/D12 125[5] I/O P2.12 —General purpose digital input/output pin. I/O D12 —External memory data line 12. P2.13/D13 127[5] I/O P2.13 —General purpose digital input/output pin. I/O D13 —External memory data line 13. P2.14/D14 129[5] I/O P2.14 —General purpose digital input/output pin. I/O D14 —External memory data line 14. P2.15/D15 130[5] I/O P2.15 —General purpose digital input/output pin. I/O D15 —External memory data line 15. P2.16/D16 131[5] I/O P2.16 —General purpose digital input/output pin. I/O D16 —External memory data line 16. P2.17/D17 132[5] I/O P2.17 —General purpose digital input/output pin. I/O D17 —External memory data line 17. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 9 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface Table 3. Pin description …continued Symbol Pin Type Description P2.18/D18 133[5] I/O P2.18 —General purpose digital input/output pin. I/O D18 —External memory data line 18. P2.19/D19 134[5] I/O P2.19 —General purpose digital input/output pin. I/O D19 —External memory data line 19. P2.20/D20 136[5] I/O P2.20 —General purpose digital input/output pin. I/O D20 —External memory data line 20. P2.21/D21 137[5] I/O P2.21 —General purpose digital input/output pin. I/O D21 —External memory data line 21. P2.22/D22 1[5] I/O P2.22 —General purpose digital input/output pin. I/O D22 —External memory data line 22. P2.23/D23 10[5] I/O P2.23 —General purpose digital input/output pin. I/O D23 —External memory data line 23. P2.24/D24 11[5] I/O P2.24 —General purpose digital input/output pin. I/O D24 —External memory data line 24. P2.25/D25 12[5] I/O P2.25 —General purpose digital input/output pin. I/O D25 —External memory data line 25. P2.26/D26/ 13[5] I/O P2.26 —General purpose digital input/output pin. BOOT0 I/O D26 —External memory data line 26. I BOOT0 —WhileRESET is low, together with BOOT1 controls booting and internal operation. Internal pull-up ensures high state if pin is left unconnected. P2.27/D27/ 16[5] I/O P2.27 —General purpose digital input/output pin. BOOT1 I/O D27 —External memory data line 27. I BOOT1 —WhileRESET is low, together with BOOT0 controls booting and internal operation. Internal pull-up ensures high state if pin is left unconnected. BOOT1:0=00 selects 8-bit memory on CS0 for boot. BOOT1:0=01 selects 16-bit memory on CS0 for boot. BOOT1:0=10 selects 32-bit memory on CS0 for boot. BOOT1:0=11 selects internal flash memory. P2.28/D28 17[5] I/O P2.28 —General purpose digital input/output pin. I/O D28 —External memory data line 28. P2.29/D29 18[5] I/O P2.29 —General purpose digital input/output pin. I/O D29 —External memory data line 29. P2.30/D30/ 19[2] I/O P2.30 —General purpose digital input/output pin. AIN4 I/O D30 —External memory data line 30. I AIN4 —ADC, input 4. This analog input is always connected to its pin. P2.31/D31/ 20[2] I/O P2.31 —General purpose digital input/output pin. AIN5 I/O D31 —External memory data line 31. I AIN5 —ADC, input 5. This analog input is always connected to its pin. P3.0 to P3.31 I/O Port 3 —Port 3 is a 32-bit bidirectional I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the Pin Connect Block. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 10 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface Table 3. Pin description …continued Symbol Pin Type Description P3.0/A0 89[5] I/O P3.0 —General purpose digital input/output pin. O A0 —External memory address line 0. P3.1/A1 88[5] I/O P3.1 —General purpose digital input/output pin. O A1 —External memory address line 1. P3.2/A2 87[5] I/O P3.2 —General purpose digital input/output pin. O A2 —External memory address line 2. P3.3/A3 81[5] I/O P3.3 —General purpose digital input/output pin. O A3 —External memory address line 3. P3.4/A4 80[5] I/O P3.4 —General purpose digital input/output pin. O A4 —External memory address line 4. P3.5/A5 74[5] I/O P3.5 —General purpose digital input/output pin. O A5 —External memory address line 5. P3.6/A6 73[5] I/O P3.6 —General purpose digital input/output pin. O A6 —External memory address line 6. P3.7/A7 72[5] I/O P3.7 —General purpose digital input/output pin. O A7 —External memory address line 7. P3.8/A8 71[5] I/O P3.8 —General purpose digital input/output pin. O A8 —External memory address line 8. P3.9/A9 66[5] I/O P3.9 —General purpose digital input/output pin. O A9 —External memory address line 9. P3.10/A10 65[5] I/O P3.10 —General purpose digital input/output pin. O A10 —External memory address line 10. P3.11/A11 64[5] I/O P3.11 —General purpose digital input/output pin. O A11 —External memory address line 11. P3.12/A12 63[5] I/O P3.12 —General purpose digital input/output pin. O A12 —External memory address line 12. P3.13/A13 62[5] I/O P3.13 —General purpose digital input/output pin. O A13 —External memory address line 13. P3.14/A14 56[5] I/O P3.14 —General purpose digital input/output pin. O A14 —External memory address line 14. P3.15/A15 55[5] I/O P3.15 —General purpose digital input/output pin. O A15 —External memory address line 15. P3.16/A16 53[5] I/O P3.16 —General purpose digital input/output pin. O A16 —External memory address line 16. P3.17/A17 48[5] I/O P3.17 —General purpose digital input/output pin. O A17 —External memory address line 17. P3.18/A18 47[5] I/O P3.18 —General purpose digital input/output pin. O A18 —External memory address line 18. P3.19/A19 46[5] I/O P3.19 —General purpose digital input/output pin. O A19 —External memory address line 19. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 11 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface Table 3. Pin description …continued Symbol Pin Type Description P3.20/A20 45[5] I/O P3.20 —General purpose digital input/output pin. O A20 —External memory address line 20. P3.21/A21 44[5] I/O P3.21 —General purpose digital input/output pin. O A21 —External memory address line 21. P3.22/A22 41[5] I/O P3.22 —General purpose digital input/output pin. O A22 —External memory address line 22. P3.23/A23/ 40[5] I/O P3.23 —General purpose digital input/output pin. XCLK I/O A23 —External memory address line 23. O XCLK —Clock output. P3.24/CS3 36[5] I/O P3.24 —General purpose digital input/output pin. O CS3 —LOW-active Chip Select 3 signal. (Bank 3 addresses range 0x8300 0000 to 0x83FF FFFF) P3.25/CS2 35[5] I/O P3.25 —General purpose digital input/output pin. O CS2 —LOW-active Chip Select 2 signal. (Bank 2 addresses range 0x8200 0000 to 0x82FF FFFF) P3.26/CS1 30[5] I/O P3.26 —General purpose digital input/output pin. O CS1 —LOW-active Chip Select 1 signal. (Bank 1 addresses range 0x8100 0000 to 0x81FF FFFF) P3.27/WE 29[5] I/O P3.27 —General purpose digital input/output pin. O WE —LOW-active Write enable signal. P3.28/BLS3/ 28[2] I/O P3.28 —General purpose digital input/output pin. AIN7 O BLS3 —LOW-active Byte Lane Select signal (Bank 3). I AIN7 —ADC, input 7. This analog input is always connected to its pin. P3.29/BLS2/ 27[4] I/O P3.29 —General purpose digital input/output pin. AIN6 O BLS2 —LOW-active Byte Lane Select signal (Bank 2). I AIN6 —ADC, input 6. This analog input is always connected to its pin. P3.30/BLS1 97[4] I/O P3.30 —General purpose digital input/output pin. O BLS1 —LOW-active Byte Lane Select signal (Bank 1). P3.31/BLS0 96[4] I/O P3.31 —General purpose digital input/output pin. O BLS0 —LOW-active Byte Lane Select signal (Bank 0). TD1 22[5] O TD1: CAN1 transmitter output. RESET 135[6] I ExternalResetinput:ALOWonthispinresetsthedevice,causingI/Oports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5V tolerant. XTAL1 142[7] I Input to the oscillator circuit and internal clock generator circuits. XTAL2 141[7] O Output from the oscillator amplifier. V 3, 9, 26, 38, I Ground: 0V reference. SS 54, 67, 79, 93,103,107, 111, 128 V 139 I Analog ground: 0V reference. This should nominally be the same voltage SSA as V , but should be isolated to minimize noise and error. SS LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 12 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface Table 3. Pin description …continued Symbol Pin Type Description V 138 I PLL analog ground: 0V reference. This should nominally be the same SSA(PLL) voltage as V , but should be isolated to minimize noise and error. SS V 37, 110 I 1.8V core power supply: This is the power supply voltage for internal DD(1V8) circuitry. V 143 I Analog 1.8V core power supply: This is the power supply voltage for DDA(1V8) internal circuitry. This should be nominally the same voltage as V but DD(1V8) should be isolated to minimize noise and error. V 2,31,39,51, I 3.3V pad power supply: This is the power supply voltage for the I/O ports. DD(3V3) 57, 77, 94, 104,112,119 V 14 I Analog3.3Vpadpowersupply:Thisshouldbenominallythesamevoltage DDA(3V3) as V but should be isolated to minimize noise and error. DD(3V3) [1] 5V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10ns slew rate control. [2] 5V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10ns slew rate control. If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3ns. [3] Open-drain 5V tolerant digital I/O I2C-bus 400kHz specification compatible pad. It requires external pull-up to provide an output functionality. [4] 5VtolerantpadprovidingdigitalI/O(withTTLlevelsandhysteresisand10nsslewratecontrol)andanaloginputfunction.Ifconfigured for a digital input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital section of the pad is disabled. [5] 5V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10ns slew rate control. The pull-up resistor’s value ranges from 60kW to 300kW . [6] 5V tolerant pad providing digital input (with TTL levels and hysteresis) function only. [7] Pad provides special analog functionality. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 13 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface 6. Functional description 6.1 Architectural overview The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on RISC principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed CISC. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipelinetechniquesareemployedsothatallpartsoftheprocessingandmemorysystems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets: • The standard 32-bit ARM set. • A 16-bit Thumb set. The Thumb set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system. 6.2 On-chip SRAM On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed as 8-bit, 16-bit, and 32-bit. TheLPC2290 provides 16kB of SRAM and the LPC2290/01 provides 64kB of SRAM. 6.3 Memory map TheLPC2290 memory maps incorporate several distinct regions, as shown inFigure3. In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either on-chip bootloader, external memory BANK0 or on-chip static RAM. This is described in Section 6.18 “System control”. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 14 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface 4.0 GB 0xFFFF FFFF AHB PERIPHERALS 0xF000 0000 3.75 GB 0xEFFF FFFF VPB PERIPHERALS 0xE000 0000 3.5 GB 0xDFFF FFFF RESERVED ADDRESS SPACE 3.0 GB 0x8400 0000 0x83FF FFFF EXTERNAL MEMORY BANK3 0x8300 0000 0x82FF FFFF EXTERNAL MEMORY BANK2 0x8200 0000 0x81FF FFFF EXTERNAL MEMORY BANK1 0x8100 0000 0x80FF FFFF EXTERNAL MEMORY BANK0 0x8000 0000 2.0 GB 0x7FFF FFFF BOOT BLOCK (RE-MAPPED FROM ON-CHIP ROM MEMORY 0x7FFF E000 0x7FFF DFFF RESERVED ADDRESS SPACE 0x4001 0000 0x4000 FFFF 64 KBYTE ON-CHIP STATIC RAM (/01 ONLY) 0x4000 4000 0x4000 3FFF 16 KBYTE ON-CHIP STATIC RAM 0x4000 0000 1.0 GB 0x3FFF FFFF RESERVED ADDRESS SPACE 0x0000 0000 0.0 GB 002aaa798 Fig 3. LPC2290 and LPC2290/01 memory map 6.4 Interrupt controller The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment schememeansthatprioritiesofinterruptsfromthevariousperipheralscanbedynamically assigned and adjusted. FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possibleFIQlatencyisachievedwhenonlyonerequestisclassifiedasFIQ,becausethen the FIQ service routine can simply start dealing with that device. But if more than one requestisassignedtotheFIQclass,theFIQserviceroutinecanreadawordfromtheVIC that identifies which FIQ source(s) is (are) requesting an interrupt. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 15 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface VectoredIRQshavethemiddlepriority.Sixteenoftheinterruptrequestscanbeassigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority. The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are requesting, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwiseitprovidestheaddressofadefaultroutinethatissharedbyallthenon-vectored IRQs. The default routine can read another VIC register to see what IRQs are active. 6.4.1 Interrupt sources Table4liststheinterruptsourcesforeachperipheralfunction.Eachperipheraldevicehas one interrupt line connected to the VIC, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Table 4. Interrupt sources Block Flag(s) VIC channel # WDT Watchdog Interrupt (WDINT) 0 - Reserved for software interrupts only 1 ARM Core EmbeddedICE, DbgCommRx 2 ARM Core EmbeddedICE, DbgCommTx 3 Timer 0 Match 0 to 3 (MR0, MR1, MR2, MR3) 4 Capture 0 to 3 (CR0, CR1, CR2, CR3) Timer1 Match 0 to 3 (MR0, MR1, MR2, MR3) 5 Capture 0 to 3 (CR0, CR1, CR2, CR3) UART0 RX Line Status (RLS) 6 Transmit Holding Register Empty (THRE) RX Data Available (RDA) Character Time-out Indicator (CTI) Auto-Baud Time-Out (ABTO) (available in LPC2290/01 only) End of Auto-Baud (ABEO) UART1 RX Line Status (RLS) 7 Transmit Holding Register empty (THRE) RX Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) Auto-Baud Time-Out (ABTO) (available in LPC2290/01 only) End of Auto-Baud (ABEO) PWM0 Match 0 to 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) 8 I2C-bus SI (state change) 9 SPI0 SPIF, MODF 10 LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 16 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface Table 4. Interrupt sources …continued Block Flag(s) VIC channel # SPI1/SSP Source: SPI1 SPI Interrupt Flag (SPIF), Mode Fault (MODF) 11 Source: SSP (available in LPC2290/01 only) TX FIFO at least half empty (TXRIS) RX FIFO at least half full (RXRIS) Receive Timeout condition (RTRIS) Receive Overrun (RORRIS) PLL PLL Lock (PLOCK) 12 RTC RTCCIF (Counter Increment), RTCALF (Alarm) 13 System Control External Interrupt 0 (EINT0) 14 External Interrupt 1 (EINT1) 15 External Interrupt 2 (EINT2) 16 External Interrupt 3 (EINT3) 17 A/D ADC 18 CAN 1 ORed CAN Acceptance Filter 19 CAN1 (TX int, RX int) 20, 21 CAN2 (TX int, RX int) 22, 23 6.5 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins priortobeingactivated,andpriortoanyrelatedinterrupt(s)beingenabled.Activityofany enabled peripheral function that is not mapped to a related pin should be considered undefined. 6.6 External memory controller The external Static Memory Controller is a module which provides an interface between the system bus and external (off-chip) memory devices. It provides support for up to four independently configurable memory banks (16MB each with byte lane enable control) simultaneously.EachmemorybankiscapableofsupportingSRAM,ROM,flashEPROM, burst ROM memory, or some external I/O devices. Each memory bank may be 8-bit, 16-bit, or 32-bit wide. 6.7 General purpose parallel I/O and Fast I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registersallowsettingorclearinganynumberofoutputssimultaneously.Thevalueofthe output register may be read back, as well as the current state of the port pins. 6.7.1 Features • Direction control of individual bits. • Separate control of output set and clear. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 17 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface • All I/O default to inputs after reset. 6.7.2 Fast I/O features available in LPC2290/01 only • Fast I/O registers are located on the ARM local bus for the fastest possible I/O timing. • All GPIO registers are byte addressable. • Entire port value can be written in one instruction. • Mask registers allow single instruction to set or clear any number of bits in one port. 6.8 10-bit ADC The LPC2290 each contain a single 10-bit successive approximation ADC with eight multiplexed channels. 6.8.1 Features • Measurement range of 0V to 3.3V. • Capable of performing more than 400000 10-bit samples per second. • Burst conversion mode for single or multiple inputs. • Optional conversion on transition on input pin or Timer Match signal. 6.8.2 ADC features available in LPC2290/01 only • Every analog input has a dedicated result register to reduce interrupt overhead. • Every analog input can generate an interrupt once the conversion is completed. 6.9 CAN controllers and acceptance filter TheLPC2290containstwoCANcontrollers.TheCANisaserialcommunicationsprotocol whichefficientlysupportsdistributedreal-timecontrolwithaveryhighlevelofsecurity.Its domain of application ranges from high-speed networks to low cost multiplex wiring. 6.9.1 Features • Data rates up to 1Mbit/s on each bus. • 32-bit register and RAM access. • Compatible with CAN specification 2.0B, ISO 11898-1. • GlobalAcceptanceFilterrecognizes11-bitand29-bitRXidentifiersforallCANbuses. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard identifiers. • Full CAN messages can generate interrupts. 6.10 UARTs The LPC2290 contains two UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface. 6.10.1 Features • 16B Receive and Transmit FIFOs. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 18 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points at 1B, 4B, 8B, and 14B. • Built-in baud rate generator. • Standard modem interface signals included on UART1. 6.10.2 UART features available in LPC2290/01 only • ThetransmissionFIFOcontrolenablesimplementationofsoftware(XON/XOFF)flow control on both UARTs and hardware (CTS/RTS) flow control on UART1 only. • Fractional baud rate generator enables standard baud rates such as 115200 to be achieved with any crystal frequency above 2 MHz. • Auto-bauding. • Auto-CTS/RTS flow-control fully implemented in hardware. 6.11 I2C-bus serial I/O controller The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receiverscanoperateineithermasterorslavemode,dependingonwhetherthechiphas toinitiateadatatransferorisonlyaddressed.TheI2C-busisamulti-masterbus,itcanbe controlled by more than one bus master connected to it. The I2C-bus implemented in LPC2290 supports bit rate up to 400kbit/s (Fast I2C-bus). 6.11.1 Features • Compliant with standard I2C-bus interface. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serialclocksynchronizationallowsdeviceswithdifferentbitratestocommunicatevia one serial bus. • Serialclocksynchronizationcanbeusedasahandshakemechanismtosuspendand resume serial transfer. • The I2C-bus may be used for test and diagnostic purposes. 6.12 SPI serial I/O controller The LPC2290 contains two SPIs. The SPI is a full duplex serial interface, designed to be abletohandlemultiplemastersandslavesconnectedtoagivenbus.Onlyasinglemaster andasingleslavecancommunicateontheinterfaceduringagivendatatransfer.Duringa data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 19 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface 6.12.1 Features • Compliant with SPI specification. • Synchronous, serial, full duplex, communication. • Combined SPI master and slave. • Maximum data bit rate of one eighth of the input clock rate. 6.13 SSP serial I/O controller (available in LPC2290/01 only) The LPC2290/01 contains one Serial Synchronous Port controller (SSP). The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. However, only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. Often only one of these data flows carries meaningful data. The SSP and SPI1 share the same pins on LPC2290/01. After a reset, SPI1 is enabled and SSP is disabled. 6.13.1 Features • Synchronous Serial Communication. • 8-frame FIFOs for both transmit and receive. • Compatible with Motorola SPI, 4-wire TI SSI and National Semiconductor Microwire buses. • Master or slave operation. • Four bits to 16 bits per SPI frame. 6.14 General purpose timers The TIMER0 and TIMER1 are designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them. 6.14.1 Features • A 32-bit Timer/Counter with a programmable 32-bit prescaler. • Four 32-bit capture channels per timer that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 20 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface • Four external outputs per timer corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. 6.14.2 Timer features available in LPC2290/01 only • Timers can count cycles of the externally supplied clock providing external event counting functionality 6.15 Watchdog timer Thepurposeofthewatchdogistoresetthemicrocontrollerwithinareasonableamountof time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time. 6.15.1 Features • Internally resets chip if not periodically reloaded. • Debug mode. • Enabledbysoftwarebutrequiresahardwareresetorawatchdogreset/interrupttobe disabled. • Incorrect/incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal pre-scaler. • Selectabletimeperiodfrom(T · 256· 4)to(T · 232· 4)inmultiplesof cy(PCLK) cy(PCLK) T · 4. cy(PCLK) 6.16 Real-time clock The Real-Time Clock (RTC) is designed to provide a set of counters to measure time whennormaloridleoperatingmodeisselected.TheRTChasbeendesignedtouselittle power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode). 6.16.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra-low power design to support battery powered systems. • ProvidesSeconds,Minutes,Hours,DayofMonth,Month,Year,DayofWeek,andDay of Year. • Programmable Reference Clock Divider allows adjustment of the RTC to match various crystal frequencies. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 21 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface 6.17 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2290. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is also based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be usedformoreapplications.Forinstance,multi-phasemotorcontroltypicallyrequiresthree non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (MR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is thesameforallPWMoutputs.MultiplesingleedgecontrolledPWMoutputswillallhavea rising edge at the beginning of each PWM cycle, when an MR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the MR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). 6.17.1 Features • Seven match registers allow up to six single edge controlled or three double edge controlled PWM outputs, or a mix of both types. • The match registers also allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the outputisaconstantLOW.DoubleedgecontrolledPWMoutputscanhaveeitheredge occur at any position within a cycle. This allows for both positive going and negative going pulses. • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 22 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface • Match register updates are synchronized with pulse outputs to prevent generation of erroneouspulses.Softwaremust‘release’newmatchvaluesbeforetheycanbecome effective. • May be used as a standard timer if the PWM mode is not enabled. • A 32-bit Timer/Counter with a programmable 32-bit prescaler. 6.18 System control 6.18.1 Crystal oscillator The oscillator supports crystals in the range of 1MHz to 30MHz. The oscillator output frequencyiscalledf andtheARMprocessorclockfrequencyisreferredtoasCCLKfor osc purposes of rate equations, etc. f and CCLK are the same value unless the PLL is osc running and connected. Refer toSection 6.18.2 “PLL” for additional information. 6.18.2 PLL The PLL accepts an input clock frequency in the range of 10MHz to 25MHz. The input frequency is multiplied up into the range of 10MHz to 60MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multipliervaluecannotbehigherthan6onthisfamilyofmicrocontrollersduetotheupper frequency limit of the CPU). The CCO operates in the range of 156MHz to 320MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while thePLLisprovidingthedesiredoutputfrequency.Theoutputdividermaybesettodivide by2,4,8,or16toproducetheoutputclock.Sincetheminimumoutputdividervalueis2, itisinsuredthatthePLLoutputhasa50%dutycycle.ThePLListurnedoffandbypassed following a chip reset and may be enabled by software. The program must configure and activatethePLL,waitforthePLLtoLock,thenconnecttothePLLasaclocksource.The PLL settling time is 100m s. 6.18.3 Reset and wake-up timer ResethastwosourcesontheLPC2290:theRESETpinandwatchdogreset.TheRESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by anysourcestartstheWake-upTimer(seeWake-upTimerdescriptionbelow),causingthe internalchipresettoremainasserteduntiltheexternalresetisde-asserted,theoscillator is running, a fixed number of clocks have passed, and the on-chip flash controller has completed its initialization. Whentheinternalresetisremoved,theprocessorbeginsexecutingataddress0,whichis the reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined values. The Wake-up Timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. Thisisimportantatpower-on,alltypesofreset,andwheneveranyoftheaforementioned functionsareturnedoffforanyreason.Sincetheoscillatorandotherfunctionsareturned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the Wake-up Timer. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 23 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on manyfactors,includingtherateofV ramp(inthecaseofpower-on),thetypeofcrystal DD and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 6.18.4 External interrupt inputs The LPC2290 include up to nine edge or level sensitive External Interrupt Inputs as selectable pin functions. When the pins are combined, external events can be processed asfourindependentinterruptsignals.TheExternalInterruptInputscanoptionallybeused to wake up the processor from Power-down mode. 6.18.5 Memory mapping control The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x00000000. Vectors may be mapped to the bottom of the on-chip flash memory, or to the on-chip static RAM. This allows code running in different memory spaces to have control of the interrupts. 6.18.6 Power control The LPC2290 support two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. InPower-downmode,theoscillatorisshutdownandthechipreceivesnointernalclocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode and the logic levels of chip output pins remain static.ThePower-downmodecanbeterminatedandnormaloperationresumedbyeither a reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero. A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. 6.18.7 APB bus TheAPBdividerdeterminestherelationshipbetweentheprocessorclock(CCLK)andthe clockusedbyperipheraldevices(PCLK).TheAPBdividerservestwopurposes.Thefirst is to provide peripherals with the desired PCLK via APB bus so that they can operate at the speed chosen for the ARM processor. In order to achieve this, the APB bus may be slowed down to1⁄ to1⁄ of the processor clock rate. Because the APB bus must work 2 4 properly at power-up (and its timing cannot be altered if it does not work since the APB divider control registers reside on the APB bus), the default condition at reset is for the APB bus to run at1⁄ of the processor clock rate. The second purpose of the APB divider 4 is to allow power savings when an application does not require any peripherals to run at the full processor rate. Because the APB divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 24 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface 6.19 Emulation and debugging The LPC2290 support emulation and debugging via a JTAG serial port. A trace port allowstracingprogramexecution.Debuggingandtracefunctionsaremultiplexedonlywith GPIOs on Port 1. This means that all communication, timer and interface peripherals residingonPort0areavailableduringthedevelopmentanddebuggingphaseastheyare when the application is run in the embedded system itself. 6.19.1 EmbeddedICE Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the remote debug protocol commands to the JTAG data needed to access the ARM core. The ARM core has a Debug Communication Channel function built-in. The debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The debug communication channel is accessed as a coprocessor 14 by the program running on the ARM7TDMI-S core. The debug communication channel allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The debug communication channel data and control registers are mapped in to addresses in the EmbeddedICE logic. 6.19.2 Embedded trace Since the LPC2290 has significant amounts of on-chip memory, it is not possible to determinehowtheprocessorcoreisoperatingsimplybyobservingtheexternalpins.The Embedded Trace Macrocell (ETM) provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to the trace port. TheETMisconnecteddirectlytotheARMcoreandnottothemainAMBAsystembus.It compresses the trace information and exports it through a narrow trace port. An external trace port analyzer must capture the trace information under software debugger control. Instructiontrace(orPCtrace)showstheflowofexecutionoftheprocessorandprovidesa list of all the instructions that were executed. Instruction trace is significantly compressed byonlybroadcastingbranchaddressesaswellasasetofstatussignalsthatindicatethe pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requiresastaticimageofthecodebeingexecuted.Self-modifyingcodecannotbetraced because of this restriction. 6.19.3 RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC (Debug Communications Channel), which is present in the EmbeddedICE logic. The LPC2290 contain a specific configuration of RealMonitor software programmed into the on-chip flash memory. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 25 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit V supply voltage (1.8 V) internal rail - 0.5 +2.5 V DD(1V8) V supply voltage (3.3 V) external rail - 0.5 +3.6 V DD(3V3) V analog supply voltage (3.3V) - 0.5 +4.6 V DDA(3V3) V analog input voltage - 0.5 +5.1 V IA V input voltage 5V tolerant I/O pins [2][3] - 0.5 +6.0 V I other I/O pins [2][4] - 0.5 V + 0.5 V DD(3V3) I supply current per supply pin [5] - 100 mA DD I ground current per ground pin [5] - 100 mA SS T storage temperature [6] - 65 +150 (cid:176) C stg P total power dissipation (per based on package heat - 1.5 W tot(pack) package) transfer,notdevicepower consumption V electrostatic discharge voltage human body model; all [7] - 2000 +2000 V esd pins [1] The following applies toTable5: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive staticcharge.Nonetheless,itissuggestedthatconventionalprecautionsbetakentoavoidapplyinggreaterthantheratedmaximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V unless SS otherwise noted. [2] Including voltage on outputs in 3-state mode. [3] Only valid when the V supply voltage is present. DD(3V3) [4] Not to exceed 4.6 V. [5] The peak current is limited to 25 times the corresponding maximum current. [6] Dependent on package type. [7] Human body model: equivalent to discharging a 100pF capacitor through a 1.5kW series resistor. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 26 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface 8. Static characteristics Table 6. Static characteristics T =- 40(cid:176) C to +85(cid:176) C for industrial applications, unless otherwise specified. amb Symbol Parameter Conditions Min Typ[1] Max Unit V supply voltage (1.8 V) internal rail 1.65 1.8 1.95 V DD(1V8) V supply voltage (3.3 V) external rail 3.0 3.3 3.6 V DD(3V3) V analog supply voltage 2.5 3.3 3.6 V DDA(3V3) (3.3V) Standard port pins,RESET, RTCK I LOW-level input current V =0V; no pull-up - - 3 m A IL I I HIGH-level input current V =V ; no pull-down - - 3 m A IH I DD(3V3) I OFF-state output current V =0V, V =V ; - - 3 m A OZ O O DD(3V3) nopull-up/down I I/O latch-up current - (0.5V ) < V < 100 - - mA latch DD(3V3) I (1.5V ); T < 125(cid:176) C DD(3V3) j V input voltage [2][3][4] 0 - 5.5 V I V output voltage output active 0 - V V O DD(3V3) V HIGH-level input voltage 2.0 - - V IH V LOW-level input voltage - - 0.8 V IL V hysteresis voltage - 0.4 - V hys V HIGH-level output voltage I =- 4 mA [5] V - 0.4 - - V OH OH DD(3V3) V LOW-level output voltage I =- 4 mA [5] - - 0.4 V OL OL I HIGH-level output current V =V - 0.4V [5] - 4 - - mA OH OH DD(3V3) I LOW-level output current V =0.4V [5] 4 - - mA OL OL I HIGH-level short-circuit V =0V [6] - - - 45 mA OHS OH output current I LOW-level short-circuit V =V [6] - - 50 mA OLS OL DD(3V3) output current I pull-down current V =5V [7] 10 50 150 m A pd I I pull-up current V =0V [8] - 15 - 50 - 85 m A pu I V < V < 5V [7] 0 0 0 m A DD(3V3) I I active mode supply V =1.8V, - 50 - mA DD(act) DD(1V8) current CCLK=60MHz, T =25(cid:176) C, code amb while(1){} executed from flash, no active peripherals I Power-downmodesupply V =1.8V, - 10 - m A DD(pd) DD(1V8) current T =25(cid:176) C, amb V =1.8V, - 110 500 m A DD(1V8) T =85(cid:176) C amb V =1.8V, - 300 1000 m A DD(1V8) T =125(cid:176) C amb LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 27 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface Table 6. Static characteristics …continued T =- 40(cid:176) C to +85(cid:176) C for industrial applications, unless otherwise specified. amb Symbol Parameter Conditions Min Typ[1] Max Unit I2C-bus pins V HIGH-level input voltage 0.7V - - V IH DD(3V3) V LOW-level input voltage - - 0.3V V IL DD(3V3) V hysteresis voltage - 0.5V - V hys DD(3V3) V LOW-level output voltage I =3 mA [5] - - 0.4 V OL OLS I input leakage current V =V ; to V - 2 4 m A LI I DD(3V3) SS V =5V - 10 22 m A I Oscillator pins V input voltage on pin 0 - 1.8 V i(XTAL1) XTAL1 V output voltage on pin 0 - 1.8 V o(XTAL2) XTAL2 [1] Typical ratings are not guaranteed. The values listed are at room temperature (+25(cid:176) C), nominal supply voltages. [2] Including voltage on outputs in 3-state mode. [3] V supply voltages must be present. DD(3V3) [4] 3-state outputs go into 3-state mode when V is grounded. DD(3V3) [5] Accounts for 100mV voltage drop in all supply lines. [6] Only allowed for a short time period. [7] Minimum condition for V =4.5V, maximum condition for V =5.5V. I I [8] Applies to P1[25:16]. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 28 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface Table 7. ADC static characteristics V =2.5V to 3.6V; T =- 40(cid:176) C to +125(cid:176) C unless otherwise specified. ADC frequency 4.5MHz. DDA amb Symbol Parameter Conditions Min Typ Max Unit V analog input voltage 0 - V V IA DDA C analog input - - 1 pF ia capacitance E differential linearity - - – 1 LSB D error [1][2][3] E integral non-linearity [1][4] - - – 2 LSB L(adj) E offset error [1][5] - - – 3 LSB O E gain error [1][6] - - – 0.5 % G E absolute error [1][7] - - – 4 LSB T [1] Conditions: V =0V, V =3.3V. SSA DDA [2] The ADC is monotonic, there are no missing codes. [3] The differential linearity error (E ) is the difference between the actual step width and the ideal step width. SeeFigure4. D [4] The integral non-linearity (E ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after L(adj) appropriate adjustment of gain and offset errors. SeeFigure4. [5] The offset error (E ) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the O ideal curve. SeeFigure4. [6] The gain error (E ) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset G error, and the straight line which fits the ideal transfer curve. SeeFigure4. [7] The absolute voltage error (E ) is the maximum difference between the center of the steps of the actual transfer curve of the T non-calibrated ADC and the ideal transfer curve. SeeFigure4. LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 29 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface offset gain error error EO EG 1023 1022 1021 1020 1019 1018 (2) 7 code (1) out 6 5 (5) 4 (4) 3 (3) 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) VDDA - VSSA offset 1 LSB = 1024 error EO 002aaa668 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E ). D (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 4. ADC characteristics LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 30 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface 9. Dynamic characteristics Table 8. Dynamic characteristics T =- 40(cid:176) C to +125(cid:176) C; V , V over specified ranges.[1] amb DD(1V8) DD(3V3) Symbol Parameter Conditions Min Typ Max Unit External clock f oscillator frequency supplied by an external 1 - 50 MHz osc oscillator (signal generator) external clock frequency 1 - 30 MHz supplied by an external crystal oscillator external clock frequency if 10 - 25 MHz on-chip PLL is used external clock frequency if 10 - 25 MHz on-chip bootloader is used for initial code download T clock cycle time 20 - 1000 ns cy(clk) t clock HIGH time T · 0.4 - - ns CHCX cy(clk) t clock LOW time T · 0.4 - - ns CLCX cy(clk) t clock rise time - - 5 ns CLCH t clock fall time - - 5 ns CHCL Port pins (except P0.2 and P0.3) t rise time - 10 - ns r t fall time - 10 - ns f I2C-bus pins (P0.2 and P0.3) t fall time V to V [2] 20+0.1· C - - ns f IH IL b [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Bus capacitance C in pF, from 10 pF to 400 pF. b LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 31 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface Table 9. External memory interface dynamic characteristics C =25pF, T =40(cid:176) C L amb Symbol Parameter Conditions Min Typ Max Unit Common to read and write cycles t XCLK HIGH to address valid - - 10 ns CHAV time t XCLK HIGH to CS LOW time - - 10 ns CHCSL t XCLK HIGH to CS HIGH - - 10 ns CHCSH time t XCLK HIGH to address - - 10 ns CHANV invalid time Read cycle parameters t CS LOW to address valid [1] - 5 - +10 ns CSLAV time t OE LOW to address valid [1] - 5 - +10 ns OELAV time t CS LOW to OE LOW time - 5 - +5 ns CSLOEL t memory access time [2][3] (T · (2+ WST1)) + - - ns am cy(CCLK) (- 20) t memory access time (initial [2][3] (T · (2+WST1))+ - - ns am(ibr) cy(CCLK) burst-ROM) (- 20) t memory access time [2][4] T +(- 20) - - ns am(sbr) cy(CCLK) (subsequent burst-ROM) t data hold time [5] 0 - - ns h(D) t CS HIGH to OE HIGH time - 5 - +5 ns CSHOEH t OE HIGH to address invalid - 5 - +5 ns OEHANV time t XCLK HIGH to OE LOW time - 5 - +5 ns CHOEL t XCLK HIGH to OE HIGH - 5 - +5 ns CHOEH time Write cycle parameters t address valid to CS LOW [1] T - 10 - - ns AVCSL cy(CCLK) time t CS LOW to data valid time - 5 - +5 ns CSLDV t CS LOW to WE LOW time - 5 - +5 ns CSLWEL t CS LOW to BLS LOW time - 5 - +5 ns CSLBLSL t WE LOW to data valid time - 5 - +5 ns WELDV t CS LOW to data valid time - 5 - +5 ns CSLDV t WE LOW to WE HIGH time [2] T · (1+WST2)- 5 - T · (1+ ns WELWEH cy(CCLK) cy(CCLK) WST2) + 5 t BLS LOW to BLS HIGH time [2] T · (1+WST2)- 5 - T · ns BLSLBLSH cy(CCLK) cy(CCLK) (1+WST2) + 5 t WE HIGH to address invalid [2] T - 5 - T +5 ns WEHANV cy(CCLK) cy(CCLK) time t WEHIGHtodatainvalidtime [2] (2· T )- 5 - (2· T )+5 ns WEHDNV cy(CCLK) cy(CCLK) t BLSHIGHtoaddressinvalid [2] T - 5 - T +5 ns BLSHANV cy(CCLK) cy(CCLK) time LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 32 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface Table 9. External memory interface dynamic characteristics …continued C =25pF, T =40(cid:176) C L amb Symbol Parameter Conditions Min Typ Max Unit t BLS HIGH to data invalid [2] (2· T )- 5 - (2· T )+5 ns BLSHDNV cy(CCLK) cy(CCLK) time t XCLK HIGH to data valid - - 10 ns CHDV time t XCLK HIGH to WE LOW - - 10 ns CHWEL time t XCLK HIGH to BLS LOW - - 10 ns CHBLSL time t XCLK HIGH to WE HIGH - - 10 ns CHWEH time t XCLK HIGH to BLS HIGH - - 10 ns CHBLSH time t XCLK HIGH to data invalid - - 10 ns CHDNV time [1] Except on initial access, in which case the address is set up T earlier. cy(CCLK) [2] T =1⁄ cy(CCLK) CCLK. [3] Latest of address valid, CS LOW, OE LOW to data valid. [4] Address valid to data valid. [5] Earliest of CS HIGH, OE HIGH, address change to data invalid. Table 10. Standard read access specifications Access cycle Max frequency WST setting Memory access time requirement WST‡ 0; round up to integer standard read fMAX£ t----2-----+-----W-+----S2---T0----1--n---s- WST1‡ t---R---A---M------+----2---0------n---s-–2 tRAM£ tcy(CCLK)· (2+WST1)–20 ns RAM tcy(CCLK) standard write fMAX£ t-----1-----+-----W----+-S---T-5---2--n----s- WST2‡ t--W-----R---I--T---E----–-----t--C---Y---C-----+-----5-- tWRITE£ tcy(CCLK)· (1+WST2)–5 ns WRITE tcy(CCLK) burst read-initial fMAX£ t---I-2N----I-+-T----W+-----S2---0T----1-n----s- WST1‡ t---I-N-t--c-I-y-T--(--C+---C--2-L--0-K----)n----s-–2 tINIT£ tcy(CCLK)· (2+WST1)–20 ns burst read - subsequent 3· f £ ----------------1----------------- N/A tROM£ tcy(CCLK)–20 ns MAX t +20 ns ROM LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 33 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface 9.1 Timing XCLK tCSLAV tCSHOEH CS addr tam th(D) data tCSLOEL tOELAV tOEHANV OE tCHOEL tCHOEH 002aaa749 Fig 5. External memory read access XCLK tCSLDV CS tAVCSL tWELWEH tCSLWEL tBLSLBLSH BLS/WE tWEHANV tCSLBLSL tWELDV tBLSHANV addr tWEHDNV tCSLDV tBLSHDNV data OE 002aaa750 Fig 6. External memory write access LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 34 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface VDD - 0.5 V 0.2VDD + 0.9 V 0.2VDD - 0.1 V 0.45 V tCHCX tCHCL tCLCX tCLCH Tcy(clk) 002aaa907 Fig 7. External clock timing 9.2 LPC2290 power consumption measurements 002aab452 60 IDD current (mA) (1) (2) 40 20 0 0 10 20 30 40 50 60 frequency (MHz) Test conditions: code executed from on-chip RAM; all peripherals are enabled in PCONP register; PCLK =CCLK⁄ . 4 (1) 1.8 V core at 25(cid:176) C (typical) (2) 1.65 V core at 25(cid:176) C (typical) Fig 8. LPC2290 I measured at different frequencies (CCLK) and temperatures DD(act) LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 35 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface 002aab453 15 IDD current (mA) 10 (1) (2) 5 0 0 10 20 30 40 50 60 frequency (MHz) Test conditions: Idle mode entered executing code from on-chip RAM; all peripherals are enabled in PCONP register; PCLK=CCLK⁄ . 4 (1) 1.8 V core at 25(cid:176) C (typical) (2) 1.65 V core at 25(cid:176) C (typical) Fig 9. LPC2290 I idle measured at different frequencies (CCLK) and temperatures DD 002aab454 500 IDD current (1) (m A) (2) 400 (3) 300 200 100 0 - 100 - 50 0 50 100 150 temp ((cid:176)C) Test conditions: Power-down mode entered executing code from on-chip RAM; all peripherals are enabled in PCONP register. (1) 1.95 V core (2) 1.8 V core (3) 1.65 V core Fig 10. LPC2290 I measured at different temperatures DD(pd) LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 36 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface 10. Package outline LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1 c y X A 108 73 109 72 ZE e E HE A A2 A1 (A 3 ) q wM Lp bp L pin 1 index detail X 144 37 1 36 wM ZD v M A e bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(1) e HD HE L Lp v w y ZD(1) ZE(1) q mm 1.6 00..1055 11..4355 0.25 00..2177 00..2009 2109..19 2109..19 0.5 2221..1855 2221..1855 1 00..7455 0.2 0.08 0.08 11..41 11..41 70oo Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 00-03-14 SOT486-1 136E23 MS-026 03-02-20 Fig 11. Package outline SOT486-1 (LQFP144) LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 37 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface 11. Abbreviations Table 11. Abbreviations Acronym Description ADC Analog-to-Digital Converter AMBA Advanced Microcontroller Bus Architecture APB AMBA Peripheral Bus CAN Controller Area Network CISC Complex Instruction Set Computer CPU Central Processing Unit FIFO First In, First Out GPIO General Purpose Input/Output PLL Phase-Locked Loop PWM Pulse Width Modulator RAM Random Access Memory RISC Reduced Instruction Set Computer SPI Serial Peripheral Interface SRAM Static Random Access Memory SSP Synchronous Serial Port TTL Transistor-Transistor Logic UART Universal Asynchronous Receiver/Transmitter LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 38 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface 12. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC2290_3 20061116 Product data sheet - LPC2290-02 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • New features specific to the LPC2290/01 have been added throughout. LPC2290-02 20041223 Product data - LPC2290-01 LPC2290-01 20040209 Preliminary data - - LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 39 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface 13. Legal information 13.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] Theproductstatusofdevice(s)describedinthisdocumentmayhavechangedsincethisdocumentwaspublishedandmaydifferincaseofmultipledevices.Thelatestproductstatus information is available on the Internet at URLhttp://www.nxp.com. 13.2 Definitions result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore Draft —The document is a draft version only. The content is still under such inclusion and/or use is at the customer’s own risk. internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any Applications —Applications that are described herein for any of these representations or warranties as to the accuracy or completeness of products are for illustrative purposes only. NXP Semiconductors makes no informationincludedhereinandshallhavenoliabilityfortheconsequencesof representation or warranty that such applications will be suitable for the use of such information. specified use without further testing or modification. Short data sheet —A short data sheet is an extract from a full data sheet Limiting values —Stress above one or more limiting values (as defined in withthesameproducttypenumber(s)andtitle.Ashortdatasheetisintended theAbsoluteMaximumRatingsSystemofIEC60134)maycausepermanent forquickreferenceonlyandshouldnotbereliedupontocontaindetailedand damagetothedevice.Limitingvaluesarestressratingsonlyandoperationof full information. For detailed and full information see the relevant full data the device at these or any other conditions above those given in the sheet, which is available on request via the local NXP Semiconductors sales Characteristics sections of this document is not implied. Exposure to limiting office. In case of any inconsistency or conflict with the short data sheet, the values for extended periods may affect device reliability. full data sheet shall prevail. Terms and conditions of sale —NXP Semiconductors products are sold subjecttothegeneraltermsandconditionsofcommercialsale,aspublished 13.3 Disclaimers athttp://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of General —Information in this document is believed to be accurate and any inconsistency or conflict between information in this document and such reliable.However,NXPSemiconductorsdoesnotgiveanyrepresentationsor terms and conditions, the latter will prevail. warranties,expressedorimplied,astotheaccuracyorcompletenessofsuch No offer to sell or license —Nothing in this document may be interpreted information and shall have no liability for the consequences of use of such or construed as an offer to sell products that is open for acceptance or the information. grant,conveyanceorimplicationofanylicenseunderanycopyrights,patents Right to make changes —NXPSemiconductorsreservestherighttomake or other industrial or intellectual property rights. changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice.Thisdocumentsupersedesandreplacesallinformationsuppliedprior 13.4 Trademarks to the publication hereof. Notice:Allreferencedbrands,productnames,servicenamesandtrademarks Suitability for use —NXP Semiconductors products are not designed, are the property of their respective owners. authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or I2C-bus —logois a trademark of NXP B.V. malfunctionofaNXPSemiconductorsproductcanreasonablybeexpectedto 14. Contact information For additional information, please visit:http://www.nxp.com For sales office addresses, send an email to:salesaddresses@nxp.com LPC2290_3 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 03 — 16 November 2006 40 of 41

LPC2290 NXP Semiconductors 16/32-bit ARM microcontroller with external memory interface 15. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 6.17.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6.18 System control. . . . . . . . . . . . . . . . . . . . . . . . 23 6.18.1 Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 23 2.1 Enhancements introduced with LPC2290/01 6.18.2 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6.18.3 Reset and wake-up timer. . . . . . . . . . . . . . . . 23 2.2 Key features common for LPC2290 and 6.18.4 External interrupt inputs. . . . . . . . . . . . . . . . . 24 LPC2290/01 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6.18.5 Memory mapping control . . . . . . . . . . . . . . . . 24 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 6.18.6 Power control. . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2 6.18.7 APB bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.19 Emulation and debugging. . . . . . . . . . . . . . . . 25 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 6.19.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.19.2 Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 25 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.19.3 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 Functional description . . . . . . . . . . . . . . . . . . 14 7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1 Architectural overview. . . . . . . . . . . . . . . . . . . 14 8 Static characteristics . . . . . . . . . . . . . . . . . . . 27 6.2 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 14 9 Dynamic characteristics. . . . . . . . . . . . . . . . . 31 6.3 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 14 9.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 15 9.2 LPC2290 power consumption measurements 35 6.4.1 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 16 10 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 37 6.5 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 17 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.6 External memory controller. . . . . . . . . . . . . . . 17 6.7 General purpose parallel I/O and Fast I/O . . . 17 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . 39 6.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13 Legal information . . . . . . . . . . . . . . . . . . . . . . 40 6.7.2 Fast I/O features available in LPC2290/01 13.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 40 only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.8 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 13.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.8.2 ADC features available in LPC2290/01 only. . 18 14 Contact information . . . . . . . . . . . . . . . . . . . . 40 6.9 CAN controllers and acceptance filter . . . . . . 18 15 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.10 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.10.2 UART features available in LPC2290/01 only. 19 6.11 I2C-bus serial I/O controller . . . . . . . . . . . . . . 19 6.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.12 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 19 6.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.13 SSP serial I/O controller (available in LPC2290/01 only). . . . . . . . . . . . . . . . . . . . . . 20 6.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.14 General purpose timers . . . . . . . . . . . . . . . . . 20 6.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.14.2 Timer features available in LPC2290/01 only. 21 6.15 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 21 6.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.16 Real-time clock. . . . . . . . . . . . . . . . . . . . . . . . 21 6.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.17 Pulse width modulator . . . . . . . . . . . . . . . . . . 22 Pleasebeawarethatimportantnoticesconcerningthisdocumentandtheproduct(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2006. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 16 November 2006 Document identifier: LPC2290_3

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