LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, USB 2.0 full-speed device, 10-bit ADC and DAC Rev. 5 — 12 August 2011 Product data sheet 1. General description The LPC2141/42/44/46/48 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, that combine the microcontroller with embedded high-speed flash memory ranging from 32kB to 512 kB. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30% with minimal performance penalty. Due to their tiny size and low power consumption, LPC2141/42/44/46/48 are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale. Serial communications interfaces ranging from a USB 2.0 Full-speed device, multiple UARTs, SPI, SSP to I2C-bus and on-chip SRAM of 8kB up to 40kB, make these devices very well suited for communication gateways and protocol converters, soft modems, voice recognition and low end imaging, providing both large buffer size and high processing power. Various 32-bit timers, single or dual 10-bit ADC(s), 10-bit DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers suitable for industrial control and medical systems. 2. Features and benefits 2.1 Key features  16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.  8kB to 40kB of on-chip static RAM and 32kB to 512kB of on-chip flash memory. 128-bit wide interface/accelerator enables high-speed 60MHz operation.  In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot loader software. Single flash sector or full chip erase in 400 ms and programming of 256B in 1 ms.  EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the on-chip RealMonitor software and high-speed tracing of instruction execution.  USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM. In addition, the LPC2146/48 provides 8 kB of on-chip RAM accessible to USB by DMA.  One or two (LPC2141/42 vs. LPC2144/46/48) 10-bit ADCs provide a total of 6/14 analog inputs, with conversion times as low as 2.44s per channel.  Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only).  Two 32-bit timers/external event counters (with four capture and four compare channels each), PWM unit (six outputs) and watchdog.  Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input.

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers  Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400kbit/s), SPI and SSP with buffering and variable data length capabilities.  Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses.  Up to 45 of 5V tolerant fast general purpose I/O pins in a tiny LQFP64 package.  Up to 21 external interrupt pins available.  60MHz maximum CPU clock available from programmable on-chip PLL with settling time of 100s.  On-chip integrated oscillator operates with an external crystal from 1MHz to 25MHz.  Power saving modes include Idle and Power-down.  Individual enable/disable of peripheral functions as well as peripheral clock scaling for additional power optimization.  Processor wake-up from Power-down mode via external interrupt or BOD.  Single power supply chip with POR and BOD circuits: CPU operating voltage range of 3.0V to 3.6V (3.3V10%) with 5V tolerant I/O pads. 3. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC2141FBD64 LQFP64 plastic low profile quad flat package; 64 leads; SOT314-2 body 10101.4mm LPC2142FBD64 LPC2144FBD64 LPC2146FBD64 LPC2148FBD64 3.1 Ordering options Table 2. Ordering opt ions Type number Flash RAM Endpoint ADC (channels DAC Temperature memory USB RAM overall) range LPC2141FBD64 32kB 8kB 2kB 1 (6 channels) - 40 C to +85 C LPC2142FBD64 64kB 16kB 2kB 1 (6 channels) 1 40 C to +85 C LPC2144FBD64 128kB 16kB 2kB 2 (14 channels) 1 40 C to +85 C LPC2146FBD64 256kB 32kB + 8kB shared with 2kB 2 (14 channels) 1 40 C to +85 C USB DMA[1] LPC2148FBD64 512kB 32kB + 8kB shared with 2kB 2 (14 channels) 1 40 C to +85 C USB DMA[1] [1] While the USB DMA is the primary user of the additional 8kB RAM, this RAM is also accessible at any time by the CPU as a general purpose RAM for data and code storage. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 2 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 4. Block diagram TMS(1) TDI(1) XTAL2 TRST(1) TCK(1) TDO(1) XTAL1 RST LPC2141/42/44/46/48 TEST/DEBUG CE PLL0 INTERFACE A R P0[31P:208[]2 a5n:0d] FAST GENERAL ARM7TDMI-S ON TDULE scylsotcekm FUSNYCSTTIEOMNS P1[31:16] PURPOSE I/O ATIMO L PLL1 U AHB BRIDGE M E VECTORED USB INTERRUPT ARM7 local bus clock CONTROLLER AMBA AHB (Advanced High-performance Bus) INTERNAL INTERNAL SRAM FLASH CONTROLLER CONTROLLER 8 kB RAM AHB 8 kB/16 kB/ 32 kB/64 kB/128 kB/ AHB TO APB APB SHARED WITH DECODER 32 kB 256 kB/512 kB BRIDGE DIVIDER USB DMA(3) SRAM FLASH D+ USB 2.0 FULL-SPEED D− EXTERNAL EINT3 to EINT0 DEVICE CONTROLLER UP_LED INTERRUPTS WITH DMA(3) CONNECT VBUS 4 × CAP0 SCL0, SCL1 4 × CAP1 CAPTURE/COMPARE I2C-BUS SERIAL 8 × MAT0 (W/EXTERNAL CLOCK) INTERFACES 0 AND 1 TIMER 0/TIMER 1 SDA0, SDA1 8 × MAT1 AD0[7:6] and SCK0, SCK1 AD0[4:1] A/D CONVERTERS SPI AND SSP MOSI0, MOSI1 AD1[7:0](2) 0 AND 1(2) SERIAL INTERFACES MISO0, MISO1 SSEL0, SSEL1 TXD0, TXD1 AOUT(4) D/A CONVERTER UART0/UART1 RXD0, RXD1 DSR1(2),CTS1(2), RTS1(2), DTR1(2) DCD1(2),RI1(2) P0[31:28] and RTXC1 P0[25:0] GENERAL PURPOSE I/O REAL-TIME CLOCK RTXC2 P1[31:16] VBAT WATCHDOG PWM6 to PWM0 PWM0 TIMER SYSTEM CONTROL 002aab560 (1) Pins shared with GPIO. (2) LPC2144/46/48 only. (3) USB DMA controller with 8kB of RAM accessible as general purpose RAM and/or DMA is available in LPC2146/48 only. (4) LPC2142/44/46/48 only. Fig 1. Block diagram LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 3 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 5. Pinning information 5.1 Pinning 2 3 NT3 AP1. AT1. EI C M 1/ 1/ 1/ SSEL MOSI MISO 3/ 2/ 3/ 1.27/TDO REF TAL1 TAL2 1.28/TDI SSA 0.23/VBUS ESET 1.29/TCK 0.20/MAT1. 0.19/MAT1. 0.18/CAP1. 1.30/TMS DD SS BAT P V X X P V P R P P P P P V V V 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 P0.21/PWM5/CAP1.3 1 48 P1.20/TRACESYNC P0.22/CAP0.0/MAT0.0 2 47 P0.17/CAP1.2/SCK1/MAT1.2 RTCX1 3 46 P0.16/EINT0/MAT0.2/CAP0.2 P1.19/TRACEPKT3 4 45 P0.15/EINT2 RTCX2 5 44 P1.21/PIPESTAT0 VSS 6 43 VDD VDDA 7 42 VSS P1.18/TRACEPKT2 8 41 P0.14/EINT1/SDA1 LPC2141 P0.25/AD0.4 9 40 P1.22/PIPESTAT1 D+ 10 39 P0.13/MAT1.1 D− 11 38 P0.12/MAT1.0 P1.17/TRACEPKT1 12 37 P0.11/CAP1.1/SCL1 P0.28/AD0.1/CAP0.2/MAT0.2 13 36 P1.23/PIPESTAT2 P0.29/AD0.2/CAP0.3/MAT0.3 14 35 P0.10/CAP1.0 P0.30/AD0.3/EINT3/CAP0.0 15 34 P0.9/RXD1/PWM6/EINT3 P1.16/TRACEPKT0 16 33 P0.8/TXD1/PWM4 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 002aab733 T S 1 T 0 0 D K S 1 6 0 7 2 2 K P0.31/UP_LED/CONNEC VS P0.0/TXD0/PWM P1.31/TRS P0.1/RXD0/PWM3/EINT P0.2/SCL0/CAP0. VD P1.26/RTC VS P0.3/SDA0/MAT0.0/EINT P0.4/SCK0/CAP0.1/AD0. P1.25/EXTIN P0.5/MISO0/MAT0.1/AD0. P0.6/MOSI0/CAP0. P0.7/SSEL0/PWM2/EINT P1.24/TRACECL Fig 2. LPC2141 pinning LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 4 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 2 3 NT3 AP1. AT1. EI C M 1/ 1/ 1/ SSEL MOSI MISO 3/ 2/ 3/ 1.27/TDO REF TAL1 TAL2 1.28/TDI SSA 0.23/VBUS ESET 1.29/TCK 0.20/MAT1. 0.19/MAT1. 0.18/CAP1. 1.30/TMS DD SS BAT P V X X P V P R P P P P P V V V 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 P0.21/PWM5/CAP1.3 1 48 P1.20/TRACESYNC P0.22/CAP0.0/MAT0.0 2 47 P0.17/CAP1.2/SCK1/MAT1.2 RTCX1 3 46 P0.16/EINT0/MAT0.2/CAP0.2 P1.19/TRACEPKT3 4 45 P0.15/EINT2 RTCX2 5 44 P1.21/PIPESTAT0 VSS 6 43 VDD VDDA 7 42 VSS P1.18/TRACEPKT2 8 41 P0.14/EINT1/SDA1 LPC2142 P0.25/AD0.4/AOUT 9 40 P1.22/PIPESTAT1 D+ 10 39 P0.13/MAT1.1 D− 11 38 P0.12/MAT1.0 P1.17/TRACEPKT1 12 37 P0.11/CAP1.1/SCL1 P0.28/AD0.1/CAP0.2/MAT0.2 13 36 P1.23/PIPESTAT2 P0.29/AD0.2/CAP0.3/MAT0.3 14 35 P0.10/CAP1.0 P0.30/AD0.3/EINT3/CAP0.0 15 34 P0.9/RXD1/PWM6/EINT3 P1.16/TRACEPKT0 16 33 P0.8/TXD1/PWM4 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 002aab734 T S 1 T 0 0 D K S 1 6 0 7 2 2 K P0.31/UP_LED/CONNEC VS P0.0/TXD0/PWM P1.31/TRS P0.1/RXD0/PWM3/EINT P0.2/SCL0/CAP0. VD P1.26/RTC VS P0.3/SDA0/MAT0.0/EINT P0.4/SCK0/CAP0.1/AD0. P1.25/EXTIN P0.5/MISO0/MAT0.1/AD0. P0.6/MOSI0/CAP0. P0.7/SSEL0/PWM2/EINT P1.24/TRACECL Fig 3. LPC2142 pinning LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 5 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 2 3 NT3 AP1. AT1. EI C M 1/ 1/ 1/ SSEL MOSI MISO 3/ 2/ 3/ 1.27/TDO REF TAL1 TAL2 1.28/TDI SSA 0.23/VBUS ESET 1.29/TCK 0.20/MAT1. 0.19/MAT1. 0.18/CAP1. 1.30/TMS DD SS BAT P V X X P V P R P P P P P V V V 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 P0.21/PWM5/AD1.6/CAP1.3 1 48 P1.20/TRACESYNC P0.22/AD1.7/CAP0.0/MAT0.0 2 47 P0.17/CAP1.2/SCK1/MAT1.2 RTCX1 3 46 P0.16/EINT0/MAT0.2/CAP0.2 P1.19/TRACEPKT3 4 45 P0.15/RI1/EINT2/AD1.5 RTCX2 5 44 P1.21/PIPESTAT0 VSS 6 43 VDD VDDA 7 42 VSS P1.18/TRACEPKT2 8 41 P0.14/DCD1/EINT1/SDA1 LPC2144/2146/2148 P0.25/AD0.4/AOUT 9 40 P1.22/PIPESTAT1 D+ 10 39 P0.13/DTR1/MAT1.1/AD1.4 D− 11 38 P0.12/DSR1/MAT1.0/AD1.3 P1.17/TRACEPKT1 12 37 P0.11/CTS1/CAP1.1/SCL1 P0.28/AD0.1/CAP0.2/MAT0.2 13 36 P1.23/PIPESTAT2 P0.29/AD0.2/CAP0.3/MAT0.3 14 35 P0.10/RTS1/CAP1.0/AD1.2 P0.30/AD0.3/EINT3/CAP0.0 15 34 P0.9/RXD1/PWM6/EINT3 P1.16/TRACEPKT0 16 33 P0.8/TXD1/PWM4/AD1.1 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 002aab735 T S 1 T 0 0 D K S 1 6 0 7 0 2 K P0.31/UP_LED/CONNEC VS P0.0/TXD0/PWM P1.31/TRS P0.1/RXD0/PWM3/EINT P0.2/SCL0/CAP0. VD P1.26/RTC VS P0.3/SDA0/MAT0.0/EINT P0.4/SCK0/CAP0.1/AD0. P1.25/EXTIN P0.5/MISO0/MAT0.1/AD0. P0.6/MOSI0/CAP0.2/AD1. P0.7/SSEL0/PWM2/EINT P1.24/TRACECL Fig 4. LPC2144/46/48 pinning LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 6 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 5.2 Pin description Table 3. Pin descripti on Symbol Pin Type Description P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. Total of 31 pins of the Port 0 can be used as a general purpose bidirectional digital I/Os while P0.31 is output only pin. The operation of port 0 pins depends upon the pin function selected via the pin connect block. Pins P0.24, P0.26 and P0.27 are not available. P0.0/TXD0/ 19[1] I/O P0.0 — General purpose input/output digital pin (GPIO). PWM1 O TXD0 — Transmitter output for UART0. O PWM1 — Pulse Width Modulator output 1. P0.1/RXD0/ 21[2] I/O P0.1 — General purpose input/output digital pin (GPIO). PWM3/EINT0 I RXD0 — Receiver input for UART0. O PWM3 — Pulse Width Modulator output 3. I EINT0 — External interrupt 0 input. P0.2/SCL0/ 22[3] I/O P0.2 — General purpose input/output digital pin (GPIO). CAP0.0 I/O SCL0 — I2C0 clock input/output. Open-drain output (for I2C-bus compliance). I CAP0.0 — Capture input for Timer0, channel 0. P0.3/SDA0/ 26[3] I/O P0.3 — General purpose input/output digital pin (GPIO). MAT0.0/EINT1 I/O SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus compliance). O MAT0.0 — Match output for Timer0, channel 0. I EINT1 — External interrupt 1 input. P0.4/SCK0/ 27[4] I/O P0.4 — General purpose input/output digital pin (GPIO). CAP0.1/AD0.6 I/O SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave. I CAP0.1 — Capture input for Timer0, channel 1. I AD0.6 — ADC 0, input 6. P0.5/MISO0/ 29[4] I/O P0.5 — General purpose input/output digital pin (GPIO). MAT0.1/AD0.7 I/O MISO0 — Master In Slave Out for SPI0. Data input to SPI master or data output from SPI slave. O MAT0.1 — Match output for Timer0, channel 1. I AD0.7 — ADC 0, input 7. P0.6/MOSI0/ 30[4] I/O P0.6 — General purpose input/output digital pin (GPIO). CAP0.2/AD1.0 I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data input to SPI slave. I CAP0.2 — Capture input for Timer0, channel 2. I AD1.0 — ADC 1, input 0. Available in LPC2144/46/48 only. P0.7/SSEL0/ 31[2] I/O P0.7 — General purpose input/output digital pin (GPIO). PWM2/EINT2 I SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave. O PWM2 — Pulse Width Modulator output 2. I EINT2 — External interrupt 2 input. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 7 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 3. Pin description …continued Symbol Pin Type Description P0.8/TXD1/ 33[4] I/O P0.8 — General purpose input/output digital pin (GPIO). PWM4/AD1.1 O TXD1 — Transmitter output for UART1. O PWM4 — Pulse Width Modulator output 4. I AD1.1 — ADC 1, input 1. Available in LPC2144/46/48 only. P0.9/RXD1/ 34[2] I/O P0.9 — General purpose input/output digital pin (GPIO). PWM6/EINT3 I RXD1 — Receiver input for UART1. O PWM6 — Pulse Width Modulator output 6. I EINT3 — External interrupt 3 input. P0.10/RTS1/ 35[4] I/O P0.10 — General purpose input/output digital pin (GPIO). CAP1.0/AD1.2 O RTS1 — Request to Send output for UART1. LPC2144/46/48 only. I CAP1.0 — Capture input for Timer1, channel 0. I AD1.2 — ADC 1, input 2. Available in LPC2144/46/48 only. P0.11/CTS1/ 37[3] I/O P0.11 — General purpose input/output digital pin (GPIO). CAP1.1/SCL1 I CTS1 — Clear to Send input for UART1. Available in LPC2144/46/48 only. I CAP1.1 — Capture input for Timer1, channel 1. I/O SCL1 — I2C1 clock input/output. Open-drain output (for I2C-bus compliance) P0.12/DSR1/ 38[4] I/O P0.12 — General purpose input/output digital pin (GPIO). MAT1.0/AD1.3 I DSR1 — Data Set Ready input for UART1. Available in LPC2144/46/48 only. O MAT1.0 — Match output for Timer1, channel 0. I AD1.3 — ADC 1 input 3. Available in LPC2144/46/48 only. P0.13/DTR1/ 39[4] I/O P0.13 — General purpose input/output digital pin (GPIO). MAT1.1/AD1.4 O DTR1 — Data Terminal Ready output for UART1. LPC2144/46/48 only. O MAT1.1 — Match output for Timer1, channel 1. I AD1.4 — ADC 1 input 4. Available in LPC2144/46/48 only. P0.14/DCD1/ 41[3] I/O P0.14 — General purpose input/output digital pin (GPIO). EINT1/SDA1 I DCD1 — Data Carrier Detect input for UART1. LPC2144/46/48 only. I EINT1 — External interrupt 1 input. I/O SDA1 — I2C1 data input/output. Open-drain output (for I2C-bus compliance). Note: LOW on this pin while RESET is LOW forces on-chip boot loader to take over control of the part after reset. P0.15/RI1/ 45[4] I/O P0.15 — General purpose input/output digital pin (GPIO). EINT2/AD1.5 I RI1 — Ring Indicator input for UART1. Available in LPC2144/46/48 only. I EINT2 — External interrupt 2 input. I AD1.5 — ADC 1, input 5. Available in LPC2144/46/48 only. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 8 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 3. Pin description …continued Symbol Pin Type Description P0.16/EINT0/ 46[2] I/O P0.16 — General purpose input/output digital pin (GPIO). MAT0.2/CAP0.2 I EINT0 — External interrupt 0 input. O MAT0.2 — Match output for Timer0, channel 2. I CAP0.2 — Capture input for Timer0, channel 2. P0.17/CAP1.2/ 47[1] I/O P0.17 — General purpose input/output digital pin (GPIO). SCK1/MAT1.2 I CAP1.2 — Capture input for Timer1, channel 2. I/O SCK1 — Serial Clock for SSP. Clock output from master or input to slave. O MAT1.2 — Match output for Timer1, channel 2. P0.18/CAP1.3/ 53[1] I/O P0.18 — General purpose input/output digital pin (GPIO). MISO1/MAT1.3 I CAP1.3 — Capture input for Timer1, channel 3. I/O MISO1 — Master In Slave Out for SSP. Data input to SPI master or data output from SSP slave. O MAT1.3 — Match output for Timer1, channel 3. P0.19/MAT1.2/ 54[1] I/O P0.19 — General purpose input/output digital pin (GPIO). MOSI1/CAP1.2 O MAT1.2 — Match output for Timer1, channel 2. I/O MOSI1 — Master Out Slave In for SSP. Data output from SSP master or data input to SSP slave. I CAP1.2 — Capture input for Timer1, channel 2. P0.20/MAT1.3/ 55[2] I/O P0.20 — General purpose input/output digital pin (GPIO). SSEL1/EINT3 O MAT1.3 — Match output for Timer1, channel 3. I SSEL1 — Slave Select for SSP. Selects the SSP interface as a slave. I EINT3 — External interrupt 3 input. P0.21/PWM5/ 1[4] I/O P0.21 — General purpose input/output digital pin (GPIO). AD1.6/CAP1.3 O PWM5 — Pulse Width Modulator output 5. I AD1.6 — ADC 1, input 6. Available in LPC2144/46/48 only. I CAP1.3 — Capture input for Timer1, channel 3. P0.22/AD1.7/ 2[4] I/O P0.22 — General purpose input/output digital pin (GPIO). CAP0.0/MAT0.0 I AD1.7 — ADC 1, input 7. Available in LPC2144/46/48 only. I CAP0.0 — Capture input for Timer0, channel 0. O MAT0.0 — Match output for Timer0, channel 0. P0.23/V 58[1] I/O P0.23 — General purpose input/output digital pin (GPIO). BUS I V — Indicates the presence of USB bus power. BUS Note: This signal must be HIGH for USB reset to occur. P0.25/AD0.4/ 9[5] I/O P0.25 — General purpose input/output digital pin (GPIO). AOUT I AD0.4 — ADC 0, input 4. O AOUT — DAC output. Available in LPC2142/44/46/48 only. P0.28/AD0.1/ 13[4] I/O P0.28 — General purpose input/output digital pin (GPIO). CAP0.2/MAT0.2 I AD0.1 — ADC 0, input 1. I CAP0.2 — Capture input for Timer0, channel 2. O MAT0.2 — Match output for Timer0, channel 2. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 9 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 3. Pin description …continued Symbol Pin Type Description P0.29/AD0.2/ 14[4] I/O P0.29 — General purpose input/output digital pin (GPIO). CAP0.3/MAT0.3 I AD0.2 — ADC 0, input 2. I CAP0.3 — Capture input for Timer0, channel 3. O MAT0.3 — Match output for Timer0, channel 3. P0.30/AD0.3/ 15[4] I/O P0.30 — General purpose input/output digital pin (GPIO). EINT3/CAP0.0 I AD0.3 — ADC 0, input 3. I EINT3 — External interrupt 3 input. I CAP0.0 — Capture input for Timer0, channel 0. P0.31/UP_LED/ 17[6] O P0.31 — General purpose output only digital pin (GPO). CONNECT O UP_LED — USB GoodLink LED indicator. It is LOW when device is configured (non-control endpoints enabled). It is HIGH when the device is not configured or during global suspend. O CONNECT — Signal used to switch an external 1.5k resistor under the software control. Used with the SoftConnect USB feature. Important: This is an digital output only pin. This pin MUST NOT be externally pulled LOW when RESET pin is LOW or the JTAG port will be disabled. P1.0 to P1.31 I/O Port 1: Port 1 is a 32-bit bidirectional I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. Pins 0 through 15 of port1 are not available. P1.16/ 16[6] I/O P1.16 — General purpose input/output digital pin (GPIO). Standard TRACEPKT0 I/O port with internal pull-up. O TRACEPKT0 — Trace Packet, bit 0. P1.17/ 12[6] I/O P1.17 — General purpose input/output digital pin (GPIO). Standard TRACEPKT1 I/O port with internal pull-up. O TRACEPKT1 — Trace Packet, bit 1. P1.18/ 8[6] I/O P1.18 — General purpose input/output digital pin (GPIO). Standard TRACEPKT2 I/O port with internal pull-up. O TRACEPKT2 — Trace Packet, bit 2. P1.19/ 4[6] I/O P1.19 — General purpose input/output digital pin (GPIO). Standard TRACEPKT3 I/O port with internal pull-up. O TRACEPKT3 — Trace Packet, bit 3. P1.20/ 48[6] I/O P1.20 — General purpose input/output digital pin (GPIO). Standard TRACESYNC I/O port with internal pull-up. O TRACESYNC — Trace Synchronization. Note: LOW on this pin while RESET is LOW enables pins P1.25:16 to operate as Trace port after reset. P1.21/ 44[6] I/O P1.21 — General purpose input/output digital pin (GPIO). Standard PIPESTAT0 I/O port with internal pull-up. O PIPESTAT0 — Pipeline Status, bit 0. P1.22/ 40[6] I/O P1.22 — General purpose input/output digital pin (GPIO). Standard PIPESTAT1 I/O port with internal pull-up. O PIPESTAT1 — Pipeline Status, bit 1. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 10 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 3. Pin description …continued Symbol Pin Type Description P1.23/ 36[6] I/O P1.23 — General purpose input/output digital pin (GPIO). Standard PIPESTAT2 I/O port with internal pull-up. O PIPESTAT2 — Pipeline Status, bit 2. P1.24/ 32[6] I/O P1.24 — General purpose input/output digital pin (GPIO). Standard TRACECLK I/O port with internal pull-up. O TRACECLK — Trace Clock. P1.25/EXTIN0 28[6] I/O P1.25 — General purpose input/output digital pin (GPIO). Standard I/O port with internal pull-up. I EXTIN0 — External Trigger Input. P1.26/RTCK 24[6] I/O P1.26 — General purpose input/output digital pin (GPIO). I/O RTCK — Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional pin with internal pull-up. Note: LOW on RTCK while RESET is LOW enables pins P1[31:26] to operate as Debug port after reset. P1.27/TDO 64[6] I/O P1.27 — General purpose input/output digital pin (GPIO). O TDO — Test Data out for JTAG interface. P1.28/TDI 60[6] I/O P1.28 — General purpose input/output digital pin (GPIO). I TDI — Test Data in for JTAG interface. P1.29/TCK 56[6] I/O P1.29 — General purpose input/output digital pin (GPIO). I TCK — Test Clock for JTAG interface. This clock must be slower than 1 of the CPU clock (CCLK) for the JTAG interface to operate. 6 P1.30/TMS 52[6] I/O P1.30 — General purpose input/output digital pin (GPIO). I TMS — Test Mode Select for JTAG interface. P1.31/TRST 20[6] I/O P1.31 — General purpose input/output digital pin (GPIO). I TRST — Test Reset for JTAG interface. D+ 10[7] I/O USB bidirectional D+ line. D 11[7] I/O USB bidirectional D line. RESET 57[8] I External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5V tolerant. XTAL1 62[9] I Input to the oscillator circuit and internal clock generator circuits. XTAL2 61[9] O Output from the oscillator amplifier. RTCX1 3[9][10] I Input to the RTC oscillator circuit. RTCX2 5[9][10] O Output from the RTC oscillator circuit. V 6, 18, 25, 42, I Ground: 0V reference. SS 50 V 59 I Analog ground: 0V reference. This should nominally be the same SSA voltage as V , but should be isolated to minimize noise and error. SS V 23, 43, 51 I 3.3V power supply: This is the power supply voltage for the core and DD I/O ports. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 11 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 3. Pin description …continued Symbol Pin Type Description V 7 I Analog 3.3V power supply: This should be nominally the same DDA voltage as V but should be isolated to minimize noise and error. DD This voltage is only used to power the on-chip ADC(s) and DAC. VREF 63 I ADC reference voltage: This should be nominally less than or equal to the V voltage but should be isolated to minimize noise and error. DD Level on this pin is used as a reference for ADC(s) and DAC. VBAT 49 I RTC power supply voltage: 3.3V on this pin supplies the power to the RTC. [1] 5V tolerant pad (no built-in pull-up resistor) providing digital I/O functions with TTL levels and hysteresis and 10ns slew rate control. [2] 5V tolerant pad (no built-in pull-up resistor) providing digital I/O functions with TTL levels and hysteresis and 10ns slew rate control. If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. [3] Open-drain 5V tolerant digital I/O I2C-bus 400kHz specification compatible pad. It requires external pull-up to provide an output functionality. [4] 5V tolerant pad (no built-in pull-up resistor) providing digital I/O (with TTL levels and hysteresis and 10ns slew rate control) and analog input function. If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital section of the pad is disabled. [5] 5V tolerant pad (no built-in pull-up resistor) providing digital I/O (with TTL levels and hysteresis and 10ns slew rate control) and analog output function. When configured as the DAC output, digital section of the pad is disabled. [6] 5V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10ns slew rate control. The pull-up resistor’s value typically ranges from 60 k to 300 k. [7] Pad is designed in accordance with the Universal Serial Bus (USB) specification, revision 2.0 (Full-speed and Low-speed mode only). [8] 5V tolerant pad providing digital input (with TTL levels and hysteresis) function only. [9] Pad provides special analog functionality. [10] When unused, the RTCX1 pin can be grounded or left floating. For lowest power leave it floating. The other RTC pin, RTCX2, should be left floating. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 12 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 6. Functional description 6.1 Architectural overview The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers (CISC). This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets: • The standard 32-bit ARM set. • A 16-bit Thumb set. The Thumb set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system. The particular flash implementation in the LPC2141/42/44/46/48 allows for full speed execution also in ARM mode. It is recommended to program performance critical and short code sections (such as interrupt service routines and DSP algorithms) in ARM mode. The impact on the overall code size will be minimal but the speed can be increased by 30% over Thumb mode. 6.2 On-chip flash program memory The LPC2141/42/44/46/48 incorporate a 32kB, 64kB, 128kB, 256kB and 512kB flash memory system respectively. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. Due to the architectural solution chosen for an on-chip boot loader, flash memory available for user’s code on LPC2141/42/44/46/48 is 32kB, 64kB, 128kB, 256kB and 500kB respectively. The LPC2141/42/44/46/48 flash memory provides a minimum of 100000 erase/write cycles and 20 years of data-retention. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 13 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 6.3 On-chip static RAM On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bit, 16-bit, and 32-bit. The LPC2141, LPC2142/44 and LPC2146/48 provide 8kB, 16kB and 32kB of static RAM respectively. In case of LPC2146/48 only, an 8kB SRAM block intended to be utilized mainly by the USB can also be used as a general purpose RAM for data storage and code storage and execution. 6.4 Memory map The LPC2141/42/44/46/48 memory map incorporates several distinct regions, as shown in Figure5. In addition, the CPU interrupt vectors may be remapped to allow them to reside in either flash memory (the default) or on-chip static RAM. This is described in Section 6.19 “System control”. 4.0 GB 0xFFFF FFFF AHB PERIPHERALS 3.75 GB 0xF000 0000 VPB PERIPHERALS 3.5 GB 0xE000 0000 3.0 GB RESERVED ADDRESS SPACE 0xC000 0000 0x8000 0000 2.0 GB BOOT BLOCK (12 kB REMAPPED FROM 0x7FFF FFFF ON-CHIP FLASH MEMORY 0x7FFF D000 0x7FFF CFFF RESERVED ADDRESS SPACE 0x7FD0 2000 0x7FD0 1FFF 8 kB ON-CHIP USB DMA RAM (LPC2146/2148) 0x7FD0 0000 0x7FCF FFFF RESERVED ADDRESS SPACE 0x4000 8000 0x4000 7FFF 32 kB ON-CHIP STATIC RAM (LPC2146/2148) 0x4000 4000 0x4000 3FFF 16 kB ON-CHIP STATIC RAM (LPC2142/2144) 0x4000 2000 0x4000 1FFF 8 kB ON-CHIP STATIC RAM (LPC2141) 0x4000 0000 1.0 GB 0x3FFF FFFF RESERVED ADDRESS SPACE 0x0008 0000 0x0007 FFFF TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY (LPC2148) 0x0004 0000 0x0003 FFFF TOTAL OF 256 kB ON-CHIP NON-VOLATILE MEMORY (LPC2146) 0x0002 0000 0x0001 FFFF TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY (LPC2144) 0x0001 0000 0x0000 FFFF TOTAL OF 64 kB ON-CHIP NON-VOLATILE MEMORY (LPC2142) 0x0000 8000 0x0000 7FFF TOTAL OF 32 kB ON-CHIP NON-VOLATILE MEMORY (LPC2141) 0.0 GB 0x0000 0000 002aab558 Fig 5. LPC2141/42/44/46/48 memory map LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 14 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 6.5 Interrupt controller The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt reQuest (FIQ), vectored Interrupt ReQuest (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine does not need to branch into the interrupt service routine but can run from the interrupt vector location. If more than one request is assigned to the FIQ class, the FIQ service routine will read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority. The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active. 6.5.1 Interrupt sources Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source. 6.6 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. The Pin Control Module with its pin select registers defines the functionality of the microcontroller in a given hardware environment. After reset all pins of Port 0 and Port 1 are configured as input with the following exceptions: If debug is enabled, the JTAG pins will assume their JTAG functionality; if trace is enabled, the Trace pins will assume their trace functionality. The pins associated with the I2C0 and I2C1 interface are open drain. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 15 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 6.7 Fast general purpose parallel I/O (GPIO) Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins. LPC2141/42/44/46/48 introduce accelerated GPIO functions over prior LPC2000 devices: • GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing. • Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. • All GPIO registers are byte addressable. • Entire port value can be written in one instruction. 6.7.1 Features • Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. • Direction control of individual bits. • Separate control of output set and clear. • All I/O default to inputs after reset. 6.8 10-bit ADC The LPC2141/42 contain one and the LPC2144/46/48 contain two analog to digital converters. These converters are single 10-bit successive approximation analog to digital converters. While ADC0 has six channels, ADC1 has eight channels. Therefore, total number of available ADC inputs for LPC2141/42 is 6 and for LPC2144/46/48 is 14. 6.8.1 Features • 10 bit successive approximation analog to digital converter. • Measurement range of 0V to VREF (2.5V  VREF  V ). DDA • Each converter capable of performing more than 400000 10-bit samples per second. • Every analog input has a dedicated result register to reduce interrupt overhead. • Burst conversion mode for single or multiple inputs. • Optional conversion on transition on input pin or timer match signal. • Global Start command for both converters (LPC2142/44/46/48 only). 6.9 10-bit DAC The DAC enables the LPC2141/42/44/46/48 to generate a variable analog output. The maximum DAC output voltage is the VREF voltage. 6.9.1 Features • 10-bit DAC. • Buffered output. • Power-down mode available. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 16 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers • Selectable speed versus power. 6.10 USB 2.0 device controller The USB is a 4-wire serial bus that supports communication between a host and a number (127 max) of peripherals. The host controller allocates the USB bandwidth to attached devices through a token based protocol. The bus supports hot plugging, unplugging, and dynamic configuration of the devices. All transactions are initiated by the host controller. The LPC2141/42/44/46/48 is equipped with a USB device controller that enables 12Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory and DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate end point buffer memory. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. A DMA controller (available in LPC2146/48 only) can transfer data between an endpoint buffer and the USB RAM. 6.10.1 Features • Fully compliant with USB 2.0 Full-speed specification. • Supports 32 physical (16 logical) endpoints. • Supports control, bulk, interrupt and isochronous endpoints. • Scalable realization of endpoints at run time. • Endpoint maximum packet size selection (up to USB maximum specification) by software at run time. • RAM message buffer size based on endpoint realization and maximum packet size. • Supports SoftConnect and GoodLink LED indicator. These two functions are sharing one pin. • Supports bus-powered capability with low suspend current. • Supports DMA transfer on all non-control endpoints (LPC2146/48 only). • One duplex DMA channel serves all endpoints (LPC2146/48 only). • Allows dynamic switching between CPU controlled and DMA modes (only in LPC2146/48). • Double buffer implementation for bulk and isochronous endpoints. 6.11 UARTs The LPC2141/42/44/46/48 each contain two UARTs. In addition to standard transmit and receive data lines, the LPC2144/46/48 UART1 also provides a full modem control handshake interface. Compared to previous LPC2000 microcontrollers, UARTs in LPC2141/42/44/46/48 introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers to achieve standard baud rates such as 115200 with any crystal frequency above 2MHz. In addition, auto-CTS/RTS flow-control functions are fully implemented in hardware (UART1 in LPC2144/46/48 only). LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 17 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 6.11.1 Features • 16B Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points at 1B, 4B, 8B, and 14B • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Transmission FIFO control enables implementation of software (XON/XOFF) flow control on both UARTs. • LPC2144/46/48 UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). 6.12 I2C-bus serial I/O controller The LPC2141/42/44/46/48 each contain two I2C-bus controllers. The I2C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line (SCL), and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the capability to both receive and send information (such as memory)). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, it can be controlled by more than one bus master connected to it. The I2C-bus implemented in LPC2141/42/44/46/48 supports bit rates up to 400kbit/s (Fast I2C-bus). 6.12.1 Features • Compliant with standard I2C-bus interface. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. 6.13 SPI serial I/O controller The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a full duplex serial interface, designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 18 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 6.13.1 Features • Compliant with SPI specification. • Synchronous, Serial, Full Duplex, Communication. • Combined SPI master and slave. • Maximum data bit rate of one eighth of the input clock rate. 6.14 SSP serial I/O controller The LPC2141/42/44/46/48 each contain one Serial Synchronous Port controller (SSP). The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. However, only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with data frames of 4bits to 16bits of data flowing from the master to the slave and from the slave to the master. Often only one of these data flows carries meaningful data. 6.14.1 Features • Compatible with Motorola’s SPI, TI’s 4-wire SSI and National Semiconductor’s Microwire buses. • Synchronous serial communication. • Master or slave operation. • 8-frame FIFOs for both transmit and receive. • Fourbits to 16 bits per frame. 6.15 General purpose timers/external event counters The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them. The LPC2141/42/44/46/48 can count external events on one of the capture inputs if the minimum external pulse is equal or longer than a period of the PCLK. In this configuration, unused capture lines can be selected as regular timer capture inputs, or used as external interrupts. 6.15.1 Features • A 32-bit timer/counter with a programmable 32-bit prescaler. • External event counter or timer operation. • Four 32-bit capture channels per timer/counter that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 19 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Four external outputs per timer/counter corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. 6.16 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time. 6.16.1 Features • Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal pre-scaler. • Selectable time period from (T  256 4) to (T  232 4) in multiples of cy(PCLK) cy(PCLK) T 4. cy(PCLK) 6.17 Real-time clock The RTC is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode). 6.17.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra-low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the external crystal/oscillator input at XTAL1. Programmable reference clock divider allows fine adjustment of the RTC. • Dedicated power supply pin can be connected to a battery or the main 3.3V. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 20 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 6.18 Pulse width modulator The PWM is based on the standard timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2141/42/44/46/48. The timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is also based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (MR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an MR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the MR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). 6.18.1 Features • Seven match registers allow up to six single edge controlled or three double edge controlled PWM outputs, or a mix of both types. • The match registers also allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the output is a constant LOW. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 21 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • May be used as a standard timer if the PWM mode is not enabled. • A 32-bit Timer/Counter with a programmable 32-bit Prescaler. 6.19 System control 6.19.1 Crystal oscillator On-chip integrated oscillator operates with external crystal in range of 1MHz to 25MHz. The oscillator output frequency is called f and the ARM processor clock frequency is osc referred to as CCLK for purposes of rate equations, etc. f and CCLK are the same osc value unless the PLL is running and connected. Refer to Section 6.19.2 “PLL” for additional information. 6.19.2 PLL The PLL accepts an input clock frequency in the range of 10MHz to 25MHz. The input frequency is multiplied up into the range of 10MHz to 60MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The CCO operates in the range of 156MHz to 320MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50% duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The PLL settling time is 100s. 6.19.3 Reset and wake-up timer Reset has two sources on the LPC2141/42/44/46/48: the RESET pin and watchdog reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by any source starts the Wake-up Timer (see Wake-up Timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip flash controller has completed its initialization. When the internal reset is removed, the processor begins executing at address 0, which is the reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined values. The Wake-up Timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the Wake-up Timer. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 22 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of V ramp (in the case of power on), the type of crystal DD and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 6.19.4 Brownout detector The LPC2141/42/44/46/48 include 2-stage monitoring of the voltage on the V pins. If DD this voltage falls below 2.9V, the BOD asserts an interrupt signal to the VIC. This signal can be enabled for interrupt; if not, software can monitor the signal by reading dedicated register. The second stage of low voltage detection asserts reset to inactivate the LPC2141/42/44/46/48 when the voltage on the V pins falls below 2.6V. This reset DD prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1V, at which point the POR circuitry maintains the overall reset. Both the 2.9V and 2.6V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.9V detection to reliably interrupt, or a regularly-executed event loop to sense the condition. 6.19.5 Code security This feature of the LPC2141/42/44/46/48 allow an application to control whether it can be debugged or protected from observation. If after reset on-chip boot loader detects a valid checksum in flash and reads 0x87654321 from address 0x1FC in flash, debugging will be disabled and thus the code in flash will be protected from observation. Once debugging is disabled, it can be enabled only by performing a full chip erase using the ISP. 6.19.6 External interrupt inputs The LPC2141/42/44/46/48 include up to nine edge or level sensitive External Interrupt Inputs as selectable pin functions. When the pins are combined, external events can be processed as four independent interrupt signals. The External Interrupt Inputs can optionally be used to wake-up the processor from Power-down mode. Additionally capture input pins can also be used as external interrupts without the option to wake the device up from Power-down mode. 6.19.7 Memory mapping control The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x00000000. Vectors may be mapped to the bottom of the on-chip flash memory, or to the on-chip static RAM. This allows code running in different memory spaces to have control of the interrupts. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 23 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 6.19.8 Power control The LPC2141/42/44/46/48 supports two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode and the logic levels of chip output pins remain static. The Power-down mode can be terminated and normal operation resumed by either a reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero. Selecting an external 32kHz clock instead of the PCLK as a clock-source for the on-chip RTC will enable the microcontroller to have the RTC active during Power-down mode. Power-down current is increased with RTC active. However, it is significantly lower than in Idle mode. A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings during active and Idle mode. 6.19.9 APB bus The APB divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first is to provide peripherals with the desired PCLK via APB bus so that they can operate at the speed chosen for the ARM processor. In order to achieve this, the APB bus may be slowed down to 1 to 1 of the processor clock rate. Because the APB bus must work 2 4 properly at power-up (and its timing cannot be altered if it does not work since the APB divider control registers reside on the APB bus), the default condition at reset is for the APB bus to run at 1 of the processor clock rate. The second purpose of the APB divider 4 is to allow power savings when an application does not require any peripherals to run at the full processor rate. Because the APB divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode. 6.20 Emulation and debugging The LPC2141/42/44/46/48 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on Port 1. This means that all communication, timer and interface peripherals residing on Port 0 are available during the development and debugging phase as they are when the application is run in the embedded system itself. 6.20.1 EmbeddedICE Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the remote debug protocol commands to the JTAG data needed to access the ARM core. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 24 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The DCC is accessed as a co-processor 14 by the program running on the ARM7TDMI-S core. The DCC allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The DCC data and control registers are mapped in to addresses in the EmbeddedICE logic. This clock must be slower than 1 of the CPU clock (CCLK) for the JTAG interface to 6 operate. 6.20.2 Embedded trace Since the LPC2141/42/44/46/48 have significant amounts of on-chip memory, it is not possible to determine how the processor core is operating simply by observing the external pins. The Embedded Trace Macrocell (ETM) provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to the trace port. The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external trace port analyzer must capture the trace information under software debugger control. Instruction trace (or PC trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction. 6.20.3 RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2141/42/44/46/48 contain a specific configuration of RealMonitor software programmed into the on-chip flash memory. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 25 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 7. Limiting values Table 4. Limiting valu es In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit V supply voltage (core and external rail) 0.5 +3.6 V DD V analog 3.3 V pad supply voltage 0.5 +4.6 V DDA V input voltage on pin VBAT for the RTC 0.5 +4.6 V i(VBAT) V input voltage on pin VREF 0.5 +4.6 V i(VREF) V analog input voltage on ADC related 0.5 +5.1 V IA pins V input voltage 5V tolerant I/O [2] 0.5 +6.0 V I pins; only valid when the V DD supply voltage is present other I/O pins [2][3] 0.5 V + 0.5 V DD I supply current per supply pin [4] - 100 mA DD I ground current per ground pin [4] - 100 mA SS I sink current for I2C-bus; DC; - 20 mA sink T = 85 C T storage temperature [5] 65 +150 C stg P total power dissipation (per package) based on package - 1.5 W tot(pack) heat transfer, not device power consumption V electrostatic discharge voltage human body model [6] esd all pins 4000 +4000 V [1] The following applies to the Limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Including voltage on outputs in 3-state mode. [3] Not to exceed 4.6V. [4] The peak current is limited to 25 times the corresponding maximum current. [5] Dependent on package type. [6] Human body model: equivalent to discharging a 100pF capacitor through a 1.5k series resistor. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 26 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 8. Static characteristics Table 5. Static charac teristics T =40C to +85C for commercial applications, unless otherwise specified. amb Symbol Parameter Conditions Min Typ[1] Max Unit V supply voltage [2] 3.0 3.3 3.6 V DD V analog supply voltage 3.3V pad 3.0 3.3 3.6 V DDA V input voltage on pin [3] 2.0 3.3 3.6 V i(VBAT) VBAT V input voltage on pin 2.5 3.3 V V i(VREF) DDA VREF Standard port pins, RESET, P1.26/RTCK I LOW-level input current V =0V; no pull-up - - 3 A IL I I HIGH-level input current V =V ; no pull-down - - 3 A IH I DD I OFF-state output V =0V; V =V ; no - - 3 A OZ O O DD current pull-up/down I I/O latch-up current (0.5V ) < V < (1.5V ); - - 100 mA latch DD I DD T < 125C j V input voltage pin configured to provide a [4][5][6] 0 - 5.5 V I digital function [7] V output voltage output active 0 - V V O DD V HIGH-level input voltage 2.0 - - V IH V LOW-level input voltage - - 0.8 V IL V hysteresis voltage 0.4 - - V hys V HIGH-level output I =4 mA [8] V  0.4 - - V OH OH DD voltage V LOW-level output I =4 mA [8] - - 0.4 V OL OL voltage I HIGH-level output V =V 0.4V [8] 4 - - mA OH OH DD current I LOW-level output V =0.4V [8] 4 - - mA OL OL current I HIGH-level short-circuit V =0V [9] - - 45 mA OHS OH output current I LOW-level short-circuit V =V [9] - - 50 mA OLS OL DDA output current I pull-down current V =5V [10] 10 50 150 A pd I I pull-up current V =0V [11] 15 50 85 A pu I V <V <5V [10] 0 0 0 A DD I LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 27 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 5. Static characteristics …continued T =40C to +85C for commercial applications, unless otherwise specified. amb Symbol Parameter Conditions Min Typ[1] Max Unit I active mode supply V =3.3V; T =25C; - 15 50 DD(act) DD amb current code while(1){} executed from flash, no active peripherals CCLK=10MHz mA CCLK=60MHz - 40 70 mA V =3.3V; T =25C; - 27 70 DD amb code executed from flash; USB enabled and active; all other peripherals disabled CCLK=12MHz mA CCLK=60MHz - 57 90 mA I Power-down mode V =3.3V; T =25C - 40 100 A DD(pd) DD amb supply current V =3.3V; T =85C - 250 500 A DD amb I Power-down mode RTCclock=32kHz [12] - 15 30 BATpd battery supply current (fromRTCXnpins); T =25C amb V =3.0V; V =2.5V A DD i(VBAT) V =3.0V; V =3.0V - 20 40 A DD i(VBAT) I active mode battery CCLK=60MHz; [12] - 78 - BATact supply current PCLK=15MHz; PCLKenabledtoRTCK; RTCclock=32kHz (fromRTCXnpins); T =25C amb V =3.0V; V =3.0V A DD i(VBAT) I optimized active mode PCLK disabled to RTCK in the [12][13] - 23 - BATact(opt) battery supply current PCONP register; RTCclock=32kHz (fromRTCXn pins); T =25C; V =3.3V amb i(VBAT) CCLK=25MHz A CCLK=60MHz - 30 - A I2C-bus pins V HIGH-level input voltage 0.7V - - V IH DD V LOW-level input voltage - - 0.3V V IL DD V hysteresis voltage - 0.05V - V hys DD V LOW-level output I =3 mA [8] - - 0.4 V OL OLS voltage I input leakage current V =V [14] - 2 4 A LI I DD V =5V - 10 22 A I Oscillator pins V input voltage on pin 0.5 1.8 1.95 V i(XTAL1) XTAL1 LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 28 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 5. Static characteristics …continued T =40C to +85C for commercial applications, unless otherwise specified. amb Symbol Parameter Conditions Min Typ[1] Max Unit V output voltage on pin 0.5 1.8 1.95 V o(XTAL2) XTAL2 V input voltage on pin 0.5 1.8 1.95 V i(RTCX1) RTCX1 V output voltage on pin 0.5 1.8 1.95 V o(RTCX2) RTCX2 USB pins I OFF-state output 0V<V <3.3V - - 10 A OZ I current V V line input voltage - - 5.25 V BUS BUS on the USB connector V differential input |(D+)(D)| 0.2 - - V DI sensitivity V differential includes V range 0.8 - 2.5 V CM DI common-mode range V single-ended receiver 0.8 - 2.0 V th(rs)se switching threshold voltage V LOW output level R of 1.5k to 3.6V - - 0.3 V OL L V HIGH output level R of 15k to GND 2.8 - 3.6 V OH L C transceiver capacitance pin to GND - - 20 pF trans Z driver output impedance steady state drive [15] 29 - 44  DRV for driver which is not high-speed capable R pull-up resistance SoftConnect=ON 1.1 - 1.9 k pu [1] Typical ratings are not guaranteed. The values listed are at room temperature (25C), nominal supply voltages. [2] Core and external rail. [3] The RTC typically fails when V drops below 1.6V. i(VBAT) [4] Including voltage on outputs in 3-state mode. [5] V supply voltages must be present. DD [6] 3-state outputs go into 3-state mode when V is grounded. DD [7] Please also see the errata note mentioned in errata sheet. [8] Accounts for 100mV voltage drop in all supply lines. [9] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [10] Minimum condition for V =4.5V, maximum condition for V =5.5V. I I [11] Applies to P1.16 to P1.31. [12] On pin VBAT. [13] Optimized for low battery consumption. [14] To V . SS [15] Includes external resistors of 33±1% on D+ and D. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 29 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 9. Dynamic characteristics Table 6. Dynamic cha racteristics of USB pins (full-speed) C = 50 pF; R = 1.5k on D+ to V , unless otherwise specified. L pu DD Symbol Parameter Conditions Min Typ Max Unit t rise time 10% to 90% 4 - 20 ns r t fall time 10% to 90% 4 - 20 ns f t differential rise and fall time (t/t) 90 - 110 % FRFM r f matching V output signal crossover voltage 1.3 - 2.0 V CRS t source SE0 interval of EOP see Figure7 160 - 175 ns FEOPT t source jitter for differential transition see Figure7 2 - +5 ns FDEOP to SE0 transition t receiver jitter to next transition 18.5 - +18.5 ns JR1 t receiver jitter for paired transitions 10% to 90% 9 - +9 ns JR2 t EOP width at receiver must reject as [1] 40 - - ns EOPR1 EOP; see Figure7 t EOP width at receiver must accept as [1] 82 - - ns EOPR2 EOP; see Figure7 [1] Characterized but not implemented as production test. Guaranteed by design. Table 7. Dynamic cha racteristics T =40C to +85C for commercial applications, V over specified ranges[1] amb DD Symbol Parameter Conditions Min Typ[2] Max Unit External clock f oscillator frequency 10 - 25 MHz osc T clock cycle time 40 - 100 ns cy(clk) t clock HIGH time T 0.4 - - ns CHCX cy(clk) t clock LOW time T 0.4 - - ns CLCX cy(clk) t clock rise time - - 5 ns CLCH t clock fall time - - 5 ns CHCL Port pins (except P0.2, P0.3, P0.11, and P0.14) t output rise time - 10 - ns r(o) t output fall time - 10 - ns f(o) I2C-bus pins (P0.2, P0.3, P0.11, and P0.14) t output fall time V to V 20 + 0.1  C [3] - - ns f(o) IH IL b [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25C), nominal supply voltages. [3] Bus capacitance C in pF, from 10 pF to 400 pF. b LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 30 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 9.1 Timing tCHCX tCHCL tCLCX tCLCH Tcy(clk) 002aaa907 Fig 6. External clock timing (with an amplitude of at least V = 200 mV) i(RMS) TPERIOD crossover point extended crossover point differential data lines source EOP width: tFEOPT differential data to SE0/EOP skew n × TPERIOD + tFDEOP receiver EOP width: tEOPR1, tEOPR2 002aab561 Fig 7. Differential data-to-EOP transition skew and EOP width LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 31 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 10. ADC electrical characteristics Table 8. ADC static c haracteristics V =2.5V to 3.6V; T =40C to +85C unless otherwise specified; ADC frequency 4.5MHz. DDA amb Symbol Parameter Conditions Min Typ Max Unit V analog input voltage 0 - V V IA DDA C analog input capacitance - - 1 pF ia E differential linearity error V =0V, V =3.3V [1][2] - - 1 LSB D SSA DDA E integral non-linearity V =0V, V =3.3V [3] - - 2 LSB L(adj) SSA DDA E offset error V =0V, V =3.3V [4] - - 3 LSB O SSA DDA E gain error V =0V, V =3.3V [5] - - 0.5 % G SSA DDA E absolute error V =0V, V =3.3V [6] - - 4 LSB T SSA DDA R voltage source interface [7] - - 40 k vsi resistance [1] The ADC is monotonic, there are no missing codes. [2] The differential linearity error (E ) is the difference between the actual step width and the ideal step width. See Figure8. D [3] The integral non-linearity (E ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after L(adj) appropriate adjustment of gain and offset errors. See Figure8. [4] The offset error (E ) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the O ideal curve. See Figure8. [5] The gain error (E ) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset G error, and the straight line which fits the ideal transfer curve. See Figure8. [6] The absolute error (E ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated T ADC and the ideal transfer curve. See Figure8. [7] See Figure9. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 32 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers offset gain error error EO EG 1023 1022 1021 1020 1019 1018 (2) 7 code (1) out 6 5 (5) 4 (4) 3 (3) 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO Vi(VREF) − VSSA 1 LSB = 1024 002aae604 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 8. ADC characteristics LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 33 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers LPC2141/42/44/46/48 20 kΩ ADx.y Rvsi ADx.ySAMPLE 3 pF 5 pF VEXT VSS 002aab834 Fig 9. Suggested ADC interface - LPC2141/42/44/46/48 ADx.y pin LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 34 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 11. DAC electrical characteristics Table 9. DAC electric al characteristics V =3.0V to 3.6V; T =40C to +85C unless otherwise specified DDA amb Symbol Parameter Conditions Min Typ Max Unit E differential linearity error - 1 - LSB D E integral non-linearity - 1.5 - LSB L(adj) E offset error - 0.6 - % O E gain error - 0.6 - % G C load capacitance - 200 - pF L R load resistance 1 - - k L LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 35 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 12. Application information 12.1 Suggested USB interface solutions VDD CONNECT soft-connect switch LPC2141/42/ R1 44/46/48 1.5 kΩ VBUS D+ RS = 33 Ω USB-B connector D− RS = 33 Ω VSS 002aab563 Fig 10. LPC2141/42/44/46/48 USB interface using the CONNECT function on pin 17 VDD R2 LPC2141/42/ R1 44/46/48 UP_LED 1.5 kΩ VBUS D+ RS = 33 Ω USB-B connector D− RS = 33 Ω VSS 002aab562 Fig 11. LPC2141/42/44/46/48 USB interface using the UP_LED function on pin 17 12.2 Crystal oscillator XTAL input and component selection The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with C = 100 pF. To limit the input voltage to the specified range, choose an additional i capacitor to ground C which attenuates the input voltage by a factor C / (C + C ). In g i i g slave mode, a minimum of 200 mV (RMS) is needed. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 36 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers LPC2xxx XTAL1 Ci Cg 100 pF 002aae718 Fig 12. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100pF (Figure12), with an amplitude between 200mV(RMS) and 1000mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTAL2 pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure13 and in Table10 and Table11. Since the feedback resistance is integrated on chip, only a crystal and the capacitances C and C need to be connected externally in case of X1 X2 fundamental mode oscillation (the fundamental frequency is represented by L, C and L R ). Capacitance C in Figure13 represents the parallel package capacitance and should S P not be larger than 7 pF. Parameters F , C , R and C are supplied by the crystal OSC L S P manufacturer. LPC2xxx L XTAL1 XTAL2 = CL CP XTAL RS CX1 CX2 002aag469 Fig 13. Oscillator modes and models: oscillation mode of operation and external crystal model used for C /C evaluation X1 X2 Table 10. Recommended values for C /C in oscillation mode (crystal and external X1 X2 components parameters): low frequency mode Fundamental oscillation Crystal load Maximum crystal External load frequency F capacitance C series resistance R capacitors C /C OSC L S X1 X2 1MHz to 5MHz 10 pF < 300 18 pF, 18 pF 20 pF < 300 39 pF, 39 pF 30 pF < 300 57pF, 57pF LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 37 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Table 10. Recommended values for C /C in oscillation mode (crystal and external X1 X2 components parameters): low frequency mode Fundamental oscillation Crystal load Maximum crystal External load frequency F capacitance C series resistance R capacitors C /C OSC L S X1 X2 5MHz to 10MHz 10 pF < 300 18 pF, 18 pF 20 pF < 200 39 pF, 39 pF 30 pF < 100 57 pF, 57 pF 10MHz to 15MHz 10 pF < 160 18 pF, 18 pF 20 pF < 60 39 pF, 39 pF 15MHz to 20MHz 10 pF < 80 18 pF, 18 pF Table 11. Recommended values for C /C in oscillation mode (crystal and external X1 X2 components parameters): high frequency mode Fundamental oscillation Crystal load Maximum crystal External load frequency F capacitance C series resistance R capacitors C , C OSC L S X1 X2 15MHz to 20MHz 10 pF < 180 18 pF, 18 pF 20 pF < 100 39 pF, 39 pF 20MHz to 25MHz 10 pF < 160 18 pF, 18 pF 20 pF < 80 39 pF, 39 pF 12.3 RTC 32 kHz oscillator component selection LPC2xxx L RTCX1 RTCX2 = CL CP 32 kHz XTAL RS CX1 CX2 002aaf495 Fig 14. RTC oscillator modes and models: oscillation mode of operation and external crystal model used for C /C evaluation X1 X2 The RTC external oscillator circuit is shown in Figure14. Since the feedback resistance is integrated on chip, only a crystal, the capacitances C and C need to be connected X1 X2 externally to the microcontroller. Table12 gives the crystal parameters that should be used. C is the typical load L capacitance of the crystal and is usually specified by the crystal manufacturer. The actual C influences oscillation frequency. When using a crystal that is manufactured for a L different load capacitance, the circuit will oscillate at a slightly different frequency (depending on the quality of the crystal) compared to the specified one. Therefore for an accurate time reference it is advised to use the load capacitors as specified in Table12 LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 38 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers that belong to a specific C . The value of external capacitances C and C specified in L X1 X2 this table are calculated from the internal parasitic capacitances and the C . Parasitics L from PCB and package are not taken into account. Table 12. Recommended values for the RTC external 32kHz oscillator C /C components X1 X2 Crystal load capacitance Maximum crystal series External load capacitors C /C X1 X2 C resistance R L S 11 pF < 100k 18pF, 18pF 13 pF < 100k 22pF, 22pF 15 pF < 100k 27pF, 27pF 12.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors C , C , and C in case of x1 x2 x3 third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plane. Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C and C should be chosen smaller x1 x2 accordingly to the increase in parasitics of the PCB layout. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 39 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 13. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 33 49 32 ZE e E HE A A2 A1 (A 3 ) wM θ bp Lp pin 1 index L 64 17 1 16 detail X ZD v M A e wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(1) e HD HE L Lp v w y ZD(1) ZE(1) θ mm 1.6 00..2005 11..4355 0.25 00..2177 00..1182 190..91 190..91 0.5 1121..1855 1121..1855 1 00..7455 0.2 0.12 0.1 11..4055 11..4055 70oo Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 00-01-19 SOT314-2 136E10 MS-026 03-02-25 Fig 15. Package outline SOT314-2 (LQFP64) LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 40 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 14. Abbreviations Table 13. Acronym list Acronym Description ADC Analog-to-Digital Converter APB Advanced Peripheral Bus BOD Brown-Out Detection CPU Central Processing Unit DAC Digital-to-Analog Converter DCC Debug Communications Channel DMA Direct Memory Access EOP End Of Packet FIFO First In, First Out GPIO General Purpose Input/Output PLL Phase-Locked Loop POR Power-On Reset PWM Pulse Width Modulator RAM Random Access Memory SE0 Single Ended Zero SPI Serial Peripheral Interface SRAM Static Random Access Memory SSP Synchronous Serial Port UART Universal Asynchronous Receiver/Transmitter USB Universal Serial Bus LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 41 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 15. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC2141_42_44_46_48 v.5 20110812 Product data sheet - LPC2141_42_44_46_48 v.4 Modifications: • Table 3 “Pin description”: Added Table note [10] to RTCX1 and RTCX2 pins. • Table 4 “Limiting values”: Added parameter I . sink • Table 5 “Static characteristics”, I2C-bus pins: Changed typical hysteresis voltage from 0.5V to 0.05V . DD DD • Table 5 “Static characteristics”: Updated min, typical and max values for oscillator pins V , V , V , and V . i(XTAL1) o(XTAL2) i(RTCX1) o(RTCX2) • Table 5 “Static characteristics”: Updated Table note [15]. • Added Section 11 “DAC electrical characteristics”. • Added Section 12.2 “Crystal oscillator XTAL input and component selection”. • Added Section 12.3 “RTC 32 kHz oscillator component selection”. • Added Section 12.4 “XTAL and RTCX Printed Circuit Board (PCB) layout guidelines”. • Updated Figure 8 “ADC characteristics”. LPC2141_42_44_46_48 v.4 20081117 Product data sheet - LPC2141_42_44_46_48 v.3 Modifications: • Replaced all occurrences of VPB with APB. • Table3: clarified which pins do/don’t have internal pull-ups. • Table4: changed storage temperature range from 40C/125C to 65C/150C. • Table5: added Table note7 to input voltage spec. • Table5: modified Table note9. • Table5: moved hysteresis voltage (0.4 V) from typ to min column. • Figure8: updated figure and figure title, removed note LPC2141_42_44_46_48 v.3 20071019 Product data sheet - LPC2141_42_44_46_48 v.2 LPC2141_42_44_46_48 v.2 20060828 Product data sheet - LPC2141_42_44_46_48 v.1 LPC2141_42_44_46_48 v.1 20051003 Preliminary data sheet - - LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 42 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URLhttp://www.nxp.com. 16.2 Definitions malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of Draft — The document is a draft version only. The content is still under NXP Semiconductors products in such equipment or applications and internal review and subject to formal approval, which may result in therefore such inclusion and/or use is at the customer’s own risk. modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of Applications — Applications that are described herein for any of these information included herein and shall have no liability for the consequences of products are for illustrative purposes only. NXP Semiconductors makes no use of such information. representation or warranty that such applications will be suitable for the specified use without further testing or modification. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended Customers are responsible for the design and operation of their applications for quick reference only and should not be relied upon to contain detailed and and products using NXP Semiconductors products, and NXP Semiconductors full information. For detailed and full information see the relevant full data accepts no liability for any assistance with applications or customer product sheet, which is available on request via the local NXP Semiconductors sales design. It is customer’s sole responsibility to determine whether the NXP office. In case of any inconsistency or conflict with the short data sheet, the Semiconductors product is suitable and fit for the customer’s applications and full data sheet shall prevail. products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate Product specification — The information and data provided in a Product design and operating safeguards to minimize the risks associated with their data sheet shall define the specification of the product as agreed between applications and products. NXP Semiconductors and its customer, unless NXP Semiconductors and NXP Semiconductors does not accept any liability related to any default, customer have explicitly agreed otherwise in writing. In no event however, damage, costs or problem which is based on any weakness or default in the shall an agreement be valid in which the NXP Semiconductors product is customer’s applications or products, or the application or use by customer’s deemed to offer functions and qualities beyond those described in the third party customer(s). Customer is responsible for doing all necessary Product data sheet. testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and 16.3 Disclaimers the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limited warranty and liability — Information in this document is believed to Limiting values — Stress above one or more limiting values (as defined in be accurate and reliable. However, NXP Semiconductors does not give any the Absolute Maximum Ratings System of IEC60134) will cause permanent representations or warranties, expressed or implied, as to the accuracy or damage to the device. Limiting values are stress ratings only and (proper) completeness of such information and shall have no liability for the operation of the device at these or any other conditions above those given in consequences of use of such information. the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or In no event shall NXP Semiconductors be liable for any indirect, incidental, repeated exposure to limiting values will permanently and irreversibly affect punitive, special or consequential damages (including - without limitation - lost the quality and reliability of the device. profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such Terms and conditions of commercial sale — NXP Semiconductors damages are based on tort (including negligence), warranty, breach of products are sold subject to the general terms and conditions of commercial contract or any other legal theory. sale, as published at http://www.nxp.com/profile/terms, unless otherwise Notwithstanding any damages that customer might incur for any reason agreed in a valid written individual agreement. In case an individual whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards agreement is concluded only the terms and conditions of the respective customer for the products described herein shall be limited in accordance agreement shall apply. NXP Semiconductors hereby expressly objects to with the Terms and conditions of commercial sale of NXP Semiconductors. applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without No offer to sell or license — Nothing in this document may be interpreted or limitation specifications and product descriptions, at any time and without construed as an offer to sell products that is open for acceptance or the grant, notice. This document supersedes and replaces all information supplied prior conveyance or implication of any license under any copyrights, patents or to the publication hereof. other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, Export control — This document as well as the item(s) described herein authorized or warranted to be suitable for use in life support, life-critical or may be subject to export control regulations. Export might require a prior safety-critical systems or equipment, nor in applications where failure or authorization from national authorities. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 43 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers Non-automotive qualified products — Unless this data sheet expressly NXP Semiconductors’ specifications such use shall be solely at customer’s states that this specific NXP Semiconductors product is automotive qualified, own risk, and (c) customer fully indemnifies NXP Semiconductors for any the product is not suitable for automotive use. It is neither qualified nor tested liability, damages or failed product claims resulting from customer design and in accordance with automotive testing or application requirements. NXP use of the product for automotive applications beyond NXP Semiconductors’ Semiconductors accepts no liability for inclusion and/or use of standard warranty and NXP Semiconductors’ product specifications. non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in 16.4 Trademarks automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the Notice: All referenced brands, product names, service names and trademarks product for such automotive applications, use and specifications, and (b) are the property of their respective owners. whenever customer uses the product for automotive applications beyond 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 44 of 45

LPC2141/42/44/46/48 NXP Semiconductors Single-chip 16-bit/32-bit microcontrollers 18. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 6.19.5 Code security. . . . . . . . . . . . . . . . . . . . . . . . . 23 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 6.19.6 External interrupt inputs. . . . . . . . . . . . . . . . . 23 2.1 Key features. . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6.19.7 Memory mapping control. . . . . . . . . . . . . . . . 23 6.19.8 Power control. . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 6.19.9 APB bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2 6.20 Emulation and debugging . . . . . . . . . . . . . . . 24 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.20.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 24 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 6.20.2 Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 25 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.20.3 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 26 6 Functional description . . . . . . . . . . . . . . . . . . 13 8 Static characteristics . . . . . . . . . . . . . . . . . . . 27 6.1 Architectural overview . . . . . . . . . . . . . . . . . . 13 9 Dynamic characteristics. . . . . . . . . . . . . . . . . 30 6.2 On-chip flash program memory . . . . . . . . . . . 13 9.1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 14 10 ADC electrical characteristics. . . . . . . . . . . . 32 6.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 15 11 DAC electrical characteristics. . . . . . . . . . . . 35 6.5.1 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 15 12 Application information . . . . . . . . . . . . . . . . . 36 6.6 Pin connect block. . . . . . . . . . . . . . . . . . . . . . 15 12.1 Suggested USB interface solutions. . . . . . . . 36 6.7 Fast general purpose parallel I/O (GPIO). . . . 16 12.2 Crystal oscillator XTAL input and component 6.7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.8 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 12.3 RTC 32 kHz oscillator component selection . 38 6.8.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 12.4 XTAL and RTCX Printed Circuit Board (PCB) 6.9 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 layout guidelines . . . . . . . . . . . . . . . . . . . . . . 39 6.9.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 40 6.10 USB 2.0 device controller. . . . . . . . . . . . . . . . 17 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.10.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . 42 6.11 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.11.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16 Legal information . . . . . . . . . . . . . . . . . . . . . . 43 6.12 I2C-bus serial I/O controller . . . . . . . . . . . . . . 18 16.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 43 6.12.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.13 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 18 16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.13.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 16.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.14 SSP serial I/O controller. . . . . . . . . . . . . . . . . 19 17 Contact information . . . . . . . . . . . . . . . . . . . . 44 6.14.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 18 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.15 General purpose timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.15.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.16 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 20 6.16.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.17 Real-time clock. . . . . . . . . . . . . . . . . . . . . . . . 20 6.17.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.18 Pulse width modulator . . . . . . . . . . . . . . . . . . 21 6.18.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.19 System control . . . . . . . . . . . . . . . . . . . . . . . . 22 6.19.1 Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 22 6.19.2 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.19.3 Reset and wake-up timer . . . . . . . . . . . . . . . . 22 6.19.4 Brownout detector . . . . . . . . . . . . . . . . . . . . . 23 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 August 2011 Document identifier: LPC2141_42_44_46_48

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: N XP: LPC2141FBD64,151 LPC2142FBD64,151 LPC2144FBD64,151 LPC2146FBD64,151 LPC2148FBD64,151 LPC2146FBD64,557