LPC1110/11/12/13/14/15 32-bit ARM Cortex-M0 microcontroller; up to 64 kB flash and 8 kB SRAM Rev. 9.2 — 26 March 2014 Product data sheet 1. General description The LPC1110/11/12/13/14/15 are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC1110/11/12/13/14/15 operate at CPU frequencies of up to 50MHz. The peripheral complement of the LPC1110/11/12/13/14/15 includes up to 64 kB of flash memory, up to 8kB of data memory, one Fast-mode Plus I2C-bus interface, one RS-485/EIA-485 UART, up to two SPI interfaces with SSP features, four general purpose counter/timers, a 10-bit ADC, and up to 42 general purpose I/O pins. Remark: The LPC111x series consists of the LPC1100 series (parts LPC111x/101/201/301), LPC1100L series (parts LPC111x/002/102/202/302), and the LPC1100XL series (parts LPC111x/103/203/303/323/333). The LPC1100L and LPC1100XL series include the power profiles, a windowed watchdog timer, and a configurable open-drain mode. For related documentation, see Section 16 “References”. 2. Features and benefits  System: ARM Cortex-M0 processor, running at frequencies of up to 50MHz. ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC). Non-Maskable Interrupt (NMI) input selectable from several input sources (LPC1100XL series only). Serial Wire Debug. System tick timer.  Memory: 64kB (LPC1115), 56kB (LPC1114/333), 48kB (LPC1114/323), 32 kB (LPC1114/102/201/202/203/301/302/303), 24 kB (LPC1113), 16 kB (LPC1112), 8kB (LPC1111), or 4 kB (LPC1110) on-chip flash programming memory. 256 byte page erase function (LPC1100XL series only) 8 kB, 4 kB, 2 kB, or 1 kB SRAM. In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software.

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller  Digital peripherals: Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. In addition, a configurable open-drain mode is supported on the LPC1100L and LPC1100XL series. GPIO pins can be used as edge and level sensitive interrupt sources. High-current output driver (20 mA) on one pin. High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus (not on LPC1112FDH20/102). Four general purpose counter/timers with up to eight capture inputs and up to 13 match outputs. Programmable WatchDog Timer (WDT) the LPC1100 series only. Programmable windowed WDT on the LPC1100L and LPC1100XL series only.  Analog peripherals: 10-bit ADC with input multiplexing among 5, 6, or 8 pins depending on package size.  Serial interfaces: UART with fractional baud rate generation, internal FIFO, and RS-485 support. Two SPI controllers with SSP features and with FIFO and multi-protocol capabilities (second SPI on LPC1100 and LPC1100L series LQFP48 package only). I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode (not on LPC1112FDH20/102).  Clock generation: 12MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock. Crystal oscillator with an operating range of 1MHz to 25MHz. Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3MHz. PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator. Clock output function with divider that can reflect the system oscillator clock, IRC clock, CPU clock, and the Watchdog clock.  Power control: Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, and Deep power-down modes. Power profiles residing in boot ROM allowing to optimize performance and minimize power consumption for any given application through one simple function call. (LPC1100L and LPC1100XL series only.) Three reduced power modes: Sleep, Deep-sleep, and Deep power-down. Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 13 of the functional pins. Power-On Reset (POR). Brownout detect with up to four separate thresholds for interrupt and forced reset.  Unique device serial number for identification.  Single power supply (1.8V to 3.6V).  Available as LQFP48 package, HVQFN33 package, and TFBGA48 package. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 2 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller  LPC1100L series available as TSSOP28 package, DIP28 package, TSSOP20 package, and SO20 package.  Extended temperature (40C to +105C) for selected parts (see Table2). 3. Applications  eMetering  Lighting  Alarm systems  White goods 4. Ordering information Table 1. Ordering info rmation Type number Package Name Description Version SO20, TSSOP20, TSSOP28, and DIP28 packages LPC1110FD20 SO20 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 LPC1111FDH20/002 TSSOP20 TSSOP20: plastic thin shrink small outline package; 20 leads; body SOT360-1 width 4.4 mm LPC1112FD20/102 SO20 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 LPC1112FDH20/102 TSSOP20 TSSOP20: plastic thin shrink small outline package; 20 leads; body SOT360-1 width 4.4 mm LPC1112FDH28/102 TSSOP28 TSSOP28: plastic thin shrink small outline package; 28 leads; body SOT361-1 width 4.4 mm LPC1114FDH28/102 TSSOP28 TSSOP28: plastic thin shrink small outline package; 28 leads; body SOT361-1 width 4.4 mm LPC1114FN28/102 DIP28 DIP28: plastic dual in-line package; 28 leads (600 mil) SOT117-1 HVQFN24/33, LQFP48, and TFBGA48 packages LPC1111FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1111FHN33/102 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1111FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1111FHN33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1111FHN33/103 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1111JHN33/103 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1111FHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1111JHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1112FHN33/101 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1112FHN33/102 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 3 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 1. Ordering information …continued Type number Package Name Description Version LPC1112FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1112FHN33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1112FHN24/202 HVQFN24 HVQFN24: plastic thermal enhanced very thin quad flat package; no SOT616-3 leads; 24 terminals; body 4 x 4 x 0.85 mm LPC1112FHI33/102 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 5  5  0.85 mm LPC1112FHI33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 5  5  0.85 mm LPC1112FHI33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 5  5  0.85 mm LPC1112JHI33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 5  5  0.85 mm LPC1112FHN33/103 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1112JHN33/103 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1112JHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1112FHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1113FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1113FHN33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1113FHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1113JHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1113FHN33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1113FHN33/302 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1113FHN33/303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1113JHN33/303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1114FHN33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1114FHN33/202 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1114FHN33/301 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1114FHN33/302 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 4 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 1. Ordering information …continued Type number Package Name Description Version LPC1114FHI33/302 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 5  5  0.85 mm LPC1114FHI33/303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 5  5  0.85 mm LPC1114JHI33/303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 5  5  0.85 mm LPC1114FHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1114JHN33/203 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1114FHN33/303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1114JHN33/303 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1114FHN33/333 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1114JHN33/333 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no n/a leads; 33 terminals; body 7  7  0.85 mm LPC1113FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1113FBD48/302 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1113FBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1113JBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1114FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1114FBD48/302 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1114FBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1114JBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1114FBD48/323 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1114JBD48/323 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1114FBD48/333 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1114JBD48/333 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1115FBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 5 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 1. Ordering information …continued Type number Package Name Description Version LPC1115JBD48/303 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC1115FET48/303 TFBGA48 plastic thin fine-pitch ball grid array package; 48 balls; body 4.5  4.5 SOT1155-2  0.7mm LPC1115JET48/303 TFBGA48 plastic thin fine-pitch ball grid array package; 48 balls; body 4.5  4.5 SOT1155-2  0.7mm 4.1 Ordering options Table 2. Ordering opt ions Type number Series Flash Total Power UART I2C/ SPI ADC GPIO Package Temp[1] SRAM profiles Fast+ channel LPC1110 LPC1110FD20 LPC1100L 4 kB 1 kB yes 1 1 1 5 16 SO20 F LPC1111 LPC1111FDH20/002 LPC1100L 8 kB 2 kB yes 1 1 1 5 16 TSSOP20 F LPC1111FHN33/101 LPC1100 8 kB 2 kB no 1 1 1 8 28 HVQFN33 F LPC1111FHN33/102 LPC1100L 8 kB 2 kB yes 1 1 1 8 28 HVQFN33 F LPC1111FHN33/103 LPC1100XL 8 kB 2 kB yes 1 1 2 8 28 HVQFN33 F LPC1111JHN33/103 LPC1100XL 8 kB 2 kB yes 1 1 2 8 28 HVQFN33 J LPC1111FHN33/201 LPC1100 8 kB 4 kB no 1 1 1 8 28 HVQFN33 F LPC1111FHN33/202 LPC1100L 8 kB 4 kB yes 1 1 1 8 28 HVQFN33 F LPC1111FHN33/203 LPC1100XL 8 kB 4 kB yes 1 1 2 8 28 HVQFN33 F LPC1111JHN33/203 LPC1100XL 8 kB 4 kB yes 1 1 2 8 28 HVQFN33 J LPC1112 LPC1112FD20/102 LPC1100L 16 kB 4 kB yes 1 1 1 5 16 SO20 F LPC1112FDH20/102 LPC1100L 16 kB 4 kB yes 1 - 1 5 14 TSSOP20 F LPC1112FDH28/102 LPC1100L 16 kB 4 kB yes 1 1 1 6 22 TSSOP28 F LPC1112FHN24/202 LPC1100L 16 kB 4 kB yes 1 1 1 6 19 HVQFN24 F LPC1112FHN33/101 LPC1100 16 kB 2 kB no 1 1 1 8 28 HVQFN33 F LPC1112FHN33/102 LPC1100L 16 kB 2 kB yes 1 1 1 8 28 HVQFN33 F LPC1112FHN33/103 LPC1100XL 16 kB 2 kB yes 1 1 2 8 28 HVQFN33 F LPC1112JHN33/103 LPC1100XL 16 kB 2 kB yes 1 1 2 8 28 HVQFN33 J LPC1112FHN33/201 LPC1100 16 kB 4 kB no 1 1 1 8 28 HVQFN33 F LPC1112FHN33/202 LPC1100L 16 kB 4 kB yes 1 1 1 8 28 HVQFN33 F LPC1112FHN33/203 LPC1100XL 16 kB 4 kB yes 1 1 2 8 28 HVQFN33 F LPC1112JHN33/203 LPC1100XL 16 kB 4 kB yes 1 1 2 8 28 HVQFN33 J LPC1112FHI33/102 LPC1100L 16 kB 2 kB yes 1 1 1 8 28 HVQFN33 F LPC1112FHI33/202 LPC1100L 16 kB 4 kB yes 1 1 1 8 28 HVQFN33 F LPC1112FHI33/203 LPC1100XL 16 kB 4 kB yes 1 1 2 8 28 HVQFN33 F LPC1112JHI33/203 LPC1100XL 16 kB 4 kB yes 1 1 2 8 28 HVQFN33 J LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 6 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 2. Ordering options …continued Type number Series Flash Total Power UART I2C/ SPI ADC GPIO Package Temp[1] SRAM profiles Fast+ channel LPC1113 LPC1113FHN33/201 LPC1100 24 kB 4 kB no 1 1 1 8 28 HVQFN33 F LPC1113FHN33/202 LPC1100L 24 kB 4 kB yes 1 1 1 8 28 HVQFN33 F LPC1113FHN33/203 LPC1100XL 24 kB 4 kB yes 1 1 2 8 28 HVQFN33 F LPC1113JHN33/203 LPC1100XL 24 kB 4 kB yes 1 1 2 8 28 HVQFN33 J LPC1113FHN33/301 LPC1100 24 kB 8 kB no 1 1 1 8 28 HVQFN33 F LPC1113FHN33/302 LPC1100L 24 kB 8 kB yes 1 1 1 8 28 HVQFN33 F LPC1113FHN33/303 LPC1100XL 24 kB 8 kB yes 1 1 2 8 28 HVQFN33 F LPC1113JHN33/303 LPC1100XL 24 kB 8 kB yes 1 1 2 8 28 HVQFN33 J LPC1113FBD48/301 LPC1100 24 kB 8 kB no 1 1 2 8 42 LQFP48 F LPC1113FBD48/302 LPC1100L 24 kB 8 kB yes 1 1 2 8 42 LQFP48 F LPC1113FBD48/303 LPC1100XL 24 kB 8 kB yes 1 1 2 8 42 LQFP48 F LPC1113JBD48/303 LPC1100XL 24 kB 8 kB yes 1 1 2 8 42 LQFP48 J LPC1114 LPC1114FDH28/102 LPC1100L 32 kB 4 kB yes 1 1 1 6 22 TSSOP28 F LPC1114FN28/102 LPC1100L 32 kB 4 kB yes 1 1 1 6 22 DIP28 F LPC1114FHN33/201 LPC1100 32 kB 4 kB no 1 1 1 8 28 HVQFN33 F LPC1114FHN33/202 LPC1100L 32 kB 4 kB yes 1 1 1 8 28 HVQFN33 F LPC1114FHN33/203 LPC1100XL 32 kB 4 kB yes 1 1 2 8 28 HVQFN33 F LPC1114JHN33/203 LPC1100XL 32 kB 4 kB yes 1 1 2 8 28 HVQFN33 J LPC1114FHN33/301 LPC1100 32 kB 8 kB no 1 1 1 8 28 HVQFN33 F LPC1114FHN33/302 LPC1100L 32 kB 8 kB yes 1 1 1 8 28 HVQFN33 F LPC1114FHN33/303 LPC1100XL 32 kB 8 kB yes 1 1 2 8 28 HVQFN33 F LPC1114JHN33/303 LPC1100XL 32 kB 8 kB yes 1 1 2 8 28 HVQFN33 J LPC1114FHN33/333 LPC1100XL 56 kB 8 kB yes 1 1 2 8 28 HVQFN33 F LPC1114JHN33/333 LPC1100XL 56 kB 8 kB yes 1 1 2 8 28 HVQFN33 J LPC1114FHI33/302 LPC1100L 32 kB 8 kB yes 1 1 1 8 28 HVQFN33 F LPC1114FHI33/303 LPC1100XL 32 kB 8 kB yes 1 1 2 8 28 HVQFN33 F LPC1114JHI33/303 LPC1100XL 32 kB 8 kB yes 1 1 2 8 28 HVQFN33 J LPC1114FBD48/301 LPC1100 32 kB 8 kB no 1 1 2 8 42 LQFP48 F LPC1114FBD48/302 LPC1100L 32 kB 8 kB yes 1 1 2 8 42 LQFP48 F LPC1114FBD48/303 LPC1100XL 32 kB 8 kB yes 1 1 2 8 42 LQFP48 F LPC1114JBD48/303 LPC1100XL 32 kB 8 kB yes 1 1 2 8 42 LQFP48 J LPC1114FBD48/323 LPC1100XL 48 kB 8 kB yes 1 1 2 8 42 LQFP48 F LPC1114JBD48/323 LPC1100XL 48 kB 8 kB yes 1 1 2 8 42 LQFP48 J LPC1114FBD48/333 LPC1100XL 56 kB 8 kB yes 1 1 2 8 42 LQFP48 F LPC1114JBD48/333 LPC1100XL 56 kB 8 kB yes 1 1 2 8 42 LQFP48 J LPC1115 LPC1115FBD48/303 LPC1100XL 64 kB 8 kB yes 1 1 2 8 42 LQFP48 F LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 7 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 2. Ordering options …continued Type number Series Flash Total Power UART I2C/ SPI ADC GPIO Package Temp[1] SRAM profiles Fast+ channel LPC1115JBD48/303 LPC1100XL 64 kB 8 kB yes 1 1 2 8 42 LQFP48 J LPC1115FET48/303 LPC1100XL 64 kB 8 kB yes 1 1 2 8 42 TFBGA48 F LPC1115JET48/303 LPC1100XL 64 kB 8 kB yes 1 1 2 8 42 TFBGA48 J [1] F = 40C to +85C, J = 40C to +105C. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 8 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 5. Block diagram XTALIN SWD XTALOUT(3) RESET LPC1110/11/12/13/14 IRC CLOCK GENERATION, TEST/DEBUG POWER CONTROL, CLKOUT INTERFACE SYSTEM POR FUNCTIONS ARM clocks and CORTEX-M0 controls FLASH SRAM ROM system bus 4/8/16/24/32 kB 1/2/4/8 kB slave slave slave slave GPIO ports HIGH-SPEED AHB-LITE BUS PIO0/1/2/3 GPIO slave AHB TO APB BRIDGE RXD TXD UART 10-bit ADC AD[7:0](4) DTR, DSR, CTS(5), DCD, RI, RTS(5) SCK0, SSEL0 CT32B0_MAT[3:0](3) SPI0 MISO0, MOSI0 32-bit COUNTER/TIMER 0 CT32B0_CAP0(3) SCK1, SSEL1 CT32B1_MAT[3:0](3) SPI1(1) MISO1, MOSI1 32-bit COUNTER/TIMER 1 CT32B1_CAP0(3) CT16B0_MAT[2:0](3) I2C-BUS(2) SSDCAL 16-bit COUNTER/TIMER 0 CT16B0_CAP0(3) CT16B1_MAT[1:0](3) 16-bit COUNTER/TIMER 1 WDT CT16B1_CAP0(3) IOCONFIG SYSTEM CONTROL PMU 002aae696 (1) LQFP48 packages only. (2) Not on LPC1112FDH20/102. (3) All pins available on LQFP48 and HVQFN33 packages. CT16B1_MAT1 not available on TSSOP28/DIP28 packages. CT32B1_MAT3, CT16B1_CAP0, CT16B1_MAT[1:0], CT32B0_CAP0 not available on TSSOP20/SO20 packages. CT16B1_MAT[1:0], CT32B0_CAP0 not available on the HVQFN24 package. XTALOUT not available on LPC1112FHN24. (4) AD[7:0] available on LQFP48 and HVQFN33 packages. AD[5:0] available on TSSOP28/DIP28 packages. AD[4:0] available on TSSOP20/SO20 packages. (5) All pins available on LQFP48 packages. RXD, TXD, DTR, CTS, RTS available on HVQFN 33 packages. RXD, TXD, CTS, RTS available on TSSOP28/DIP28 packages. RXD, TXD, CTS available on HVQFN24 packages. RXD, TXD available on TSSOP20/SO20 packages. Fig 1. LPC1100/LPC1100L series block diagram LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 9 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller XTALIN SWD XTALOUT RESET LPC1111/12/13/14/15XL IRC CLOCK GENERATION, TEST/DEBUG POWER CONTROL, CLKOUT INTERFACE SYSTEM POR FUNCTIONS ARM clocks and CORTEX-M0 controls FLASH 8/16/24/32/ SRAM system bus 48/56/64 kB 2/4/8 kB ROM slave slave slave slave GPIO ports HIGH-SPEED AHB-LITE BUS PIO0/1/2/3 GPIO slave AHB TO APB BRIDGE RXD TXD UART 10-bit ADC AD[7:0] DTR, DSR(1), CTS, DCD(1), RI(1), RTS SCK0, SSEL0 SPI0 CT32B0_MAT[3:0] MISO0, MOSI0 32-bit COUNTER/TIMER 0 CT32B0_CAP[1:0] SCK1, SSEL1 SPI1 CT32B1_MAT[3:0] MISO1, MOSI1 32-bit COUNTER/TIMER 1 CT32B1_CAP[1:0] I2C-BUS SCL CT16B0_MAT[2:0] SDA 16-bit COUNTER/TIMER 0 CT16B0_CAP[1:0] CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 WWDT CT16B1_CAP[1:0] IOCONFIG SYSTEM CONTROL PMU 002aag780 (1) LQFP48 and TFBGA48 only. Fig 2. LPC1100XL series block diagram LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 10 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6. Pinning information 6.1 Pinning Table 3. Pin description overview Part Pin description table Pinning diagram LPC1110FD20 Table4 Figure8 LPC1111FDH20/002 Table4 Figure9 LPC1112FD20/102 Table4 Figure10 LPC1112FDH20/102 Table5 Figure9 LPC1112FHN24/202 Table6 Figure11 LPC1112FDH28/102 Table7 Figure12 LPC1114FDH28/102 Table7 Figure13 LPC1114FN28/102 Table7 Figure13 LPC1111FHN33/101 Table9 Figure6 LPC1111FHN33/102 Table9 Figure6 LPC1111JHN33/103 Table11 Figure7 LPC1111FHN33/103 Table11 Figure7 LPC1111FHN33/201 Table9 Figure6 LPC1111FHN33/202 Table9 Figure6 LPC1111FHN33/203 Table11 Figure7 LPC1111JHN33/203 Table11 Figure7 LPC1112FHN33/101 Table9 Figure6 LPC1112FHN33/102 Table9 Figure6 LPC1112FHN33/103 Table11 Figure7 LPC1112JHN33/103 Table11 Figure7 LPC1112FHN33/201 Table9 Figure6 LPC1112FHN33/202 Table9 Figure6 LPC1112FHN33/203 Table11 Figure7 LPC1112JHN33/203 Table11 Figure7 LPC1112FHI33/202 Table9 Figure6 LPC1112FHI33/203 Table11 Figure7 LPC1112JHI33/203 Table11 Figure7 LPC1113FHN33/201 Table9 Figure6 LPC1113FHN33/202 Table9 Figure6 LPC1113FHN33/203 Table11 Figure7 LPC1113JHN33/203 Table11 Figure7 LPC1113FHN33/301 Table9 Figure6 LPC1113FHN33/302 Table9 Figure6 LPC1113FHN33/303 Table11 Figure7 LPC1113JHN33/303 Table11 Figure7 LPC1114FHN33/201 Table9 Figure6 LPC1114FHN33/202 Table9 Figure6 LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 11 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 3. Pin description overview Part Pin description table Pinning diagram LPC1114FHN33/203 Table11 Figure7 LPC1114JHN33/203 Table11 Figure7 LPC1114FHN33/301 Table9 Figure6 LPC1114FHN33/302 Table9 Figure6 LPC1114JHN33/303 Table11 Figure7 LPC1114FHN33/303 Table11 Figure7 LPC1114FHN33/333 Table11 Figure7 LPC1114JHN33/333 Table11 Figure7 LPC1114FHI33/302 Table9 Figure6 LPC1114FHI33/303 Table11 Figure7 LPC1114JHI33/303 Table11 Figure7 LPC1113FBD48/301 Table8 Figure3 LPC1113FBD48/302 Table8 Figure3 LPC1113FBD48/303 Table10 Figure4 LPC1113JBD48/303 Table10 Figure4 LPC1114FBD48/301 Table8 Figure3 LPC1114FBD48/302 Table8 Figure3 LPC1114FBD48/303 Table10 Figure4 LPC1114JBD48/303 Table10 Figure4 LPC1114FBD48/323 Table10 Figure4 LPC1114JBD48/323 Table10 Figure4 LPC1114FBD48/333 Table10 Figure4 LPC1114JBD48/333 Table10 Figure4 LPC1115FBD48/303 Table10 Figure4 LPC1115JBD48/303 Table10 Figure4 LPC1115FET48/303 Table10 Figure5 LPC1115JET48/303 Table10 Figure5 LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 12 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller P U 2 E T K A A M W _ MAT1 MAT0 CAP0 MAT3/ T32B1 3/RI 7/TXD/CT32B0_ 6/RXD/CT32B0_ 5/RTS/CT32B0_ 2/DCD 11/AD7 4/AD5/CT32B1_ O/PIO1_3/AD4/C 3/RI/MOSI1 1/DSR PIO3_ PIO1_ PIO1_ PIO1_ VDD PIO3_ PIO1_ VSS PIO1_ SWDI PIO2_ PIO3_ 8 7 6 5 4 3 2 1 0 9 8 7 4 4 4 4 4 4 4 4 4 3 3 3 PIO2_6 1 36 PIO3_0/DTR PIO2_0/DTR/SSEL1 2 35 R/PIO1_2/AD3/CT32B1_MAT1 RESET/PIO0_0 3 34 R/PIO1_1/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2 4 33 R/PIO1_0/AD1/CT32B1_CAP0 VSS 5 LPC1113FBD48/301 32 R/PIO0_11/AD0/CT32B0_MAT3 XTALIN 6 LPC1113FBD48/302 31 PIO2_11/SCK0 XTALOUT 7 LPC1114FBD48/301 30 PIO1_10/AD6/CT16B1_MAT1 LPC1114FBD48/302 VDD 8 29 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO1_8/CT16B1_CAP0 9 28 PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0 10 27 PIO0_8/MISO0/CT16B0_MAT0 PIO2_7 11 26 PIO2_2/DCD/MISO1 PIO2_8 12 25 PIO2_10 3 4 5 6 7 8 9 0 1 2 3 4 1 1 1 1 1 1 1 2 2 2 2 2 002aae697 1 3 L A 0 4 4 5 5 0 S 9 K _ C D T _ _ _ _ K T _ 2_1/DSR/SC PIO0 PIO0_4/S PIO0_5/S CT16B1_MA PIO3 PIO2 PIO2 PIO3 PIO0_6/SC PIO0_7/C PIO2 O 9/ PI 1_ O PI Fig 3. LPC1100 and LPC1100L series pin configuration LQFP48 package LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 13 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller P U 2 1 E T K K A D C A M X S W _ R 3/RI/CT16B0_CAP0 7/TXD/CT32B0_MAT1 6/RXD/CT32B0_MAT0 5/RTS/CT32B0_CAP0 2/DCD/CT16B0_MAT2/ 11/AD7/CT32B1_CAP1 4/AD5/CT32B1_MAT3/ O/PIO1_3/AD4/CT32B1 3/RI/MOSI1 1/DSR/CT16B0_MAT1/ PIO3_ PIO1_ PIO1_ PIO1_ VDD PIO3_ PIO1_ VSS PIO1_ SWDI PIO2_ PIO3_ 8 7 6 5 4 3 2 1 0 9 8 7 4 4 4 4 4 4 4 4 4 3 3 3 PIO2_6/CT32B0_MAT1 1 36 PIO3_0/DTR/CT16B0_MAT0/TXD PIO2_0/DTR/SSEL1 2 35 R/PIO1_2/AD3/CT32B1_MAT1 RESET/PIO0_0 3 34 R/PIO1_1/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2 4 33 R/PIO1_0/AD1/CT32B1_CAP0 VSS 5 32 R/PIO0_11/AD0/CT32B0_MAT3 XTALIN 6 31 PIO2_11/SCK0/CT32B0_CAP1 LPC1113, LPC1114, LPC1115 XTALOUT 7 30 PIO1_10/AD6/CT16B1_MAT1/MISO1 VDD 8 29 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO1_8/CT16B1_CAP0 9 28 PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0 10 27 PIO0_8/MISO0/CT16B0_MAT0 PIO2_7/CT32B0_MAT2/RXD 11 26 PIO2_2/DCD/MISO1 PIO2_8/CT32B0_MAT3/TXD 12 25 PIO2_10 3 4 5 6 7 8 9 0 1 2 3 4 1 1 1 1 1 1 1 2 2 2 2 2 002aag781 1 3 L A 1 D 1 0 D 0 S 0 PIO2_1/DSR/SCK PIO0_ PIO0_4/SC PIO0_5/SD 9/CT16B1_MAT0/MOSI 3_4/CT16B0_CAP1/RX 4/CT16B1_MAT1/SSEL PIO2_5/CT32B0_MAT 3_5/CT16B1_CAP1/TX PIO0_6/SCK PIO0_7/CT PIO2_9/CT32B0_CAP _ O _ O O1 PI O2 PI PI PI Fig 4. LPC1100XL series pin configuration LQFP48 package LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 14 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller ball A1 LPC1115 index area 1 2 3 4 5 6 7 8 A B C D E F G H aaa-008364 Transparent top view Fig 5. LPC1100XL series pin configuration TFBGA48 package P U 2 E T K A A M W _ MAT1 MAT0 CAP0 MAT3/ T32B1 7/TXD/CT32B0_ 6/RXD/CT32B0_ 5/RTS/CT32B0_ 2 11/AD7 4/AD5/CT32B1_ O/PIO1_3/AD4/C itnedrmexin aarle 1a PIO1_ PIO1_ PIO1_ VDD PIO3_ PIO1_ PIO1_ SWDI 2 1 0 9 8 7 6 5 3 3 3 2 2 2 2 2 PIO2_0/DTR 1 24 R/PIO1_2/AD3/CT32B1_MAT1 RESET/PIO0_0 2 23 R/PIO1_1/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2 3 22 R/PIO1_0/AD1/CT32B1_CAP0 XTALIN 4 21 R/PIO0_11/AD0/CT32B0_MAT3 XTALOUT 5 20 PIO1_10/AD6/CT16B1_MAT1 VDD 6 19 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO1_8/CT16B1_CAP0 7 33 VSS 18 PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0 8 17 PIO0_8/MISO0/CT16B0_MAT0 9 10 11 12 13 14 15 16 3 L A 0 4 5 0 S PIO0_ O0_4/SC O0_5/SD B1_MAT PIO3_ PIO3_ 0_6/SCK O0_7/CT 002aae698 PI PI T16 PIO PI C 9/ _ 1 O PI Transparent top view Fig 6. LPC1100 and LPC1100L series pin configuration HVQFN33 7x7 and 5x5 packages LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 15 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller P U 2 E T K A A M 7/TXD/CT32B0_MAT1 6/RXD/CT32B0_MAT0 5/RTS/CT32B0_CAP0 2/CT16B0_MAT2/SCK1 11/AD7/CT32B1_CAP1 4/AD5/CT32B1_MAT3/W O/PIO1_3/AD4/CT32B1_ itnedrmexin aarle 1a PIO1_ PIO1_ PIO1_ VDD PIO3_ PIO1_ PIO1_ SWDI 2 1 0 9 8 7 6 5 3 3 3 2 2 2 2 2 PIO2_0/DTR/SSEL1 1 24 R/PIO1_2/AD3/CT32B1_MAT1 RESET/PIO0_0 2 23 R/PIO1_1/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2 3 22 R/PIO1_0/AD1/CT32B1_CAP0 XTALIN 4 21 R/PIO0_11/AD0/CT32B0_MAT3 XTALOUT 5 20 PIO1_10/AD6/CT16B1_MAT1/MISO1 VDD 6 19 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO1_8/CT16B1_CAP0 7 33 VSS 18 PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0 8 17 PIO0_8/MISO0/CT16B0_MAT0 9 10 11 12 13 14 15 16 3 L A 1 D D 0 S PIO0_ PIO0_4/SC PIO0_5/SD _MAT0/MOSI B0_CAP1/RX B1_CAP1/TX PIO0_6/SCK PIO0_7/CT 002aag782 B1 16 16 6 T T 1 C C 9/CT 3_4/ 3_5/ _ O O O1 PI PI PI Transparent top view Fig 7. LPC1100XL series pin configuration HVQFN33 PIO0_8/MISO0/CT16B0_MAT0 1 20 PIO0_4/SCL PIO0_9/MOSI0/CT16B0_MAT1 2 19 PIO0_2/SSEL0/CT16B0_CAP0 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 3 18 PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO0_11/AD0/CT32B0_MAT3 4 17 RESET/PIO0_0 LPC1110FD20 PIO0_5/SDA 5 LPC1112FD20/ 16 VSS PIO0_6/SCK0 6 102 15 VDD R/PIO1_0/AD1/CT32B1_CAP0 7 14 XTALIN R/PIO1_1/AD2/CT32B1_MAT0 8 13 XTALOUT R/PIO1_2/AD3/CT32B1_MAT1 9 12 PIO1_7/TXD/CT32B0_MAT1 SWDIO/PIO1_3/AD4/CT32B1_MAT2 10 11 PIO1_6/RXD/CT32B0_MAT0 002aag595 Fig 8. LPC1100L series pin configuration SO20 package LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 16 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller PIO0_8/MISO0/CT16B0_MAT0 1 20 PIO0_4/SCL PIO0_9/MOSI0/CT16B0_MAT1 2 19 PIO0_2/SSEL0/CT16B0_CAP0 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 3 18 PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO0_11/AD0/CT32B0_MAT3 4 17 RESET/PIO0_0 PIO0_5/SDA 5 16 VSS LPC1111FDH20/002 PIO0_6/SCK0 6 15 VDD R/PIO1_0/AD1/CT32B1_CAP0 7 14 XTALIN R/PIO1_1/AD2/CT32B1_MAT0 8 13 XTALOUT R/PIO1_2/AD3/CT32B1_MAT1 9 12 PIO1_7/TXD/CT32B0_MAT1 SWDIO/PIO1_3/AD4/CT32B1_MAT2 10 11 PIO1_6/RXD/CT32B0_MAT0 002aag596 Fig 9. LPC1100L series pin configuration TSSOP20 package with I2C-bus pins PIO0_8/MISO0/CT16B0_MAT0 1 20 PIO0_3 PIO0_9/MOSI0/CT16B0_MAT1 2 19 PIO0_2/SSEL0/CT16B0_CAP0 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 3 18 PIO0_1/CLKOUT/CT32B0_MAT2 R/PIO0_11/AD0/CT32B0_MAT3 4 17 RESET/PIO0_0 VDDA 5 16 VSS LPC1112FDH20/102 VSSA 6 15 VDD R/PIO1_0/AD1/CT32B1_CAP0 7 14 XTALIN R/PIO1_1/AD2/CT32B1_MAT0 8 13 XTALOUT R/PIO1_2/AD3/CT32B1_MAT1 9 12 PIO1_7/TXD/CT32B0_MAT1 SWDIO/PIO1_3/AD4/CT32B1_MAT2 10 11 PIO1_6/RXD/CT32B0_MAT0 002aag597 Fig 10. LPC1100L series pin configuration TSSOP20 package with V and V pins DDA SSA 7 6 4 3 _ _ _ _ terminal 1 PIO1 PIO1 VDD VSS PIO1 PIO1 index area 4 3 2 1 0 9 2 2 2 2 2 1 RESET/PIO0_0 1 18 PIO1_2 PIO0_1 2 17 PIO1_1 VSS 3 LPC1112FHN24 16 PIO1_0 XTALIN 4 15 PIO0_11 VDD 5 14 PIO0_10 PIO1_8 6 13 PIO0_9 7 8 9 10 11 12 2 4 5 6 7 8 _ _ _ _ _ _ 0 0 0 0 0 0 002aah173 O O O O O O PI PI PI PI PI PI Transparent top view Fig 11. LPC1100L series pin configuration HVQFN24 package LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 17 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller PIO0_8/MISO0/CT16B0_MAT0 1 28 PIO0_7/CTS PIO0_9/MOSI0/CT16B0_MAT1 2 27 PIO0_4/SCL SWCLK/PIO0_10/SCK0/CT16B0_MAT2 3 26 PIO0_3 R/PIO0_11/AD0/CT32B0_MAT3 4 25 PIO0_2/SSEL0/CT16B0_CAP0 PIO0_5/SDA 5 24 PIO0_1/CLKOUT/CT32B0_MAT2 PIO0_6/SCK0 6 23 RESET/PIO0_0 VDDA 7 LPC1112FDH28/102 22 VSS LPC1114FDH28/102 VSSA 8 21 VDD R/PIO1_0/AD1/CT32B1_CAP0 9 20 XTALIN R/PIO1_1/AD2/CT32B1_MAT0 10 19 XTALOUT R/PIO1_2/AD3/CT32B1_MAT1 11 18 PIO1_9/CT16B1_MAT0 SWDIO/PIO1_3/AD4/CT32B1_MAT2 12 17 PIO1_8/CT16B1_CAP0 PIO1_4/AD5/CT32B1_MAT3/WAKEUP 13 16 PIO1_7/TXD/CT32B0_MAT1 PIO1_5/RTS/CT32B0_CAP0 14 15 PIO1_6/RXD/CT32B0_MAT0 002aag598 Fig 12. LPC1100L pin configuration TSSOP28 package PIO0_8/MISO0/CT16B0_MAT0 1 28 PIO0_7/CTS PIO0_9/MOSI0/CT16B0_MAT1 2 27 PIO0_4/SCL SWCLK/PIO0_10/SCK0/CT16B0_MAT2 3 26 PIO0_3 R/PIO0_11/AD0/CT32B0_MAT3 4 25 PIO0_2/SSEL0/CT16B0_CAP0 PIO0_5/SDA 5 24 PIO0_1/CLKOUT/CT32B0_MAT2 PIO0_6/SCK0 6 23 RESET/PIO0_0 VDDA 7 22 VSS LPC1114FN28/ VSSA 8 102 21 VDD R/PIO1_0/AD1/CT32B1_CAP0 9 20 XTALIN R/PIO1_1/AD2/CT32B1_MAT0 10 19 XTALOUT R/PIO1_2/AD3/CT32B1_MAT1 11 18 PIO1_9/CT16B1_MAT0 SWDIO/PIO1_3/AD4/CT32B1_MAT2 12 17 PIO1_8/CT16B1_CAP0 PIO1_4/AD5/CT32B1_MAT3/WAKEUP 13 16 PIO1_7/TXD/CT32B0_MAT1 PIO1_5/RTS/CT32B0_CAP0 14 15 PIO1_6/RXD/CT32B0_MAT0 002aag599 Fig 13. LPC1100L series pin configuration DIP28 package LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 18 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6.2 Pin description Table 4. LPC1100L se ries: LPC1110/11/12 pin description table (SO20 and TSSOP20 package with I2C-bus pins) Symbol 0/0 Start Type Reset Description O2P2 logic state SO input [1] n SS PiT PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. RESET/PIO0_0 17 [2] yes I I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power-down mode is not used. I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter. PIO0_1/CLKOUT/ 18 [3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level on CT32B0_MAT2 this pin during reset starts the ISP command handler. O - CLKOUT — Clockout pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. PIO0_2/SSEL0/ 19 [3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin. CT16B0_CAP0 I/O - SSEL0 — Slave Select for SPI0. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. PIO0_4/SCL 20 [4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain). I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_5/SDA 5 [4] yes I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain). I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_6/SCK0 6 [3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. PIO0_8/MISO0/ 1 [3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin. CT16B0_MAT0 I/O - MISO0 — Master In Slave Out for SPI0. O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. PIO0_9/MOSI0/ 2 [3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin. CT16B0_MAT1 I/O - MOSI0 — Master Out Slave In for SPI0. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. SWCLK/PIO0_10/ 3 [3] yes I I; PU SWCLK — Serial wire clock. SCK0/ I/O - PIO0_10 — General purpose digital input/output pin. CT16B0_MAT2 I/O - SCK0 — Serial clock for SPI0. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 19 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 4. LPC1100L series: LPC1110/11/12 pin description table (SO20 and TSSOP20 package with I2C-bus pins) …continued Symbol 0/0 Start Type Reset Description O2P2 logic state SO input [1] Pin TSS R/PIO0_11/ 4 [5] yes I I; PU R — Reserved. Configure for an alternate function in the AD0/CT32B0_MAT3 IOCONFIG block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. PIO1_0 to PIO1_7 I/O Port 1 — Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. R/PIO1_0/ 7 [5] yes I I; PU R — Reserved. Configure for an alternate function in the AD1/CT32B1_CAP0 IOCONFIG block. I/O - PIO1_0 — General purpose digital input/output pin. I - AD1 — A/D converter, input 1. I - CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. R/PIO1_1/ 8 [5] no O I; PU R — Reserved. Configure for an alternate function in the AD2/CT32B1_MAT0 IOCONFIG block. I/O - PIO1_1 — General purpose digital input/output pin. I - AD2 — A/D converter, input 2. O - CT32B1_MAT0 — Match output 0 for 32-bit timer 1. R/PIO1_2/ 9 [5] no I I; PU R — Reserved. Configure for an alternate function in the AD3/CT32B1_MAT1 IOCONFIG block. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. SWDIO/PIO1_3/ 10 [5] no I/O I; PU SWDIO — Serial wire debug input/output. AD4/CT32B1_MAT2 I/O - PIO1_3 — General purpose digital input/output pin. I - AD4 — A/D converter, input 4. O - CT32B1_MAT2 — Match output 2 for 32-bit timer 1. PIO1_6/RXD/ 11 [3] no I/O I; PU PIO1_6 — General purpose digital input/output pin. CT32B0_MAT0 I - RXD — Receiver input for UART. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. PIO1_7/TXD/ 12 [3] no I/O I; PU PIO1_7 — General purpose digital input/output pin. CT32B0_MAT1 O - TXD — Transmitter output for UART. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. V 15 - - 3.3 V supply voltage to the internal regulator, the external rail, and DD the ADC. Also used as the ADC reference voltage. XTALIN 14 [6] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 13 [6] - O - Output from the oscillator amplifier. V 16 - - Ground. SS LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 20 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V level ); IA = inactive, DD no pull-up/down enabled. [2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure51). [4] I2C-bus pin compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure51). [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. Table 5. LPC1100L se ries: LPC1112 pin description table (TSSOP20 with V and V pins) DDA SSA Symbol 0 Start Type Reset Description 2 P logic state O S input [1] S T n Pi PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. RESET/PIO0_0 17 [2] yes I I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power-down mode is not used. I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter. PIO0_1/CLKOUT/ 18 [3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW CT32B0_MAT2 level on this pin during reset starts the ISP command handler. O - CLKOUT — Clockout pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. PIO0_2/SSEL0/ 19 [3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin. CT16B0_CAP0 I/O - SSEL0 — Slave Select for SPI0. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. PIO0_3 20 [3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin. PIO0_8/MISO0/ 1 [3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin. CT16B0_MAT0 I/O - MISO0 — Master In Slave Out for SPI0. O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. PIO0_9/MOSI0/ 2 [3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin. CT16B0_MAT1 I/O - MOSI0 — Master Out Slave In for SPI0. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 21 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 5. LPC1100L series: LPC1112 pin description table (TSSOP20 with VDDA and VSSA pins) …continued Symbol 0 Start Type Reset Description 2 P logic state O S input [1] S T n Pi SWCLK/PIO0_10/ 3 [3] yes I I; PU SWCLK — Serial wire clock. SCK0/ I/O - PIO0_10 — General purpose digital input/output pin. CT16B0_MAT2 I/O - SCK0 — Serial clock for SPI0. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. R/PIO0_11/ 4 [4] yes I I; PU R — Reserved. Configure for an alternate function in the AD0/CT32B0_MAT3 IOCONFIG block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. PIO1_0 to PIO1_7 I/O Port 1 — Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. R/PIO1_0/ 7 [4] yes I I; PU R — Reserved. Configure for an alternate function in the AD1/CT32B1_CAP0 IOCONFIG block. I/O - PIO1_0 — General purpose digital input/output pin. I - AD1 — A/D converter, input 1. I - CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. R/PIO1_1/ 8 [4] no O I; PU R — Reserved. Configure for an alternate function in the AD2/CT32B1_MAT0 IOCONFIG block. I/O - PIO1_1 — General purpose digital input/output pin. I - AD2 — A/D converter, input 2. O - CT32B1_MAT0 — Match output 0 for 32-bit timer 1. R/PIO1_2/ 9 [4] no I I; PU R — Reserved. Configure for an alternate function in the AD3/CT32B1_MAT1 IOCONFIG block. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. SWDIO/PIO1_3/ 10 [4] no I/O I; PU SWDIO — Serial wire debug input/output. AD4/CT32B1_MAT2 I/O - PIO1_3 — General purpose digital input/output pin. I - AD4 — A/D converter, input 4. O - CT32B1_MAT2 — Match output 2 for 32-bit timer 1. PIO1_6/RXD/ 11 [3] no I/O I; PU PIO1_6 — General purpose digital input/output pin. CT32B0_MAT0 I - RXD — Receiver input for UART. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. PIO1_7/TXD/ 12 [3] no I/O I; PU PIO1_7 — General purpose digital input/output pin. CT32B0_MAT1 O - TXD — Transmitter output for UART. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. V 15 - I - 3.3 V supply voltage to the internal regulator and the external DD rail. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 22 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 5. LPC1100L series: LPC1112 pin description table (TSSOP20 with VDDA and VSSA pins) …continued Symbol 0 Start Type Reset Description 2 P logic state O S input [1] S T n Pi V 5 - I - 3.3 V supply voltage to the ADC. Also used as the ADC DDA reference voltage. XTALIN 14 [5] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 13 [5] - O - Output from the oscillator amplifier. V 16 - I - Ground. SS V 6 - I - Analog ground. SSA [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V level ); IA = inactive, DD no pull-up/down enabled. [2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure51). [4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure51). [5] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. Table 6. LPC1100L se ries: LPC1112 (HVQFN24 package) Symbol HVQFN Start Type Reset Description pin logic state input [1] RESET/PIO0_0 1[2] yes I I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power-down mode is not used. I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter. PIO0_1/CLKOUT/ 2[3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW CT32B0_MAT2 level on this pin during reset starts the ISP command handler. O - CLKOUT — Clockout pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. PIO0_2/SSEL0/ 7[3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin. CT16B0_CAP0 I/O - SSEL0 — Slave Select for SPI0. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. PIO0_4/SCL 8[4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain). I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 23 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 6. LPC1100L series: LPC1112 (HVQFN24 package) …continued Symbol HVQFN Start Type Reset Description pin logic state input [1] PIO0_5/SDA 9[4] yes I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain). I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_6/SCK0 10[3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. PIO0_7/CTS 11[3] yes I/O I; PU PIO0_7 — General purpose digital input/output pin (high-current output driver). I - CTS — Clear To Send input for UART. PIO0_8/MISO0/ 12[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin. CT16B0_MAT0 I/O - MISO0 — Master In Slave Out for SPI0. O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. PIO0_9/MOSI0/ 13[3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin. CT16B0_MAT1 I/O - MOSI0 — Master Out Slave In for SPI0. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. SWCLK/PIO0_10/ 14[3] yes I I; PU SWCLK — Serial wire clock. SCK0/ I/O - PIO0_10 — General purpose digital input/output pin. CT16B0_MAT2 I/O - SCK0 — Serial clock for SPI0. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. R/PIO0_11/ 15[5] yes I I; PU R — Reserved. Configure for an alternate function in the AD0/CT32B0_MAT3 IOCONFIG block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. R/PIO1_0/ 16[5] yes I I; PU R — Reserved. Configure for an alternate function in the AD1/CT32B1_CAP0 IOCONFIG block. I/O - PIO1_0 — General purpose digital input/output pin. I - AD1 — A/D converter, input 1. I - CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. R/PIO1_1/ 17[5] no O I; PU R — Reserved. Configure for an alternate function in the AD2/CT32B1_MAT0 IOCONFIG block. I/O - PIO1_1 — General purpose digital input/output pin. I - AD2 — A/D converter, input 2. O - CT32B1_MAT0 — Match output 0 for 32-bit timer 1. R/PIO1_2/ 18[5] no I I; PU R — Reserved. Configure for an alternate function in the AD3/CT32B1_MAT1 IOCONFIG block. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 24 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 6. LPC1100L series: LPC1112 (HVQFN24 package) …continued Symbol HVQFN Start Type Reset Description pin logic state input [1] SWDIO/PIO1_3/ 19[5] no I/O I; PU SWDIO — Serial wire debug input/output. AD4/CT32B1_MAT2 I/O - PIO1_3 — General purpose digital input/output pin. I - AD4 — A/D converter, input 4. O - CT32B1_MAT2 — Match output 2 for 32-bit timer 1. PIO1_4/AD5/ 20[5] no I/O I; PU PIO1_4 — General purpose digital input/output pin with 10 ns CT32B1_MAT3/ glitch filter. In Deep power-down mode, this pin serves as the WAKEUP Deep power-down mode wake-up pin with 20 ns glitch filter. Pull this pin HIGH externally before entering Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. I - AD5 — A/D converter, input 5. O - CT32B1_MAT3 — Match output 3 for 32-bit timer 1. PIO1_6/RXD/ 23[3] no I/O I; PU PIO1_6 — General purpose digital input/output pin. CT32B0_MAT0 I - RXD — Receiver input for UART. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. PIO1_7/TXD/ 24[3] no I/O I; PU PIO1_7 — General purpose digital input/output pin. CT32B0_MAT1 O - TXD — Transmitter output for UART. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. PIO1_8/ 6[3] no I/O I; PU PIO1_8 — General purpose digital input/output pin. CT16B1_CAP0 I - CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. XTALIN 4[6] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. V 5; 22 - I - 1.8 V supply voltage to the internal regulator, the external rail, DD and the ADC. Also used as the ADC reference voltage. V 3; 21 - I - Ground. SS [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V level); IA = inactive, DD no pull-up/down enabled. [2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure52 for the reset pad configuration. [3] Pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure51). [4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] Pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled (see Figure51). [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 25 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 7. LPC1100L se ries: LPC1112/14 pin description table (TSSOP28 and DIP28 packages) Symbol 8/ Start Type Reset Description 2 logic state P O input [1] S S T28 n P PiDI PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. RESET/PIO0_0 23 [2] yes I I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power-down mode is not used. I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter. PIO0_1/CLKOUT/ 24 [3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW level CT32B0_MAT2 on this pin during reset starts the ISP command handler. O - CLKOUT — Clockout pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. PIO0_2/SSEL0/ 25 [3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin. CT16B0_CAP0 I/O - SSEL0 — Slave Select for SPI0. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. PIO0_3 26 [3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin. PIO0_4/SCL 27 [4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain). I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_5/SDA 5 [4] yes I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain). I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_6/SCK0 6 [3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. PIO0_7/CTS 28 [3] yes I/O I; PU PIO0_7 — General purpose digital input/output pin (high-current output driver). I - CTS — Clear To Send input for UART. PIO0_8/MISO0/ 1 [3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin. CT16B0_MAT0 I/O - MISO0 — Master In Slave Out for SPI0. O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. PIO0_9/MOSI0/ 2 [3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin. CT16B0_MAT1 I/O - MOSI0 — Master Out Slave In for SPI0. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 26 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 7. LPC1100L series: LPC1112/14 pin description table (TSSOP28 and DIP28 packages) …continued Symbol 8/ Start Type Reset Description 2 logic state P O input [1] S S8 T2 n P PiDI SWCLK/PIO0_10/ 3 [3] yes I I; PU SWCLK — Serial wire clock. SCK0/ I/O - PIO0_10 — General purpose digital input/output pin. CT16B0_MAT2 I/O - SCK0 — Serial clock for SPI0. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. R/PIO0_11/ 4 [5] yes I I; PU R — Reserved. Configure for an alternate function in the AD0/CT32B0_MAT3 IOCONFIG block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. PIO1_0 to PIO1_9 I/O Port 1 — Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. R/PIO1_0/ 9 [5] yes I I; PU R — Reserved. Configure for an alternate function in the AD1/CT32B1_CAP0 IOCONFIG block. I/O - PIO1_0 — General purpose digital input/output pin. I - AD1 — A/D converter, input 1. I - CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. R/PIO1_1/ 10 [5] no O I; PU R — Reserved. Configure for an alternate function in the AD2/CT32B1_MAT0 IOCONFIG block. I/O - PIO1_1 — General purpose digital input/output pin. I - AD2 — A/D converter, input 2. O - CT32B1_MAT0 — Match output 0 for 32-bit timer 1. R/PIO1_2/ 11 [5] no I I; PU R — Reserved. Configure for an alternate function in the AD3/CT32B1_MAT1 IOCONFIG block. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. SWDIO/PIO1_3/ 12 [5] no I/O I; PU SWDIO — Serial wire debug input/output. AD4/CT32B1_MAT2 I/O - PIO1_3 — General purpose digital input/output pin. I - AD4 — A/D converter, input 4. O - CT32B1_MAT2 — Match output 2 for 32-bit timer 1. PIO1_4/AD5/ 13 [5] no I/O I; PU PIO1_4 — General purpose digital input/output pin with 10 ns CT32B1_MAT3/ glitch filter. In Deep power-down mode, this pin serves as the Deep WAKEUP power-down mode wake-up pin with 20 ns glitch filter. Pull this pin HIGH externally before entering Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. I - AD5 — A/D converter, input 5. O - CT32B1_MAT3 — Match output 3 for 32-bit timer 1. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 27 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 7. LPC1100L series: LPC1112/14 pin description table (TSSOP28 and DIP28 packages) …continued Symbol 8/ Start Type Reset Description 2 logic state P O input [1] S S8 T2 n P PiDI PIO1_5/RTS/ 14 [3] no I/O I; PU PIO1_5 — General purpose digital input/output pin. CT32B0_CAP0 O - RTS — Request To Send output for UART. I - CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. PIO1_6/RXD/ 15 [3] no I/O I; PU PIO1_6 — General purpose digital input/output pin. CT32B0_MAT0 I - RXD — Receiver input for UART. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. PIO1_7/TXD/ 16 [3] no I/O I; PU PIO1_7 — General purpose digital input/output pin. CT32B0_MAT1 O - TXD — Transmitter output for UART. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. PIO1_8/ 17 [3] no I/O I; PU PIO1_8 — General purpose digital input/output pin. CT16B1_CAP0 I - CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. PIO1_9/ 18 [3] no I/O I; PU PIO1_9 — General purpose digital input/output pin. CT16B1_MAT0 O - CT16B1_MAT0 — Match output 0 for 16-bit timer 1. V 21 - - 3.3 V supply voltage to the internal regulator and the external rail. DD V 7 - - - 3.3 V supply voltage to the ADC. Also used as the ADC reference DDA voltage. XTALIN 20 [6] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 19 [6] - O - Output from the oscillator amplifier. V 22 - - Ground. SS V 8 - - - Analog ground. SSA [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V level ); IA = inactive, DD no pull-up/down enabled. [2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure52 for the reset pad configuration. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure51). [4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure51). [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 28 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 8. LPC1100 and LPC1100L series: LPC1113/14 pin description table (LQFP48 package) Symbol Pin Start Type Reset Description logic state input [1] PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. RESET/PIO0_0 3[2] yes I I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power-down mode is not used. I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter. PIO0_1/CLKOUT/ 4[3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW CT32B0_MAT2 level on this pin during reset starts the ISP command handler. O - CLKOUT — Clockout pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. PIO0_2/SSEL0/ 10[3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin. CT16B0_CAP0 I/O - SSEL0 — Slave Select for SPI0. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. PIO0_3 14[3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin. PIO0_4/SCL 15[4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain). I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_5/SDA 16[4] yes I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain). I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_6/SCK0 22[3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. PIO0_7/CTS 23[3] yes I/O I; PU PIO0_7 — General purpose digital input/output pin (high-current output driver). I - CTS — Clear To Send input for UART. PIO0_8/MISO0/ 27[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin. CT16B0_MAT0 I/O - MISO0 — Master In Slave Out for SPI0. O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. PIO0_9/MOSI0/ 28[3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin. CT16B0_MAT1 I/O - MOSI0 — Master Out Slave In for SPI0. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 29 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 8. LPC1100 and LPC1100L series: LPC1113/14 pin description table (LQFP48 package) …continued Symbol Pin Start Type Reset Description logic state input [1] SWCLK/PIO0_10/ 29[3] yes I I; PU SWCLK — Serial wire clock. SCK0/ I/O - PIO0_10 — General purpose digital input/output pin. CT16B0_MAT2 I/O - SCK0 — Serial clock for SPI0. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. R/PIO0_11/ 32[5] yes I I; PU R — Reserved. Configure for an alternate function in the AD0/CT32B0_MAT3 IOCONFIG block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. PIO1_0 to PIO1_11 I/O Port 1 — Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. R/PIO1_0/ 33[5] yes I I; PU R — Reserved. Configure for an alternate function in the AD1/CT32B1_CAP0 IOCONFIG block. I/O - PIO1_0 — General purpose digital input/output pin. I - AD1 — A/D converter, input 1. I - CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. R/PIO1_1/ 34[5] no O I; PU R — Reserved. Configure for an alternate function in the AD2/CT32B1_MAT0 IOCONFIG block. I/O - PIO1_1 — General purpose digital input/output pin. I - AD2 — A/D converter, input 2. O - CT32B1_MAT0 — Match output 0 for 32-bit timer 1. R/PIO1_2/ 35[5] no I I; PU R — Reserved. Configure for an alternate function in the AD3/CT32B1_MAT1 IOCONFIG block. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. SWDIO/PIO1_3/ 39[5] no I/O I; PU SWDIO — Serial wire debug input/output. AD4/CT32B1_MAT2 I/O - PIO1_3 — General purpose digital input/output pin. I - AD4 — A/D converter, input 4. O - CT32B1_MAT2 — Match output 2 for 32-bit timer 1. PIO1_4/AD5/ 40[5] no I/O I; PU PIO1_4 — General purpose digital input/output pin with 10 ns CT32B1_MAT3/ glitch filter. In Deep power-down mode, this pin serves as the WAKEUP Deep power-down mode wake-up pin with 20 ns glitch filter. Pull this pin HIGH externally before entering Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. I - AD5 — A/D converter, input 5. O - CT32B1_MAT3 — Match output 3 for 32-bit timer 1. PIO1_5/RTS/ 45[3] no I/O I; PU PIO1_5 — General purpose digital input/output pin. CT32B0_CAP0 O - RTS — Request To Send output for UART. I - CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 30 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 8. LPC1100 and LPC1100L series: LPC1113/14 pin description table (LQFP48 package) …continued Symbol Pin Start Type Reset Description logic state input [1] PIO1_6/RXD/ 46[3] no I/O I; PU PIO1_6 — General purpose digital input/output pin. CT32B0_MAT0 I - RXD — Receiver input for UART. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. PIO1_7/TXD/ 47[3] no I/O I; PU PIO1_7 — General purpose digital input/output pin. CT32B0_MAT1 O - TXD — Transmitter output for UART. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. PIO1_8/ 9[3] no I/O I; PU PIO1_8 — General purpose digital input/output pin. CT16B1_CAP0 I - CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. PIO1_9/ 17[3] no I/O I; PU PIO1_9 — General purpose digital input/output pin. CT16B1_MAT0 O - CT16B1_MAT0 — Match output 0 for 16-bit timer 1. PIO1_10/AD6/ 30[5] no I/O I; PU PIO1_10 — General purpose digital input/output pin. CT16B1_MAT1 I - AD6 — A/D converter, input 6. O - CT16B1_MAT1 — Match output 1 for 16-bit timer 1. PIO1_11/AD7 42[5] no I/O I; PU PIO1_11 — General purpose digital input/output pin. I - AD7 — A/D converter, input 7. PIO2_0 to PIO2_11 I/O Port 2 — Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. PIO2_0/DTR/SSEL1 2[3] no I/O I; PU PIO2_0 — General purpose digital input/output pin. O - DTR — Data Terminal Ready output for UART. I/O - SSEL1 — Slave Select for SPI1. PIO2_1/DSR/SCK1 13[3] no I/O I; PU PIO2_1 — General purpose digital input/output pin. I - DSR — Data Set Ready input for UART. I/O - SCK1 — Serial clock for SPI1. PIO2_2/DCD/MISO1 26[3] no I/O I; PU PIO2_2 — General purpose digital input/output pin. I - DCD — Data Carrier Detect input for UART. I/O - MISO1 — Master In Slave Out for SPI1. PIO2_3/RI/MOSI1 38[3] no I/O I; PU PIO2_3 — General purpose digital input/output pin. I - RI — Ring Indicator input for UART. I/O - MOSI1 — Master Out Slave In for SPI1. PIO2_4 19[3] no I/O I; PU PIO2_4 — General purpose digital input/output pin. PIO2_5 20[3] no I/O I; PU PIO2_5 — General purpose digital input/output pin. PIO2_6 1[3] no I/O I; PU PIO2_6 — General purpose digital input/output pin. PIO2_7 11[3] no I/O I; PU PIO2_7 — General purpose digital input/output pin. PIO2_8 12[3] no I/O I; PU PIO2_8 — General purpose digital input/output pin. PIO2_9 24[3] no I/O I; PU PIO2_9 — General purpose digital input/output pin. PIO2_10 25[3] no I/O I; PU PIO2_10 — General purpose digital input/output pin. PIO2_11/SCK0 31[3] no I/O I; PU PIO2_11 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 31 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 8. LPC1100 and LPC1100L series: LPC1113/14 pin description table (LQFP48 package) …continued Symbol Pin Start Type Reset Description logic state input [1] PIO3_0 to PIO3_5 I/O Port 3 — Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_6 to PIO3_11 are not available. PIO3_0/DTR 36[3] no I/O I; PU PIO3_0 — General purpose digital input/output pin. O - DTR — Data Terminal Ready output for UART. PIO3_1/DSR 37[3] no I/O I; PU PIO3_1 — General purpose digital input/output pin. I - DSR — Data Set Ready input for UART. PIO3_2/DCD 43[3] no I/O I; PU PIO3_2 — General purpose digital input/output pin. I - DCD — Data Carrier Detect input for UART. PIO3_3/RI 48[3] no I/O I; PU PIO3_3 — General purpose digital input/output pin. I - RI — Ring Indicator input for UART. PIO3_4 18[3] no I/O I; PU PIO3_4 — General purpose digital input/output pin. PIO3_5 21[3] no I/O I; PU PIO3_5 — General purpose digital input/output pin. V 8; 44 - I - 3.3 V supply voltage to the internal regulator, the external rail, DD and the ADC. Also used as the ADC reference voltage. XTALIN 6[6] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 7[6] - O - Output from the oscillator amplifier. V 5; 41 - I - Ground. SS [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to 2.6 V for LPC111x/101/201/301, pins pulled up to full V level on LPC111x/002/102/202/302 (V = 3.3 V)); IA = inactive, no pull-up/down DD DD enabled. [2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure52 for the reset pad configuration. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure51). [4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure51). [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 32 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 9. LPC1100 and LPC1100L series: LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin Start Type Reset Description logic state input [1] PIO0_0 to PIO0_11 Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. RESET/PIO0_0 2[2] yes I I;PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power-down mode is not used. I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter. PIO0_1/CLKOUT/ 3[3] yes I/O I;PU PIO0_1 — General purpose digital input/output pin. A LOW level on CT32B0_MAT2 this pin during reset starts the ISP command handler. O - CLKOUT — Clock out pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. PIO0_2/SSEL0/ 8[3] yes I/O I;PU PIO0_2 — General purpose digital input/output pin. CT16B0_CAP0 I/O - SSEL0 — Slave select for SPI0. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. PIO0_3 9[3] yes I/O I;PU PIO0_3 — General purpose digital input/output pin. PIO0_4/SCL 10[4] yes I/O I;IA PIO0_4 — General purpose digital input/output pin (open-drain). I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_5/SDA 11[4] yes I/O I;IA PIO0_5 — General purpose digital input/output pin (open-drain). I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_6/SCK0 15[3] yes I/O I;PU PIO0_6 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. PIO0_7/CTS 16[3] yes I/O I;PU PIO0_7 — General purpose digital input/output pin (high-current output driver). I - CTS — Clear To Send input for UART. PIO0_8/MISO0/ 17[3] yes I/O I;PU PIO0_8 — General purpose digital input/output pin. CT16B0_MAT0 I/O - MISO0 — Master In Slave Out for SPI0. O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. PIO0_9/MOSI0/ 18[3] yes I/O I;PU PIO0_9 — General purpose digital input/output pin. CT16B0_MAT1 I/O - MOSI0 — Master Out Slave In for SPI0. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. SWCLK/PIO0_10/ 19[3] yes I I;PU SWCLK — Serial wire clock. SCK0/ I/O - PIO0_10 — General purpose digital input/output pin. CT16B0_MAT2 I/O - SCK0 — Serial clock for SPI0. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 33 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 9. LPC1100 and LPC1100L series: LPC1111/12/13/14 pin description table (HVQFN33 package) …continued Symbol Pin Start Type Reset Description logic state input [1] R/PIO0_11/AD0/ 21[5] yes - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG CT32B0_MAT3 block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. PIO1_0 to PIO1_11 Port 1 — Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. R/PIO1_0/AD1/ 22[5] yes - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG CT32B1_CAP0 block. I/O - PIO1_0 — General purpose digital input/output pin. I - AD1 — A/D converter, input 1. I - CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. R/PIO1_1/AD2/ 23[5] no - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG CT32B1_MAT0 block. I/O - PIO1_1 — General purpose digital input/output pin. I - AD2 — A/D converter, input 2. O - CT32B1_MAT0 — Match output 0 for 32-bit timer 1. R/PIO1_2/AD3/ 24[5] no - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG CT32B1_MAT1 block. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. SWDIO/PIO1_3/ 25[5] no I/O I;PU SWDIO — Serial wire debug input/output. AD4/CT32B1_MAT2 I/O - PIO1_3 — General purpose digital input/output pin. I - AD4 — A/D converter, input 4. O - CT32B1_MAT2 — Match output 2 for 32-bit timer 1. PIO1_4/AD5/ 26[5] no I/O I;PU PIO1_4 — General purpose digital input/output pin with 10 ns glitch CT32B1_MAT3/ filter. In Deep power-down mode, this pin serves as the Deep WAKEUP power-down mode wake-up pin with 20 ns glitch filter. Pull this pin HIGH externally before entering Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. I - AD5 — A/D converter, input 5. O - CT32B1_MAT3 — Match output 3 for 32-bit timer 1. PIO1_5/RTS/ 30[3] no I/O I;PU PIO1_5 — General purpose digital input/output pin. CT32B0_CAP0 O - RTS — Request To Send output for UART. I - CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. PIO1_6/RXD/ 31[3] no I/O I;PU PIO1_6 — General purpose digital input/output pin. CT32B0_MAT0 I - RXD — Receiver input for UART. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 34 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 9. LPC1100 and LPC1100L series: LPC1111/12/13/14 pin description table (HVQFN33 package) …continued Symbol Pin Start Type Reset Description logic state input [1] PIO1_7/TXD/ 32[3] no I/O I;PU PIO1_7 — General purpose digital input/output pin. CT32B0_MAT1 O - TXD — Transmitter output for UART. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. PIO1_8/ 7[3] no I/O I;PU PIO1_8 — General purpose digital input/output pin. CT16B1_CAP0 I - CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. PIO1_9/ 12[3] no I/O I;PU PIO1_9 — General purpose digital input/output pin. CT16B1_MAT0 O - CT16B1_MAT0 — Match output 0 for 16-bit timer 1. PIO1_10/AD6/ 20[5] no I/O I;PU PIO1_10 — General purpose digital input/output pin. CT16B1_MAT1 I - AD6 — A/D converter, input 6. O - CT16B1_MAT1 — Match output 1 for 16-bit timer 1. PIO1_11/AD7 27[5] no I/O I;PU PIO1_11 — General purpose digital input/output pin. I - AD7 — A/D converter, input 7. PIO2_0 Port 2 — Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. Pins PIO2_1 to PIO2_11 are not available. PIO2_0/DTR 1[3] no I/O I;PU PIO2_0 — General purpose digital input/output pin. O - DTR — Data Terminal Ready output for UART. PIO3_0 to PIO3_5 Port 3 — Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_0, PIO3_1, PIO3_3 and PIO3_6 to PIO3_11 are not available. PIO3_2 28[3] no I/O I;PU PIO3_2 — General purpose digital input/output pin. PIO3_4 13[3] no I/O I;PU PIO3_4 — General purpose digital input/output pin. PIO3_5 14[3] no I/O I;PU PIO3_5 — General purpose digital input/output pin. V 6; 29 - I - 3.3 V supply voltage to the internal regulator, the external rail, and the DD ADC. Also used as the ADC reference voltage. XTALIN 4[6] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 5[6] - O - Output from the oscillator amplifier. V 33 - - - Thermal pad. Connect to ground. SS [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to 2.6 V for LPC111x/101/201/301, pins pulled up to full VDD level on LPC111x/002/102/202/302 (VDD = 3.3 V)); IA = inactive, no pull-up/down enabled. [2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure52 for the reset pad configuration. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure51). [4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant (see Figure51). LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 35 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. Table 10. LPC1100XL s eries: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package) Symbol 8 Start Type Reset Description 48 A4 logic state FP BG input [1] Q F L T PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. RESET/PIO0_0 3[2] C1[2] yes I I; PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power-down mode is not used. I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter. PIO0_1/CLKOUT/ 4[3] C2[3] yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A CT32B0_MAT2 LOW level on this pin during reset starts the ISP command handler. O - CLKOUT — Clockout pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. PIO0_2/SSEL0/ 10[3] F1[3] yes I/O I; PU PIO0_2 — General purpose digital input/output pin. CT16B0_CAP0 I/O - SSEL0 — Slave Select for SPI0. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. PIO0_3 14[3] H2[3] yes I/O I; PU PIO0_3 — General purpose digital input/output pin. PIO0_4/SCL 15[4] G3[4] yes I/O I; IA PIO0_4 — General purpose digital input/output pin (open-drain). I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_5/SDA 16[4] H3[4] yes I/O I; IA PIO0_5 — General purpose digital input/output pin (open-drain). I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_6/SCK0 22[3] H6[3] yes I/O I; PU PIO0_6 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. PIO0_7/CTS 23[3] G7[3] yes I/O I; PU PIO0_7 — General purpose digital input/output pin (high-current output driver). I - CTS — Clear To Send input for UART. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 36 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 10. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package) …continued Symbol 8 Start Type Reset Description 48 A4 logic state FP BG input [1] Q F L T PIO0_8/MISO0/ 27[3] F8[3] yes I/O I; PU PIO0_8 — General purpose digital input/output pin. CT16B0_MAT0 I/O - MISO0 — Master In Slave Out for SPI0. O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. PIO0_9/MOSI0/ 28[3] F7[3] yes I/O I; PU PIO0_9 — General purpose digital input/output pin. CT16B0_MAT1 I/O - MOSI0 — Master Out Slave In for SPI0. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. SWCLK/PIO0_10/ 29[3] E7[3] yes I I; PU SWCLK — Serial wire clock. SCK0/ I/O - PIO0_10 — General purpose digital input/output pin. CT16B0_MAT2 I/O - SCK0 — Serial clock for SPI0. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. R/PIO0_11/ 32[5] D8[5] yes I I; PU R — Reserved. Configure for an alternate function in AD0/CT32B0_MAT3 the IOCONFIG block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. PIO1_0 to PIO1_11 I/O Port 1 — Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. R/PIO1_0/ 33[5] C7[5] yes I I; PU R — Reserved. Configure for an alternate function in AD1/CT32B1_CAP0 the IOCONFIG block. I/O - PIO1_0 — General purpose digital input/output pin. I - AD1 — A/D converter, input 1. I - CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. R/PIO1_1/ 34[5] C8[5] no O I; PU R — Reserved. Configure for an alternate function in AD2/CT32B1_MAT0 the IOCONFIG block. I/O - PIO1_1 — General purpose digital input/output pin. I - AD2 — A/D converter, input 2. O - CT32B1_MAT0 — Match output 0 for 32-bit timer 1. R/PIO1_2/ 35[5] B7[5] no I I; PU R — Reserved. Configure for an alternate function in AD3/CT32B1_MAT1 the IOCONFIG block. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. SWDIO/PIO1_3/ 39[5] B6[5] no I/O I; PU SWDIO — Serial wire debug input/output. AD4/CT32B1_MAT2 I/O - PIO1_3 — General purpose digital input/output pin. I - AD4 — A/D converter, input 4. O - CT32B1_MAT2 — Match output 2 for 32-bit timer 1. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 37 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 10. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package) …continued Symbol 8 Start Type Reset Description 48 A4 logic state FP BG input [1] Q F L T PIO1_4/AD5/ 40[5] A6[5] no I/O I; PU PIO1_4 — General purpose digital input/output pin with CT32B1_MAT3/ 10 ns glitch filter. In Deep power-down mode, this pin WAKEUP serves as the Deep power-down mode wake-up pin with 20 ns glitch filter. Pull this pin HIGH externally before entering Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. I - AD5 — A/D converter, input 5. O - CT32B1_MAT3 — Match output 3 for 32-bit timer 1. PIO1_5/RTS/ 45[3] A3[3] no I/O I; PU PIO1_5 — General purpose digital input/output pin. CT32B0_CAP0 O - RTS — Request To Send output for UART. I - CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. PIO1_6/RXD/ 46[3] B3[3] no I/O I; PU PIO1_6 — General purpose digital input/output pin. CT32B0_MAT0 I - RXD — Receiver input for UART. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. PIO1_7/TXD/ 47[3] B2[3] no I/O I; PU PIO1_7 — General purpose digital input/output pin. CT32B0_MAT1 O - TXD — Transmitter output for UART. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. PIO1_8/ 9[3] F2[3] no I/O I; PU PIO1_8 — General purpose digital input/output pin. CT16B1_CAP0 I - CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. PIO1_9/ 17[3] G4[3] no I/O I; PU PIO1_9 — General purpose digital input/output pin. CT16B1_MAT0/ O - CT16B1_MAT0 — Match output 0 for 16-bit timer 1. MOSI1 I/O - MOSI1 — Master Out Slave In for SPI1. PIO1_10/AD6/ 30[5] E8[5] no I/O I; PU PIO1_10 — General purpose digital input/output pin. CT16B1_MAT1/ I - AD6 — A/D converter, input 6. MISO1 O - CT16B1_MAT1 — Match output 1 for 16-bit timer 1. I/O - MISO1 — Master In Slave Out for SPI1. PIO1_11/AD7/ 42[5] A5[5] no I/O I; PU PIO1_11 — General purpose digital input/output pin. CT32B1_CAP1 I - AD7 — A/D converter, input 7. I - CT32B1_CAP1 — Capture input 1 for 32-bit timer 1. PIO2_0 to PIO2_11 I/O Port 2 — Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. PIO2_0/DTR/SSEL1 2[3] B1[3] no I/O I; PU PIO2_0 — General purpose digital input/output pin. O - DTR — Data Terminal Ready output for UART. I/O - SSEL1 — Slave Select for SPI1. PIO2_1/DSR/SCK1 13[3] H1[3] no I/O I; PU PIO2_1 — General purpose digital input/output pin. I - DSR — Data Set Ready input for UART. I/O - SCK1 — Serial clock for SPI1. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 38 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 10. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package) …continued Symbol 8 Start Type Reset Description 48 A4 logic state FP BG input [1] Q F L T PIO2_2/DCD/MISO1 26[3] G8[3] no I/O I; PU PIO2_2 — General purpose digital input/output pin. I - DCD — Data Carrier Detect input for UART. I/O - MISO1 — Master In Slave Out for SPI1. PIO2_3/RI/MOSI1 38[3] A7[3] no I/O I; PU PIO2_3 — General purpose digital input/output pin. I - RI — Ring Indicator input for UART. I/O - MOSI1 — Master Out Slave In for SPI1. PIO2_4/ 19[3] G5[3] no I/O I; PU PIO2_4 — General purpose digital input/output pin. CT16B1_MAT1/ O - CT16B1_MAT1 — Match output 1 for 16-bit timer 1. SSEL1 O - SSEL1 — Slave Select for SPI1. PIO2_5/ 20[3] H5[3] no I/O I; PU PIO2_5 — General purpose digital input/output pin. CT32B0_MAT0 O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. PIO2_6/ 1[3] A1[3] no I/O I; PU PIO2_6 — General purpose digital input/output pin. CT32B0_MAT1 O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. PIO2_7/ 11[3] G2[3] no I/O I; PU PIO2_7 — General purpose digital input/output pin. CT32B0_MAT2/RXD O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. I - RXD — Receiver input for UART. PIO2_8/ 12[3] G1[3] no I/O I; PU PIO2_8 — General purpose digital input/output pin. CT32B0_MAT3/TXD O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. O - TXD — Transmitter output for UART. PIO2_9/ 24[3] H7[3] no I/O I; PU PIO2_9 — General purpose digital input/output pin. CT32B0_CAP0 I - CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. PIO2_10 25[3] H8[3] no I/O I; PU PIO2_10 — General purpose digital input/output pin. PIO2_11/SCK0/ 31[3] D7[3] no I/O I; PU PIO2_11 — General purpose digital input/output pin. CT32B0_CAP1 I/O - SCK0 — Serial clock for SPI0. I - CT32B0_CAP1 — Capture input for 32-bit timer 0. PIO3_0 to PIO3_5 I/O Port 3 — Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_6 to PIO3_11 are not available. PIO3_0/DTR/ 36[3] B8[3] no I/O I; PU PIO3_0 — General purpose digital input/output pin. CT16B0_MAT0/TXD O - DTR — Data Terminal Ready output for UART. O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. O - TXD — Transmitter Output for UART. PIO3_1/DSR/ 37[3] A8[3] no I/O I; PU PIO3_1 — General purpose digital input/output pin. CT16B0_MAT1/RXD I - DSR — Data Set Ready input for UART. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. I - RXD — Receiver input for UART. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 39 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 10. LPC1100XL series: LPC1113/14/15 pin description table (LQFP48 and TFBGA48 package) …continued Symbol 8 Start Type Reset Description 48 A4 logic state FP BG input [1] Q F L T PIO3_2/DCD/ 43[3] A4[3] no I/O I; PU PIO3_2 — General purpose digital input/output pin. CT16B0_MAT2/ I - DCD — Data Carrier Detect input for UART. SCK1 O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. I/O - SCK1 — Serial clock for SPI1. PIO3_3/RI/ 48[3] A2[3] no I/O I; PU PIO3_3 — General purpose digital input/output pin. CT16B0_CAP0 I - RI — Ring Indicator input for UART. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. PIO3_4/ 18[3] H4[3] no I/O I; PU PIO3_4 — General purpose digital input/output pin. CT16B0_CAP1/RXD I - CT16B0_CAP1 — Capture input 1 for 16-bit timer 0. I - RXD — Receiver input for UART PIO3_5/ 21[3] G6[3] no I/O I; PU PIO3_5 — General purpose digital input/output pin. CT16B1_CAP1/TXD I - CT16B1_CAP1 — Capture input 1 for 16-bit timer 1. O - TXD — Transmitter output for UART V 8; 44 E2; - I - 3.3 V supply voltage to the internal regulator, the DD B4 external rail, and the ADC. Also used as the ADC reference voltage. XTALIN 6[6] D1[6] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 7[6] E1[6] - O - Output from the oscillator amplifier. V 5; 41 D2; - I - Ground. SS B5 [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V level (V = 3.3 V)); DD DD IA = inactive, no pull-up/down enabled. [2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure52 for the reset pad configuration. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure51). [4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure51). [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 40 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 11. LPC1100XL s eries: LPC1111/12/13/14 pin description table (HVQFN33 package) Symbol Pin Start Type Reset Description logic state input [1] PIO0_0 to PIO0_11 Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block. RESET/PIO0_0 2[2] yes I I;PU RESET — External reset input with 20 ns glitch filter. A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states and processor execution to begin at address 0. In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power-down mode is not used. I/O - PIO0_0 — General purpose digital input/output pin with 10 ns glitch filter. PIO0_1/CLKOUT/ 3[3] yes I/O I;PU PIO0_1 — General purpose digital input/output pin. A LOW level on CT32B0_MAT2 this pin during reset starts the ISP command handler. O - CLKOUT — Clock out pin. O - CT32B0_MAT2 — Match output 2 for 32-bit timer 0. PIO0_2/SSEL0/ 8[3] yes I/O I;PU PIO0_2 — General purpose digital input/output pin. CT16B0_CAP0 I/O - SSEL0 — Slave select for SPI0. I - CT16B0_CAP0 — Capture input 0 for 16-bit timer 0. PIO0_3 9[3] yes I/O I;PU PIO0_3 — General purpose digital input/output pin. PIO0_4/SCL 10[4] yes I/O I;IA PIO0_4 — General purpose digital input/output pin (open-drain). I/O - SCL — I2C-bus, open-drain clock input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_5/SDA 11[4] yes I/O I;IA PIO0_5 — General purpose digital input/output pin (open-drain). I/O - SDA — I2C-bus, open-drain data input/output. High-current sink only if I2C Fast-mode Plus is selected in the I/O configuration register. PIO0_6/SCK0 15[3] yes I/O I;PU PIO0_6 — General purpose digital input/output pin. I/O - SCK0 — Serial clock for SPI0. PIO0_7/CTS 16[3] yes I/O I;PU PIO0_7 — General purpose digital input/output pin (high-current output driver). I - CTS — Clear To Send input for UART. PIO0_8/MISO0/ 17[3] yes I/O I;PU PIO0_8 — General purpose digital input/output pin. CT16B0_MAT0 I/O - MISO0 — Master In Slave Out for SPI0. O - CT16B0_MAT0 — Match output 0 for 16-bit timer 0. PIO0_9/MOSI0/ 18[3] yes I/O I;PU PIO0_9 — General purpose digital input/output pin. CT16B0_MAT1 I/O - MOSI0 — Master Out Slave In for SPI0. O - CT16B0_MAT1 — Match output 1 for 16-bit timer 0. SWCLK/PIO0_10/ 19[3] yes I I;PU SWCLK — Serial wire clock. SCK0/ I/O - PIO0_10 — General purpose digital input/output pin. CT16B0_MAT2 I/O - SCK0 — Serial clock for SPI0. O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 41 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 11. LPC1100XL series: LPC1111/12/13/14 pin description table (HVQFN33 package) …continued Symbol Pin Start Type Reset Description logic state input [1] R/PIO0_11/AD0/ 21[5] yes - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG CT32B0_MAT3 block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0. PIO1_0 to PIO1_11 Port 1 — Port 1 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. R/PIO1_0/AD1/ 22[5] yes - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG CT32B1_CAP0 block. I/O - PIO1_0 — General purpose digital input/output pin. I - AD1 — A/D converter, input 1. I - CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. R/PIO1_1/AD2/ 23[5] no - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG CT32B1_MAT0 block. I/O - PIO1_1 — General purpose digital input/output pin. I - AD2 — A/D converter, input 2. O - CT32B1_MAT0 — Match output 0 for 32-bit timer 1. R/PIO1_2/AD3/ 24[5] no - I;PU R — Reserved. Configure for an alternate function in the IOCONFIG CT32B1_MAT1 block. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. SWDIO/PIO1_3/ 25[5] no I/O I;PU SWDIO — Serial wire debug input/output. AD4/CT32B1_MAT2 I/O - PIO1_3 — General purpose digital input/output pin. I - AD4 — A/D converter, input 4. O - CT32B1_MAT2 — Match output 2 for 32-bit timer 1. PIO1_4/AD5/ 26[5] no I/O I;PU PIO1_4 — General purpose digital input/output pin with 10 ns glitch CT32B1_MAT3/ filter. In Deep power-down mode, this pin serves as the Deep WAKEUP power-down mode wake-up pin with 20 ns glitch filter. Pull this pin HIGH externally before entering Deep power-down mode. Pull this pin LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. I - AD5 — A/D converter, input 5. O - CT32B1_MAT3 — Match output 3 for 32-bit timer 1. PIO1_5/RTS/ 30[3] no I/O I;PU PIO1_5 — General purpose digital input/output pin. CT32B0_CAP0 O - RTS — Request To Send output for UART. I - CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. PIO1_6/RXD/ 31[3] no I/O I;PU PIO1_6 — General purpose digital input/output pin. CT32B0_MAT0 I - RXD — Receiver input for UART. O - CT32B0_MAT0 — Match output 0 for 32-bit timer 0. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 42 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 11. LPC1100XL series: LPC1111/12/13/14 pin description table (HVQFN33 package) …continued Symbol Pin Start Type Reset Description logic state input [1] PIO1_7/TXD/ 32[3] no I/O I;PU PIO1_7 — General purpose digital input/output pin. CT32B0_MAT1 O - TXD — Transmitter output for UART. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0. PIO1_8/ 7[3] no I/O I;PU PIO1_8 — General purpose digital input/output pin. CT16B1_CAP0 I - CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. PIO1_9/ 12[3] no I/O I;PU PIO1_9 — General purpose digital input/output pin. CT16B1_MAT0/ O - CT16B1_MAT0 — Match output 0 for 16-bit timer 1. MOSI1 I/O - MOSI1 — Master Out Slave In for SPI1 PIO1_10/AD6/ 20[5] no I/O I;PU PIO1_10 — General purpose digital input/output pin. CT16B1_MAT1/ I - AD6 — A/D converter, input 6. MISO1 O - CT16B1_MAT1 — Match output 1 for 16-bit timer 1. I/O - MISO1 — Master In Slave Out for SPI1 PIO1_11/AD7/ 27[5] no I/O I;PU PIO1_11 — General purpose digital input/output pin. CT32B1_CAP1 I - AD7 — A/D converter, input 7. I - CT32B1_CAP1 — Capture input 1 for 32-bit timer 1. PIO2_0 Port 2 — Port 2 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. Pins PIO2_1 to PIO2_11 are not available. PIO2_0/DTR/SSEL1 1[3] no I/O I;PU PIO2_0 — General purpose digital input/output pin. O - DTR — Data Terminal Ready output for UART. I/O - SSEL1 — Slave Select for SPI1. PIO3_0 to PIO3_5 Port 3 — Port 3 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 3 pins depends on the function selected through the IOCONFIG register block. Pins PIO3_0, PIO3_1, PIO3_3 and PIO3_6 to PIO3_11 are not available. PIO3_2/ 28[3] no I/O I;PU PIO3_2 — General purpose digital input/output pin. CT16B0_MAT2/ O - CT16B0_MAT2 — Match output 2 for 16-bit timer 0. SCK1 I/O - SCK1 — Serial clock for SPI1. PIO3_4/ 13[3] no I/O I;PU PIO3_4 — General purpose digital input/output pin. CT16B0_CAP1/RXD I - CT16B0_CAP1 — Capture input 1 for 16-bit timer 0. I - RXD — Receiver input for UART. PIO3_5/ 14[3] no I/O I;PU PIO3_5 — General purpose digital input/output pin. CT16B1_CAP1/TXD I - CT16B1_CAP1 — Capture input 1 for 16-bit timer 1. O - TXD — Transmitter output for UART. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 43 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 11. LPC1100XL series: LPC1111/12/13/14 pin description table (HVQFN33 package) …continued Symbol Pin Start Type Reset Description logic state input [1] V 6; 29 - I - 3.3 V supply voltage to the internal regulator, the external rail, and the DD ADC. Also used as the ADC reference voltage. XTALIN 4[6] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. XTALOUT 5[6] - O - Output from the oscillator amplifier. V 33 - - - Thermal pad. Connect to ground. SS [1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V level (V = 3.3 V)); DD DD IA = inactive, no pull-up/down enabled. [2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure52 for the reset pad configuration. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure51). [4] I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant (see Figure51). [6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 44 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7. Functional description 7.1 ARM Cortex-M0 processor The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.2 On-chip flash program memory The LPC1110/11/12/13/14/15 contain 64kB (LPC1115), 56kB (LPC1114/333), 48kB (LPC1114/323), 32 kB (LPC1114), 24 kB (LPC1113), 16 kB (LPC1112), 8kB (LPC1111) or 4kB (LPC1110) of on-chip flash memory. 7.3 On-chip SRAM The LPC1110/11/12/13/14/15 contain a total of 8 kB, 4 kB, 2 kB, or 1 kB on-chip static RAM memory. 7.4 Memory map The LPC1110/11/12/13/14/15 incorporate several distinct memory regions, shown in the following figures. Figure14 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either type is allocated 16kB of space. This allows simplifying the address decoding for each peripheral. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 45 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LPC1110/11/12/13/14 AHB peripherals 0x5020 0000 4 GB 0xFFFF FFFF reserved 0xE010 0000 127-16 reserved private peripheral bus 0xE000 0000 0x5004 0000 reserved 12-15 GPIO PIO3 0x5003 0000 0x5020 0000 8-11 GPIO PIO2 0x5002 0000 AHB peripherals 0x5000 0000 4-7 GPIO PIO1 0x5001 0000 0-3 GPIO PIO0 0x5000 0000 reserved APB peripherals 0x4008 0000 31-23 reserved 0x4008 0000 0x4005 C000 APB peripherals 22 SPI1(1) 0x4005 8000 1 GB 0x4000 0000 21-19 reserved 0x4004 C000 18 system control 0x4004 8000 reserved 17 IOCONFIG 0x4004 4000 16 SPI0 0x4004 0000 15 flash controller 0x4003 C000 0.5 GB 0x2000 0000 14 PMU 0x4003 8000 reserved 13-10 reserved 0x1FFF 4000 0x4002 8000 16 kB boot ROM 0x1FFF 0000 9 reserved 0x4002 4000 reserved 8 reserved 0x4002 0000 0x1000 2000 8 kB SRAM (LPC1113/14/301/302) 7 ADC 0x4001 C000 0x1000 1000 4 kB SRAM (LPC1111/12/13/14/201/102/202) 0x1000 0800 6 32-bit counter/timer 1 0x4001 8000 2 kB SRAM (LPC1111/12/101/002/102) 5 32-bit counter/timer 0 0x4001 4000 0x1000 0400 1 kB SRAM (LPC1110) 4 16-bit counter/timer 1 0x4001 0000 0x1000 0000 3 16-bit counter/timer 0 0x4000 C000 reserved 2 UART 0x4000 8000 0x0000 8000 32 kB on-chip flash (LPC1114) 1 WDT 0x4000 4000 0x0000 6000 0 I2C-bus(2) 0x4000 0000 24 kB on-chip flash (LPC1113) 0x0000 4000 16 kB on-chip flash (LPC1112) 0x0000 2000 8 kB on-chip flash (LPC1111) 0x0000 00C0 0x0000 1000 active interrupt vectors 4 kB on-chip flash (LPC1110) 0x0000 0000 0 GB 0x0000 0000 002aae699 (1) LQFP48 package only. (1) Not on part LPC1112FDH20/102. Fig 14. LPC1100 and LPC1100L series memory map LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 46 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LPC1111/12/13/14/15XL AHB peripherals 0x5020 0000 4 GB 0xFFFF FFFF reserved 0xE010 0000 127-16 reserved private peripheral bus 0xE000 0000 0x5004 0000 reserved 12-15 GPIO PIO3 0x5003 0000 0x5020 0000 8-11 GPIO PIO2 0x5002 0000 AHB peripherals 0x5000 0000 4-7 GPIO PIO1 0x5001 0000 0-3 GPIO PIO0 0x5000 0000 reserved APB peripherals 0x4008 0000 31-23 reserved 0x4008 0000 0x4005 C000 APB peripherals 22 SPI1 0x4005 8000 1 GB 0x4000 0000 21-19 reserved 0x4004 C000 reserved 18 system control 0x4004 8000 17 IOCONFIG 0x4004 4000 0.5 GB 0x2000 0000 16 SPI0 0x4004 0000 15 flash controller 0x4003 C000 reserved 14 PMU 0x4003 8000 0x1FFF 4000 16 kB boot ROM 13-10 reserved 0x1FFF 0000 0x4002 8000 reserved 0x1000 2000 9 reserved 0x4002 4000 8 kB SRAM (LPC1113/14/15/303/323/333) 0x1000 1000 8 reserved 0x4002 0000 4 kB SRAM (LPC1111/12/13/14/203) 7 ADC 0x4001 C000 0x1000 0800 6 32-bit counter/timer 1 0x4001 8000 2 kB SRAM (LPC1111/12/103) 0x1000 0000 5 32-bit counter/timer 0 0x4001 4000 reserved 4 16-bit counter/timer 1 0x4001 0000 0x0001 0000 3 16-bit counter/timer 0 0x4000 C000 64 kB on-chip flash (LPC1115) 2 UART 0x4000 8000 0x0000 E000 56 kB on-chip flash (LPC1114/333) 1 WWDT 0x4000 4000 0x0000 C000 48 kB on-chip flash (LPC1114/323) 0 I2C-bus 0x4000 0000 0x0000 8000 32 kB on-chip flash (LPC1114) 0x0000 6000 24 kB on-chip flash (LPC1113) 0x0000 4000 16 kB on-chip flash (LPC1112) 0x0000 2000 0x0000 00C0 active interrupt vectors 002aag788 8 kB on-chip flash (LPC1111) 0x0000 0000 0 GB 0x0000 0000 Fig 15. LPC1100XL series memory map 7.5 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.5.1 Features • Controls system exceptions and peripheral interrupts. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 47 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • In the LPC1110/11/12/13/14/15, the NVIC supports 32 vectored interrupts including up to 13 inputs to the start logic from individual GPIO pins. • Four programmable interrupt priority levels with hardware priority level masking. • Software interrupt generation. 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any GPIO pin (total of up to 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a level, or rising edge or falling edge, or both. 7.6 IOCONFIG block The IOCONFIG block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.7 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC1110/11/12/13/14/15 use accelerated GPIO functions: • GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing can be achieved. • Entire port value can be written in one instruction. Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. 7.7.1 Features • Bit level port registers allow a single instruction to set or clear any number of bits in one write operation. • Direction control of individual bits. • All I/O default to inputs with pull-ups enabled after reset with the exception of the I2C-bus pins PIO0_4 and PIO0_5. • Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG block for each GPIO pin (except for pins PIO0_4 and PIO0_5). • On the LPC1100, all GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 2.6 V (V = 3.3 V) if their pull-up resistor is enabled in the IOCONFIG block. DD LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 48 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • On the LPC1100L and LPC1100XL series, all GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (V = 3.3 V) if their pull-up resistor is enabled in the DD IOCONFIG block. • Programmable open-drain mode for series LPC1100L and LPC1100XL. 7.8 UART The LPC1110/11/12/13/14/15 contain one UART. Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. The UART includes a fractional baud rate generator. Standard baud rates such as 115200Bd can be achieved with any crystal frequency above 2MHz. 7.8.1 Features • Maximum UART data bit rate of 3.125 MBit/s. • 16Byte Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points at 1B, 4B, 8B, and 14B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • FIFO control mechanism that enables software flow control implementation. • Support for RS-485/9-bit mode. • Support for modem control. 7.9 SPI serial I/O controller The LPC1100 and LPC1100L series contain two SPI controllers on the LQFP48 package and one SPI controller on the HVQFN33/TSSOP28/DIP28/TSSOP20/SO20 packages (SPI0). The LPC1100XL series contain two SPI controllers. Both SPI controllers support SSP features. The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SPI supports full duplex transfers, with frames of 4bits to 16bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.9.1 Features • Maximum SPI speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode) • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses • Synchronous serial communication LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 49 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Master or slave operation • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame 7.10 I2C-bus serial I/O controller The LPC1110/11/12/13/14/15 contain one I2C-bus controller. Remark: Part LPC1112FDH20/102 does not contain the I2C-bus controller. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 7.10.1 Features • The I2C-interface is a standard I2C-bus compliant interface with open-drain pins. The I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • The I2C-bus controller supports multiple address recognition and a bus monitor mode. 7.11 10-bit ADC The LPC1110/11/12/13/14/15 contain one ADC. It is a single 10-bit successive approximation ADC with eight channels. 7.11.1 Features • 10-bit successive approximation ADC. • Input multiplexing among 8 pins. • Power-down mode. • Measurement range 0 V to V . DD • 10-bit conversion time  2.44s (up to 400 kSamples/s). • Burst conversion mode for single or multiple inputs. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 50 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Optional conversion on transition of input pin or timer match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. 7.12 General purpose external event counter/timers The LPC1110/11/12/13/14/15 include two 32-bit counter/timers and two 16-bit counter/timers. The counter/timer is designed to count cycles of the system derived clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. Each counter/timer also includes up to two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.12.1 Features • A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. • Counter or timer operation. • Up to two capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • The timer and prescaler may be configured to be cleared on a designated capture event. This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge. • Four match registers per timer that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. 7.13 System tick timer The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval (typically 10 ms). 7.14 Watchdog timer (LPC1100 series, LPC111x/101/201/301) Remark: The watchdog timer without windowed features is available on parts LPC111x/101/201/301. The purpose of the watchdog is to reset the microcontroller within a selectable time period. 7.14.1 Features • Internally resets chip if not periodically reloaded. • Debug mode. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 51 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 24-bit timer with internal prescaler. • Selectable time period from (T 2564) to (T 2244) in cy(WDCLK) cy(WDCLK) multiples of T 4. cy(WDCLK) • The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator (IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. 7.15 Windowed WatchDog Timer (LPC1100L and LPC1100XL series) Remark: The windowed watchdog timer is available on the LPC1100L and LPC1100XL series only. The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window. 7.15.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect feed sequence causes reset or interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 24-bit timer with internal prescaler. • Selectable time period from (T 2564) to (T 2244) in cy(WDCLK) cy(WDCLK) multiples of T 4. cy(WDCLK) • The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated watchdog oscillator (WDO). This gives a wide range of potential timing choices of watchdog operation under different power conditions. 7.16 Clocking and power control 7.16.1 Crystal oscillators The LPC1110/11/12/13/14/15 include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 52 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Following reset, the LPC1110/11/12/13/14/15 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. See Figure16 for an overview of the LPC1110/11/12/13/14/15 clock generation. AHB clock 0 (system) SYSTEM CLOCK system clock DIVIDER 18 AHB clocks 1 to 18 (memories and peripherals) SYSAHBCLKCTRL[1:18] (AHB clock enable) SPI0 PERIPHERAL SPI0 CLOCK DIVIDER IRC oscillator main clock UART PERIPHERAL UART watchdog oscillator CLOCK DIVIDER SPI1 PERIPHERAL SPI1 MAINCLKSEL CLOCK DIVIDER (main clock select) IRC oscillator SYSTEM PLL system oscillator IRC oscillator WDT CLOCK WDT SYSPLLCLKSEL DIVIDER (system PLL clock select) watchdog oscillator WDTUEN (WDT clock update enable) IRC oscillator system oscillator CLKOUT PIN CLOCK CLKOUT pin watchdog oscillator DIVIDER CLKOUTUEN (CLKOUT update enable) 002aae514 Fig 16. LPC1110/11/12/13/14/15 clock generation block diagram 7.16.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12MHz. The IRC is trimmed to 1% accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC1110/11/12/13/14/15 use the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.16.1.2 System oscillator The system oscillator can be used as the clock source for the CPU, with or without using the PLL. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 53 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller The system oscillator operates at frequencies of 1MHz to 25MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the system PLL. 7.16.1.3 Watchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is programmable between 9.4 kHz and 2.3 MHz. The frequency spread over processing and temperature is 40 %. 7.16.2 System PLL The PLL accepts an input clock frequency in the range of 10MHz to 25MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156MHz to 320MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The PLL output frequency must be lower than 100 MHz. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50% duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100s. 7.16.3 Clock output The LPC1110/11/12/13/14/15 features a clock output function that routes the IRC oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin. 7.16.4 Wake-up process The LPC1110/11/12/13/14/15 begin operation at power-up and when awakened from Deep power-down mode by using the 12MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the system oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. 7.16.5 Power control The LPC1110/11/12/13/14/15 support a variety of power control features. There are three special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 7.16.5.1 Power profiles (LPC1100L and LPC1100XL series only) The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile. The power configuration routine configures the LPC1110/11/12/13/14/15 for one of the following power modes: LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 54 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Default mode corresponding to power configuration after reset. • CPU performance mode corresponding to optimized processing capability. • Efficiency mode corresponding to optimized balance of current consumption and CPU performance. • Low-current mode corresponding to lowest power consumption. In addition, the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock. 7.16.5.2 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.16.5.3 Deep-sleep mode In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut down. As an exception, the user has the option to keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows for additional power savings. Up to 13 pins total serve as external wake-up pins to the start logic to wake up the chip from Deep-sleep mode. Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source should be switched to IRC before entering Deep-sleep mode, because the IRC can be switched on and off glitch-free. 7.16.5.4 Deep power-down mode In Deep power-down mode, power is shut off to the entire chip with the exception of the WAKEUP pin. The LPC1110/11/12/13/14/15 can wake up from Deep power-down mode via the WAKEUP pin. A LOW-going pulse as short as 50 ns wakes up the part from Deep power-down mode. When entering Deep power-down mode, an external pull-up resistor is required on the WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from floating while in Deep power-down mode. 7.17 System control 7.17.1 Start logic The start logic connects external pins to corresponding interrupts in the NVIC. Each pin shown in Table8 to Table9 as input to the start logic has an individual interrupt in the NVIC interrupt vector table. The start logic pins can serve as external interrupt pins when the chip is running. In addition, an input signal on the start logic pins can wake up the chip from Deep-sleep mode when all clocks are shut down. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 55 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller The start logic must be configured in the system configuration block and in the NVIC before being used. 7.17.2 Reset Reset has four sources on the LPC1110/11/12/13/14/15: the RESET pin, the Watchdog reset, Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller. A LOW-going pulse as short as 50 ns resets the part. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. An external pull-up resistor is required on the RESET pin if Deep power-down mode is used. 7.17.3 Brownout detection The LPC1110/11/12/13/14/15 includes up to four levels for monitoring the voltage on the V pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt DD signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. Four threshold levels can be selected to cause a forced reset of the chip. 7.17.4 Code security (Code Read Protection - CRP) This feature of the LPC1110/11/12/13/14/15 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For details see the LPC111x user manual. There are three levels of Code Read Protection: 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. 2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected fully disables any access to the chip via the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via the UART. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 56 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be disabled. For details see the LPC111x user manual. 7.17.5 APB interface The APB peripherals are located on one APB bus. 7.17.6 AHBLite The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main static RAM, and the Boot ROM. 7.17.7 External interrupt inputs All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs serve as external interrupts (see Section7.17.1). 7.18 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four breakpoints and two watchpoints is supported. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 57 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 8. Limiting values Table 12. Limiting valu es In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit V supply voltage (core and external rail) [2] 0.5 +4.6 V DD V input voltage 5V tolerant I/O [2][3] 0.5 +5.5 V I pins; only valid when the V DD supply voltage is present 5 V tolerant [2][4] 0.5 +5.5 V open-drain pins PIO0_4 and PIO0_5 V analog input voltage pin configured as [2][5] 0.5 4.6 V IA analog input I supply current per supply pin - 100 mA DD I ground current per ground pin - 100 mA SS I I/O latch-up current (0.5V ) < V < - 100 mA latch DD I (1.5V ); DD T < 125C j T storage temperature non-operating [6] 65 +150 C stg T maximum junction temperature - 150 C j(max) P total power dissipation (per package) based on package - 1.5 W tot(pack) heat transfer, not device power consumption V electrostatic discharge voltage human body [7] - +6500 V ESD model; all pins [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not guaranteed. The conditions for functional operation are specified in Table16. [2] Maximum/minimum voltage above the maximum operating voltage (see Table16) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. [3] Including voltage on outputs in 3-state mode. [4] V present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when V is powered down. DD DD [5] See Table18 for maximum operating voltage. [6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details. [7] Human body model: equivalent to discharging a 100pF capacitor through a 1.5k series resistor. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 58 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9. Thermal characteristics The average chip junction temperature, T (C), can be calculated using the following j equation: Tj = Tamb+PDRthj–a (1) • T = ambient temperature (C), amb • R = the package junction-to-ambient thermal resistance (C/W) th(j-a) • P = sum of internal and I/O power dissipation D The internal power dissipation is the product of I and V . The I/O power dissipation of DD DD the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 13. Thermal cha racteristics Symbol Parameter Conditions Min Typ Max Unit T maximum junction - - 125 C j(max) temperature Table 14. LPC111x/x01 Thermal resistance value (C/W): ±15 % HVQFN33 LQFP48 ja ja JEDEC (4.5 in  4 in) JEDEC (4.5 in  4 in) 0 m/s 40.4 0 m/s 82.1 1 m/s 32.7 1 m/s 73.7 2.5 m/s 28.3 2.5 m/s 68.2 Single-layer (4.5 in  3 in) 8-layer (4.5 in  3 in) 0 m/s 84.8 0 m/s 115.2 1 m/s 61.6 1 m/s 94.7 2.5 m/s 53.1 2.5 m/s 86.3 jc 20.3 jc 29.6 jb 1.1 jb 34.2 LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 59 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 15. LPC111x/x02 Thermal resistance value (C/W): ±15 % HVQFN33 LQFP48 ja ja JEDEC (4.5 in  4 in) JEDEC (4.5 in  4 in) 0 m/s 40.8 0 m/s 83.3 1 m/s 33.1 1 m/s 74.9 2.5 m/s 28.7 2.5 m/s 69.4 Single-layer (4.5 in  3 in) 8-layer (4.5 in  3 in) 0 m/s 85.2 0 m/s 116.3 1 m/s 62 1 m/s 96 2.5 m/s 53.5 2.5 m/s 87.5 jc 17.9 jc 28.3 jb 1.5 jb 35.5 LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 60 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10. Static characteristics 10.1 LPC1100, LPC1100L series Table 16. Static charac teristics (LPC1100, LPC1100L series) T =40C to +85C, unless otherwise specified. amb Symbol Parameter Conditions Min Typ[1] Max Unit V supply voltage (core 1.8 3.3 3.6 V DD and external rail) LPC1100 series (LPC111x/101/201/301) power consumption I supply current Active mode; code DD while(1){} executed from flash system clock=12MHz [2][3][4] - 3 - mA [5][6] V = 3.3 V DD system clock=50MHz [2][3][5] - 9 - mA [6][7] V = 3.3 V DD Sleep mode; [2][3][4] - 2 - mA [5][6] system clock = 12 MHz V = 3.3 V DD Deep-sleep mode; [2][3][8] - 6 - A V = 3.3V DD Deep power-down mode; [2][9] - 220 - nA V = 3.3V DD LPC1100L series (LPC111x/002/102/202/302) power consumption in low-current mode[11] I supply current Active mode; code DD while(1){} executed from flash system clock=1MHz [2][3][5] - 840 - A [6][10] V = 3.3 V DD system clock=6MHz [2][3][5] - 1 - mA [6][10] V = 3.3 V DD system clock=12MHz [2][3][4] - 2 - mA [5][6] V = 3.3 V DD system clock=50MHz [2][3][5] - 7 - mA [6][7] V = 3.3 V DD Sleep mode; [2][3][4] - 1 - mA [5][6] system clock = 12 MHz V = 3.3 V DD system clock=50MHz [2][3][4] - 5 - mA [5][6] V = 3.3 V DD Deep-sleep mode; [2][3][8] - 2 - A V = 3.3V DD Deep power-down mode; [2][9] - 220 - nA V = 3.3V DD LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 61 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 16. Static characteristics (LPC1100, LPC1100L series) …continued T =40C to +85C, unless otherwise specified. amb Symbol Parameter Conditions Min Typ[1] Max Unit Standard port pins, RESET I LOW-level input current V =0V; on-chip pull-up - 0.5 10 nA IL I resistor disabled I HIGH-level input V =V ; on-chip - 0.5 10 nA IH I DD current pull-down resistor disabled I OFF-state output V =0V; V =V ; - 0.5 10 nA OZ O O DD current on-chip pull-up/down resistors disabled V input voltage pin configured to provide [12][13] 0 - 5.0 V I a digital function [14] V output voltage output active 0 - V V O DD V HIGH-level input 0.7V - - V IH DD voltage V LOW-level input voltage - - 0.3V V IL DD V hysteresis voltage - 0.4 - V hys V HIGH-level output 2.5 V  V  3.6 V; V  0.4 - - V OH DD DD voltage I =4 mA OH 1.8 V  V < 2.5 V; V  0.4 - - V DD DD I =3 mA OH V LOW-level output 2.5 V  V  3.6 V; - - 0.4 V OL DD voltage I =4 mA OL 1.8 V  V < 2.5 V; - - 0.4 V DD I =3 mA OL I HIGH-level output V =V 0.4V; 4 - - mA OH OH DD current 2.5 V  V  3.6 V DD 1.8 V  V < 2.5 V 3 - - mA DD I LOW-level output V =0.4V 4 - - mA OL OL current 2.5 V  V  3.6 V DD 1.8 V  V < 2.5 V 3 - - mA DD I HIGH-level short-circuit V =0V [15] - - 45 mA OHS OH output current I LOW-level short-circuit V =V [15] - - 50 mA OLS OL DD output current I pull-down current V =5V 10 50 150 A pd I I pull-up current V =0V; 15 50 85 A pu I 2.0 V  V  3.6 V DD 1.8 V  V < 2.0 V 10 50 85 A DD V <V <5V 0 0 0 A DD I High-drive output pin (PIO0_7) I LOW-level input current V =0V; on-chip pull-up - 0.5 10 nA IL I resistor disabled I HIGH-level input V =V ; on-chip - 0.5 10 nA IH I DD current pull-down resistor disabled LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 62 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 16. Static characteristics (LPC1100, LPC1100L series) …continued T =40C to +85C, unless otherwise specified. amb Symbol Parameter Conditions Min Typ[1] Max Unit I OFF-state output V =0V; V =V ; - 0.5 10 nA OZ O O DD current on-chip pull-up/down resistors disabled V input voltage pin configured to provide [12][13] 0 - 5.0 V I a digital function [14] V output voltage output active 0 - V V O DD V HIGH-level input 0.7V - - V IH DD voltage V LOW-level input voltage - - 0.3V V IL DD V hysteresis voltage 0.4 - - V hys V HIGH-level output 2.5 V  V  3.6 V; V  0.4 - - V OH DD DD voltage I =20 mA OH 1.8 V  V < 2.5 V; V  0.4 - - V DD DD I =12 mA OH V LOW-level output 2.5 V  V  3.6 V; - - 0.4 V OL DD voltage I =4 mA OL 1.8 V  V < 2.5 V; - - 0.4 V DD I =3 mA OL I HIGH-level output V =V 0.4V; 20 - - mA OH OH DD current 2.5 V  V  3.6 V DD 1.8 V  V < 2.5 V 12 - - mA DD I LOW-level output V =0.4V 4 - - mA OL OL current 2.5 V  V  3.6 V DD 1.8 V  V < 2.5 V 3 - - mA DD I LOW-level short-circuit V =V [15] - - 50 mA OLS OL DD output current I pull-down current V =5V 10 50 150 A pd I I pull-up current V =0V 15 50 85 A pu I 2.0 V  V  3.6 V DD 1.8 V  V < 2.0 V 10 50 85 A DD V <V <5V 0 0 0 A DD I I2C-bus pins (PIO0_4 and PIO0_5) V HIGH-level input 0.7V - - V IH DD voltage V LOW-level input voltage - - 0.3V V IL DD V hysteresis voltage - 0.05V - V hys DD I LOW-level output V =0.4V; I2C-bus pins 3.5 - - mA OL OL current configured as standard mode pins 2.5 V  V  3.6 V DD 1.8 V  V < 2.5 V 3 - - DD LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 63 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 16. Static characteristics (LPC1100, LPC1100L series) …continued T =40C to +85C, unless otherwise specified. amb Symbol Parameter Conditions Min Typ[1] Max Unit I LOW-level output V =0.4V; I2C-bus pins 20 - - mA OL OL current configured as Fast-mode Plus pins 2.5 V  V  3.6 V DD 1.8 V  V < 2.5 V 16 - - DD I input leakage current V =V [16] - 2 4 A LI I DD V =5V - 10 22 A I Oscillator pins V crystal input voltage 0.5 1.8 1.95 V i(xtal) V crystal output voltage 0.5 1.8 1.95 V o(xtal) Pin capacitance C input/output pins configured for analog - - 7.1 pF io capacitance function I2C-bus pins (PIO0_4 and - - 2.5 pF PIO0_5) pins configured as GPIO - - 2.8 pF [1] Typical ratings are not guaranteed. The values listed are at room temperature (25C), nominal supply voltages. [2] Tamb=25C. [3] I measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. DD [4] IRC enabled; system oscillator disabled; system PLL disabled. [5] BOD disabled. [6] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration block. [7] IRC disabled; system oscillator enabled; system PLL enabled. [8] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF. [9] WAKEUP pin and RESET pin are pulled HIGH externally. [10] System oscillator enabled; IRC disabled; system PLL disabled. [11] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. [12] Including voltage on outputs in 3-state mode. [13] V supply voltage must be present. DD [14] 3-state outputs go into 3-state mode in Deep power-down mode. [15] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [16] To V . SS LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 64 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.2 LPC1100XL series Table 17. Static charac teristics (LPC1100XL series) T =40C to +105C, unless otherwise specified. amb Symbol Parameter Conditions Min Typ[1] Max Unit V supply voltage (core 1.8 3.3 3.6 V DD and external rail) LPC1100XL series (LPC111x/103/203/303/323/333) power consumption in low-current mode[2] I supply current Active mode; code DD while(1){} executed from flash system clock=3MHz [3][4][5] - 600 - A [6][7] V = 3.3 V DD system clock=6MHz [3][4][5] - 850 - A [6][7] V = 3.3 V DD system clock=12MHz [3][4][6] - 1.4 - mA [7][8] V = 3.3 V DD system clock=50MHz [3][4][6] - 5.8 - mA [7][9] V = 3.3 V DD Sleep mode; [3][4][6] - 700 - A [7][8] system clock = 12 MHz V = 3.3 V DD system clock=50MHz [3][4][6] - 2.2 - mA [7][8] V = 3.3 V DD Deep-sleep mode; [3][4] - 1.8 15 A V = 3.3V; 25 C [10] DD Deep-sleep mode; [4][10] - - 50 A V = 3.3V; 105 C [11] DD Deep power-down mode; [3][12] - 220 1000 nA V = 3.3V; 25 C DD Deep power-down mode; [11][12] - - 3 A V = 3.3V; 105 C DD Standard port pins, RESET I LOW-level input current V =0V; on-chip pull-up - 0.5 10 nA IL I resistor disabled I HIGH-level input V =V ; on-chip - 0.5 10 nA IH I DD current pull-down resistor disabled I OFF-state output V =0V; V =V ; - 0.5 10 nA OZ O O DD current on-chip pull-up/down resistors disabled V input voltage pin configured to provide [13][14] 0 - 5.0 V I a digital function [15] V output voltage output active 0 - V V O DD V HIGH-level input 0.7V - - V IH DD voltage LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 65 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 17. Static characteristics (LPC1100XL series) …continued T =40C to +105C, unless otherwise specified. amb Symbol Parameter Conditions Min Typ[1] Max Unit V LOW-level input voltage - - 0.3V V IL DD V hysteresis voltage - 0.4 - V hys V HIGH-level output 2.5 V  V  3.6 V; V  0.4 - - V OH DD DD voltage I =4 mA OH 1.8 V  V < 2.5 V; V  0.4 - - V DD DD I =3 mA OH V LOW-level output 2.5 V  V  3.6 V; - - 0.4 V OL DD voltage I =4 mA OL 1.8 V  V < 2.5 V; - - 0.4 V DD I =3 mA OL I HIGH-level output V =V 0.4V; 4 - - mA OH OH DD current 2.5 V  V  3.6 V DD 1.8 V  V < 2.5 V 3 - - mA DD I LOW-level output V =0.4V 4 - - mA OL OL current 2.5 V  V  3.6 V DD 1.8 V  V < 2.5 V 3 - - mA DD I HIGH-level short-circuit V =0V [16] - - 45 mA OHS OH output current I LOW-level short-circuit V =V [16] - - 50 mA OLS OL DD output current I pull-down current V =5V 10 50 150 A pd I I pull-up current V =0V; 15 50 85 A pu I 2.0 V  V  3.6 V DD 1.8 V  V < 2.0 V 10 50 85 A DD V <V <5V 0 0 0 A DD I High-drive output pin (PIO0_7) I LOW-level input current V =0V; on-chip pull-up - 0.5 10 nA IL I resistor disabled I HIGH-level input V =V ; on-chip - 0.5 10 nA IH I DD current pull-down resistor disabled I OFF-state output V =0V; V =V ; - 0.5 10 nA OZ O O DD current on-chip pull-up/down resistors disabled V input voltage pin configured to provide [13][14] 0 - 5.0 V I a digital function [15] V output voltage output active 0 - V V O DD V HIGH-level input 0.7V - - V IH DD voltage V LOW-level input voltage - - 0.3V V IL DD V hysteresis voltage 0.4 - - V hys LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 66 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 17. Static characteristics (LPC1100XL series) …continued T =40C to +105C, unless otherwise specified. amb Symbol Parameter Conditions Min Typ[1] Max Unit V HIGH-level output 2.5 V  V  3.6 V; V  0.4 - - V OH DD DD voltage I =20 mA OH 1.8 V  V < 2.5 V; V  0.4 - - V DD DD I =12 mA OH V LOW-level output 2.5 V  V  3.6 V; - - 0.4 V OL DD voltage I =4 mA OL 1.8 V  V < 2.5 V; - - 0.4 V DD I =3 mA OL I HIGH-level output V =V 0.4V; 20 - - mA OH OH DD current 2.5 V  V  3.6 V DD 1.8 V  V < 2.5 V 12 - - mA DD I LOW-level output V =0.4V 4 - - mA OL OL current 2.5 V  V  3.6 V DD 1.8 V  V < 2.5 V 3 - - mA DD I LOW-level short-circuit V =V [16] - - 50 mA OLS OL DD output current I pull-down current V =5V 10 50 150 A pd I I pull-up current V =0V 15 50 85 A pu I 2.0 V  V  3.6 V DD 1.8 V  V < 2.0 V 10 50 85 A DD V <V <5V 0 0 0 A DD I I2C-bus pins (PIO0_4 and PIO0_5) V HIGH-level input 0.7V - - V IH DD voltage V LOW-level input voltage - - 0.3V V IL DD V hysteresis voltage - 0.05V - V hys DD I LOW-level output V =0.4V; I2C-bus pins 3.5 - - mA OL OL current configured as standard mode pins 2.5 V  V  3.6 V DD 1.8 V  V < 2.5 V 3 - - DD I LOW-level output V =0.4V; I2C-bus pins 20 - - mA OL OL current configured as Fast-mode Plus pins 2.5 V  V  3.6 V DD 1.8 V  V < 2.5 V 16 - - DD I input leakage current V =V [17] - 2 4 A LI I DD V =5V - 10 22 A I LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 67 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 17. Static characteristics (LPC1100XL series) …continued T =40C to +105C, unless otherwise specified. amb Symbol Parameter Conditions Min Typ[1] Max Unit Oscillator pins V crystal input voltage 0.5 1.8 1.95 V i(xtal) V crystal output voltage 0.5 1.8 1.95 V o(xtal) Pin capacitance C input/output pins configured for analog - - 7.1 pF io capacitance function I2C-bus pins (PIO0_4 and - - 2.5 pF PIO0_5) pins configured as GPIO - - 2.8 pF [1] Typical ratings are not guaranteed. The values listed are at room temperature (25C), nominal supply voltages. [2] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. [3] Tamb=25C. [4] I measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. DD [5] System oscillator enabled; IRC disabled; system PLL disabled. [6] BOD disabled. [7] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration block. [8] IRC enabled; system oscillator disabled; system PLL disabled. [9] IRC disabled; system oscillator enabled; system PLL enabled. [10] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF. [11] 105C spec applies only to parts with the J designator (e.g. LPC1115JET48). [12] WAKEUP pin and RESET pin are pulled HIGH externally. [13] Including voltage on outputs in 3-state mode. [14] V supply voltage must be present. DD [15] 3-state outputs go into 3-state mode in Deep power-down mode. [16] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [17] To V . SS LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 68 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.3 ADC static characteristics Table 18. ADC static c haracteristics T =40C to +105C unless otherwise specified; ADC frequency 4.5MHz, V = 2.5 V to 3.6 V. amb DD Symbol Parameter Conditions Min Typ Max Unit V analog input voltage 0 - V V IA DD C analog input capacitance - - 1 pF ia E differential linearity error [1][2] - - 1 LSB D E integral non-linearity [3] - - 1.5 LSB L(adj) E offset error [4] - - 3.5 LSB O E gain error [5] - - 0.6 % G E absolute error [6] - - 4 LSB T R voltage source interface - - 40 k vsi resistance R input resistance [7][8] - - 2.5 M i [1] The ADC is monotonic, there are no missing codes. [2] The differential linearity error (E ) is the difference between the actual step width and the ideal step width. See Figure17. D [3] The integral non-linearity (E ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after L(adj) appropriate adjustment of gain and offset errors. See Figure17. [4] The offset error (E ) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the O ideal curve. See Figure17. [5] The gain error (E ) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset G error, and the straight line which fits the ideal transfer curve. See Figure17. [6] The absolute error (E ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated T ADC and the ideal transfer curve. See Figure17. [7] Tamb = 25 C; maximum sampling frequency fs = 400 kSamples/s and analog input capacitance Cia = 1 pF. [8] Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs  Cia). LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 69 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller offset gain error error EO EG 1023 1022 1021 1020 1019 1018 (2) 7 code (1) out 6 5 (5) 4 (4) 3 (3) 2 1 1 LSB (ideal) 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO VDD − VSS 1 LSB = 1024 002aaf426 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve. Fig 17. ADC characteristics LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 70 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.4 BOD static characteristics Table 19. BOD static characteristics[1] T =25C. amb Symbol Parameter Conditions Min Typ Max Unit V threshold voltage interrupt level 1 th assertion - 2.22 - V de-assertion - 2.35 - V interrupt level 2 assertion - 2.52 - V de-assertion - 2.66 - V interrupt level 3 assertion - 2.80 - V de-assertion - 2.90 - V reset level 0 assertion - 1.46 - V de-assertion - 1.63 - V reset level 1 assertion - 2.06 - V de-assertion - 2.15 - V reset level 2 assertion - 2.35 - V de-assertion - 2.43 - V reset level 3 assertion - 2.63 - V de-assertion - 2.71 - V [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC111x user manual. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 71 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.5 Power consumption LPC1100 series (LPC111x/101/201/301) Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC111x user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. • Configure GPIO pins as outputs using the GPIOnDIR registers. • Write 0 to all GPIOnDATA registers to drive the outputs LOW. 002aaf390 12 IDD (mA) 48 MHz(2) 8 36 MHz(2) 24 MHz(2) 4 12 MHz(1) 0 1.8 2.4 3.0 3.6 VDD (V) Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 18. Active mode: Typical supply current I versus supply voltage V for different DD DD system clock frequencies (for LPC111x/101/201/301) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 72 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf391 12 IDD (mA) 48 MHz(2) 8 36 MHz(2) 24 MHz(2) 4 12 MHz(1) 0 −40 −15 10 35 60 85 temperature (°C) Conditions: V = 3.3 V; active mode entered executing code while(1){} from flash; all DD peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 19. Active mode: Typical supply current I versus temperature for different system DD clock frequencies (for LPC111x/101/201/301) 002aaf392 8 IDD (mA) 48 MHz(2) 6 36 MHz(2) 4 24 MHz(2) 12 MHz(1) 2 0 −40 −15 10 35 60 85 temperature (°C) Conditions: V = 3.3 V; sleep mode entered from flash; all peripherals disabled in the DD SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 20. Sleep mode: Typical supply current I versus temperature for different system DD clock frequencies (for LPC111x/101/201/301) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 73 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf394 40 IDD (μA) 30 3.6 V 3.3 V 2.0 V 1.8 V 20 10 0 −40 −15 10 35 60 85 temperature (°C) Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 21. Deep-sleep mode: Typical supply current I versus temperature for different DD supply voltages V (for LPC111x/101/201/301) DD 002aaf457 0.8 IDD (μA) 0.6 VDD = 3.6 V 3.3 V 2.0 V 1.8 V 0.4 0.2 0 −40 −15 10 35 60 85 temperature (°C) Fig 22. Deep power-down mode: Typical supply current I versus temperature for DD different supply voltages V (for LPC111x/101/201/301) DD LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 74 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.6 Power consumption LPC1100L series (LPC111x/002/102/202/302) Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC111x user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. • Configure GPIO pins as outputs using the GPIOnDIR registers. • Write 0 to all GPIOnDATA registers to drive the outputs LOW. 002aaf980 10 IDD (mA) 8 48 MHz(2) 6 36 MHz(2) 4 24 MHz(2) 12 MHz(1) 2 0 1.8 2.4 3.0 3.6 VDD (V) Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 23. Active mode: Typical supply current I versus supply voltage V for different DD DD system clock frequencies (for LPC111x/002/102/202/302) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 75 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf981 10 IDD (mA) 8 48 MHz(2) 6 36 MHz(2) 4 24 MHz(2) 12 MHz(1) 2 0 −40 −15 10 35 60 85 temperature (°C) Conditions: V = 3.3 V; active mode entered executing code while(1){} from flash; all DD peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 24. Active mode: Typical supply current I versus temperature for different system DD clock frequencies (for LPC111x/002/102/202/302) 002aaf982 6 IDD (mA) 48 MHz(2) 4 36 MHz(2) 24 MHz(2) 2 12 MHz(1) 0 −40 −15 10 35 60 85 temperature (°C) Conditions: V = 3.3 V; sleep mode entered from flash; all peripherals disabled in the DD SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 25. Sleep mode: Typical supply current I versus temperature for different system DD clock frequencies (for LPC111x/002/102/202/302) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 76 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf977 5.5 IDD (μA) 4.5 3.5 VDD = 3.3 V, 3.6 V 1.8 V 2.5 1.5 −40 −15 10 35 60 85 temperature (°C) Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 26. Deep-sleep mode: Typical supply current I versus temperature for different DD supply voltages V (for LPC111x/002/102/202/302) DD 002aaf978 0.8 IDD (μA) VDD = 3.6 V 0.6 3.3 V 1.8 V 0.4 0.2 0 −40 −15 10 35 60 85 temperature (°C) Fig 27. Deep power-down mode: Typical supply current I versus temperature for DD different supply voltages V (for LPC111x/002/102/202/302) DD LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 77 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.7 Power consumption LPC1100XL series (LPC111x/103/203/303/323/333) Table 20. Power cons umption at very low frequencies using the watchdog oscillator Symbol Parameter Conditions[1] Min Typ[2] Max Unit I supply current Active mode; code DD while(1){} executed from flash system clock=8.8kHz - 275 - A system clock=257 kHz - 305 - A system clock=515 kHz - 335 - A system clock=784 kHz - 368 - A system clock=1028kHz - 396 - A system clock=2230kHz - 538 - A Sleep mode; system clock = 8.8 kHz - 274 - A system clock=257kHz - 285 - A system clock=515kHz - 295 - A system clock=784kHz - 309 - A system clock=1028kHz - 317 - A system clock=2230kHz - 368 - A [1] WDT OSC enabled, VDD = 3.3 V, Temp = 25C. Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled, IRC disabled, System Oscillator disabled, System PLL disabled, BOD disabled. All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to UART and SPI0/1 disabled in system configuration block. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25C), nominal supply voltages. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 78 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC111x user manual): • Configure all pins as GPIO with pull-up resistor disabled in the IOCONFIG block. • Configure GPIO pins as outputs using the GPIOnDIR registers. • Write 0 to all GPIOnDATA registers to drive the outputs LOW. (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:25)(cid:27)(cid:22)(cid:25) (cid:25) (cid:23)(cid:23)(cid:23)(cid:27)(cid:27)(cid:27)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:44)(cid:44)(cid:44)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39) (cid:22)(cid:22)(cid:22)(cid:25)(cid:25)(cid:25)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:11)(cid:11)(cid:11)(cid:80)(cid:80)(cid:80)(cid:36)(cid:36)(cid:36)(cid:12)(cid:12)(cid:12) (cid:21)(cid:21)(cid:21)(cid:23)(cid:23)(cid:23)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:24) (cid:20)(cid:20)(cid:20)(cid:21)(cid:21)(cid:21)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:25)(cid:25)(cid:25)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:23)(cid:23)(cid:23)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:23) (cid:22)(cid:22)(cid:22)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:21)(cid:21)(cid:21)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:20)(cid:20)(cid:20)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:22) (cid:21) (cid:20) (cid:19) (cid:20)(cid:17)(cid:27) (cid:21)(cid:17)(cid:23) (cid:22) (cid:22)(cid:17)(cid:25) (cid:57)(cid:39)(cid:39)(cid:3)(cid:11)(cid:57)(cid:12) Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz to 6 MHz: system oscillator enabled; PLL, IRC disabled. 12 MHz: IRC enabled; system oscillator, PLL disabled. 24 MHz to 48 MHz: IRC disabled; system oscillator, PLL enabled. Fig 28. Active mode: Typical supply current I versus supply voltage V for different DD DD system clock frequencies (for LPC111xXL) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 79 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:25)(cid:27)(cid:22)(cid:26) (cid:25) (cid:23)(cid:23)(cid:23)(cid:27)(cid:27)(cid:27)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:44)(cid:44)(cid:44)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39) (cid:22)(cid:22)(cid:22)(cid:25)(cid:25)(cid:25)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:11)(cid:11)(cid:11)(cid:80)(cid:80)(cid:80)(cid:36)(cid:36)(cid:36)(cid:12)(cid:12)(cid:12) (cid:21)(cid:21)(cid:21)(cid:23)(cid:23)(cid:23)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:24) (cid:20)(cid:20)(cid:20)(cid:21)(cid:21)(cid:21)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:25)(cid:25)(cid:25)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:23)(cid:23)(cid:23)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:23) (cid:22)(cid:22)(cid:22)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:21)(cid:21)(cid:21)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:20)(cid:20)(cid:20)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:22) (cid:21) (cid:20) (cid:19) (cid:16)(cid:23)(cid:19) (cid:16)(cid:20)(cid:19) (cid:21)(cid:19) (cid:24)(cid:19) (cid:27)(cid:19) (cid:20)(cid:20)(cid:19) (cid:87)(cid:72)(cid:80)(cid:83)(cid:72)(cid:85)(cid:68)(cid:87)(cid:88)(cid:85)(cid:72)(cid:3)(cid:11)(cid:131)(cid:38)(cid:12) Conditions: V = 3.3 V; active mode entered executing code while(1){} from flash; all DD peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz to 6 MHz: system oscillator enabled; PLL, IRC disabled. 12 MHz: IRC enabled; system oscillator, PLL disabled. 24 MHz to 48 MHz: IRC disabled; system oscillator, PLL enabled. Fig 29. Active mode: Typical supply current I versus temperature for different system DD clock frequencies (for LPC111xXL) (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:25)(cid:27)(cid:22)(cid:27) (cid:21)(cid:17)(cid:24) (cid:23)(cid:23)(cid:23)(cid:27)(cid:27)(cid:27)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:44)(cid:44)(cid:44)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39) (cid:22)(cid:22)(cid:22)(cid:25)(cid:25)(cid:25)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:11)(cid:11)(cid:11)(cid:80)(cid:80)(cid:80)(cid:36)(cid:36)(cid:36)(cid:12)(cid:12)(cid:12) (cid:21)(cid:21)(cid:21)(cid:23)(cid:23)(cid:23)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:21) (cid:20)(cid:20)(cid:20)(cid:21)(cid:21)(cid:21)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:25)(cid:25)(cid:25)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:22)(cid:22)(cid:22)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:20)(cid:20)(cid:20)(cid:3)(cid:3)(cid:3)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93) (cid:20)(cid:17)(cid:24) (cid:20) (cid:19)(cid:17)(cid:24) (cid:19) (cid:16)(cid:23)(cid:19) (cid:16)(cid:20)(cid:19) (cid:21)(cid:19) (cid:24)(cid:19) (cid:27)(cid:19) (cid:20)(cid:20)(cid:19) (cid:87)(cid:72)(cid:80)(cid:83)(cid:72)(cid:85)(cid:68)(cid:87)(cid:88)(cid:85)(cid:72)(cid:3)(cid:11)(cid:131)(cid:38)(cid:12) Conditions: V = 3.3 V; sleep mode entered from flash; all peripherals disabled in the DD SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz to 6 MHz: system oscillator enabled; PLL, IRC disabled. 12 MHz: IRC enabled; system oscillator, PLL disabled. 24 MHz to 48 MHz: IRC disabled; system oscillator, PLL enabled. Fig 30. Sleep mode: Typical supply current I versus temperature for different system DD clock frequencies (for LPC111xXL) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 80 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aah553 20 IDD (μA) 15 VDD = 3.6 V 10 3.3 V 1.8 V 5 0 -40 -10 20 50 80 110 temperature (°C) Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 31. Deep-sleep mode: Typical supply current I versus temperature for different DD supply voltages V (for LPC111xXL) DD 002aah554 2 IDD (μA) 1.5 VDD = 3.6 V 1 3.3 V 1.8 V 0.5 0 -40 -10 20 50 80 110 temperature (°C) Fig 32. Deep power-down mode: Typical supply current I versus temperature for DD different supply voltages V (for LPC111xXL) DD LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 81 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.8 CoreMark data Remark: All CoreMark data were taken with the Keil uVision v. 4.6 tool. (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:25)(cid:27)(cid:23)(cid:19) (cid:21) (cid:72)(cid:72)(cid:72)(cid:73)(cid:73)(cid:73)(cid:73)(cid:73)(cid:73)(cid:76)(cid:76)(cid:76)(cid:70)(cid:70)(cid:70)(cid:76)(cid:76)(cid:76)(cid:72)(cid:72)(cid:72)(cid:81)(cid:81)(cid:81)(cid:70)(cid:70)(cid:70)(cid:92)(cid:92)(cid:92) (cid:38)(cid:38)(cid:38)(cid:48)(cid:48)(cid:48) (cid:70)(cid:70)(cid:70)(cid:83)(cid:83)(cid:83)(cid:88)(cid:88)(cid:88) (cid:11)(cid:11)(cid:11)(cid:11)(cid:11)(cid:11)(cid:76)(cid:76)(cid:76)(cid:87)(cid:87)(cid:87)(cid:72)(cid:72)(cid:72)(cid:85)(cid:85)(cid:85)(cid:68)(cid:68)(cid:68)(cid:87)(cid:87)(cid:87)(cid:76)(cid:76)(cid:76)(cid:82)(cid:82)(cid:82)(cid:81)(cid:81)(cid:81)(cid:86)(cid:86)(cid:86)(cid:18)(cid:18)(cid:18)(cid:86)(cid:86)(cid:86)(cid:12)(cid:12)(cid:12)(cid:18)(cid:18)(cid:18)(cid:48)(cid:48)(cid:48)(cid:43)(cid:43)(cid:43)(cid:93)(cid:93)(cid:93)(cid:12)(cid:12)(cid:12) (cid:20)(cid:17)(cid:25) (cid:71)(cid:71)(cid:71)(cid:72)(cid:72)(cid:72)(cid:73)(cid:73)(cid:73)(cid:68)(cid:68)(cid:68)(cid:88)(cid:88)(cid:88)(cid:79)(cid:79)(cid:79)(cid:87)(cid:87)(cid:87)(cid:18)(cid:18)(cid:18)(cid:79)(cid:79)(cid:79)(cid:82)(cid:82)(cid:82)(cid:90)(cid:90)(cid:90)(cid:16)(cid:16)(cid:16)(cid:70)(cid:70)(cid:70)(cid:88)(cid:88)(cid:88)(cid:85)(cid:85)(cid:85)(cid:85)(cid:85)(cid:85)(cid:72)(cid:72)(cid:72)(cid:81)(cid:81)(cid:81)(cid:87)(cid:87)(cid:87) (cid:20)(cid:17)(cid:21) (cid:19)(cid:17)(cid:27) (cid:19)(cid:17)(cid:23) (cid:19) (cid:19) (cid:20)(cid:19) (cid:21)(cid:19) (cid:22)(cid:19) (cid:23)(cid:19) (cid:24)(cid:19) (cid:73)(cid:85)(cid:72)(cid:84)(cid:88)(cid:72)(cid:81)(cid:70)(cid:92)(cid:3)(cid:11)(cid:48)(cid:43)(cid:93)(cid:12) V = 3.3 V; T = 25 °C; active mode; typical samples. DD Fig 33. CoreMark score for different Power API modes (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:25)(cid:27)(cid:24)(cid:19) (cid:20)(cid:24) (cid:44)(cid:44)(cid:44)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39) (cid:11)(cid:11)(cid:11)(cid:80)(cid:80)(cid:80)(cid:36)(cid:36)(cid:36)(cid:12)(cid:12)(cid:12) (cid:20)(cid:21) (cid:70)(cid:70)(cid:70)(cid:83)(cid:83)(cid:83)(cid:88)(cid:88)(cid:88) (cid:71)(cid:71)(cid:71)(cid:72)(cid:72)(cid:72)(cid:73)(cid:73)(cid:73)(cid:68)(cid:68)(cid:68)(cid:88)(cid:88)(cid:88)(cid:79)(cid:79)(cid:79)(cid:87)(cid:87)(cid:87) (cid:28) (cid:72)(cid:72)(cid:72)(cid:73)(cid:73)(cid:73)(cid:73)(cid:73)(cid:73)(cid:76)(cid:76)(cid:76)(cid:70)(cid:70)(cid:70)(cid:76)(cid:76)(cid:76)(cid:72)(cid:72)(cid:72)(cid:81)(cid:81)(cid:81)(cid:70)(cid:70)(cid:70)(cid:92)(cid:92)(cid:92) (cid:79)(cid:79)(cid:79)(cid:82)(cid:82)(cid:82)(cid:90)(cid:90)(cid:90)(cid:16)(cid:16)(cid:16)(cid:70)(cid:70)(cid:70)(cid:88)(cid:88)(cid:88)(cid:85)(cid:85)(cid:85)(cid:85)(cid:85)(cid:85)(cid:72)(cid:72)(cid:72)(cid:81)(cid:81)(cid:81)(cid:87)(cid:87)(cid:87) (cid:25) (cid:22) (cid:19) (cid:19) (cid:20)(cid:19) (cid:21)(cid:19) (cid:22)(cid:19) (cid:23)(cid:19) (cid:24)(cid:19) (cid:73)(cid:85)(cid:72)(cid:84)(cid:88)(cid:72)(cid:81)(cid:70)(cid:92)(cid:3)(cid:11)(cid:48)(cid:43)(cid:93)(cid:12) V = 3.3 V; T = 25 °C; active mode; typical samples. System oscillator enabled; main clock DD derived from external clock signal; PLL and SYSAHBCLKDIV enabled for frequencies > 20 MHz. Fig 34. CoreMark current consumption for different power modes using external clock LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 82 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller (cid:68)(cid:68)(cid:68)(cid:16)(cid:19)(cid:19)(cid:25)(cid:27)(cid:22)(cid:28) (cid:20)(cid:24) (cid:44)(cid:44)(cid:44)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39)(cid:39) (cid:11)(cid:11)(cid:11)(cid:80)(cid:80)(cid:80)(cid:36)(cid:36)(cid:36)(cid:12)(cid:12)(cid:12) (cid:20)(cid:21) (cid:71)(cid:71)(cid:71)(cid:72)(cid:72)(cid:72)(cid:73)(cid:73)(cid:73)(cid:68)(cid:68)(cid:68)(cid:88)(cid:88)(cid:88)(cid:79)(cid:79)(cid:79)(cid:87)(cid:87)(cid:87) (cid:70)(cid:70)(cid:70)(cid:83)(cid:83)(cid:83)(cid:88)(cid:88)(cid:88) (cid:28) (cid:72)(cid:72)(cid:72)(cid:73)(cid:73)(cid:73)(cid:73)(cid:73)(cid:73)(cid:76)(cid:76)(cid:76)(cid:70)(cid:70)(cid:70)(cid:76)(cid:76)(cid:76)(cid:72)(cid:72)(cid:72)(cid:81)(cid:81)(cid:81)(cid:70)(cid:70)(cid:70)(cid:92)(cid:92)(cid:92) (cid:79)(cid:79)(cid:79)(cid:82)(cid:82)(cid:82)(cid:90)(cid:90)(cid:90)(cid:16)(cid:16)(cid:16)(cid:70)(cid:70)(cid:70)(cid:88)(cid:88)(cid:88)(cid:85)(cid:85)(cid:85)(cid:85)(cid:85)(cid:85)(cid:72)(cid:72)(cid:72)(cid:81)(cid:81)(cid:81)(cid:87)(cid:87)(cid:87) (cid:25) (cid:22) (cid:19) (cid:19) (cid:20)(cid:19) (cid:21)(cid:19) (cid:22)(cid:19) (cid:23)(cid:19) (cid:24)(cid:19) (cid:73)(cid:85)(cid:72)(cid:84)(cid:88)(cid:72)(cid:81)(cid:70)(cid:92)(cid:3)(cid:11)(cid:48)(cid:43)(cid:93)(cid:12) V = 3.3 V; T = 25 °C; active mode; typical samples. IRC enabled; main clock derived from IRC; DD PLL and SYSAHBCLKDIV enabled as needed. Fig 35. CoreMark current consumption for different power modes using IRC LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 83 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.9 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at T =25 C. Unless amb noted otherwise, the system oscillator and PLL are running in both measurements. The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz. Table 21. Power consumption for individual analog and digital blocks Peripheral Typical supply current in Notes mA n/a 12 MHz 48 MHz IRC 0.27 - - System oscillator running; PLL off; independent of main clock frequency. System oscillator 0.22 - - IRC running; PLL off; independent of main clock at 12 MHz frequency. Watchdog 0.004 - - System oscillator running; PLL off; independent oscillator at of main clock frequency. 500kHz/2 BOD 0.051 - - Independent of main clock frequency. Main PLL - 0.21 - ADC - 0.08 0.29 CLKOUT - 0.12 0.47 Main clock divided by 4 in the CLKOUTDIV register. CT16B0 - 0.02 0.06 CT16B1 - 0.02 0.06 CT32B0 - 0.02 0.07 CT32B1 - 0.02 0.06 GPIO - 0.23 0.88 GPIO pins configured as outputs and set to LOW. Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register. IOCONFIG - 0.03 0.10 I2C - 0.04 0.13 ROM - 0.04 0.15 SPI0 - 0.12 0.45 SPI1 - 0.12 0.45 UART - 0.22 0.82 WDT/WWDT - 0.02 0.06 Main clock selected as clock source for the WDT. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 84 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.10 Electrical pin characteristics 002aah548 3.6 T = 105°C VOH 85 °C (V) 25 °C -40 °C 3.2 2.8 2.4 2 0 10 20 30 40 50 60 IOH (mA) Conditions: V = 3.3 V; on pin PIO0_7. DD Fig 36. High-drive output: Typical HIGH-level output voltage V versus HIGH-level OH output current I . OH 002aah549 60 T = 105°C IOL 85 °C (mA) 25 °C -40 °C 40 20 0 0 0.2 0.4 0.6 VOL (V) Conditions: V = 3.3 V; on pins PIO0_4 and PIO0_5. DD Fig 37. I2C-bus pins (high current sink): Typical LOW-level output current I versus OL LOW-level output voltage V OL LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 85 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aah550 15 T = 105°C IOL 85 °C (mA) 25 °C -40 °C 10 5 0 0 0.2 0.4 0.6 VOL (V) Conditions: V = 3.3 V; standard port pins and PIO0_7. DD Fig 38. Typical LOW-level output current I versus LOW-level output voltage V OL OL 002aah551 3.6 VOH (V) T = 105 °C 85 °C 3.2 25 °C -40 °C 2.8 2.4 2 0 8 16 24 IOH (mA) Conditions: V = 3.3 V; standard port pins. DD Fig 39. Typical HIGH-level output voltage V versus HIGH-level output source current OH I OH LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 86 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aah552 10 Ipu (μA) -10 -30 T = 105 °C 85 °C 25 °C -40 °C -50 -70 0 1 2 3 4 5 VI (V) Conditions: V = 3.3 V; standard port pins. DD Fig 40. Typical pull-up current I versus input voltage V pu I 002aah547 80 T = 105 °C 85 °C Ipd 25 °C (μA) -40 °C 60 40 20 0 0 1 2 3 4 5 VI (V) Conditions: V = 3.3 V; standard port pins. DD Fig 41. Typical pull-down current I versus input voltage V pd I LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 87 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11. Dynamic characteristics 11.1 Power-up ramp conditions Table 22. Power-up characteristics[1] T =40C to +85C. amb Symbol Parameter Conditions Min Typ Max Unit t rise time at t = t : 0 < V 400 mV [2] 0 - 500 ms r 1 I t wait time [2][3] 12 - - s wait V input voltage at t = t on pin V 0 - 400 mV I 1 DD [1] Does not apply to the LPC1100XL series (LPC111x/103/203/303/323/333). [2] See Figure42. [3] The wait time specifies the time the power supply must be at levels below 400 mV before ramping up. tr VDD 400 mV 0 twait t = t1 002aag001 Condition: 0 < VI 400 mV at start of power-up (t = t1) Fig 42. Power-up ramp 11.2 Flash memory Table 23. Flash characteristics T =40C to +105C, unless otherwise specified. T =85C for flash programming. amb amb Symbol Parameter Conditions Min Typ Max Unit N endurance [1] 10000 100000 - cycles endu t retention time powered 10 - - years ret unpowered 20 - - years t erase time sector or multiple 95 100 105 ms er consecutive sectors t programming time [2] 0.95 1 1.05 ms prog [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. Flash programming operation temperature must not exceed Tamb = 85 C. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 88 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11.3 External clock Table 24. Dynamic characteristic: external clock T =40C to +105C; V over specified ranges.[1] amb DD Symbol Parameter Conditions Min Typ[2] Max Unit f oscillator frequency 1 - 25 MHz osc T clock cycle time 40 - 1000 ns cy(clk) t clock HIGH time T 0.4 - - ns CHCX cy(clk) t clock LOW time T 0.4 - - ns CLCX cy(clk) t clock rise time - - 5 ns CLCH t clock fall time - - 5 ns CHCL [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25C), nominal supply voltages. tCHCX tCHCL tCLCX tCLCH Tcy(clk) 002aaa907 Fig 43. External clock timing (with an amplitude of at least V = 200mV) i(RMS) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 89 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11.4 Internal oscillators Table 25. Dynamic characteristic: internal oscillators T =40C to +105C; 2.7 V  V  3.6 V.[1] amb DD Symbol Parameter Conditions Min Typ[2] Max Unit f internal RC oscillator frequency - 11.88 12 12.12 MHz osc(RC) [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25C), nominal supply voltages. 002aaf403 12.15 f (MHz) VDD = 3.6 V 3.3 V 3.0 V 12.05 2.7 V 2.4 V 2.0 V 11.95 11.85 −40 −15 10 35 60 85 temperature (°C) Conditions: Frequency values are typical values. 12 MHz  1 % accuracy is guaranteed for 2.7 V  VDD  3.6 V and Tamb=40C to +85C. Variations between parts may cause the IRC to fall outside the 12 MHz  1 % accuracy specification for voltages below 2.7 V. Fig 44. Internal RC oscillator frequency versus temperature (F parts) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 90 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aah597 12.15 fosc(RC) (MHz) 12.1 3.6 V 3.3 V 12.05 3.0 V 2.7 V 2.4 V 12 2.0 V 11.95 11.9 11.85 -50 -10 30 70 110 temperature (°C) Conditions: Frequency values are typical values. 12 MHz  1 % accuracy is guaranteed for 2.7 V  VDD  3.6 V and Tamb=40C to +105C. Variations between parts may cause the IRC to fall outside the 12 MHz  1 % accuracy specification for voltages below 2.7 V. Fig 45. Internal RC oscillator frequency versus temperature (J parts) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 91 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 26. Dynamic characteristics: Watchdog oscillator Symbol Parameter Conditions Min Typ[1] Max Unit f internal oscillator DIVSEL = 0x1F, FREQSEL = 0x1 [2][3] - 9.4 - kHz osc(int) frequency in the WDTOSCCTRL register; DIVSEL = 0x00, FREQSEL = 0xF [2][3] - 2300 - kHz in the WDTOSCCTRL register [1] Typical ratings are not guaranteed. The values listed are at room temperature (25C), nominal supply voltages. [2] The typical frequency spread over processing and temperature (Tamb = 40 C to +105 C) is 40 %. [3] See the LPC111x user manual. 11.5 I/O pins Table 27. Dynamic characteristic: I/O pins[1] T =40C to +105C; 3.0 V  V  3.6 V. amb DD Symbol Parameter Conditions Min Typ Max Unit t rise time pin 3.0 - 5.0 ns r configured as output t fall time pin 2.5 - 5.0 ns f configured as output [1] Applies to standard port pins and RESET pin. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 92 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11.6 I2C-bus Table 28. Dynamic characteristic: I2C-bus pins[1] T =40C to +105C.[2] amb Symbol Parameter Conditions Min Max Unit f SCL clock Standard-mode 0 100 kHz SCL frequency Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz t fall time [4][5][6][7] of both SDA and - 300 ns f SCL signals Standard-mode Fast-mode 20 + 0.1  C 300 ns b Fast-mode Plus - 120 ns t LOW period of Standard-mode 4.7 - s LOW the SCL clock Fast-mode 1.3 - s Fast-mode Plus 0.5 - s t HIGH period of Standard-mode 4.0 - s HIGH the SCL clock Fast-mode 0.6 - s Fast-mode Plus 0.26 - s t data hold time [3][4][8] Standard-mode 0 - s HD;DAT Fast-mode 0 - s Fast-mode Plus 0 - s t data set-up [9][10] Standard-mode 250 - ns SU;DAT time Fast-mode 100 - ns Fast-mode Plus 50 - ns [1] See the I2C-bus specification UM10204 for details. [2] Parameters are valid over operating temperature range unless otherwise specified. [3] t is the data hold time that is measured from the falling edge of SCL; applies to data in transmission HD;DAT and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [5] C = total capacitance of one bus line in pF. b [6] The maximum t for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA f output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. [8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [9] t is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in SU;DAT transmission and the acknowledge. [10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement t =250 ns must then be met. This will automatically be the case if the device does not stretch the SU;DAT LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 93 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller tf tSU;DAT 70 % 70 % SDA 30 % 30 % tf tHD;DAT tVD;DAT tHIGH 70 % 70 % 70 % 70 % SCL 30 % 30 % 30 % 30 % tLOW S 1 / fSCL 002aaf425 Fig 46. I2C-bus pins clock timing 11.7 SPI interfaces Table 29. Dynamic cha racteristics of SPI pins in SPI mode Symbol Parameter Conditions Min Typ Max Unit SPI master (in SPI mode) T clock cycle time full-duplex mode [1] 50 - - ns cy(clk) when only transmitting [1] 40 ns t data set-up time in SPI mode [2] 15 - - ns DS 2.4 V  V  3.6 V DD 2.0 V  V < 2.4 V [2] 20 ns DD 1.8 V  V < 2.0 V [2] 24 - - ns DD t data hold time in SPI mode [2] 0 - - ns DH t data output valid time in SPI mode [2] - - 10 ns v(Q) t data output hold time in SPI mode [2] 0 - - ns h(Q) SPI slave (in SPI mode) T PCLK cycle time 20 - - ns cy(PCLK) t data set-up time in SPI mode [3][4] 0 - - ns DS t data hold time in SPI mode [3][4] 3  T + 4 - - ns DH cy(PCLK) t data output valid time in SPI mode [3][4] - - 3  T + 11 ns v(Q) cy(PCLK) t data output hold time in SPI mode [3][4] - - 2  T + 5 ns h(Q) cy(PCLK) [1] Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the main clock frequency f , the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register), main and the SPI CPSDVSR parameter (specified in the SPI clock prescale register). [2] Tamb = 40 C to 105 C. [3] Tcy(clk) = 12  Tcy(PCLK). [4] Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 94 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) MOSI DATA VALID DATA VALID tDS tDH CPHA = 1 MISO DATA VALID DATA VALID tv(Q) th(Q) MOSI DATA VALID DATA VALID tDS tDH CPHA = 0 MISO DATA VALID DATA VALID 002aae829 Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 47. SPI master timing in SPI mode LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 95 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tDS tDH MOSI DATA VALID DATA VALID tv(Q) th(Q) CPHA = 1 MISO DATA VALID DATA VALID tDS tDH MOSI DATA VALID DATA VALID tv(Q) th(Q) CPHA = 0 MISO DATA VALID DATA VALID 002aae830 Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 48. SPI slave timing in SPI mode LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 96 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 12. Application information 12.1 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in Table18: • The ADC input trace must be short and as close as possible to the LPC1110/11/12/13/14/15 chip. • The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines. • Because the ADC and the digital core share the same power supply, the power supply line must be adequately filtered. • To improve the ADC performance in a very noisy environment, put the device in Sleep mode during the ADC conversion. 12.2 Use of ADC input trigger signals For applications that use trigger signals to start conversions and require a precise sample frequency, ensure that the period of the trigger signal is an integral multiple of the period of the ADC clock. 12.3 XTAL input The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with C = 100 pF. To limit the input voltage to the specified range, choose an additional i capacitor to ground C which attenuates the input voltage by a factor C/(C + C ). In slave g i i g mode, a minimum of 200 mV (RMS) is needed. LPC1xxx XTALIN Ci Cg 100 pF 002aae788 Fig 49. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100pF (Figure49), with an amplitude between 200mV (RMS) and 1000mV (RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure50 and in Table30 and Table31. Since the feedback resistance is integrated on chip, only a crystal and the capacitances C and C need to be connected externally in case of X1 X2 LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 97 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller fundamental mode oscillation (the fundamental frequency is represented by L, C and L R ). Capacitance C in Figure50 represents the parallel package capacitance and should S P not be larger than 7 pF. Parameters F , C , R and C are supplied by the crystal OSC L S P manufacturer (see Table30). LPC1xxx L XTALIN XTALOUT = CL CP XTAL RS CX1 CX2 002aaf424 Fig 50. Oscillator modes and models: oscillation mode of operation and external crystal model used for C /C evaluation X1 X2 Table 30. Recommended values for C /C in oscillation mode (crystal and external X1 X2 components parameters) low frequency mode Fundamental oscillation Crystal load Maximum crystal External load frequency F capacitance C series resistance R capacitors C , C OSC L S X1 X2 1MHz to 5MHz 10 pF < 300 18 pF, 18 pF 20 pF < 300 39 pF, 39 pF 30 pF < 300 57pF, 57pF 5MHz to 10MHz 10 pF < 300 18 pF, 18 pF 20 pF < 200 39 pF, 39 pF 30 pF < 100 57 pF, 57 pF 10MHz to 15MHz 10 pF < 160 18 pF, 18 pF 20 pF < 60 39 pF, 39 pF 15MHz to 20MHz 10 pF < 80 18 pF, 18 pF Table 31. Recommended values for C /C in oscillation mode (crystal and external X1 X2 components parameters) high frequency mode Fundamental oscillation Crystal load Maximum crystal External load frequency F capacitance C series resistance R capacitors C , C OSC L S X1 X2 15MHz to 20MHz 10 pF < 180 18 pF, 18 pF 20 pF < 100 39 pF, 39 pF 20MHz to 25MHz 10 pF < 160 18 pF, 18 pF 20 pF < 80 39 pF, 39 pF LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 98 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 12.4 XTAL Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors C , C , and C in case X1 X2 X3 of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C and C should be chosen smaller X1 X2 accordingly to the increase in parasitics of the PCB layout. 12.5 Standard I/O pad configuration Figure51 shows the possible pin modes for standard I/O pins with analog input function: • Digital output driver • Digital input: Pull-up enabled/disabled • Digital input: Pull-down enabled/disabled • Digital input: Repeater mode enabled/disabled • Digital output: Pseudo open-drain mode enable/disabled • Analog input LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 99 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller VDD VDD open-drain enable strong pin configured output enable ESD pull-up as digital output driver data output PIN strong pull-down ESD VSS VDD weak pull-up pull-up enable weak repeater mode pin configured enable pull-down as digital input pull-down enable data input select analog input pin configured analog input as analog input 002aah159 Open-drain mode available on series LPC1100L and LPC1100XL. Fig 51. Standard I/O pad configuration 12.6 Reset pad configuration VDD VDD VDD Rpu ESD 20 ns RC reset PIN GLITCH FILTER ESD VSS 002aaf274 Fig 52. Reset pad configuration LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 100 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 12.7 ElectroMagnetic Compatibility (EMC) Radiated emission measurements according to the IEC61967-2 standard using the TEM-cell method are shown for the LPC1114FBD48/302 in Table32. Table 32. ElectroMagnetic Compatibility (EMC) for part LPC1114FBD48/302 (TEM-cell method) V = 3.3 V; T = 25 C. DD amb Parameter Frequency band System clock = Unit 12 MHz 24 MHz 48 MHz Input clock: IRC (12 MHz) maximum 150 kHz to 30 MHz 7 5 7 dBV peak level 30 MHz to 150 MHz 2 1 10 dBV 150 MHz to 1 GHz 4 8 16 dBV IEC level[1] - O N M - Input clock: crystal oscillator (12 MHz) maximum 150 kHz to 30 MHz 7 7 7 dBV peak level 30 MHz to 150 MHz 2 1 8 dBV 150 MHz to 1 GHz 4 7 14 dBV IEC level[1] - O N M - [1] IEC levels refer to Appendix D in the IEC61967-2 Specification. LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 101 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 12.8 ADC effective input impedance A simplified diagram of the ADC input channels can be used to determine the effective input impedance seen from an external voltage source. See Figure53. ADC Block Source Rmux Rsw Rs ADC COMPARATOR <2 kΩ <1.3 kΩ Rin Cia Cio VEXT VSS 002aah615 Fig 53. ADC input channel The effective input impedance, R , seen by the external voltage source, V , is the in EXT parallel impedance of ((1/f x C ) + R + R ) and (1/f x C ), and can be calculated s ia mux sw s io using Equation2 with f = sampling frequency s C = ADC analog input capacitance ia R = analog mux resistance mux R = switch resistance sw C = pin capacitance io R = --------1----------+R +R  --------1---------- (2) in f C mux sw f C  s ia s io Under nominal operating condition V = 3.3 V and with the maximum sampling DD frequency fs = 400 kHz, the parameters assume the following values: C = 1 pF (max) ia R = 2 kΩ (max) mux R = 1.3 kΩ (max) sw C = 7.1 pF (max) io The effective input impedance with these parameters is R = 308 kΩ. in LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 102 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 13. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE v M A Z 20 11 Q A2 A A1 (A 3 ) pin 1 index θ Lp L 1 10 detail X e w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z(1) θ 0.3 2.45 0.49 0.32 13.0 7.6 10.65 1.1 1.1 0.9 mm 2.65 0.25 1.27 1.4 0.25 0.25 0.1 0.1 2.25 0.36 0.23 12.6 7.4 10.00 0.4 1.0 0.4 8o 0.012 0.096 0.019 0.013 0.51 0.30 0.419 0.043 0.043 0.035 0o inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004 0.004 0.089 0.014 0.009 0.49 0.29 0.394 0.016 0.039 0.016 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT163-1 075E04 MS-013 03-02-19 Fig 54. Package outline SOT163-1 (SO20) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 103 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 D E A X c y HE v M A Z 20 11 Q A2 (A 3 ) A pin 1 index A1 θ Lp L 1 10 detail X w M e bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1.1 00..1055 00..9850 0.25 00..3109 00..21 66..64 44..53 0.65 66..62 1 00..7550 00..43 0.2 0.13 0.1 00..52 80oo Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT360-1 MO-153 03-02-19 Fig 55. Package outline SOT360-1 (TSSOP20) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 104 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1 D E A X c y HE v M A Z 28 15 Q A2 (A 3 ) A pin 1 index A1 θ Lp L 1 14 detail X w M e bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1.1 00..1055 00..9850 0.25 00..3109 00..21 99..86 44..53 0.65 66..62 1 00..7550 00..43 0.2 0.13 0.1 00..85 80oo Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT361-1 MO-153 03-02-19 Fig 56. Package outline SOT361-1 (TSSOP28) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 105 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller DIP28: plastic dual in-line package; 28 leads (600 mil) SOT117-1 ne D ME a pl g n ati se A2 A L A1 c Z e w M b1 (e ) 1 b 28 15 MH pin 1 index E 1 14 0 5 10 mm scale DIMENSIONS (mm dimensions are derived from the original inch dimensions) UNIT mAax. mAi n1 . mAa 2x . b b1 c D(1) E(1) e e1 L ME MH w mZax(.1) 1.7 0.53 0.32 36 14.1 3.9 15.80 17.15 mm 5.1 0.51 4 2.54 15.24 0.25 1.7 1.3 0.38 0.23 35 13.7 3.4 15.24 15.90 0.066 0.020 0.013 1.41 0.56 0.15 0.62 0.68 inches 0.2 0.02 0.16 0.1 0.6 0.01 0.067 0.051 0.014 0.009 1.34 0.54 0.13 0.60 0.63 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT117-1 051G05 MO-015 SC-510-28 03-02-13 Fig 57. Package outline SOT117-1 (DIP28) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 106 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm D B A terminal 1 index area A E A1 c detail X C e1 v C A B y1 C y e 1/2 e b w C 9 16 L 8 17 e Eh e2 1/2 e 1 24 terminal 1 index area 32 25 Dh X 0 2.5 5 mm scale Dimensions (mm are the original dimensions) Unit(1) A(1) A1 b c D(1) Dh E(1) Eh e e1 e2 L v w y y1 max 0.05 0.30 5.1 3.75 5.1 3.75 0.5 mm nom 0.85 0.2 0.5 3.5 3.5 0.1 0.05 0.05 0.1 min 0.00 0.18 4.9 3.45 4.9 3.45 0.3 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn33f_po Outline References European Issue date version IEC JEDEC JEITA projection 11-10-11 MO-220 11-10-17 Fig 58. Package outline (HVQFN33 5x5) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 107 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm D B A terminal 1 index area E A A1 c detail X e1 C v C A B e b w C y1C y 9 16 L 8 17 e Eh e2 33 1 24 X terminal 1 32 25 index area Dh 0 2.5 5 mm scale Dimensions Unit A(1) A1 b c D(1) Dh E(1) Eh e e1 e2 L v w y y1 max 1.00 0.05 0.35 7.1 4.85 7.1 4.85 0.75 mm nom 0.85 0.02 0.28 0.2 7.0 4.70 7.0 4.70 0.65 4.55 4.55 0.60 0.1 0.05 0.08 0.1 min 0.80 0.00 0.23 6.9 4.55 6.9 4.55 0.45 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn33_po Outline References European Issue date version IEC JEDEC JEITA projection 09-03-17 - - - 09-03-23 Fig 59. Package outline (HVQFN33 7x7) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 108 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 A1 (A 3 ) wM θ pin 1 index bp Lp 48 13 L detail X 1 12 ZD vM A e wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. A1 A2 A3 bp c D(1) E(1) e HD HE L Lp v w y ZD(1) ZE(1) θ mm 1.6 00..2005 11..4355 0.25 00..2177 00..1182 76..19 76..19 0.5 98..1855 98..1855 1 00..7455 0.2 0.12 0.1 00..9555 00..9555 70oo Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 00-01-19 SOT313-2 136E05 MS-026 03-02-25 Fig 60. Package outline SOT313-2 (LQFP48) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 109 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm SOT616-3 D B A terminal 1 index area A A1 E c detail X e1 C 1/2 e e b v M C A B y1 C y 7 12 w M C L 13 6 e Eh e2 1/2 e 1 18 terminal 1 index area 24 19 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) A(1) UNIT max. A1 b c D(1) Dh E(1) Eh e e1 e2 L v w y y1 0.05 0.30 4.1 2.75 4.1 2.75 0.5 mm 1 0.2 0.5 2.5 2.5 0.1 0.05 0.05 0.1 0.00 0.18 3.9 2.45 3.9 2.45 0.3 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 04-11-19 SOT616-3 - - - MO-220 - - - 05-03-10 Fig 61. Package outline SOT616-3 (HVQFN24) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 110 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 x 4.5 x 0.7 mm SOT1155-2 D B A ball A1 index area A2 E A A1 detail X e1 C Ø v C A B e 1/2 e b Ø w C y1C y H e G F E e2 D 1/2 e C B A ball A1 1 2 3 4 5 6 7 8 solder mask open area X index area not for solder ball 0 5 mm scale Dimensions Unit A A1 A2 b D E e e1 e2 v w y y1 max 1.10 0.30 0.80 0.35 4.6 4.6 mm nom 0.95 0.25 0.70 0.30 4.5 4.5 0.5 3.5 3.5 0.15 0.05 0.08 0.1 min 0.85 0.20 0.65 0.25 4.4 4.4 sot1155-2_po Outline References European Issue date version IEC JEDEC JEITA projection 13-06-17 SOT1155-2 - - - 13-06-19 Fig 62. Package outline TFBGA48 (SOT1155-2) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 111 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 14. Soldering 13.40 0.60 (20×) 1.50 8.00 11.00 11.40 1.27 (18×) solder lands occupied area placement accuracy ± 0.25 Dimensions in mm sot163-1_fr Fig 63. Reflow soldering of the SO20 package LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 112 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Footprint information for reflow soldering of TSSOP20 package SOT360-1 Hx Gx P2 (0.125) (0.125) Hy Gy By Ay C D2 (4x) P1 D1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.650 0.750 7.200 4.500 1.350 0.400 0.600 6.900 5.300 7.300 7.450 sot360-1_fr Fig 64. Reflow soldering of the TSSOP20 package LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 113 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Footprint information for reflow soldering of TSSOP28 package SOT361-1 Hx Gx P2 (0.125) (0.125) Hy Gy By Ay C D2 (4x) P1 D1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.650 0.750 7.200 4.500 1.350 0.400 0.600 9.500 5.300 11.800 7.450 sot361-1_fr Fig 65. Reflow soldering of the TSSOP28 package LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 114 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Footprint information for reflow soldering of HVQFN24 package SOT616-3 Hx Gx D P 0.025 0.025 C (0.105) SPx nSPx SPy ot Hy Gy y t SLy By Ay P nSPy S SPx tot SLx Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste occupied area nSPx nSPy 2 2 Dimensions in mm P Ax Ay Bx By C D SLx SLy SPx tot SPy tot SPx SPy Gx Gy Hx Hy 0.500 5.000 5.000 3.200 3.200 0.900 0.240 2.500 2.500 1.500 1.500 0.550 0.550 4.300 4.300 5.250 5.250 07-05-07 Issue date sot616-3_fr 09-06-15 Fig 66. Reflow soldering of the HVQFN24 package LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 115 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Footprint information for reflow soldering of HVQFN33 package Hx Gx see detail X P nSPx Ay Hy Gy SLy By nSPy C D SLx Bx Ax 0.60 solder land 0.30 solder paste detail X occupied area Dimensions in mm P Ax Ay Bx By C D Gx Gy Hx Hy SLx SLy nSPx nSPy 0.5 5.95 5.95 4.25 4.25 0.85 0.27 5.25 5.25 6.2 6.2 3.75 3.75 3 3 11-11-15 Issue date 002aag766 11-11-20 Fig 67. Reflow soldering of the HVQFN33 package (5x5) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 116 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Footprint information for reflow soldering of HVQFN33 package OID = 8.20 OA PID = 7.25 PA+OA OwDtot = 5.10 OA evia = 4.25 0.20 SR W = 0.30 CU chamfer (4×) e = 0.65 P S OIE = 8.20 OA OwEtot = 5.10 OA EHS = 4.85 CU 4.55 SR SEhtot = 2.70 SP GapE = 0.70 SPE = 1.00 SP 45 DM evia = 1.05 evia = 4.25 LbE = 5.80 CU PIE = 7.25 PA+OA LaE = 7.95 CU 0. SPD = 1.00 SP 0.45 DM GapD = 0.70 SP evia = 2.40 B-side SDhtot = 2.70 SP Solder resist covered via 4.55 SR DHS = 4.85 CU 0.30 PH LbD = 5.80 CU 0.60 SR cover LaD = 7.95 CU 0.60 CU (A-side fully covered) number of vias: 20 solder land solder land plus solder paste solder paste deposit solder resist Remark: occupied area Dimensions in mm Stencil thickness: 0.125 mm 001aao134 Fig 68. Reflow soldering of the HVQFN33 package (7x7) LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 117 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Footprint information for reflow soldering of LQFP48 package SOT313-2 Hx Gx P2 P1 (0.125) Hy Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy 0.500 0.560 10.350 10.350 7.350 7.350 1.500 0.280 0.500 7.500 7.500 10.650 10.650 sot313-2_fr Fig 69. Reflow soldering of the LQFP48 package LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 118 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Footprint information for reflow soldering of TFBGA48 package SOT1155-2 Hx P P Hy see detail X solder land solder paste deposit solder land plus solder paste SL occupied area SP SR solder resist detail X DIMENSIONS in mm P SL SP SR Hx Hy 0.50 0.225 0.275 0.325 4.75 4.75 sot1155-2_fr Fig 70. Reflow soldering for the TFBGA48 package LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 119 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 15. Abbreviations Table 33. Abbreviations Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General Purpose Input/Output PLL Phase-Locked Loop RC Resistor-Capacitor SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port TEM Transverse ElectroMagnetic UART Universal Asynchronous Receiver/Transmitter 16. References [1] LPC111x/LPC11Cxx User manual UM10398: http://www.nxp.com/documents/user_manual/UM10398.pdf [2] LPC111x Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC111X.pdf LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 120 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 17. Revision history Table 34. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC111X v.9.2 20140326 Product data sheet - LPC111X v.9.1 Modifications: • Pin description tables for RESET/PIO0_0 updated: In deep power-down mode, this pin must be pulled HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed. See Section6.2. • Pin description notes relating to open-drain I2C-bus pins updated for clarity in Section6.2. • Pin description of the WAKEUP pin updated for clarity. See Section6.2. • Parts added: LPC1114JHI33/303, LPC1111JHN33/103, LPC1112JHN33/203, LPC1113JHN33/203, LPC1114JHN33/303, LPC1114JBD48/333, LPC1112FHI33/102, LPC1114JBD48/303, LPC1114JBD48/323, LPC1113JBD48/303, LPC1113JHN33/303, LPC1112JHN33/103, LPC1111JHN33/203, LPC1114JHN33/203. LPC111X v.9.1 20131213 Product data sheet - LPC111X v.9 Modifications: • Table 17 “Static characteristics (LPC1100XL series)”: – Added I max spec for Deep-sleep and Deep power-down modes @ 25 C and DD 105 C. – Added Table note 11 “105°C spec applies only to the LPC1112JHI33, LPC1114JHN33, LPC1115JBD48, and LPC1115JET48 parts.” – Updated Table note 12 “WAKEUP pin and RESET pin are pulled HIGH externally.” • Table 16 “Static characteristics (LPC1100, LPC1100L series)”: – Updated Table note 9 “WAKEUP pin and RESET pin are pulled HIGH externally.” LPC111X v.9 20131029 Product data sheet - LPC111X v.8.2 Modifications: • Added LPC1112JHI33/203, LPC1114JHN33/333, LPC1115JBD48/303, and LPC1115JET48/303 parts. • Removed t and t from Figure 47 “SPI master timing in SPI mode” and Figure clk(H) clk(L) 48 “SPI slave timing in SPI mode”; spec not characterized. • Table 22 “Power-up characteristics[1]”: Added table note “Does not apply to LPC1100XL series”. LPC111X v.8.2 20130805 Product data sheet - LPC111X v.8.1 Modifications: • Added LPC1115FET48/303. LPC111X v.8.1 20130524 Product data sheet - LPC111X v.8 Modifications: • Table4 thru Table11: Added “5 V tolerant pad” to RESET/PIO0_0 table note. • Added Section 9 “Thermal characteristics”. • SRAM size corrected for part LPC1112FHN24/202 (4 kB). See Table2. LPC111X v.8 20130220 Product data sheet - LPC111X v.7.5 Modifications: • Table 16 “Static characteristics” added Pin capacitance section. • Default pin state corrected for pins PIO0_4 and PIO0_5 (I; IA) in Table 11 “LPC1100XL series: LPC1111/12/13/14 pin description table (HVQFN33 package)”. • Table 12 “Limiting values” expanded for clarity. • Table 19 “Power consumption at very low frequencies using the watchdog oscillator” added. • Added Section 12.2 “Use of ADC input trigger signals”. • Added Section 12.8 “ADC effective input impedance”. LPC111X v.7.5 20121002 Product data sheet - LPC111X v.7.4 LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 121 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 34. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes Modifications: BOD level 0 for reset added in Table15. LPC111X v.7.4 20120730 Product data sheet - LPC111X v.7.3 Modifications: • Function SSEL1 added to pin PIO2_0 in Figure 6 “LPC1100XL series pin configuration HVQFN33” and Table 11 “LPC1100XL series: LPC1111/12/13/14 pin description table (HVQFN33 package)”. • BOD level 0 for reset and interrupt removed. LPC111X v.7.3 20120706 Product data sheet - LPC111X v.7.2 Modifications: • Corrected pinout for part LPC1112FHN24/202. Pin XTALOUT replaced by V . See DD Table6 and Figure10. LPC111X v.7.2 20120604 Product data sheet - LPC111X v.7.1 Modifications: • For parameters I , V , I , V , changed conditions to 1.8 V  V < 2.5 V and 2.5 OL OL OH OH DD V  V  3.6 V in Table13). DD • Capture-clear feature added to general-purpose counter/timers (see Section7.12; LPC1100XL series only). • Figure47 updated for parts with configurable open-drain mode. • Added Section 9.5 “CoreMark data” • Added LPC1100L series part (LPC1112FHN24/202). • WDOSc frequency range corrected. LPC111X v.7.1 20120401 Product data sheet - LPC111X v.7 Modifications: • Added HVQFN33 (5x5) reflow soldering information. LPC111X v.7 20120301 Product data sheet - LPC1110_11_12_13_14 v.6 Modifications: • LPC1100XL series parts added (LPC1111FHN33/103, LPC1111FHN33/203, LPC1112FHN33/103, LPC1112FHN33/203, LPC1112FHI33/203, LPC1113FBD48/303, LPC1113FHN33/203, LPC1113FHN33/303, LPC1114FBD48/303, LPC1114FHN33/203, LPC1114FHN33/303, LPC1114FHI33/303, LPC1114FBD48/323, LPC1114FBD48/333, LPC1114FHN33/333, LPC1115FBD48/303). LPC1110_11_12_13_14 v.6 20111102 Product data sheet - LPC1111_12_13_14 v.5 Modifications: • Parts LPC1112FHI33/202 and LPC1114FHI33/302 added. • Parts LPC1112FDH28/102, LPC1114FDH28/102, LPC1114FN28/102, LPC1112FDH20/102, LPC1110FD20, LPC1111FDH20/002, LPC1112FD20/102 added. LPC1111_12_13_14 v.5 20110622 Product data sheet - LPC1111_12_13_14 v.4 Modifications: • ADC sampling frequency corrected in Table7 (Table note7). • Pull-up level specified in Table3 to Table4 and Section7.7.1. • Parameter T corrected on Table17. cy(clk) • WWDT for parts LPC111x/102/202/302 added in Section2 and Section7.15. • Programmable open-drain mode for parts LPC111x/102/202/302 added in Section2 and Section7.12. • Condition for parameter T in Table5 updated. stg • Table note4 of Table5 updated. • Section13 added. • Removed PLCC44 package information. LPC1111_12_13_14 v.4 20110210 Product data sheet - LPC1111_12_13_14 v.3 LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 122 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 34. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes Modifications: • Power consumption graphs added for parts LPC111x/102/202/302 (Figure13 to Figure17). • Parameter V for I2C bus pins: typical value corrected V = 0.05V in Table7. hys hys DD • Typical value for parameter N added in Table 12 “Flash characteristics”. endu • I2C-bus pins configured as standard mode pins, parameter I changed to 3.5 mA OL (minimum) for 2.0 V  V  3.6 V. DD • Section 11.6 “ElectroMagnetic Compatibility (EMC)” added. • Power-up characterization added (Section 10.1 “Power-up ramp conditions”). LPC1111_12_13_14 v.3 20101110 Product data sheet - LPC1111_12_13_14 v.2 Modifications: • Parts LPC111x/102/202/302 added (LPC1100L series). • Power consumption data for parts LPC111x/102/202/302 added in Table7. • PLL output frequency limited to 100 MHz in Section7.15.2. • Description of RESET and WAKEUP functions updated in Section6. • WDT description updated in Section7.14. The WDT is a 24-bit timer. • Power profiles added to Section2 and Section7 for parts LPC111x/102/202/302. LPC1111_12_13_14 v.2 20100818 Product data sheet - LPC1111_12_13_14 v.1 Modifications: • V limit changed to 6500 V (min) /+6500 V (max) in Table6. ESD • t updated for SPI in master mode (Table17). DS • Deep-sleep mode functionality changed to allow BOD and watchdog oscillator as the only analog blocks allowed to remain running in Deep-sleep mode (Section7.15.5.3). • V range changed to 3.0 V  V  3.6 V in Table15. DD DD • Reset state of pins and start logic functionality added in Table3 to Table5. • Section7.16.1 added. • Section “Memory mapping control” removed. • V and I specifications updated for high-drive pins in Table7. OH OH • Section9.4 added. LPC1111_12_13_14 v.1 20100416 Product data sheet - - LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 123 of 127

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LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 20. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 7.16.5.1 Power profiles (LPC1100L and LPC1100XL 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 series only). . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.16.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7.16.5.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 55 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 7.16.5.4 Deep power-down mode . . . . . . . . . . . . . . . . 55 4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 6 7.17 System control. . . . . . . . . . . . . . . . . . . . . . . . 55 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.17.1 Start logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6 Pinning information. . . . . . . . . . . . . . . . . . . . . 11 7.17.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.17.3 Brownout detection . . . . . . . . . . . . . . . . . . . . 56 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 19 7.17.4 Code security (Code Read Protection - CRP) 56 7 Functional description . . . . . . . . . . . . . . . . . . 45 7.17.5 APB interface. . . . . . . . . . . . . . . . . . . . . . . . . 57 7.17.6 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.1 ARM Cortex-M0 processor. . . . . . . . . . . . . . . 45 7.17.7 External interrupt inputs. . . . . . . . . . . . . . . . . 57 7.2 On-chip flash program memory . . . . . . . . . . . 45 7.18 Emulation and debugging . . . . . . . . . . . . . . . 57 7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 45 7.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 45 8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 58 7.5 Nested Vectored Interrupt Controller (NVIC) . 47 9 Thermal characteristics . . . . . . . . . . . . . . . . . 59 7.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10 Static characteristics . . . . . . . . . . . . . . . . . . . 61 7.5.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 48 10.1 LPC1100, LPC1100L series. . . . . . . . . . . . . . 61 7.6 IOCONFIG block . . . . . . . . . . . . . . . . . . . . . . 48 10.2 LPC1100XL series. . . . . . . . . . . . . . . . . . . . . 65 7.7 Fast general purpose parallel I/O. . . . . . . . . . 48 10.3 ADC static characteristics . . . . . . . . . . . . . . . 69 7.7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.4 BOD static characteristics . . . . . . . . . . . . . . . 71 7.8 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.5 Power consumption LPC1100 series 7.8.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 (LPC111x/101/201/301). . . . . . . . . . . . . . . . . 72 7.9 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 49 10.6 Power consumption LPC1100L series 7.9.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 (LPC111x/002/102/202/302) . . . . . . . . . . . . . 75 7.10 I2C-bus serial I/O controller . . . . . . . . . . . . . . 50 10.7 Power consumption LPC1100XL series 7.10.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 (LPC111x/103/203/303/323/333). . . . . . . . . . 78 7.11 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.8 CoreMark data. . . . . . . . . . . . . . . . . . . . . . . . 82 7.11.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.9 Peripheral power consumption . . . . . . . . . . . 84 7.12 General purpose external event 10.10 Electrical pin characteristics. . . . . . . . . . . . . . 85 counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 51 11 Dynamic characteristics. . . . . . . . . . . . . . . . . 88 7.12.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.1 Power-up ramp conditions. . . . . . . . . . . . . . . 88 7.13 System tick timer . . . . . . . . . . . . . . . . . . . . . . 51 11.2 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 88 7.14 Watchdog timer (LPC1100 series, 11.3 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 89 LPC111x/101/201/301). . . . . . . . . . . . . . . . . . 51 11.4 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 90 7.14.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.5 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.15 Windowed WatchDog Timer 11.6 I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 (LPC1100L and LPC1100XL series). . . . . . . . 52 11.7 SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . . 94 7.15.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12 Application information . . . . . . . . . . . . . . . . . 97 7.16 Clocking and power control . . . . . . . . . . . . . . 52 7.16.1 Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 52 12.1 ADC usage notes. . . . . . . . . . . . . . . . . . . . . . 97 7.16.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 53 12.2 Use of ADC input trigger signals . . . . . . . . . . 97 7.16.1.2 System oscillator . . . . . . . . . . . . . . . . . . . . . . 53 12.3 XTAL input. . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.16.1.3 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 54 12.4 XTAL Printed Circuit Board (PCB) layout 7.16.2 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . 54 guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.16.3 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.5 Standard I/O pad configuration . . . . . . . . . . . 99 7.16.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . . 54 12.6 Reset pad configuration. . . . . . . . . . . . . . . . 100 7.16.5 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.7 ElectroMagnetic Compatibility (EMC) . . . . . 101 continued >> LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.2 — 26 March 2014 126 of 127

LPC1110/11/12/13/14/15 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 12.8 ADC effective input impedance . . . . . . . . . . 102 13 Package outline. . . . . . . . . . . . . . . . . . . . . . . 103 14 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 15 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . 120 16 References. . . . . . . . . . . . . . . . . . . . . . . . . . . 120 17 Revision history. . . . . . . . . . . . . . . . . . . . . . . 121 18 Legal information. . . . . . . . . . . . . . . . . . . . . . 124 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 124 18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 124 18.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . 124 18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 125 19 Contact information. . . . . . . . . . . . . . . . . . . . 125 20 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 26 March 2014 Document identifier: LPC111X

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: N XP: LPC1111FHN33/101,5 LPC1111FHN33/201,5 LPC1112FHN33/101,5 LPC1112FHN33/201,5 LPC1113FBD48/301,1 LPC1113FHN33/201,5 LPC1113FHN33/301,5 LPC1114FBD48/301,1 LPC1114FHN33/201,5 LPC1114FHN33/301,5 LPC1114FHN33/301:5 LPC1113FBD48/303,1 LPC1114FBD48/303,1 LPC1112FHI33/202,5 LPC1110FD20,529 LPC1112FD20/102,52 LPC1114FN28/102,12 LPC1112FHN24/2021 LPC1111FDH20/002,5 LPC1112FDH20/102:5 LPC1112FDH28/102:5 LPC1112FHI33/2025 LPC1112FHN33/202:5 LPC1112LVFHI33/103 LPC1112LVFHN24/003 LPC1114FDH28/102:5 LPC1114LVFHI33/303 LPC1114LVFHN24/103 LPC1114LVFHN24/303 LPC1111FHN33/102,5 LPC1111FHN33/202,5 LPC1112FHN33/102,5 LPC1112FHN33/202,5 LPC1113FBD48/302,1 LPC1113FHN33/202,5 LPC1113FHN33/302,5 LPC1114FA44/302,52 LPC1114FBD48/302,1 LPC1114FHN33/202,5 LPC1114FHN33/302,5 LPC1114FHN33/302:5 LPC1111FHN33/102'5 LPC1114FBD48/301:1 LPC1111FHN33/103,5 LPC1111FHN33/203,5 LPC1112FHI33/203,5 LPC1112FHN33/103,5 LPC1112FHN33/203,5 LPC1113FHN33/203,5 LPC1113FHN33/303,5 LPC1114FBD48/323,1 LPC1114FBD48/333,1 LPC1114FHI33/303,5 LPC1114FHN33/203,5 LPC1114FHN33/303,5 LPC1114FHN33/333,5 LPC1115FBD48/303,1 LPC1114FHI33/302,5 LPC1114JBD48/333QL LPC1113JBD48/303QL LPC1112JHI33/203E LPC1114JHI33/303E LPC1112JHN33/203E LPC1111JHN33/103E LPC1115JET48/303 LPC1113JHN33/203E LPC1115JBD48/303 LPC1114JHN33/303E LPC1112FHN24/202,1 LPC1112FHI33/102,5 LPC1113FHN33/302:5 LPC1113FHN33/302K LPC1113FHN33/202:5 LPC1114JHN33/333E LPC1115FET48/303QL LPC1114JHN33/203E LPC1115JBD48/303QL LPC1115JET48/303QL LPC1114FBD48/303J LPC1114JBD48/323QL LPC1114JBD48/303QL LPC1111JHN33/203E LPC1112JHN33/103E LPC1113JHN33/303E LPC1114FBD48/323J LPC1112FHN24/202J LPC1115FET48/303Y LPC1114FHN33/303Y