Product Sample & Technical Tools & Support & Folder Buy Documents Software Community LP3961,LP3964 SNVS056J–MAY2000–REVISEDJUNE2015 LP396x 800-mA Fast Ultra-Low-Dropout Linear Regulators 1 Features 3 Description • InputSupplyVoltage:2.5Vto7V The LP396x series of fast ultra-low-dropout linear 1 regulators operate from a 2.5-V to 7-V input supply. A • Ultra-LowDropoutVoltage wide range of preset output voltage options are • LowGroundPinCurrent available. These ultra-low dropout linear regulators • LoadRegulationof0.02% respond very fast to step changes in load which makes them suitable for low-voltage microprocessor • 15-µAQuiescentCurrentinShutdownMode applications. The LP3961 and LP3964 are developed • SpecifiedOutputCurrentof0.8-ADC on a CMOS process which allows low quiescent • OutputVoltageAccuracy ±1.5% current operation independent of output load current, as well as operation under extremely low dropout • ERROR FlagIndicatesOutputStatus(LP3961) conditions. • SenseOptionImprovesBetterLoadRegulation (LP3964) Dropout Voltage: Ultra-low dropout voltage; typically 24 mV at 80-mA load current and 240 mV at 800-mA • ExtremelyLowOutputCapacitorRequirements loadcurrent. • OvertemperatureandOvercurrentProtection Ground Pin Current: Typically 4 mA at 800-mA load • −40°Cto125°CJunctionTemperatureRange current. 2 Applications ERROR Flag: ERROR flag goes low when the output voltagedrops10%belownominalvalue(forLP3961). • MicroprocessorPowerSupplies SENSE: SENSE pin improves regulation at remote • GTL,GTL+,BTL,andSSTLBusTerminators loads(forLP3964). • PowerSuppliesforDSPs Precision Output Voltage: Multiple output voltage • SCSITerminator options are available ranging from 1.2 V to 5 V and • PostRegulators adjustable (LP3964), with a specified accuracy of • High-EfficiencyLinearRegulators ±1.5% at room temperature, and ±3% over all • BatteryChargers conditions(varyingline,load,andtemperature). • OtherBattery-PoweredApplications DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) LP3961 SOT-223(5) 6.50mm×3.56mm LP3964 TO-263(5) 10.16mm×8.42mm LP3964 TO-220(5) 14.986mm×10.16mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. space LP3964TypicalApplicationCircuits LP3961TypicalApplicationCircuit A. *SD and ERROR pins must be pulled high through a 10-kΩ pullup resistor. Connect theERRORpintogroundifthisfunctionis notused. *SeenoteAonLP3961TypicalApplication Circuit. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

LP3961,LP3964 SNVS056J–MAY2000–REVISEDJUNE2015 www.ti.com Table of Contents 1 Features.................................................................. 1 7.4 DeviceFunctionalModes........................................13 2 Applications........................................................... 1 8 ApplicationandImplementation........................ 14 3 Description............................................................. 1 8.1 ApplicationInformation ..........................................14 4 RevisionHistory..................................................... 2 8.2 TypicalApplications................................................14 5 PinConfigurationsandFunctions....................... 3 9 PowerSupplyRecommendations...................... 19 6 Specifications......................................................... 4 10 Layout................................................................... 19 6.1 AbsoluteMaximumRatings......................................4 10.1 LayoutGuidelines.................................................19 6.2 ESDRatings..............................................................4 10.2 LayoutExample....................................................19 6.3 RecommendedOperatingConditions.......................4 10.3 HeatsinkingTO-220Packages.............................20 6.4 ThermalInformation..................................................4 11 DeviceandDocumentationSupport................. 21 6.5 ElectricalCharacteristics...........................................5 11.1 RelatedLinks........................................................21 6.6 TypicalCharacteristics .............................................7 11.2 CommunityResources..........................................21 7 DetailedDescription............................................ 10 11.3 Trademarks...........................................................21 7.1 Overview.................................................................10 11.4 ElectrostaticDischargeCaution............................21 7.2 FunctionalBlockDiagram.......................................10 11.5 Glossary................................................................21 7.3 FeatureDescription.................................................11 12 Mechanical,Packaging,andOrderable Information........................................................... 21 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionI(December2014)toRevisionJ Page • ChangedpinnamestoconformtoTInomenclature(V toOUT,V toIN)....................................................................... 1 OUT IN • Changed"I"to"O"tocorrectI/OtypeforERRORflag ......................................................................................................... 3 • DeletedLeadtemperaturerow-infoinPOA ........................................................................................................................ 4 • DeletedheatsinkingsectionsreTO-263andSOT-223packages;notconsistentwithupdatedthermalmetrics ..............20 ChangesfromRevisionH(April2013)toRevisionI Page • AddedPinConfigurationandFunctionssection,HandlingRatingtable,FeatureDescriptionsection,Device FunctionalModes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layout section,DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderableInformation section ................................................................................................................................................................................... 1 ChangesfromRevisionG(April2013)toRevisionH Page 2 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 www.ti.com SNVS056J–MAY2000–REVISEDJUNE2015 5 Pin Configurations and Functions 5-PinNDC 5-PinNDH 5-PinKTT SOT-223Package TO-220Package(LP3964) SFM/TO-263Package TopView TopView TopView PinFunctions PIN NO. LP3964 I/O DESCRIPTION NAME LP3961 TO-220 SOT-223 SFM/TO-263 ERROR 4 — — O ERRORflag GND 5 5 3 — Ground IN 2 2 2 I Inputsupply OUT 3 3 4 O Outputvoltage SD 1 1 1 I Shutdown SENSE/AD — 4 5 I Remotesensepinoroutputadjustpin J Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 SNVS056J–MAY2000–REVISEDJUNE2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings(1)(2) MIN MAX UNIT Powerdissipation(3) InternallyLimited InputSupplyVoltage(Survival) −0.3 7.5 V ShutdownInputVoltage(Survival) −0.3 V +0.3 V IN OutputVoltage(Survival)(4), (5) −0.3 7.5 V I (Survival) Short-CircuitProtected OUT MaximumVoltageforERRORpin V +0.3 V IN MaximumVoltageforSENSEpin V +0.3 V OUT Storagetemperature,T –65 150 °C stg (1) Absolutemaximumratingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.RecommendedOperatingConditionsindicate conditionsforwhichthedeviceisintendedtobefunctional,butdoesnotensurespecificperformancelimits.Forensuredspecifications andtestconditions,seeElectricalCharacteristics.Theensuredspecificationsapplyonlyforthetestconditionslisted.Some performancecharacteristicsmaydegradewhenthedeviceisnotoperatedunderthelistedtestconditions. (2) IfMilitary-orAerospace-specifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityandspecifications. (3) Themaximumallowablepowerdissipationisafunctionofthemaximumjunctiontemperature,T ,thejunction-to-ambientthermal J(MAX) resistance,R ,andtheambienttemperature,T .Themaximumallowablepowerdissipationatanyambienttemperatureiscalculated θJA A using:P =(T –T )/R . (MAX) J(MAX) A θJA (4) Ifusedinadual-supplysystemwheretheregulatorloadisreturnedtoanegativesupply,theLP396Xoutputmustbediode-clampedto ground. (5) TheoutputPMOSstructurecontainsadiodebetweentheINandOUTpins.Thisdiodeisnormallyreversebiased.Thisdiodewillget forwardbiasedifthevoltageattheOUTpinisforcedtobehigherthanthevoltageattheINpin.Thisdiodecantypicallywithstand200 mAofDCcurrentand1Aofpeakcurrent. 6.2 ESD Ratings VALUE UNIT V Electrostaticdischarge Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V (ESD) (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.. 6.3 Recommended Operating Conditions MIN MAX UNIT Inputsupplyvoltage(operating)(1) 2.5 7 V Shutdowninputvoltage(operating) −0.3 V +0.3 V IN Maximumoperatingcurrent(DC) 0.8 A Operatingjunctiontemperature −40 125 °C (1) TheminimumoperatingvalueforV isequaltoeither[V +V ]or2.5V,whicheverisgreater. IN OUT(NOM) DROPOUT 6.4 Thermal Information LP3961,LP3964 LP3964 THERMALMETRIC(1) NDC KTT NDH UNIT 5PINS R Junction-to-ambientthermalresistance 65.2 40.3 32.1 θJA R Junction-to-case(top)thermalresistance 47.2 43.4 43.8 θJC(top) R Junction-to-boardthermalresistance 9.9 23.1 18.7 θJB °C/W ψ Junction-to-topcharacterizationparameter 3.4 11.5 8.8 JT ψ Junction-to-boardcharacterizationparameter 9.7 22.1 18.0 JB R Junction-to-case(bottom)thermalresistance N/A 1.0 1.3 θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 4 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 www.ti.com SNVS056J–MAY2000–REVISEDJUNE2015 6.5 Electrical Characteristics Unlessotherwisespecified:T =25°C,V =V +1V,I =10mA,C =33µF,V =V –0.3V. J IN O(NOM) L OUT SD IN PARAMETER TESTCONDITIONS MIN(1) TYP(2) MAX(1) UNIT V Outputvoltagetolerance(3) 10mA≤I ≤800mA, O L –1.5% 0% 1.5% V +1≤V ≤7V OUT IN 10mA≤I ≤800mA, L V +1≤V ≤7V, –3% 3% OUT IN –40°C≤T ≤125°C J V Adjustpinvoltage(ADJversion) 10mA≤I ≤800mA, ADJ L 1.198 1.216 1.234 V +1.5V≤V ≤7V OUT IN 10mA≤I ≤800mA, V L V +1.5V≤V ≤7V, 1.180 1.253 OUT IN –40°C≤T ≤125°C J ΔV Outputvoltagelineregulation(3) V +1V<V <7V 0.02% OL OUT IN V +1V<V <7V, 0.06% OUT IN –40°C≤T ≤125°C J ΔV / Outputvoltageloadregulation(3) 10mA<I <800mA 0.02% O L ΔI OUT 10mA<I <800mA, 0.08% L –40°C≤T ≤125°C J V –V Dropoutvoltage(4) I =80mA 24 30 IN OUT L I =80mA,–40°C≤T ≤125°C 35 L J mV I =800mA 240 300 L I =800mA,–40°C≤T ≤125°C 350 L J I Groundpincurrentinnormal I =80mA 3 9 GND L operationmode I =80mA,–40°C≤T ≤125°C 10 L J mA I =800mA 4 14 L I =800mA,–40°C≤T ≤125°C 15 L J I Groundpincurrentinshutdown V ≤0.2V 15 25 µA GND SD mode(5) V ≤0.2V,–40°C≤T ≤125°C 75 SD J I Peakoutputcurrent See(6) 1.2 1.5 A O(PK) See(6),–40°C≤T ≤125°C 1.1 J SHORT-CIRCUITPROTECTION I Short-circuitcurrent 2.8 A SC OVERTEMPERATUREPROTECTION Tsh(t) Shutdownthreshold 165 °C Tsh(h) Thermalshutdownhysteresis 10 °C SHUTDOWNINPUT Output=High V IN Output=High,–40°C≤T ≤ V –0.3 J IN V Shutdownthreshold 125°C V SDT Output=Low 0 Output=Low,–40°C≤T ≤125°C 0.2 J (1) Limitsare100%productiontestedat25°C.Limitsovertheoperatingtemperaturerangearespecifiedthroughcorrelationusing StatisticalQualityControl(SQC)methods.ThelimitsareusedtocalculateTI'sAverageOutgoingQualityLevel(AOQL). (2) Typicalnumbersareat25°Candrepresentthemostlikelyparametricnorm. (3) Outputvoltagelineregulationisdefinedasthechangeinoutputvoltagefromthenominalvalueduetochangeintheinputlinevoltage. Outputvoltageloadregulationisdefinedasthechangeinoutputvoltagefromthenominalvalueduetochangeinloadcurrent.Theline andloadregulationspecificationcontainsonlythetypicalnumber.However,thelimitsforlineandloadregulationareincludedinthe outputvoltagetolerancespecification. (4) Dropoutvoltageisdefinedastheminimuminput-to-outputdifferentialvoltageatwhichtheoutputdrops2%belowthenominalvalue. Dropoutvoltagespecificationappliesonlytooutputvoltagesof2.5Vandabove.Foroutputvoltagesbelow2.5V,thedrop-outvoltage isnothingbuttheinput-to-outputdifferentialvoltagebecausetheminimuminputvoltageis2.5V. (5) Thisspecificationhasbeentestedfor–40°C≤T ≤85°Cbecausethetemperatureriseofthedeviceisnegligibleundershutdown J conditions. (6) Themaximumallowablepowerdissipationisafunctionofthemaximumjunctiontemperature,T ,thejunction-to-ambientthermal J(MAX) resistance,R ,andtheambienttemperature,T .Themaximumallowablepowerdissipationatanyambienttemperatureiscalculated θJA A using:P =(T –T )/R . (MAX) J(MAX) A θJA Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 SNVS056J–MAY2000–REVISEDJUNE2015 www.ti.com Electrical Characteristics (continued) Unlessotherwisespecified:T =25°C,V =V +1V,I =10mA,C =33µF,V =V –0.3V. J IN O(NOM) L OUT SD IN PARAMETER TESTCONDITIONS MIN(1) TYP(2) MAX(1) UNIT T Turnoffdelay I =800mA 20 µs dOFF L T Turnondelay I =800mA 25 µs dON L I SDinputcurrent V =V 1 nA SD SD IN ERRORFLAGCOMPARATOR V Threshold See(7) 10% T See(7),–40°C≤T ≤125°C 5% 16% J V Thresholdhysteresis See(7) 5% TH See(7),–40°C≤T ≤125°C 2% 8% J V ERRORflagsaturation I =100µA 0.02 V EF(Sat) sink I =100µA 0.1 sink T Flagresetdelay 1 µs d I ERRORflagpinleakagecurrent 1 nA lk I ERRORflagpinsinkcurrent V =0.5V(overtemperature) 1 mA max ERROR ACPARAMETERS V =V +1.5V, 60 IN OUT C =100µF, OUT V =3.3V OUT PSRR Ripplerejection dB V =V +0.3V, 40 IN OUT C =100µF, OUT V =3.3V OUT ρ Outputnoisedensity f=120Hz 0.8 µV n(l/f) BW=10Hzto100kHz 150 e Outputnoisevoltage(rms) µV n RMS BW=300Hzto300kHz 100 (7) ERRORflagthresholdandhysteresisarespecifiedaspercentageofregulatedoutputvoltage. 6 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 www.ti.com SNVS056J–MAY2000–REVISEDJUNE2015 6.6 Typical Characteristics Unlessotherwisespecified,V =V +1V,V =2.5V,C =33µF,I =10mA,C =68µF,V =V ,and IN O(NOM) OUT OUT OUT IN SDT IN T =25°C. A Figure1.Drop-OutVoltagevsTemperatureforDifferent Figure2.Drop-OutVoltagevsTemperatureforDifferent LoadCurrents OutputVoltages(I =800mA) OUT Figure3.GroundPinCurrentvsInputVoltage(V =V ) Figure4.GroundPinCurrentvsInputVoltage(V =100 SD IN SD mV) Figure5.GroundCurrentvsTemperature(V =V ) Figure6.GroundCurrentvsTemperature(V =0V) SD IN SD Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 SNVS056J–MAY2000–REVISEDJUNE2015 www.ti.com Typical Characteristics (continued) Unlessotherwisespecified,V =V +1V,V =2.5V,C =33µF,I =10mA,C =68µF,V =V ,and IN O(NOM) OUT OUT OUT IN SDT IN T =25°C. A Figure7.GroundPinCurrentvsShutdownPinVoltage Figure8.InputVoltagevsOutputVoltage Figure9.OutputNoiseDensity,V =2.5V Figure10.OutputNoiseDensity,V =5V OUT OUT Figure11.LoadTransientResponse Figure12.RippleRejectionvsFrequency 8 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 www.ti.com SNVS056J–MAY2000–REVISEDJUNE2015 Typical Characteristics (continued) Unlessotherwisespecified,V =V +1V,V =2.5V,C =33µF,I =10mA,C =68µF,V =V ,and IN O(NOM) OUT OUT OUT IN SDT IN T =25°C. A Figure13.δV vsTemperature OUT Figure14.NoiseDensityV =3.5V,V =2.5V,I =10mA IN OUT L Figure15.LineTransientResponse Figure16.LineTransientResponse Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 SNVS056J–MAY2000–REVISEDJUNE2015 www.ti.com 7 Detailed Description 7.1 Overview The LP3961/LP3964 are a series of ultra-low dropout linear regulators. Fixed output products have output voltage options from 1.2 V to 5 V, adjustable output voltage is only available for LP3964. These regulators can providemaximum800-mAloadcurrent.Thedevicecanoperateunderextremelylowdropoutconditions. The LP3961 has an ERROR flag pin, this pin will go low when the output voltage drops 10% below nominal value. The LP3964 (fixed output products) provides a SENSE pin. The SENSE pin can improve regulation at remote loads. The LP3961, LP3964 also provide short-circuit protection and reverse current path. The devices canbeoperatedwithshutdown(SD)pincontrol. 7.2 Functional Block Diagram Figure17. LP3961BlockDiagram Figure18. LP3964BlockDiagram 10 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 www.ti.com SNVS056J–MAY2000–REVISEDJUNE2015 Functional Block Diagram (continued) Figure19. LP3964AdjustableVersionBlockDiagram 7.3 Feature Description 7.3.1 Short-CircuitProtection The LP3961 and LP3964 are short-circuit protected and in the event of a peak overcurrent condition, the short- circuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to the section onthermalinformationforpowerdissipationcalculations. 7.3.2 ERROR FlagOperation The LP3961 produces a logic low signal at the ERROR flag pin when the output drops out of regulation due to low input voltage, current limiting, or thermal limiting. This flag has a built-in hysteresis. The timing diagram in Figure 20 shows the relationship between the ERROR pin and the output voltage. In this example, the input voltageischangedtodemonstratethefunctionalityofthe ERROR flag. The internal ERROR flag comparator has an open drain output stage. Hence, the ERROR pin should be pulled high through a pull-up resistor. Although the ERROR pin can sink current of 1 mA, this current is an energy drain from the input supply. Hence, the value of the pull-up resistor should be in the range of 100 kΩ to 1 MΩ. The ERROR pin must be connected to ground if this function is not used. It should also be noted that when the SD pinispulledlow,theERROR pinisforcedtobeinvalidforreasonsofsavingpowerinshutdownmode. Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 SNVS056J–MAY2000–REVISEDJUNE2015 www.ti.com Feature Description (continued) Figure20. ERROR FlagOperation 7.3.3 SENSEPin In applications where the regulator output is not very close to the load, LP3964 can provide better remote load regulation using the SENSE pin. Figure 21 depicts the advantage of the SENSE option. LP3961 regulates the voltage at the OUT pin. Hence, the voltage at the remote load will be the regulator output voltage minus the drop across the trace resistance. For example, in the case of a 3.3-V output, if the trace resistance is 100 mΩ, the voltage at the remote load will be 3.22 V with 800 mA of load current, I . The LP3964 regulates the voltage at LOAD the SENSE pin. Connecting the SENSE pin to the remote load will provide regulation at the remote load, as showninFigure21.Ifthesenseoptionpinisnotrequired,theSENSEpinmustbeconnectedtotheOUTpin. Figure21. ImprovingRemoteLoadRegulationUsingLP3964 12 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 www.ti.com SNVS056J–MAY2000–REVISEDJUNE2015 Feature Description (continued) 7.3.4 DropoutVoltage The dropout voltage of a regulator is defined as the minimum input-to-output differential required to stay within 2% of the output voltage. The LP3961 and LP3964 use an internal MOSFET with an Rds(on) of 240 mΩ (typically).ForCMOSLDOs,thedropoutvoltageistheproductoftheloadcurrentandtheRds(on)oftheinternal MOSFET. 7.3.5 ReverseCurrentPath The internal MOSFET in LP3961 and LP3964 has an inherent parasitic diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is pulledabovetheinputinanapplication,thencurrentflowsfromtheoutputtotheinputastheparasiticdiodegets forwardbiased.Theoutputcanbepulledabovetheinputaslongasthecurrentintheparasiticdiodeislimitedto 200-mAcontinuousand1-Apeak. 7.4 Device Functional Modes 7.4.1 OperationWithV +0.35V≤ V ≤ 7V OUT(TARGET) IN For the fixed output voltage products, the devices operate if the input voltage is equal to or exceeds V (TARGET) + 0.35 V. At input voltages below the minimum V requirement, the devices do not operate OUT IN correctlyandoutputvoltagemaynotreachtargetvalue. 7.4.2 OperationWithShutdown(SD)PinControl A CMOS logic low level signal at the shutdown (SD) pin will turn off the regulator. The SD pin must be actively terminatedthrougha10-kΩ pullupresistorforaproperoperation.ThispinmustbetiedtotheINpinifnotused. Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 SNVS056J–MAY2000–REVISEDJUNE2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The LP3961, LP3964 products can provide 800-mA output current with 2.5-V to 7-V input voltage. An input capacitor of at least 68-uF is required. A minimum 33-uF output capacitor is required for loop stability. Pin SD must be tied to input if not used. For LP3961, the ERROR pin should be pulled high through a pull up resistor; if this function is not used, ERROR pin must be connected to ground . For LP3964, if the sense option is not required,theSENSEpinmustbeconnectedtotheOUTpin. 8.2 Typical Applications Figure22. LP3961TypicalApplicationCircuit Figure23. LP3964TypicalApplicationCircuits 14 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 www.ti.com SNVS056J–MAY2000–REVISEDJUNE2015 Typical Applications (continued) 8.2.1 DesignRequirements DESIGNPARAMETERS VALUE Inputvoltage 5.3V,±10% Outputvoltage 3.3V,±3% Outputcurrent 800mA(maximum) Inputcapacitor 68uF(minimum) Outputcapacitor 33uF(minimum) ERRORpullupresistor(LP3964only) 10kΩ 8.2.2 DetailedDesignProcedure 8.2.2.1 ExternalCapacitors Like any low-dropout regulator, external capacitors are required to assure stability. these capacitors must be correctlyselectedforproperperformance. 8.2.2.1.1 InputCapacitor The LP3961 or LP3964 requires a low source impedance to maintain regulator stability because the internal bias circuitry is connected directly to the IN pin. The input capacitor must be located less than 1 cm from the LP3961 or LP3964 device and connected directly to the IN and GND pins using traces which have no other currents flowingthroughthem(seetheLayoutGuidelinessection). The minimum allowable input capacitance for a given application depends on the type of the capacitor and equivalent series resistance (ESR). A lower ESR capacitor allows the use of less capacitance, while higher ESR types(likealuminumelectrolytics)requiremorecapacitance. The lowest value of input capacitance that can be used for stable full-load operation is 68 µF (assuming it is a ceramicorlow-ESRTantalumwithESRlessthan100mΩ). TodeterminetheminimuminputcapacitanceamountandESRvalue,anapproximationisused: C ESR(mΩ)/C (µF)≤1.5 (1) IN IN This shows that input capacitors with higher ESR values can be used if sufficient total capacitance is provided. Capacitor types (aluminum, ceramic, and tantalum) can be mixed in parallel, but the total equivalent input capacitance/ESRmustbedefinedasabovetoassurestableoperation. IMPORTANT: The input capacitor must maintain its ESR and capacitance in the stable range over the entire temperaturerangeoftheapplicationtoassurestability(seetheCapacitorCharacteristics section). 8.2.2.1.2 OutputCapacitor An output capacitor is also required for loop stability. It must be located less than 1 cm from the LP3961 or LP3964 device and connected directly to the OUT and GND pins using traces which have no other currents flowingthroughthem(seetheLayoutGuidelinessection). The minimum value of the output capacitance that can be used for stable full-load operation is 33 µF, but it may be increased without limit. The ESR of the output capacitor is critical because it forms a zero to provide phase leadwhichisrequiredforloopstability.TheESRmustfallwithinthespecifiedrange: 0.2Ω≤C ESR≤5Ω (2) OUT The lower limit of 200 mΩ means that ceramic capacitors are not suitable for use as LP3961 or LP3964 output capacitors (but can be used on the input). Some ceramic capacitance can be used on the output if the total equivalent ESR is in the stable range: when using a 100-µF Tantalum as the output capacitor, approximately 3 µFofceramiccapacitancecanbeappliedbeforestabilitybecomesmarginal. IMPORTANT: The output capacitor must meet the requirements for minimum amount of capacitance and also have an appropriate ESR value over the full temperature range of the application to assure stability (see the CapacitorCharacteristics section). Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 SNVS056J–MAY2000–REVISEDJUNE2015 www.ti.com 8.2.2.2 SelectingaCapacitor It is important to note that capacitance tolerance and variation with temperature must be taken into consideration when selecting a capacitor so that the minimum required amount of capacitance is provided over the full operating temperature range. In general, a good Tantalum capacitor will show very little capacitance variation with temperature, but a ceramic may not be as good (depending on dielectric type). Aluminum electrolytics also typicallyhavelargetemperaturevariationofcapacitancevalue. Equally important to consider is a capacitor's ESR change with temperature: this is not an issue with ceramics, as their ESR is extremely low. However, it is very important in Tantalum and aluminum electrolytic capacitors. Both show increasing ESR at colder temperatures, but the increase in aluminum electrolytic capacitors is so severetheymaynotbefeasibleforsomeapplications(seetheCapacitorCharacteristics section). 8.2.2.3 CapacitorCharacteristics 8.2.2.3.1 Ceramic For values of capacitance in the 10- to 100-µF range, ceramics are usually larger and more costly than Tantalums but give superior AC performance for bypassing high-frequency noise because of very low ESR (typically less than 10 mΩ). However, some dielectric types do not have good capacitance characteristics as a functionofvoltageandtemperature. Z5U and Y5V dielectric ceramics have capacitance that drops severely with applied voltage. A typical Z5U or Y5Vcapacitorcanlose60%ofitsratedcapacitancewithhalfoftheratedvoltageappliedtoit.TheZ5UandY5V also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of thetemperaturerange. X7R and X5R dielectric ceramic capacitors are strongly recommended if ceramics are used, as they typically maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of course,theyaretypicallylargerandmorecostlythanZ5U/Y5Utypesforagivenvoltageandcapacitance. 8.2.2.3.2 Tantalum Solid Tantalum capacitors are recommended for use on the output because their typical ESR is very close to the ideal value required for loop compensation. They also work well as input capacitors if selected to meet the ESR requirementspreviouslylisted. Tantalums also have good temperature stability: a good quality Tantalum will typically show a capacitance value thatvarieslessthan10to15%acrossthefulltemperaturerangeof125°Cto −40°C.ESRwillvaryonlyabout2X goingfromthehightolowtemperaturelimits. The increasing ESR at lower temperatures can cause oscillations when marginal quality capacitors are used (if theESRofthecapacitorisneartheupperlimitofthestabilityrangeatroomtemperature). 8.2.2.3.3 Aluminum This capacitor type offers the most capacitance for the money. The disadvantages are that they are larger in physical size, not widely available in surface mount, and have poor AC performance (especially at higher frequencies)duetohigherESRandESL. Compared by size, the ESR of an aluminum electrolytic is higher than either Tantalum or ceramic, and it also varies greatly with temperature. A typical aluminum electrolytic can exhibit an ESR increase of as much as 50X whengoingfrom25°Cdownto −40°C. It should also be noted that many aluminum electrolytics only specify impedance at a frequency of 120 Hz, which indicates they have poor high-frequency performance. Only aluminum electrolytics that have an impedance specified at a higher frequency (from 20 kHz to 100 kHz) should be used for the LP396X. Derating must be appliedtothemanufacturer'sESRspecification,becauseitistypicallyonlyvalidatroomtemperature. Any applications using aluminum electrolytics should be thoroughly tested at the lowest ambient operating temperaturewhereESRismaximum. 16 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 www.ti.com SNVS056J–MAY2000–REVISEDJUNE2015 8.2.2.4 RFIandEMISusceptibility Radio frequency interference (RFI) and electromagnetic interference (EMI) can degrade the performance of any integrated circuit because of the small dimensions of the geometries inside the device. In applications where circuitsourcesarepresentwhichgeneratesignalswithsignificanthigh-frequencyenergycontent(>1MHz),care mustbetakentoensurethatthisdoesnotaffecttheICregulator. If RFI and EMI noise is present on the input side of the LP396x regulator (such as applications where the input source comes from the output of a switching regulator), good ceramic bypass capacitors must be used at the inputpinoftheLP396x. If a load is connected to the LP396x output which switches at high speed (such as a clock), the high-frequency current pulses required by the load must be supplied by the capacitors on the LP396x output. Because the bandwidth of the regulator loop is less than 100 kHz, the control circuitry cannot respond to load changes above that frequency. The means the effective output impedance of the LP396x at frequencies above 100 kHz is determinedonlybytheoutputcapacitors. In applications where the load is switching at high speed, the output of the LP396x may need RF isolation from the load. It is recommended that some inductance be placed between the LP396x output capacitor and the load, andgoodRFbypasscapacitorsbeplaceddirectlyacrosstheload. PCB layout is also critical in high-noise environments, because RFI and EMI is easily radiated directly into PC traces. Noisy circuitry should be isolated from clean circuits where possible, and grounded through a separate path. At MHz frequencies, ground planes begin to look inductive and RFI/EMI can cause ground bounce across thegroundplane. In multilayer PCB applications, care should be taken in layout so that noisy power and ground planes do not radiatedirectlyintoadjacentlayerswhichcarryanalogpowerandground. 8.2.2.5 OutputAdjustment An adjustable output device has output voltage range of 1.216 V to 5.1 V. To obtain a desired output voltage, the followingequationcanbeusedwithR1alwaysa10-kΩresistor. (3) Foroutputstability,C mustbebetween68pFand100pF. F 8.2.2.6 TurnonCharacteristicsforOutputVoltagesProgrammedto2.0VorBelow As V increases during start-up, the regulator output will track the input until V reaches the minimum operating IN IN voltage (typically about 2.2 V). For output voltages programmed to 2 V or below, the regulator output may momentarily exceed its programmed output voltage during start up. Outputs programmed to voltages above 2 V arenotaffectedbythisbehavior. 8.2.2.7 OutputNoise Noiseisspecifiedintwoways: • Spot noise or output noise density is the RMS sum of all noise sources, measured at the regulator output, at a specific frequency (measured with a 1-Hz bandwidth). This type of noise is usually plotted on a curve as a functionoffrequency. • Total output noise or broadband noise is the RMS sum of spot noise over a specified bandwidth, usually severaldecadesoffrequencies. Attention should be paid to the units of measurement. Spot noise is measured in units µV/√Hz or nV/√Hz and totaloutputnoiseismeasuredinµV . (rms) The primary source of noise in low-dropout regulators is the internal reference. In CMOS regulators, noise has a low-frequency component and a high-frequency component, which depend strongly on the silicon area and quiescent current. Noise can be reduced in two ways: by increasing the transistor area or by increasing the current drawn by the internal reference. Increasing the area will decrease the chance of fitting the die into a smaller package. Increasing the current drawn by the internal reference increases the total supply current (ground pin current). Using an optimized trade-off of ground pin current and die size, LP396x achieves low noise performanceandlowquiescentcurrentoperation. Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 SNVS056J–MAY2000–REVISEDJUNE2015 www.ti.com The total output noise specification for LP396x is presented in the Electrical Characteristics table. The output noisedensityatdifferentfrequenciesisrepresentedbyacurveundertypicalperformancecharacteristics. 8.2.2.8 ShutdownOperation A CMOS logic level signal at the shutdown (SD) pin will turnoff the regulator. Pin SD must be actively terminated through a 10-kΩ pullup resistor for a proper operation. If this pin is driven from a source that actively pulls high and low (such as a CMOS rail-to-rail comparator), the pull-up resistor is not required. This pin must be tied to the INpinifnotused. 8.2.2.9 MaximumOutputCurrentCapability LP3961 and LP3964 can deliver a continuous current of 800 mA over the full operating temperature range. A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction temperature must be within the range specified under operatingconditions.Thetotalpowerdissipationofthedeviceisgivenby: P =(V −V )×I +V ×I (4) D IN OUT OUT IN GND whereI istheoperatinggroundcurrentofthedevice(specifiedundertheElectricalCharacteristicstable). GND The maximum allowable temperature rise (T ) depends on the maximum ambient temperature (T ) of the Rmax Amax application,andthemaximumallowablejunctiontemperature(T ): Jmax T =T −T (5) Rmax Jmax Amax The maximum allowable value for junction to ambient Thermal Resistance, R , can be calculated using the θJA formula: R =T /P (6) θJA Rmax D LP3961 and LP3964 are available in TO-220, SFM/TO-263, and SOT-223 packages. The thermal resistance dependsonamountofcopperareaorheatsink,andonairflow. 8.2.3 ApplicationCurves Figure24.LineTransientResponse(I =800mA) Figure25.LineTransientResponse(I =800mA) OUT OUT 18 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 www.ti.com SNVS056J–MAY2000–REVISEDJUNE2015 9 Power Supply Recommendations The LP396x devices are designed to operate from an input voltage supply range between 2.5 V and 7 V. The input voltage range provides adequate headroom in order for the device to have a regulated output. This input supplymustbewellregulated.Aninputcapacitorofatleast68 μFisrequired. 10 Layout 10.1 Layout Guidelines GoodPClayoutpracticesmustbeusedorinstabilitycanbeinducedbecauseofgroundloopsandvoltagedrops. The input and output capacitors must be directly connected to the IN, OUT, and GND pins of the LP396x using traceswhichdonothaveothercurrentsflowinginthem(Kelvinconnect). The best way to do this is to lay out C and C near the device with short traces to the IN, OUT, and GND IN OUT pins. The regulator ground pin should be connected to the external circuit ground so that the regulator and its capacitorshaveasingle-pointground. It should be noted that stability problems have been seen in applications where vias to an internal ground plane were used at the ground points of the LP396x IC and the input and output capacitors. This was caused by varying ground potentials at these nodes resulting from current flowing through the ground plane. Using a single- pointgroundtechniquefortheregulatoranditscapacitorsfixedtheproblem. BecausehighcurrentflowsthroughthetracesgoingintotheINpinandcomingfromtheOUTpin,Kelvinconnect thecapacitorleadstothesepinssothereisnovoltagedropinserieswiththeinputandoutputcapacitors. 10.2 Layout Example SD ERROR Pullup Pullup Resistor Resistor IN OUT Input Output Capacitor Capacitor Ground Figure26. LP3961TO-263PackageTypicalLayout Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 SNVS056J–MAY2000–REVISEDJUNE2015 www.ti.com Layout Example (continued) SD Pull-up SENSE Resistor IN OUT Input Output Capacitor Capacitor Ground Figure27. LP3964TO-263PackageTypicalLayout 10.3 Heatsinking TO-220 Packages The thermal resistance of a TO-220 package can be reduced by attaching it to a heatsink or a copper plane on a PCboard. Theheatsinktobeusedintheapplicationshouldhaveaheatsink-to-ambientthermalresistance, R ≤R −R −R (7) θHA θJA θCH θJC In this equation, R is the thermal resistance from the junction to the surface of the heatsink and R is the θCH θJC thermalresistancefromthejunctiontothesurfaceofthecase. 20 SubmitDocumentationFeedback Copyright©2000–2015,TexasInstrumentsIncorporated ProductFolderLinks:LP3961 LP3964

LP3961,LP3964 www.ti.com SNVS056J–MAY2000–REVISEDJUNE2015 11 Device and Documentation Support 11.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table1.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY LP3961 Clickhere Clickhere Clickhere Clickhere Clickhere LP3964 Clickhere Clickhere Clickhere Clickhere Clickhere 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.3 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2000–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:LP3961 LP3964

PACKAGE OPTION ADDENDUM www.ti.com 9-Jun-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LP3961EMP-1.8/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LBAB & no Sb/Br) LP3961EMP-2.5 NRND SOT-223 NDC 5 1000 TBD Call TI Call TI -40 to 125 LBBB LP3961EMP-2.5/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LBBB & no Sb/Br) LP3961EMP-3.3 NRND SOT-223 NDC 5 1000 TBD Call TI Call TI -40 to 125 LAZB LP3961EMP-3.3/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LAZB & no Sb/Br) LP3961EMP-5.0 NRND SOT-223 NDC 5 1000 TBD Call TI Call TI -40 to 125 LBSB LP3961EMP-5.0/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LBSB & no Sb/Br) LP3961EMPX-1.8/NOPB ACTIVE SOT-223 NDC 5 2000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LBAB & no Sb/Br) LP3961EMPX-2.5/NOPB ACTIVE SOT-223 NDC 5 2000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LBBB & no Sb/Br) LP3961EMPX-3.3 NRND SOT-223 NDC 5 2000 TBD Call TI Call TI -40 to 125 LAZB LP3961ES-1.8 NRND DDPAK/ KTT 5 45 TBD Call TI Call TI -40 to 125 LP3961ES TO-263 -1.8 LP3961ES-1.8/NOPB ACTIVE DDPAK/ KTT 5 45 Green (RoHS SN Level-3-245C-168 HR -40 to 125 LP3961ES TO-263 & no Sb/Br) -1.8 LP3961ES-2.5/NOPB ACTIVE DDPAK/ KTT 5 45 Green (RoHS SN Level-3-245C-168 HR -40 to 125 LP3961ES TO-263 & no Sb/Br) -2.5 LP3961ES-3.3/NOPB ACTIVE DDPAK/ KTT 5 45 Green (RoHS SN Level-3-245C-168 HR -40 to 125 LP3961ES TO-263 & no Sb/Br) -3.3 LP3961ESX-2.5/NOPB ACTIVE DDPAK/ KTT 5 500 Green (RoHS SN Level-3-245C-168 HR -40 to 125 LP3961ES TO-263 & no Sb/Br) -2.5 LP3961ESX-3.3/NOPB ACTIVE DDPAK/ KTT 5 500 Green (RoHS SN Level-3-245C-168 HR -40 to 125 LP3961ES TO-263 & no Sb/Br) -3.3 LP3964EMP-1.8/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LBFB & no Sb/Br) LP3964EMP-2.5/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LBHB & no Sb/Br) LP3964EMP-3.3/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LBJB & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 9-Jun-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) LP3964EMP-ADJ NRND SOT-223 NDC 5 1000 TBD Call TI Call TI -40 to 125 LBPB LP3964EMP-ADJ/NOPB ACTIVE SOT-223 NDC 5 1000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LBPB & no Sb/Br) LP3964EMPX-2.5/NOPB ACTIVE SOT-223 NDC 5 2000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LBHB & no Sb/Br) LP3964EMPX-ADJ/NOPB ACTIVE SOT-223 NDC 5 2000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 LBPB & no Sb/Br) LP3964ES-1.8 NRND DDPAK/ KTT 5 45 TBD Call TI Call TI -40 to 125 LP3964ES TO-263 -1.8 LP3964ES-1.8/NOPB ACTIVE DDPAK/ KTT 5 45 Green (RoHS SN Level-3-245C-168 HR -40 to 125 LP3964ES TO-263 & no Sb/Br) -1.8 LP3964ES-2.5/NOPB ACTIVE DDPAK/ KTT 5 45 Green (RoHS SN Level-3-245C-168 HR -40 to 125 LP3964ES TO-263 & no Sb/Br) -2.5 LP3964ES-3.3/NOPB ACTIVE DDPAK/ KTT 5 45 Green (RoHS SN Level-3-245C-168 HR -40 to 125 LP3964ES TO-263 & no Sb/Br) -3.3 LP3964ES-ADJ NRND DDPAK/ KTT 5 45 TBD Call TI Call TI -40 to 125 LP3964ES TO-263 -ADJ LP3964ES-ADJ/NOPB ACTIVE DDPAK/ KTT 5 45 Green (RoHS SN Level-3-245C-168 HR -40 to 125 LP3964ES TO-263 & no Sb/Br) -ADJ LP3964ESX-2.5/NOPB ACTIVE DDPAK/ KTT 5 500 Green (RoHS SN Level-3-245C-168 HR -40 to 125 LP3964ES TO-263 & no Sb/Br) -2.5 LP3964ESX-3.3/NOPB ACTIVE DDPAK/ KTT 5 500 Green (RoHS SN Level-3-245C-168 HR -40 to 125 LP3964ES TO-263 & no Sb/Br) -3.3 LP3964ESX-ADJ/NOPB ACTIVE DDPAK/ KTT 5 500 Green (RoHS SN Level-3-245C-168 HR -40 to 125 LP3964ES TO-263 & no Sb/Br) -ADJ LP3964ET-ADJ/NOPB ACTIVE TO-220 NDH 5 45 Green (RoHS SN Level-1-NA-UNLIM -40 to 125 LP3964ET & no Sb/Br) -ADJ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 9-Jun-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) LP3961EMP-1.8/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3961EMP-2.5 SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3961EMP-2.5/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3961EMP-3.3 SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3961EMP-3.3/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3961EMP-5.0 SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3961EMP-5.0/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3961EMPX-1.8/NOPB SOT-223 NDC 5 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3961EMPX-2.5/NOPB SOT-223 NDC 5 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3961EMPX-3.3 SOT-223 NDC 5 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3961ESX-2.5/NOPB DDPAK/ KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 TO-263 LP3961ESX-3.3/NOPB DDPAK/ KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 TO-263 LP3964EMP-1.8/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3964EMP-2.5/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3964EMP-3.3/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3964EMP-ADJ SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3964EMP-ADJ/NOPB SOT-223 NDC 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) LP3964EMPX-2.5/NOPB SOT-223 NDC 5 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3964EMPX-ADJ/NOPB SOT-223 NDC 5 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 Q3 LP3964ESX-2.5/NOPB DDPAK/ KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 TO-263 LP3964ESX-3.3/NOPB DDPAK/ KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 TO-263 LP3964ESX-ADJ/NOPB DDPAK/ KTT 5 500 330.0 24.4 10.75 14.85 5.0 16.0 24.0 Q2 TO-263 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) LP3961EMP-1.8/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3961EMP-2.5 SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3961EMP-2.5/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3961EMP-3.3 SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3961EMP-3.3/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3961EMP-5.0 SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3961EMP-5.0/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3961EMPX-1.8/NOPB SOT-223 NDC 5 2000 367.0 367.0 35.0 LP3961EMPX-2.5/NOPB SOT-223 NDC 5 2000 367.0 367.0 35.0 LP3961EMPX-3.3 SOT-223 NDC 5 2000 367.0 367.0 35.0 PackMaterials-Page2

PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2019 Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) LP3961ESX-2.5/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP3961ESX-3.3/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP3964EMP-1.8/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3964EMP-2.5/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3964EMP-3.3/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3964EMP-ADJ SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3964EMP-ADJ/NOPB SOT-223 NDC 5 1000 367.0 367.0 35.0 LP3964EMPX-2.5/NOPB SOT-223 NDC 5 2000 367.0 367.0 35.0 LP3964EMPX-ADJ/NOPB SOT-223 NDC 5 2000 367.0 367.0 35.0 LP3964ESX-2.5/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP3964ESX-3.3/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP3964ESX-ADJ/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 PackMaterials-Page3

MECHANICAL DATA NDC0005A www.ti.com

MECHANICAL DATA NDH0005D www.ti.com

MECHANICAL DATA KTT0005B TS5B (Rev D) BOTTOM SIDE OF PACKAGE www.ti.com

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